JP2018147937A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high avalanche withstand capability. A semiconductor device 1 includes a semiconductor substrate 10 partitioned between an element portion 10A provided with a functional structure and a peripheral portion 10B provided with a terminal withstand voltage structure. The terminal withstand voltage structure is provided on the surface of the semiconductor substrate 10, and is provided in the semiconductor substrate 10 with a plurality of embedded insulating films 5 arranged at intervals along the direction away from the element portion 10A. The first conductive type drift region 12 and the plurality of second conductive type guard ring regions 16 provided on the surface layer portion of the semiconductor substrate 10 and each of which are arranged between adjacent embedded insulating films 5. And a second conductive type embedded region 17 of the second conductive type, which is provided in the semiconductor substrate 10 and is arranged away from the embedded insulating film 5. [Selection diagram] Fig. 1

Description

  The technology disclosed in this specification relates to a semiconductor device.

  A semiconductor device often includes a semiconductor substrate that is partitioned into an element portion provided with a functional structure and a peripheral portion provided with a termination withstand voltage structure. As such a terminal breakdown voltage structure of a semiconductor device, a plurality of guard ring regions provided in the surface layer portion of the semiconductor substrate in a range corresponding to the peripheral portion are widely employed. Patent Documents 1 to 4 exemplify semiconductor devices in which a plurality of guard ring regions are employed.

JP2015-32664 A Japanese Patent Laying-Open No. 2015-207702 JP2015-207703A JP 2008-147361 A

  When a reverse bias is applied after a forward current flows through the functional structure of the element portion, a depletion layer spreads from the element portion toward the peripheral portion. With the extension of the depletion layer, carriers remaining in the semiconductor substrate are discharged. When the amount of carriers remaining in the semiconductor substrate is large, the speed at which the depletion layer extends is reduced, and electric field concentration occurs locally at the periphery of the semiconductor substrate. In a semiconductor device provided with a plurality of guard ring regions, a pn junction composed of the guard ring region and the drift region exists with a high curvature radius in a region between adjacent guard ring regions. Therefore, the electric field may concentrate in that region. For this reason, a dynamic avalanche phenomenon due to electric field concentration may occur in a region between adjacent guard ring regions. When a dynamic avalanche phenomenon occurs between adjacent guard ring regions, an avalanche current flows in a concentrated manner on the surface of the semiconductor substrate, which may cause thermal damage due to Joule heat.

  Thus, in order for a semiconductor device employing a plurality of guard ring regions to have a high avalanche resistance, it is possible to alleviate electric field concentration in the region between adjacent guard ring regions, that is, the surface portion of the semiconductor substrate. It is essential. However, there is a concern that a dynamic avalanche phenomenon may occur inside the semiconductor substrate only by reducing the electric field concentration on the surface portion of the semiconductor substrate. For this reason, in order to have a high avalanche resistance, it is important to reduce electric field concentration inside the semiconductor substrate. An object of the present specification is to provide a semiconductor device having a high avalanche resistance.

  Examples of the semiconductor device disclosed in this specification include a diode, a MOSFET, and an IGBT. The semiconductor device can include a semiconductor substrate that is partitioned into an element portion provided with a functional structure and a peripheral portion provided with a termination withstand voltage structure. The material of the semiconductor substrate is not particularly limited, but silicon, silicon carbide, or nitride semiconductor is exemplified. The functional structure is not particularly limited, but a MOS structure is exemplified. The functional structure can have a first conductivity type element part side drift region and a second conductivity type surface region. The element part side drift region is provided in the semiconductor substrate. The surface region is provided on the surface layer portion of the semiconductor substrate and is disposed on the element portion side drift region. The surface region may be referred to as the anode region, body region, or base region. The termination breakdown voltage structure may include a plurality of buried insulating films, a first conductivity type peripheral drift region, a plurality of second conductivity type guard ring regions, and a second conductivity type second conductivity type buried region. The plurality of buried insulating films are provided on the surface of the semiconductor substrate, and are arranged at intervals along the direction away from the element portion. The plurality of buried insulating films have an insulator filled in a plurality of shallow trenches formed on the surface of the semiconductor substrate. The peripheral side drift region is provided in the semiconductor substrate. The plurality of guard ring regions are provided in the surface layer portion of the semiconductor substrate. Each of the plurality of guard ring regions is disposed between adjacent buried insulating films. The second conductivity type buried region is provided in the semiconductor substrate and is arranged away from the buried insulating film. In this semiconductor device, since the buried insulating film is provided between the adjacent guard ring regions, the electric field concentration in the region between the adjacent guard ring regions, that is, the surface portion of the semiconductor substrate is alleviated. Occurrence of the dynamic avalanche phenomenon is suppressed. Further, according to this semiconductor device, depletion is promoted inside the substrate in the peripheral portion of the semiconductor substrate by the depletion layer extending from the pn junction of the second conductivity type buried region and the peripheral drift region. Thereby, the electric field inside the substrate in the peripheral portion of the semiconductor substrate is relaxed, and the semiconductor device can have a high avalanche resistance.

  In the semiconductor device, the second conductivity type buried region may be in contact with the surface region. In this semiconductor device, since the potential of the second conductivity type buried region is stabilized, the depletion layer can quickly extend from the pn junction between the second conductivity type buried region and the peripheral drift region when a reverse bias is applied. .

  In the semiconductor device, the plurality of guard ring regions may be formed deeper than the plurality of buried insulating films. In this case, the second conductivity type buried region may be in contact with the plurality of guard ring regions. In this semiconductor device, since the second conductivity type buried region is arranged immediately below the plurality of guard ring regions, the electric field around the plurality of guard ring regions can be relaxed satisfactorily.

  In the semiconductor device, the impurity concentration of the second conductivity type buried region may be lower than the impurity concentration of the plurality of guard ring regions. In this semiconductor device, since the second conductivity type buried region is depleted satisfactorily, the electric field inside the substrate at the periphery of the semiconductor substrate is satisfactorily relaxed.

  In the semiconductor device, the termination breakdown voltage structure may be further provided so as to extend on the semiconductor substrate, and may have a field plate electrode in contact with the guard ring region. When such a field plate electrode is provided, fluctuations in breakdown voltage due to external charges can be suppressed.

The principal part sectional drawing of a semiconductor device is shown typically.

  As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 10 made of a silicon single crystal. The semiconductor substrate 10 is partitioned into an element portion 10A provided with a MOS structure and a peripheral portion 10B provided with a termination withstand voltage structure. The peripheral portion 10B is arranged so as to make a round around the element portion 10A when observed from a direction orthogonal to the surface of the semiconductor substrate 10 (hereinafter referred to as “when viewed in plan”). In addition, 10 A of element parts are specified as a range in which the body area | region 13 mentioned later exists. For this reason, the boundary between the element portion 10 </ b> A and the peripheral portion 10 </ b> B corresponds to the position of the side surface of the body region 13.

  The semiconductor device 1 includes a drain electrode 2, a source electrode 3, and a trench gate 4. The drain electrode 2 is in contact with the back surface of the semiconductor substrate 10 in a range corresponding to both the element portion 10A and the peripheral portion 10B. The source electrode 3 is in contact with the surface of the semiconductor substrate 10 in a range corresponding to the element portion 10A. The trench gate 4 is provided in a gate trench formed in the surface layer portion of the semiconductor substrate 10 in a range corresponding to the element portion 10A. In FIG. 1, only one trench gate 4 is shown, but actually, a plurality of trench gates 4 are provided in the element portion 10A. The trench gates 4 have, for example, a stripe or lattice layout when the semiconductor substrate 10 is viewed in plan.

The semiconductor substrate 10 includes an n ⁺ type drain region 11, an n type drift region 12, a p ⁺ type body region 13, an n ⁺ type source region 14, a p ⁺⁺ type body contact region 15, and a p ⁺⁺ type. A guard ring region 16, a p-type p-type buried region 17, an n ⁺ -type terminal equipotential region 18, and an n-type n-type dispersion region 19.

  The drain region 11 is provided in the back layer portion of the semiconductor substrate 10 in a range corresponding to both the element portion 10A and the peripheral portion 10B. The drain region 11 is exposed on the back surface of the semiconductor substrate 10 and is in ohmic contact with the drain electrode 2.

  The drift region 12 is provided in the semiconductor substrate 10 in a range corresponding to both the element portion 10 </ b> A and the peripheral portion 10 </ b> B, and is disposed on the drain region 11. In the element portion 10 </ b> A, the drift region 12 is disposed between the drain region 11 and the body region 13 to separate them, and is in contact with the drain region 11 and the body region 13. In the peripheral portion 10B, the drift region 12 is disposed between the drain region 11 and the p-type buried region 17 to separate them, and is disposed between the drain region 11 and the terminal equipotential region 18 to separate them. The drain region 11, the p-type buried region 17, and the terminal equipotential region 18 are in contact with each other.

  The body region 13 is provided in the surface layer portion of the semiconductor substrate 10 in a range corresponding to the element portion 10 </ b> A, and is disposed on the drift region 12. The body region 13 is disposed between and separates the drift region 12 and the source region 14 and is in contact with the drift region 12, the source region 14, and the body contact region 15. The body region 13 is an example of a surface region disclosed in this specification.

  The source region 14 is provided in the surface layer portion of the semiconductor substrate 10 in a range corresponding to the element portion 10 </ b> A, and is disposed on the body region 13. The source region 14 contacts the side surface of the trench gate 4 and also contacts the body region 13 and the body contact region 15. The source region 14 is exposed on the surface of the semiconductor substrate 10 and is in ohmic contact with the source electrode 3.

  The body contact region 15 is provided in the surface layer portion of the semiconductor substrate 10 in a range corresponding to the element portion 10 </ b> A, and is disposed on the body region 13. Body contact region 15 is in contact with body region 13 and source region 14. The body contact region 15 is exposed on the surface of the semiconductor substrate 10 and is in ohmic contact with the source electrode 3.

  The trench gate 4 is provided in a gate trench extending in the depth direction from the surface of the semiconductor substrate 10, and has a gate electrode 4a and a gate insulating film 4b covering the gate electrode 4a. The trench gate 4 passes through the source region 14 and the body region 13 and reaches the drift region 12. The gate electrode 4a of the trench gate 4 faces the body region 13 that separates the drift region 12 and the source region 14 via the gate insulating film 4b. The body region 13 facing the gate electrode 4a is a region where a channel is formed. As described above, the element portion 10 </ b> A of the semiconductor substrate 10 is provided with a MOS structure including the trench gate 4, the drift region 12, the body region 13, and the source region 14. The MOS structure incorporates a pn diode composed of a drift region 12 and a body region 13, and this pn diode operates as a freewheeling diode.

  The plurality of guard ring regions 16 are provided in the surface layer portion of the semiconductor substrate 10 in a range corresponding to the peripheral portion 10 </ b> B, and are disposed on the p-type buried region 17. The plurality of guard ring regions 16 are in contact with the p-type buried region 17, the n-type dispersed region 19 and a buried insulating film 5 described later. The plurality of guard ring regions 16 are arranged at intervals along the direction away from the element portion 10A (the left and right direction on the paper surface). Further, each of the plurality of guard ring regions 16 is arranged so as to make a round around the element portion 10A when viewed in plan. The plurality of guard ring regions 16 are exposed on the surface of the semiconductor substrate 10 and are in contact with a field plate electrode 7 described later. The plurality of guard ring regions 16 are electrically connected to the body region 13 through the RESURF region 17. For this reason, the plurality of guard ring regions 16 are not electrically floating.

  The p-type buried region 17 is provided in the semiconductor substrate 10 in a range corresponding to the peripheral portion 10 </ b> B, and is disposed on the drift region 12. The p-type buried region 17 is in contact with the drift region 12, the body region 13, the plurality of guard ring regions 16, and the n-type dispersion region 19. The p-type buried region 17 has a flat plate shape, extends along a direction away from the element portion 10 </ b> A (left and right direction in the drawing), and one end contacts the body region 13. The p-type buried region 17 extends from the body region 13 beyond the plurality of guard ring regions 16 to a position between the guard ring region 16 and the terminal equipotential region 18 when viewed in plan. The p-type buried region 17 is separated from the drain region 11 by the drift region 12 and is separated from the buried insulating film 5 described later by the n-type dispersion region 19. The lower surface of p type buried region 17 exists at a position deeper than the lower surface of body region 13. The p-type buried region 17 is arranged so as to make a round around the element portion 10A when viewed in plan. The p-type buried region 17 has a uniform impurity concentration distribution in the in-plane direction. The impurity concentration of the p-type buried region 17 is lower than the impurity concentrations of the plurality of guard ring regions 16 and the body region 13.

  The end equipotential region 18 is provided on the surface layer portion of the semiconductor substrate 10 in a range corresponding to the end of the peripheral portion 10B, and is disposed on the drift region 12. The terminal equipotential region 18 contacts the drift region 12. The terminal equipotential region 18 is arranged so as to make a round around the element portion 10A when viewed in plan. The terminal equipotential region 18 is exposed on the surface of the semiconductor substrate 10 and is in contact with the terminal electrode 8 described later.

  The plurality of n-type dispersion regions 19 are provided in the surface layer portion of the semiconductor substrate 10 in a range corresponding to the peripheral portion 10 </ b> B, and are disposed on the p-type buried region 17. Of the plurality of n-type dispersion regions 19, the n-type dispersion region 19 disposed in the element part 10A is the body region 13, the body contact region 15, the guard ring region 16, the p-type buried region 17, and a buried region described later. 5 is contacted. The n-type dispersion region 19 disposed on the most terminal side among the plurality of n-type dispersion regions 19 is in contact with the drift region 12, the guard ring region 16, the p-type buried region 17, and a buried region 5 described later. Other n-type dispersion regions 19 are in contact with the guard ring region 16, the p-type buried region 17 and a buried region 5 described later. The plurality of n-type dispersion regions 19 are arranged at intervals along the direction away from the element portion 10A (the left-right direction on the paper surface). Further, each of the plurality of n-type dispersion regions 19 is arranged so as to make a round around the element portion 10A when viewed in plan. The impurity concentration of the plurality of n-type dispersion regions 19 is higher than the impurity concentration of the drift region 12. The potentials of the n-type dispersion regions 19 other than the n-type dispersion region 19 arranged on the most terminal side among the plurality of n-type dispersion regions 19 are floating. Such floating n-type dispersion region 19 and p-type buried region 17 can form a super junction structure.

  As shown in FIG. 1, the semiconductor device 1 further includes a plurality of buried insulating films 5, an interlayer insulating film 6, a plurality of field plate electrodes 7 and a termination electrode 8.

  Each of the plurality of buried insulating films 5 has an insulator filled in a plurality of shallow trenches formed on the surface of the semiconductor substrate 10 in a range corresponding to the peripheral portion 10B. Thus, the plurality of buried insulating films 5 have a shallow trench isolation (STI) structure. The plurality of buried insulating films 5 are arranged at intervals along the direction away from the element portion 10A (the left-right direction on the paper surface). Each of the plurality of embedded insulating films 5 is arranged so as to make a round around the element portion 10A when viewed in plan. A part of the plurality of buried insulating films 5 is disposed between adjacent guard ring regions 16. In other words, each of the plurality of guard ring regions 16 is disposed between adjacent buried insulating films 5. The plurality of guard ring regions 16 are formed deeper than the buried insulating film 5.

  The interlayer insulating film 6 is provided on the semiconductor substrate 10 in a range corresponding to the peripheral portion 10B. A plurality of through holes are formed in the interlayer insulating film 6, and the field plate electrode 7 and the guard ring region 16 are in contact with each other through the through holes.

  The plurality of field plate electrodes 7 are extended on the interlayer insulating film 6 in a range corresponding to the peripheral portion 10B. The plurality of field plate electrodes 7 are arranged at intervals along a direction away from the element portion 10A (left and right direction on the paper surface). Further, each of the plurality of field plate electrodes 7 is arranged so as to make a round around the element portion 10A when viewed in plan. Each of the plurality of field plate electrodes 7 is arranged corresponding to each of the plurality of guard ring regions 16 and is in contact with each of the plurality of guard ring regions 16. The potentials of the plurality of field plate electrodes 7 are floating. Although not shown, a mold resin is formed on the peripheral portion 10 </ b> B of the semiconductor substrate 10 so as to cover the interlayer insulating film 6 and the field plate electrode 7. The plurality of field plate electrodes 7 can prevent external charges that have entered the mold resin from entering the semiconductor substrate 10 due to moisture or the like adhering to the mold resin. As a result, local collapse of the charge balance in the peripheral portion 10B of the semiconductor substrate 10 is suppressed, and a decrease in breakdown voltage of the semiconductor device 1 is suppressed.

  The termination electrode 8 is provided on the surface of the semiconductor substrate 10 in a range corresponding to the termination of the peripheral portion 10B. The termination electrode 8 is arranged so as to make a round around the element portion 10A when viewed in plan. The termination electrode 8 is disposed corresponding to the termination equipotential region 18 and is in contact with the termination equipotential region 18. The potential of the termination electrode 8 is the same as that of the drain electrode 2.

  Next, the operation of the semiconductor device 1 will be described. When a positive voltage is applied to the drain electrode 2, a ground voltage is applied to the source electrode 3, and a positive voltage is applied to the gate electrode 4a, a channel is formed in the body region 13 opposed to the gate electrode 4a, and the source region 14 Electrons flow from the source electrode 3 toward the drain electrode 2 through the channel, the drift region 12 and the drain region 11. Thus, the mode in which current flows from the drain electrode 2 toward the source electrode 3 is the on mode. On the other hand, when a positive voltage is applied to the drain electrode 2, a ground voltage is applied to the source electrode 3, and a ground voltage is applied to the gate electrode 4a, a channel is not formed in the body region 13 opposed to the gate electrode 4a, The current is cut off. Thus, the mode in which no current flows from the drain electrode 2 to the source electrode 3 is an off mode. The semiconductor device 1 can operate as a switching element by switching between an on mode and an off mode.

  For example, when the semiconductor device 1 is used in an inverter circuit, a load current flowing through a load such as a motor is passed through a pn diode (consisting of a drift region 12 and a body region 13) built in the MOS structure of the element unit 10A. There is a reflux mode to reflux. In this reflux mode, a voltage that is more positive at the source electrode 3 than at the drain electrode 2 is applied, and a forward current flows through the built-in diode. Thereafter, the semiconductor device 1 is switched to the off mode, and a reverse bias is applied so that the drain electrode 2 is more positive than the source electrode 3. In such a transition period from the reflux mode to the off mode, a dynamic avalanche phenomenon may occur in the peripheral portion 10B. The semiconductor device 1 can take measures against such a dynamic avalanche phenomenon.

  In the transition period from the reflux mode to the off mode, a depletion layer spreads from the pn junction of the drift region 12 and the body region 13 into the drift region 12 in the element portion 10A. This depletion layer extends from the element portion 10A toward the peripheral portion 10B. The depletion layer spreading from the element portion 10A reaches each of the plurality of guard ring regions 16 in order in the peripheral portion 10B along the direction away from the element portion 10A (the left-right direction on the paper surface). Can spread. In particular, in the semiconductor device 1, the p-type buried region 17 is provided in the peripheral portion 10B, and a depletion layer extending from the pn junction between the p-type buried region 17 and the drift region 12 is also added, so that the depletion layer becomes the peripheral portion 10B. Formed quickly in a wide range

  In the semiconductor device 1, the buried insulating film 5 is provided between adjacent guard ring regions 16, and a p-type buried region 17 and an n-type dispersion region 19 are further provided. If the buried insulating film 5, the p-type buried region 17, and the n-type dispersion region 19 are not provided, the region between the adjacent guard ring regions 16 includes the guard ring region 16 and the drift region 12. Since the pn junction has a small radius of curvature, the electric field is concentrated, and a dynamic avalanche phenomenon due to the electric field concentration occurs. When the dynamic avalanche phenomenon occurs between the adjacent guard ring regions 16, the avalanche current flows in a concentrated manner on the surface of the semiconductor substrate, and there is a concern about thermal damage due to Joule heat.

  In the semiconductor device 1, since the buried insulating film 5 is provided between the adjacent guard ring regions 16, electric field concentration is reduced in the region between the adjacent guard ring regions 16, and a dynamic avalanche phenomenon occurs in that region. Is suppressed. Thereby, in the semiconductor device 1, the region where the electric field concentrates moves from the surface of the semiconductor substrate 10 to the inside of the substrate. In the semiconductor device 1, since the p-type buried region 17 is further provided in the semiconductor substrate 10, a depletion layer is quickly formed inside the semiconductor substrate 10 during the transition period from the reflux mode to the off mode. The electric field inside the semiconductor substrate 10 is relaxed. Thus, in the semiconductor device 1, the occurrence of the dynamic avalanche phenomenon can be suppressed both in the surface portion of the semiconductor substrate 10 and in the substrate. Thereby, the semiconductor device can have a high avalanche resistance. In the semiconductor device 1, the lower surface of the p-type buried region 17 and the vicinity of the pn junction surface of the drift region 12 become an electric field concentration portion, and when a high surge voltage is applied, a dynamic avalanche phenomenon can occur in the vicinity of the pn junction surface. . As described above, in the semiconductor device 1, the location where the dynamic avalanche phenomenon occurs has moved to a deep position in the semiconductor substrate 10, and even if the dynamic avalanche phenomenon occurs, the avalanche current may flow diffusely in the semiconductor substrate 10. it can. Also in this respect, the semiconductor device 1 can have a high avalanche resistance.

  In the semiconductor device 1, the p-type buried region 17 is in contact with the body region 13. Thereby, since the potential of the p-type buried region 17 is stabilized, a depletion layer is quickly formed from the pn junction of the p-type buried region 17 and the drift region 12 in the transition period from the reflux mode to the off mode.

  In the semiconductor device 1, the p-type buried region 17 is in contact with the plurality of guard ring regions 16. As a result, since the p-type buried region 17 is disposed immediately below the plurality of guard ring regions 16, the electric field around the plurality of guard ring regions 16 can be favorably reduced. Furthermore, since the p-type buried region 17 and the n-type dispersion region 19 form a super junction structure, the electric field around the plurality of guard ring regions 16 can be relieved very well. Further, the depletion layer extending from the element portion 10 </ b> A can be well connected to the depletion layer extending from the pn junction between the p-type buried region 17 and the drift region 12. Thereby, the depletion layer spreading from the element portion 10 </ b> A can quickly reach each of the plurality of guard ring regions 16. Therefore, in the semiconductor device 1, during the transition period from the reflux mode to the off mode, the depletion layer is quickly formed over a wide area of the peripheral portion 10B, and the occurrence of the dynamic avalanche phenomenon can be satisfactorily suppressed.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1: Semiconductor device 2: Drain electrode 3: Source electrode 4: Trench gate 4a: Gate electrode 4b: Gate insulating film 5: Buried insulating film 6: Interlayer insulating film 7: Field plate electrode 8: Termination electrode 10: Semiconductor substrate 10A: Element portion 10B: Peripheral portion 11: Drain region 12: Drift region 13: Body region 14: Source region 15: Body contact region 16: Guard ring region 17: p-type buried region 18: Termination equipotential region

Claims (5)

A semiconductor device,
Comprising a semiconductor substrate partitioned into an element part provided with a functional structure and a peripheral part provided with a termination withstand voltage structure;
The functional structure is
A first conductivity type element side drift region provided in the semiconductor substrate;
A surface region of a second conductivity type provided on a surface layer portion of the semiconductor substrate and disposed on the element portion side drift region;
The termination withstand voltage structure is
A plurality of embedded insulating films provided on the surface of the semiconductor substrate and arranged at intervals along a direction away from the element portion, and a plurality of embedded insulating films formed on the surface of the semiconductor substrate; A plurality of buried insulating films having an insulator filled in the shallow trench;
A first conductivity type peripheral portion drift region provided in the semiconductor substrate;
A plurality of guard ring regions of a second conductivity type provided in the surface layer portion of the semiconductor substrate, each of which is disposed between the adjacent buried insulating films;
A semiconductor device comprising: a second conductivity type two conductivity type buried region provided in the semiconductor substrate and disposed apart from the buried insulating film.   The semiconductor device according to claim 1, wherein the second conductivity type buried region is in contact with the surface region. The plurality of guard ring regions are formed deeper than the plurality of buried insulating films;
The semiconductor device according to claim 1, wherein the second conductivity type buried region is in contact with the plurality of guard ring regions.   4. The semiconductor device according to claim 1, wherein an impurity concentration of the second conductivity type buried region is lower than an impurity concentration of the plurality of guard ring regions. 5.   5. The semiconductor device according to claim 1, wherein the termination breakdown voltage structure is further provided so as to extend on the semiconductor substrate and has a field plate electrode in contact with the guard ring region.

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