JP2018147933A - Manufacturing method of semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided in which a metal material is etched using a mask having appropriate etching resistance. A method of manufacturing a semiconductor device includes forming a pattern formed of an insulating material on an upper surface of a metal layer formed of a metal material, and performing ion milling using the pattern as a mask. Etching and attaching the metal material to the side surface of the pattern, and performing reactive ion etching using the pattern with the metal material attached to the side surface as a mask to process the metal layer. [Selection] Figure 10

Description

  The present disclosure relates to a method for manufacturing a semiconductor device.

  A magnetic tunnel junction (hereinafter referred to as MTJ) element used in a magnetoresistive random access memory (hereinafter referred to as MRAM) includes a fixed magnetic layer, a free magnetic layer, and a tunnel insulating film disposed therebetween. Including. The magnetization direction of the fixed magnetization layer is fixed, and the magnetization direction of the free magnetization layer is variable. The resistance value of the MTJ element is low when the magnetization direction of the free magnetic layer and the magnetization direction of the fixed magnetic layer are in the same parallel direction, and high when the antiparallel state is in the opposite direction. . The parallel state and the antiparallel state may be associated with 0 and 1 of the stored data, respectively.

  MRAM is classified into a write wiring type and a spin injection type from the viewpoint of a writing method. In the write wiring type, the magnetization direction of the free magnetic layer is controlled by the magnetic field generated by the current flowing through the write word line. In the spin injection type, the magnetization direction of the free magnetic layer is controlled by a spin transfer effect generated when a current is passed through the MTJ element. Currently, the spin injection type is the mainstream. This is because a write wiring is unnecessary in the spin injection type, and this is advantageous for miniaturization which is essential for increasing the capacity.

  In the spin injection type, the amount of current required for magnetic field reversal is determined by the current density. The smaller the element area, the smaller the amount of necessary reversal current. By miniaturizing the MTJ element, the operating current can be reduced and the memory capacity can be increased. Therefore, research and development for miniaturization has been energetically performed.

  A magnetic material is used for the MTJ element, and there is a problem that it is difficult to process by reactive ion etching (hereinafter referred to as RIE) that is usually performed by fine processing. This is because the magnetic material is not easily scraped by the gas used for etching. For this reason, a resist mask that is usually used in fine exposure has no resistance, so that a selection ratio with a material to be processed cannot be obtained, and a hard mask using a metal material (for example, Ta) is used.

  The use of a metal material for the mask in order to increase the etching resistance means that processing for processing the mask itself becomes difficult. In order to process a metal material that is a mask, a material that is easy to process and more resistant to etching than a resist mask, such as a silicon oxide mask, is often used.

However, the etching resistance of the silicon oxide film mask is not sufficient against an etching gas such as CF ₄ used in processing Ta. Specifically, the etching rate of the silicon oxide film by CF ₄ is about 3 to 5 times higher than the etching rate of Ta, and the silicon oxide mask is consumed faster during etching than the material to be processed. End up. Therefore, it is necessary to form a thick silicon oxide film mask. However, if the thickness of the mask is increased, there arises a problem that the dimensional accuracy for element formation deteriorates.

  Further, since the electric field of the plasma is concentrated on the corner portion of the mask, the corner portion on the peripheral edge of the mask is particularly easily cut. Therefore, in the case of a mask material with a high etching rate and fast consumption, the mask shape deteriorates during the etching process, and the shape of the material to be processed deteriorates reflecting the deterioration of the mask shape.

JP 2002-38285 A

  In view of the above, a method for manufacturing a semiconductor element in which a metal material is etched using a mask having appropriate etching resistance is desired.

  A method of manufacturing a semiconductor device includes: forming a pattern formed of an insulating material on an upper surface of a metal layer formed of a metal material; etching the metal layer by performing ion milling using the pattern as a mask; and Each step includes depositing a metal material on a side surface of the pattern and processing the metal layer by performing reactive ion etching using the pattern on which the metal material is adhered on the side surface as a mask.

  According to at least one embodiment, there is provided a method for manufacturing a semiconductor device, wherein a metal material is etched using a mask having appropriate etching resistance.

It is a figure which shows the fundamental structure and operation | movement of a magnetic tunnel junction. It is a figure which shows an example of a structure of the semiconductor element which uses an MTJ element as a memory cell. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 1st Example of the manufacturing method of a semiconductor element. It is a figure which shows one modification of the manufacturing method of a semiconductor element. It is a figure which shows the structure of the semiconductor element manufactured by the modification. It is a figure explaining the deformation | transformation of a mask at the time of processing a metal material by RIE using the mask without a metal side wall. It is a figure explaining the tolerance of a mask at the time of processing a metal material by RIE using a mask which has a metal side wall. It is a figure which shows the one step of the manufacturing process in the 2nd Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 2nd Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 2nd Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 2nd Example of the manufacturing method of a semiconductor element. It is a figure which shows the one step of the manufacturing process in the 2nd Example of the manufacturing method of a semiconductor element.

  In the following description, the same or corresponding components are referred to by the same or corresponding numbers, and the description thereof is omitted as appropriate.

  FIG. 1 is a diagram showing a basic configuration and operation of a magnetic tunnel junction (MTJ). The MTJ shown in FIGS. 1A and 1B includes a free magnetic layer 11, a tunnel insulating film 12, and a fixed magnetic layer 13. The MTJ shown in FIGS. 1A and 1B is a perpendicular magnetization type MTJ, and the magnetization direction is not in the direction parallel to the surface of each layer but in the direction perpendicular to the surface of each layer (that is, the thickness direction of the layer). ing.

  In the state shown in FIG. 1A, the magnetization direction of the free magnetic layer 11 faces downward as indicated by an arrow in the layer, and the magnetization direction of the fixed magnetic layer 13 faces upward as indicated by an arrow in the layer. It is suitable. Thus, when the magnetization direction of the free magnetic layer 11 and the magnetization direction of the pinned magnetic layer 13 are antiparallel (in the opposite direction), the MTJ is in a high resistance state showing a high resistance value. In the state shown in FIG. 1B, the magnetization direction of the free magnetic layer 11 faces upward as indicated by an arrow in the layer, and the magnetization direction of the fixed magnetic layer 13 faces upward as indicated by an arrow in the layer. It is suitable. As described above, when the magnetization direction of the free magnetic layer 11 and the magnetization direction of the fixed magnetic layer 13 are in a parallel state (a state in which they are directed in the same direction), the MTJ is in a low resistance state showing a low resistance value. Information can be stored in the MTJ by setting the MTJ to a low resistance state or a high resistance state.

  The magnetization of the free magnetic layer 11 can be reversed by spin injection magnetization reversal using spin-polarized electron torque (STT). For example, in the state of the magnetization direction shown in FIG. 1A, a voltage is applied so that the free magnetic layer 11 is connected to the positive electrode side and the fixed magnetic layer 13 is connected to the negative electrode side. With this voltage application, electrons flow from the fixed magnetic layer 13 side to the free magnetic layer 11 side (that is, electrons flow upward in the drawing). While an electron having a spin opposite to the magnetization direction of the pinned magnetic layer 13 has a low probability of passing through the pinned magnetic layer 13, an electron having a spin in the same direction as the magnetization direction of the pinned magnetic layer 13 has a high probability of being fixed. It passes through the layer 13 and reaches the free magnetic layer 11. Due to the influence of electrons having spins in the same direction as the magnetization direction of the fixed magnetization layer 13, the magnetization direction of the free magnetization layer 11 is reversed and has a magnetization in the same direction as the magnetization direction of the fixed magnetization layer 13 (FIG. 1). The free magnetic layer 11 is set in the state shown in FIG.

  In the state of the magnetization direction shown in FIG. 1B, a voltage is applied so that the fixed magnetic layer 13 is connected to the positive electrode side and the free magnetic layer 11 is connected to the negative electrode side. With this voltage application, electrons flow from the free magnetic layer 11 side to the fixed magnetic layer 13 side (that is, electrons flow downward in the drawing). Electrons having a spin in the same direction as the magnetization direction of the fixed magnetization layer 13 pass through the fixed magnetization layer 13 with high probability, while some of the electrons having a spin opposite to the magnetization direction of the fixed magnetization layer 13 are fixed magnetization. It is reflected by the layer 13 and affects the free magnetic layer 11. Due to the influence of electrons having a spin opposite to the magnetization direction of the fixed magnetization layer 13, the magnetization direction of the free magnetization layer 11 is reversed and has a magnetization opposite to the magnetization direction of the fixed magnetization layer 13 (FIG. 1A The free magnetic layer 11 is set in the state shown in FIG.

  FIG. 2 is a diagram illustrating an example of a configuration of a semiconductor element using an MTJ element as a memory cell. 2 includes a free magnetic layer 11, a tunnel insulating film 12, a fixed magnetic layer 13, a lower electrode 20, an upper electrode 21, an interlayer film 22, a cover insulating layer 23, a wiring 24, and a wiring 25.

  The free magnetic layer 11, the tunnel insulating film 12, and the fixed magnetic layer 13 are MTJ elements and function as memory cells that store 1-bit information. The free magnetic layer 11 and the fixed magnetic layer 13 include a layer formed of a magnetic material such as CoFe or CoFeB, and may include a layer formed of Ta, CoPt, Ru, or the like as appropriate. The tunnel insulating film 12 is a layer formed of an insulating material such as MgO.

Each of the lower electrode 20 and the upper electrode 21 is a metal layer formed of a metal material, and functions as an electrode for applying a voltage to the MTJ element. As will be described later, each of the lower electrode 20 and the upper electrode 21 may include a layer formed of Ta, a layer formed of Ru, and a layer formed of Ta from the lower side to the upper side. The interlayer film 22 and the cover insulating layer 23 may be formed of an insulating material such as SiO ₂ . The wiring 24 and the wiring 25 may be formed of a metal material such as Al or Cu, for example.

  A potential on one polarity side of the applied voltage is applied to the free magnetic layer 11 side of the MTJ element via the wiring 24 and the upper electrode 21. Further, the potential on the other polarity side of the applied voltage is applied to the free magnetic layer 11 side of the MTJ element through the wiring 25 and the lower electrode 20. Thereby, information writing and information reading with respect to the MTJ element can be performed.

  Below, the Example of the manufacturing method of a semiconductor element is described. In the following description, an example of manufacturing a semiconductor element including an MTJ element as shown in FIG. 2 will be described. However, an element to be processed and manufactured is not limited to an MTJ element. For example, as described later, the ferroelectric memory element may be processed and manufactured by using the semiconductor element manufacturing method of the present application. Moreover, in order to process and manufacture elements other than the memory element, the semiconductor element manufacturing method of the present application may be used. Specifically, when a mask having appropriate etching resistance is required when etching a metal material, the semiconductor element manufacturing method of the present application can be used.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  3 to 19 are diagrams showing each stage of the manufacturing process in the first embodiment of the semiconductor device manufacturing method. The first embodiment of the semiconductor device manufacturing method will be described below with reference to FIGS.

  As shown in FIG. 3, a silicon substrate 30 is prepared. The silicon substrate 30 is a plate-like component on which circuit elements such as MTJ elements, electrodes, and wiring as shown in FIG. 2 are formed.

As shown in FIG. 4, a silicon oxide film 31 is formed on the upper surface of the silicon substrate 30. In order to form the silicon oxide film 31, the silicon oxide film 31 may be grown on the surface of the silicon substrate 30 by thermal oxidation, or a CVP (Chemical Vapor Deposition: CVD) method or the like may be formed on the surface of the silicon substrate 30. SiO ₂ may be deposited by:

As shown in FIG. 5, a tantalum (Ta) layer 32, a ruthenium (Ru) layer 33, and a tantalum (Ta) layer 34 are formed on the silicon oxide film 31 in this order by sputtering. The tantalum layer 32, the ruthenium layer 33, and the tantalum layer 34 function as the lower electrode 20 (see FIG. 2) of the MTJ element. Since the adhesion between Ru and SiO ₂ is poor, the tantalum layer 32 is an adhesion layer provided between Ru and SiO ₂ for adhesion. The ruthenium layer 33 is a layer provided to reduce the resistance value of the lower electrode 20. The tantalum layer 34 is an etching stopper layer when processing the MTJ element provided on the upper surface of the lower electrode 20.

  As shown in FIG. 6, a fixed magnetic layer 35, an insulating layer 36, a free magnetic layer 37, a tantalum layer 38, a ruthenium layer 39, and a tantalum layer 40 are formed in this order on the tantalum layer 34. The fixed magnetic layer 35, the insulating layer 36, and the free magnetic layer 37, which are each layer of the MTJ element, may be formed by sputtering. The fixed magnetization layer 35 may be a 1 nm thick layer formed of, for example, CoFeB (cobalt iron boron). The insulating layer 36 may be a 0.8 nm thick layer made of, for example, MgO. The free magnetic layer 37 may be a layer having a thickness of 1.5 nm made of, for example, CoFeB. The tantalum layer 38, the ruthenium layer 39, and the tantalum layer 40 function as the upper electrode 21 (see FIG. 2) of the MTJ element. The tantalum layer 38, the ruthenium layer 39, and the tantalum layer 40 may have a film thickness of, for example, 1 nm, 10 nm, and 40 nm, respectively. The ruthenium layer 39 is a layer provided to reduce the resistance value of the upper electrode 21.

As shown in FIG. 7, an insulating layer 41 made of SiO ₂ is formed on the upper surface of the tantalum layer 40. The insulating layer 41 may be deposited by, for example, a CVD method or a sputtering method. The film thickness of the insulating layer 41 may be 70 nm, for example. The material of the insulating layer 41 is not limited to SiO ₂ , and may be, for example, silicon nitride (SiN), or aluminum oxide (Al ₂ O ₃ ).

  As shown in FIG. 8, a resist pattern 42 is formed on the upper surface of the insulating layer 41 by exposing the photoresist layer formed on the upper surface of the insulating layer 41 with a desired pattern. The resist material may be an organic material including a novolak resin as a base resin and a compound as a photosensitive agent.

In FIG. 9, the insulating layer 41 is processed by performing reactive ion etching using the resist pattern 42 (see FIG. 8) as a mask to form a pattern 41A formed of an insulating material (in this example, SiO ₂ ). . The etching gas may be a mixed gas of CF ₄ and Ar, for example. The resist pattern 42 is removed by ashing after etching. By this treatment, a pattern 41A formed of an insulating material (SiO _{2 in} this example) is formed on the upper surface of a metal layer (in this example, tantalum layer 40) formed of a metal material (Ta in this example). This pattern 41A functions as a mask in ion milling and RIE that are subsequently performed.

Instead of an insulating material such as SiO ₂ , an organic resist may be used as a mask in subsequent ion milling and RIE. However, the heat resistance of the resist is about 100 ° C., and there is a problem that its shape is likely to deteriorate due to heat during processing of Ta and MTJ elements. There is also a problem that the resist has a higher etching rate than SiO ₂ .

  As shown in FIG. 10, by performing ion milling (physical etching) using the pattern 41A as a mask, the metal layer (tantalum layer 40) is etched and the metal material (Ta) is attached to the side surface of the pattern 41A. . The ion milling here refers to physical etching using inert ions, and usable inert gas materials include Ne, Ar, Kr, and Xe. From the viewpoint of price and availability, it is common to use Ar as the inert gas material.

  By irradiating the tantalum layer 40 with a beam of Ar ions perpendicularly, a physical sputtering phenomenon occurs in which Ta atoms in the tantalum layer 40 are blown away. Etching of the tantalum layer 40 proceeds, and the blown Ta atoms are patterned. It adheres and accumulates on the side surface of 41A. Thereby, the tantalum side wall 41B is formed as a Ta thin film on the side surface of the pattern 41A. The tantalum side wall 41B functions as a part of the mask in the subsequent RIE. In ion milling, Ta hardly adheres to the upper surface of the pattern 41A, but may adhere. In that case, the Ta thin film attached to the upper surface may function as a part of the mask in the subsequent RIE.

  The amount of Ta adhering as the tantalum side wall 41B can be controlled by ion milling time (length of time for performing ion milling) and ion milling power (power applied to the electrode during ion milling). Using the same sample as the semiconductor element to be manufactured, ion milling is performed under various time conditions and various power conditions, and the thickness of the generated tantalum sidewall 41B is measured in advance. At the time of manufacturing the semiconductor element, the time and power are adjusted so that the tantalum side wall 41B having a desired thickness is formed by referring to the relationship between the thickness of the tantalum side wall 41B measured in advance and the time and power. If the thickness of the tantalum sidewall 41B is about 5 nm, the pattern 41A and the tantalum sidewall 41B can function as an appropriate mask in the subsequent RIE.

As shown in FIG. 11, the metal layer (tantalum layer 40) is processed by performing reactive ion etching using a pattern 41A having a metal material (Ta) attached to the side surface as a mask. In FIG. 11, the portion of the tantalum layer 40 not covered with the pattern 41A and the tantalum sidewall 41B is completely removed, and a part of the tantalum layer 40 remains as a Ta metal layer 40A under the pattern 41A. ing. The etching gas at this time may be, for example, a mixed gas of CF ₄ and Ar, or may be only CF ₄ . At this time, since the tantalum side wall 41B is provided on the side surface of the pattern 41A, it is possible to suppress the deformation of the shape of the etching mask and to suppress the consumption rate of the mask. The effect of providing the tantalum side wall 41B will be described in detail later.

As shown in FIG. 12, the ruthenium layer 39 and the tantalum layer 38 are processed by continuing the reactive ion etching using the mixed gas of CF ₄ and Ar from the state of FIG. As a result, the ruthenium layer 39 and the tantalum layer 38 which are not covered with the pattern 41A and the tantalum sidewall 41B are completely removed. As a result, the ruthenium layer 39 and part of the tantalum layer 38 remain as metal layers 39A and 38A below the pattern 41A.

Thereafter, the memory element layer (35, 35) existing under the metal layer using the pattern 41A with the metal material (Ta) attached to the side surface and the metal layer (40A, 39A, 38A) remaining under the pattern as a mask. Reactive ion etching for 36, 37) is performed. The etching gas at this time needs to be a gas that reacts with the material of the memory element layer (35, 36, 37), and a mixed gas of CO and NH ₃ or CH ₃ OH may be used.

  In the state shown in FIG. 12, the free magnetic layer 37, the insulating layer 36, and the fixed magnetic layer 35 that are not covered with the pattern 41 </ b> A and the tantalum sidewall 41 </ b> B are completely removed by the etching. As a result, the free magnetic layer 37, the insulating layer 36, and a part of the fixed magnetic layer 35 remain as the layers 37A, 36A, and 35A of the MTJ element below the pattern 41A.

As shown in FIG. 13, a cover insulating layer 50 made of SiO ₂ is formed by CVD. The material of the insulating cover layer 50 is not limited to SiO ₂ and may be SiN, for example. Alternatively, the cover insulating layer 50 may be a laminated film in which a SiO ₂ layer and a SiN layer are laminated.

  As shown in FIG. 14, a resist pattern 51 is formed on the upper surface of the insulating cover layer 50 by exposing the photoresist layer formed on the upper surface of the insulating cover layer 50 with a desired pattern. The resist material may be an organic material including a novolak resin as a base resin and a compound as a photosensitive agent.

In FIG. 15, the cover insulating layer 50, the tantalum layer 34, the ruthenium layer 33, and the tantalum layer 32 are processed by performing reactive ion etching using the resist pattern 51 (see FIG. 14) as a mask. The etching gas may be a mixed gas of CF ₄ and Ar, for example. The resist pattern 51 is removed by ashing after etching. By this treatment, a part of the insulating cover layer 50 remains as the insulating cover layer 50A, and the tantalum layer 34, the ruthenium layer 33, and a part of the tantalum layer 32 are the metal layer 34A that is the lower electrode 20 (see FIG. 2). , 33A, and 32A remain.

As shown in FIG. 16, an interlayer film 60 made of SiO ₂ is formed so as to cover the upper surface of silicon oxide film 31 shown in FIG. 15 and the entire upper surface and all side surfaces of the structure located thereabove. . Further, the entire upper surface formed by the upper surface of the interlayer film 60, the upper surface of the pattern 41A, and the upper surface of the tantalum side wall 41B is planarized by a CMP (Chemical Mechanical Polishing) method, an RIE whole surface etch back method, or the like. In FIG. 16, for convenience of illustration, the silicon oxide film 31, the SiO ₂ cover insulating layer 50, and the newly formed SiO ₂ interlayer film are all shown as an interlayer film 60.

  As shown in FIG. 17, a resist pattern 61 is formed on the planarized surface by exposing the photoresist layer formed on the planarized surface with a desired pattern. The resist material may be an organic material including a novolak resin as a base resin and a compound as a photosensitive agent.

In FIG. 18, by performing reactive ion etching using the resist pattern 61 (see FIG. 17) as a mask, a through hole 60A extending from the upper surface of the interlayer film 60 to the metal layer 34A is formed in the interlayer film 60. The etching gas may be a mixed gas of CF ₄ and Ar, for example. The resist pattern 61 is removed by ashing after etching.

  As shown in FIG. 19, the wiring 71 is formed so as to be in contact with the upper surfaces of the pattern 41A and the tantalum sidewall 41B, and the interlayer film 60 is formed from the upper surface of the metal layer 34A corresponding to the upper surface of the lower electrode 20 (see FIG. 2). A wiring 72 reaching the upper surface is formed. The material of the wirings 71 and 72 may be Al or Cu. The wiring forming method may be a method that is usually used for forming wiring of each material.

As described above, a semiconductor element including the MTJ element as a memory cell is obtained. In the semiconductor element shown in FIG. 19, a pattern 41A of insulating material (SiO ₂ ) and a tantalum sidewall 41B are interposed between the wiring 71 and the metal layer 40A at the upper end of the upper electrode. The electrical connection between them is secured only by the tantalum side wall 41B. Since the tantalum side wall 41B has a small cross-sectional area in a direction perpendicular to the current direction, there is a problem that a resistance value between the wiring 71 and the wiring 72 increases when a current flows through the MTJ element. Moreover, although the thickness of the tantalum side wall 41B is adjusted by the time and power of ion milling, it may vary from a desired value. Such variation is not preferable because it appears as a difference in characteristics of individual memory elements. Therefore, it is conceivable to remove the pattern 41A and the tantalum side wall 41B before forming the wiring 71 and form the wiring 71 so as to be in direct contact with the metal layer 40A. Such modifications will be described below.

  FIG. 20 is a diagram showing a modification of the method for manufacturing a semiconductor element. In FIG. 20, the pattern 41A and the tantalum sidewall 41B are completely removed from the state shown in FIG. 16 by further removing the entire upper surface formed by the upper surface of the interlayer film 60, the upper surface of the pattern 41A, and the upper surface of the tantalum sidewall 41B. Has been removed. This removal process may be realized by continuing the flattening process described in FIG.

  In the processing after the state shown in FIG. 20, the same processing as described in FIGS. 17 to 19 may be executed. That is, after removing the pattern 41A with the metal material adhering to the side surfaces, through holes are formed (FIGS. 17 and 18), and the wiring layer (wiring 71) is formed on the upper surface of the metal layer 40A exposed by removing the pattern 41A. ) May be formed.

  FIG. 21 is a diagram showing the structure of a semiconductor device manufactured according to the above modification. That is, the structure of the semiconductor element generated by completely removing the pattern 41A and the tantalum sidewall 41B as described above is shown. In the semiconductor element shown in FIG. 21, the wiring 71 is formed so as to be in direct contact with the metal layer 40 </ b> A, and the above-described problem of variation in high resistance value and resistance value is solved.

  FIG. 22 is a diagram for explaining deformation of a mask when a metal material is processed by RIE using a mask having no metal side wall. FIG. 22 is a diagram for explaining the resistance of a mask when a metal material is processed by RIE using a mask having a metal side wall.

  In FIG. 22A, a metal material memory element 82 is formed on the upper surface of the metal material lower electrode 81, a metal material upper electrode 83 is formed on the upper surface of the memory element 82, and a mask is formed on the upper surface of the upper electrode 83. 84 is formed. In this state, when RIE for processing the upper electrode 83 using the mask 84 is performed, the plasma electric field concentrates on the corner portion of the mask 84, and therefore the corner portion on the periphery of the mask 84 is particularly easily cut. Therefore, the shape of the mask 84 is deteriorated during the etching process, and the side surface of the mask 84 is not vertical but inclined as shown in FIG. As a result, reflecting the deterioration of the shape of the mask 84, the shape of the upper electrode 83 becomes a deteriorated shape having a gentle side surface instead of a vertical side surface.

  In FIG. 23A, a metal side wall 84B formed of a metal material of the upper electrode 83 by ion milling of the upper electrode 83 is provided on the side surface of the mask 84. In this state, when RIE is performed using the mask 84 and the metal side wall 84B as a mask, even if the electric field of the plasma is concentrated on the corner portion of the mask, the corner portion on the peripheral edge of the mask is protected by the metal side wall 84B. Therefore, the cutting speed is slower than in the case of no protection. Therefore, the shape of the mask does not deteriorate during the etching process, and the etching proceeds while maintaining the shape in which the side surface of the metal side wall 84B provided on the side surface of the mask 84 is substantially vertical as shown in FIG. To do. As a result, reflecting the good shape of the mask, the shape of the upper electrode 83 is also processed into a good shape having a side surface close to vertical.

  In the first embodiment of the semiconductor element manufacturing method described above, a protective film made of a metal material is provided only on the side surface of the pattern 41A. In order to obtain a mask having higher etching resistance, it is conceivable to provide a layer made of a metal material on the upper surface of the pattern 41A. Such an embodiment will be described below.

  24 to 28 are diagrams showing each stage of the manufacturing process in the second embodiment of the method for manufacturing a semiconductor device. Hereinafter, a first embodiment of a method for manufacturing a semiconductor device will be described with reference to FIGS.

The manufacturing method of the semiconductor device according to the second embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment with respect to the steps shown in FIGS. As shown in FIG. 7, the process after the formation of the insulating layer 41 made of SiO ₂ on the upper surface of the tantalum layer 40 is different from the first example in the second example.

  As shown in FIG. 24, a tantalum layer 90 made of Ta is formed on the upper surface of the insulating layer 41. The tantalum layer 90 may be formed by sputtering, and the film thickness may be 30 nm, for example. In the etching performed later, the tantalum layer 90 protects the upper surface of the pattern 41A and functions as a part of the etching mask. If the tantalum layer 90 is too thick, it is difficult to pattern the tantalum layer 90 with high accuracy. Therefore, the tantalum layer 90 is preferably formed to have an appropriate thickness in consideration of the function as a protective film and the ease of processing.

  As shown in FIG. 25, the photoresist pattern formed on the top surface of the tantalum layer 90 is exposed in a desired pattern, thereby forming a resist pattern 42 on the top surface of the tantalum layer 90. The resist material may be an organic material including a novolak resin as a base resin and a compound as a photosensitive agent.

In FIG. 26, the tantalum layer 90 and the insulating layer 41 are processed by performing reactive ion etching using the resist pattern 42 (see FIG. 8) as a mask, and a pattern 90A formed of Ta and SiO ₂ are formed. Pattern 41A is formed. Thus, the metal layer (tantalum layer 90) and the insulating layer 41 are etched to form a pattern in which the metal layer is provided on the upper surface. The etching gas may be a mixed gas of CF ₄ and Ar, for example. The resist pattern 42 is removed by ashing after etching. The patterns 90A and 41A thus formed function as a mask in ion milling and RIE that are subsequently performed.

  As shown in FIG. 27, the metal layer (tantalum layer 40) is etched by performing ion milling (physical etching) using the patterns 90A and 41A as a mask, and the metal material (Ta) is removed from the patterns 90A and 41A. Adhere to the side. The inert gas material used for ion milling may be Ar.

  Thereby, the tantalum side wall 41B is formed as a Ta thin film on the side surfaces of the patterns 90A and 41A. The amount of Ta adhering as the tantalum side wall 41B can be controlled by ion milling time (length of time for performing ion milling) and ion milling power (power applied to the electrode during ion milling). At the time of manufacturing the semiconductor element, the time and power are adjusted so that the tantalum side wall 41B having a desired thickness is formed by referring to the relationship between the thickness of the tantalum side wall 41B measured in advance and the time and power. If the thickness of the tantalum sidewall 41B is about 5 nm, the pattern 41A and the tantalum sidewall 41B can function as an appropriate mask in the subsequent RIE.

As shown in FIG. 28, a reactive ion etching is performed using the patterns 90A and 41A (see FIG. 27) provided with a metal material (Ta) on the upper surface and attached to the side surface as a mask, thereby forming a metal layer (tantalum). Layer 40) is processed. In FIG. 28, the portion of the tantalum layer 40 that is not covered with the pattern 41A and the tantalum side wall 41B and the Ta pattern 90A that protects the upper surface of the pattern 41A are completely removed by etching. As a result, only a part of the tantalum layer 40 remains as a Ta metal layer 40A under the pattern 41A. The etching gas at this time may be, for example, a mixed gas of CF ₄ and Ar, or may be only CF ₄ . At this time, since the Ta pattern 90A is provided on the upper surface of the pattern 41A and the tantalum side wall 41B is provided on the side surface, the shape of the etching mask is prevented from being deformed and the consumption rate of the mask is significantly suppressed. Can do. Therefore, a mask having a sufficient thickness and a good shape can be used in the subsequent etching process.

  The state shown in FIG. 28 is the same as the state shown in FIG. 11 except for the thickness (height) of the pattern 41A and the tantalum side wall 41B. The steps after the state shown in FIG. 11 of the semiconductor device manufacturing method according to the second embodiment are the same as those of the first embodiment and its modification shown in FIGS. As described above, a semiconductor element including the MTJ element as a memory cell is obtained.

  The above embodiment has been described by taking as an example a method of manufacturing an MRAM semiconductor element including an MTJ element as a memory cell. As described above, an element to be processed and manufactured is not limited to an MTJ element. For example, the ferroelectric memory device may be processed and manufactured by using the semiconductor device manufacturing method of the present application.

  In the case of a ferroelectric memory, the memory element layer (ferroelectric layer) is made of a ferroelectric material such as lead zirconium titanate (PZT). A lower electrode made of Pt (platinum), Ti (titanium), IrOx (iridium oxide), or the like is formed on the lower surface side of the memory element layer. An upper electrode made of Pt or IrOx or the like is formed on the upper surface side of the memory element layer. For example, in FIG. 23, the lower electrode 81, the memory element 82, and the upper electrode 83 may be formed of each material as described above and provided as a ferroelectric memory cell.

When these upper electrode, ferroelectric layer, and lower electrode are subjected to RIE processing, a mixed gas of Cl ₂ and Ar is generally used. Pr and iridium are precious metals and are difficult to process by RIE. Therefore, the mask is heavily consumed during the etching process, and the shape of the mask deteriorates due to the etching as described above with reference to FIG. The shape of the metal layer to be processed also deteriorates. Therefore, as described with reference to FIG. 23, if the metal sidewall 84B formed of the metal material of the upper electrode 83 is provided on the side surface of the mask 84 by ion milling of the upper electrode 83, the mask shape can be obtained even in the case of a ferroelectric memory. And deterioration of the shape of the metal layer to be processed can be avoided.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

11 free magnetic layer 12 tunnel insulating film 13 fixed magnetic layer 20 lower electrode 21 upper electrode 22 interlayer film 23 cover insulating layer 24 wiring 25 wiring 30 silicon substrate 31 silicon oxide film 32 tantalum layer 33 ruthenium layer 34 tantalum layer 35 fixed magnetic layer 36 Insulating layer 37 Free magnetic layer 38 Tantalum layer 39 Ruthenium layer 40 Tantalum layer

Claims (6)

Forming a pattern formed of an insulating material on an upper surface of a metal layer formed of a metal material;
Etching the metal layer by ion milling using the pattern as a mask and attaching the metal material to the side of the pattern;
A method of manufacturing a semiconductor device, comprising: steps of processing the metal layer by performing reactive ion etching using the pattern in which the metal material adheres to a side surface as a mask.   The method further comprises performing reactive ion etching on a memory element layer existing under the metal layer using the pattern in which the metal material is attached to a side surface and the metal layer remaining under the pattern as a mask. A method for producing a semiconductor device according to 1. Forming the pattern comprises:
Forming an insulating layer formed of the insulating material on the metal layer;
Forming a second metal layer on the insulating layer;
3. The method of manufacturing a semiconductor device according to claim 1, comprising etching each of the second metal layer and the insulating layer to form the pattern having the second metal layer provided on an upper surface thereof. . After processing the memory element layer, the metal material is removed from the side surface of the pattern,
3. The method of manufacturing a semiconductor device according to claim 2, further comprising: forming a wiring layer on the upper surface of the metal layer exposed by removing the pattern.   The method of manufacturing a semiconductor element according to claim 2, wherein the memory element layer includes a layer formed of a magnetic material.   3. The method of manufacturing a semiconductor element according to claim 2, wherein the memory element layer is formed of a ferroelectric material.

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