JP2018019076A - Printed circuit board - Google Patents
Printed circuit board Download PDFInfo
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- JP2018019076A JP2018019076A JP2017131560A JP2017131560A JP2018019076A JP 2018019076 A JP2018019076 A JP 2018019076A JP 2017131560 A JP2017131560 A JP 2017131560A JP 2017131560 A JP2017131560 A JP 2017131560A JP 2018019076 A JP2018019076 A JP 2018019076A
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- Japan
- Prior art keywords
- circuit board
- printed circuit
- barrier layer
- layer
- circuit pattern
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- 230000004888 barrier function Effects 0.000 claims abstract description 47
- 239000010410 layer Substances 0.000 claims description 85
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 239000011651 chromium Substances 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000012212 insulator Substances 0.000 abstract 4
- 238000000034 method Methods 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 239000011889 copper foil Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000000654 additive Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 101001134276 Homo sapiens S-methyl-5'-thioadenosine phosphorylase Proteins 0.000 description 1
- 102100022050 Protein canopy homolog 2 Human genes 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/101—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by casting or moulding of conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本発明は、プリント回路基板に関する。 The present invention relates to a printed circuit board.
電子産業の発達に伴って電子部品の高機能化、軽薄短小化への要求が急増しており、これにより、電子部品が搭載されるプリント回路基板においても高密度配線化及び薄板化が求められている。 With the development of the electronics industry, the demand for higher functionality, lighter, thinner, and smaller electronic components has increased rapidly, and this has required printed circuit boards on which electronic components are mounted to have higher density wiring and thinner plates. ing.
一方、プリント回路基板の薄型化のために、コア基板が除去されたコアレス回路基板が用いられている。コアレス回路基板を製造するためには、キャリアが必要となり、このキャリアは、コア基板の代わりに回路パターン等を形成するための支持部材として用いられる。
キャリアは、一面に回路パターンを形成することができ、以後絶縁層等を積層してビルドアップ層を形成した後に除去すれば、絶縁層から一面が露出した回路パターンを形成することができる。
On the other hand, in order to reduce the thickness of the printed circuit board, a coreless circuit board from which the core board is removed is used. In order to manufacture a coreless circuit board, a carrier is required, and this carrier is used as a support member for forming a circuit pattern or the like instead of the core board.
The carrier can form a circuit pattern on one side, and after that, if a buildup layer is formed by laminating an insulating layer or the like and then removed, a circuit pattern with one side exposed from the insulating layer can be formed.
上記のようにすると、銅箔積層板を用いて回路パターンを形成する場合よりも微細な回路パターンを形成することができる。 If it carries out as mentioned above, a finer circuit pattern can be formed than the case where a circuit pattern is formed using a copper foil laminated board.
本発明の一側面によれば、銅箔エッチング液から回路パターンを保護するために回路パターン上にバリアー層を形成した回路基板が提供される。 According to one aspect of the present invention, a circuit board having a barrier layer formed on a circuit pattern to protect the circuit pattern from a copper foil etchant is provided.
本明細書で使用した用語は、ただ特定の実施例を説明するために使用したものであり、本発明を限定するものではない。単数の表現は、文脈上明白に異なる意味ではない限り、複数の表現を含む。
本願において、ある部分がある構成要素を「含む」とする場合、これは特に言及しない限り、他の構成要素を除外することではなく、他の構成要素をさらに含むことができることを意味する。
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context.
In this application, when a part includes a component, it means that it does not exclude other components and can further include other components unless otherwise specified.
また、明細書の全般において、「上に」とは、対象部分の上または下に位置することを意味し、必ずしも重力方向を基準にして上側に位置することを意味するものではない。
また、「結合」とは、各構成要素の間の接触関係において、各構成要素の間に物理的に直接接触する場合のみを意味するものではなく、他の構成が各構成要素の間に介在され、その他の構成に構成要素がそれぞれ接触している場合まで包括する概念として使用する。
In addition, in the whole specification, “on” means that it is located above or below the target portion, and does not necessarily mean that it is located above the gravity direction.
In addition, the term “coupled” does not mean that in the contact relationship between the components, the components are physically directly in contact with each other, and other configurations are interposed between the components. It is used as a concept encompassing even when the components are in contact with other components.
本明細書において、第１、第２等の用語は、多様な構成要素を説明するために使用され、上記構成要素が上記用語により限定されることはない。上記用語は、一つの構成要素を他の構成要素から区別する目的にだけに使用される。 In this specification, terms such as “first” and “second” are used to describe various components, and the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.
図面に示された各構成の大きさ及び厚さは、説明の便宜上、任意で示したものであって、本発明が必ずしもそれらに限定されることはない。
以下では、本発明に係るプリント回路基板及びその製造方法の実施例を添付図面に基づいて詳細に説明し、添付図面に基づいて説明するに当たって、同一または対応する構成要素には同一の図面符号を付し、これに対する重複説明を省略する。
The size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited thereto.
Hereinafter, embodiments of a printed circuit board and a method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be denoted by the same reference numerals in the description with reference to the accompanying drawings. A duplicate description is omitted.
＜プリント回路基板＞
図１は、本発明の第１実施例に係るプリント回路基板１００を概略的に示す断面図である。
図１を参照すると、第１実施例に係るプリント回路基板１００は、絶縁層１０と、回路パターン２０と、バリアー層３０とを含む。
<Printed circuit board>
FIG. 1 is a cross-sectional view schematically showing a printed circuit board 100 according to a first embodiment of the present invention.
Referring to FIG. 1, the printed circuit board 100 according to the first embodiment includes an insulating layer 10, a circuit pattern 20, and a barrier layer 30.
絶縁層１０としては、プリプレグ（ＰＰＧ）、ＡＢＦ（Ａｊｉｎｏｍｏｔｏ ｂｕｉｌｄ−ｕｐ ｆｉｌｍ）、銅箔コーティング樹脂（ＲＣＣ）、液晶ポリマー（ＬＣＰ）、テフロン（登録商標）等の公知の材料を用いることができる。 As the insulating layer 10, known materials such as prepreg (PPG), ABF (Ajinomoto build-up film), copper foil coating resin (RCC), liquid crystal polymer (LCP), and Teflon (registered trademark) can be used.
回路パターン２０は、絶縁層１０の内部に形成され、一面が絶縁層１０の一面に露出するように形成されることができる。 The circuit pattern 20 may be formed inside the insulating layer 10 so that one surface is exposed on one surface of the insulating layer 10.
回路パターン２０は、本発明の一実施例のように、微細な回路パターンを形成するために、アディティブ法（ａｄｄｉｔｉｖｅ ｐｒｏｃｅｓｓ）、セミアディティブ法（ＳＡＰ、ｓｅｍｉ ａｄｄｉｔｉｖｅ ｐｒｏｃｅｓｓ）、モディファイド・セミ・アディティブ法（ＭＳＡＰ、ｍｏｄｉｆｉｅｄ ｓｅｍｉ ａｄｄｉｔｉｖｅ ｐｒｏｃｅｓｓ）を用いて形成することができ、テンティング法（ｔｅｎｔｉｎｇ ｐｒｏｃｅｓｓ）のようなサブトラックティブ法（Ｓｕｂｔｒａｃｔｉｖｅ Ｐｒｏｃｅｓｓ）を除外することではない。 The circuit pattern 20 includes an additive process, a semi-additive process (SAP), and a modified semi-additive process (in order to form a fine circuit pattern, as in the embodiment of the present invention. It can be formed using MSAP, modified semi-additive process, and does not exclude subtractive processes such as the tenting process.
回路パターン２０は、デタッチコア基板を使用して、デタッチコア基板が除去された絶縁層の一面から露出するエンベデッド回路パターン（ｅｍｂｅｄｄｅｄ ｃｉｒｃｕｉｔ ｐａｔｔｅｒｎ）であることができる。 The circuit pattern 20 may be an embedded circuit pattern that is exposed from one surface of the insulating layer from which the detached core substrate is removed using the detached core substrate.
エンベデッド回路パターン（以下、回路パターンと称し、本発明において回路パターンとは、その形成方法に応じて異なって形成される回路パターンのすべてを包括する意味である）は、デタッチコア基板の一部の構成である銅箔層が除去される工程において、エッチング液により過エッチングされる問題が発生することがある。
したがって、エッチング後に絶縁層１０の一面から露出する回路パターン２０の一面が、絶縁層の一面と実質的に同一の平面上に形成されることが好ましいが、過エッチングにより、絶縁層１０の一面よりも内側に形成されるリセス（ｒｅｃｅｓｓ）現象が発生する。
An embedded circuit pattern (hereinafter referred to as a circuit pattern, and in the present invention, the circuit pattern means that all circuit patterns formed differently depending on the forming method) is a partial configuration of the detached core substrate. In the process of removing the copper foil layer, there may be a problem of overetching with an etching solution.
Therefore, it is preferable that one surface of the circuit pattern 20 exposed from one surface of the insulating layer 10 after the etching is formed on substantially the same plane as the one surface of the insulating layer. In addition, a recess phenomenon is formed inside.
バリアー層３０は、絶縁層１０の内部に形成され、絶縁層１０に一面が露出するように形成されることができる。
本発明の一実施例に係るバリアー層３０は、回路パターン２０が銅箔エッチング液により過エッチングされることを防止するために回路パターン２０上に形成されることができる。
The barrier layer 30 is formed inside the insulating layer 10 and may be formed so that one surface is exposed to the insulating layer 10.
The barrier layer 30 according to an embodiment of the present invention may be formed on the circuit pattern 20 to prevent the circuit pattern 20 from being over-etched with a copper foil etchant.
バリアー層３０は、ニッケル（Ｎｉ）、クロム（Ｃｒ）、亜鉛（Ｚｎ）、チタン（Ｔｉ）、モリブデン（Ｍｏ）、金（Ａｕ）及び銀（Ａｇ）のうちの少なくともいずれか１種を含むか、またこれらの２種以上の合金により形成することができる。 Does the barrier layer 30 include at least one of nickel (Ni), chromium (Cr), zinc (Zn), titanium (Ti), molybdenum (Mo), gold (Au), and silver (Ag)? Further, it can be formed of two or more of these alloys.
バリアー層３０は、銅箔とは異なる材料で形成されることにより、銅箔エッチング液に反応しないことになる。
バリアー層３０は、銅箔エッチング液でエッチングされないため、バリアー層３０の下部に形成された回路パターン２０を銅箔エッチング液から保護することができる。
Since the barrier layer 30 is formed of a material different from the copper foil, the barrier layer 30 does not react with the copper foil etching solution.
Since the barrier layer 30 is not etched with the copper foil etchant, the circuit pattern 20 formed under the barrier layer 30 can be protected from the copper foil etchant.
バリアー層３０は、回路パターン２０を形成する前にデタッチコア基板に形成されることで、デタッチコア基板が除去された後にはバリアー層３０の一面が上記絶縁層１０の一面と実質的に同一の平面に形成されることができる。
バリアー層３０の厚さは、１ｎｍ乃至１００ｎｍ範囲で形成されることができるが、その範囲が制限されることはない。
The barrier layer 30 is formed on the detached core substrate before the circuit pattern 20 is formed, so that one surface of the barrier layer 30 is substantially flush with the one surface of the insulating layer 10 after the detached core substrate is removed. Can be formed.
The barrier layer 30 may have a thickness in the range of 1 nm to 100 nm, but the range is not limited.
本発明の第１実施例に係るプリント回路基板１００は、絶縁層１０の内部に形成され、回路パターン２０に電気的に接続するビア５をさらに含むことができる。説明の便宜上、１層構造のプリント回路基板のみを示したが、複数のビルドアップ層の構造を制限することはない。 The printed circuit board 100 according to the first embodiment of the present invention may further include a via 5 formed in the insulating layer 10 and electrically connected to the circuit pattern 20. For convenience of explanation, only a printed circuit board having a single layer structure is shown, but the structure of a plurality of buildup layers is not limited.
図２は、本発明の第２実施例に係るプリント回路基板２００を概略的に示す断面図である。
図２を参照すると、第２実施例に係るプリント回路基板２００は、バリアー層３０と回路パターン２０との間に形成されるシード層４０をさらに含むことができる。
シード層４０は、回路パターン２０とバリアー層３０との間の密着力を高めることができる。
FIG. 2 is a cross-sectional view schematically showing a printed circuit board 200 according to the second embodiment of the present invention.
Referring to FIG. 2, the printed circuit board 200 according to the second embodiment may further include a seed layer 40 formed between the barrier layer 30 and the circuit pattern 20.
The seed layer 40 can increase the adhesion between the circuit pattern 20 and the barrier layer 30.
図３は、本発明の第３実施例に係るプリント回路基板３００を概略的に示す断面図である。
図３を参照すると、第３実施例に係るプリント回路基板３００においては、バリアー層３０がすべて除去されたことを確認することができる。
FIG. 3 is a cross-sectional view schematically illustrating a printed circuit board 300 according to a third embodiment of the present invention.
Referring to FIG. 3, in the printed circuit board 300 according to the third embodiment, it can be confirmed that the barrier layer 30 is completely removed.
図４は、本発明の第４実施例に係るプリント回路基板４００を概略的に示す断面図である。
図４を参照すると、回路パターン２０及びバリアー層３０は、複数形成することができ、上記複数の回路パターン２０上に形成される複数のバリアー層のうちの一部は除去されることができる。
なお、プリント回路基板は、電子素子が積層されるパッケージ基板であることができ、パッケージ基板には、電子素子との電気的な接続のためにバンプを形成することができる。
バンプに接続される回路パターン２０は、バンプ間の短絡をより効果的に防止するために、バリアー層３０が除去されたリセス構造を形成することができる。
FIG. 4 is a cross-sectional view schematically showing a printed circuit board 400 according to the fourth embodiment of the present invention.
Referring to FIG. 4, a plurality of circuit patterns 20 and barrier layers 30 may be formed, and some of the plurality of barrier layers formed on the plurality of circuit patterns 20 may be removed.
Note that the printed circuit board may be a package board on which electronic elements are stacked, and bumps may be formed on the package board for electrical connection with the electronic elements.
The circuit pattern 20 connected to the bump can form a recess structure in which the barrier layer 30 is removed in order to more effectively prevent a short circuit between the bumps.
図５は、本発明の第５実施例に係るプリント回路基板５００を概略的に示す断面図であり、図６は、本発明の第６実施例に係るプリント回路基板６００を概略的に示す断面図であり、図７は、本発明の第７実施例に係るプリント回路基板７００を概略的に示す断面図であり、図８は、本発明の第８実施例に係るプリント回路基板８００を概略的に示す断面図である。 FIG. 5 is a cross-sectional view schematically illustrating a printed circuit board 500 according to a fifth embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a printed circuit board 600 according to the sixth embodiment of the present invention. FIG. 7 is a cross-sectional view schematically illustrating a printed circuit board 700 according to the seventh embodiment of the present invention. FIG. 8 schematically illustrates a printed circuit board 800 according to the eighth embodiment of the present invention. FIG.
図５から図８を参照すると、本発明の実施例に係るプリント回路基板５００、６００、７００、８００は、第１から第４実施例に係るプリント回路基板に保護層６０をさらに含む。 5 to 8, the printed circuit boards 500, 600, 700 and 800 according to the embodiments of the present invention further include a protective layer 60 on the printed circuit boards according to the first to fourth embodiments.
保護層６０は、絶縁層１０上に形成され、バリアー層３０の一部が露出するように開口部３５を含むことができる。 The protective layer 60 is formed on the insulating layer 10 and may include an opening 35 so that a part of the barrier layer 30 is exposed.
開口部３５には、図８に示すように、バンプ等の接続部１５が形成されることができる。また、接続部１５上に電子素子２５を搭載することができる。 As shown in FIG. 8, connection portions 15 such as bumps can be formed in the openings 35. In addition, the electronic element 25 can be mounted on the connection portion 15.
一方、接続部１５が形成される回路パターン２０上には、バリアー層３０が除去されることによりリセス構造を形成することができる。
リセス構造は、接続部１５を収容できる空間を広げ、側面接続部１５と接触することを防止することができる。
On the other hand, a recess structure can be formed on the circuit pattern 20 on which the connection portion 15 is formed by removing the barrier layer 30.
The recess structure can expand a space in which the connection portion 15 can be accommodated and prevent contact with the side connection portion 15.
以下では、回路パターン上にバリアー層が形成されたプリント回路基板の製造工程を図面を参照して説明する。 Hereinafter, a manufacturing process of a printed circuit board in which a barrier layer is formed on a circuit pattern will be described with reference to the drawings.
＜プリント回路基板の製造工程＞
図９ａから図９ｆは、本発明の一実施例に係るプリント回路基板の製造工程を概略的に示す断面図である。
以下では、図９ａから図９ｆを参照して、本発明の一実施例に係るプリント回路基板の製造工程を説明する。
<Manufacturing process of printed circuit board>
9a to 9f are cross-sectional views schematically illustrating a manufacturing process of a printed circuit board according to an embodiment of the present invention.
Hereinafter, a manufacturing process of a printed circuit board according to an embodiment of the present invention will be described with reference to FIGS. 9A to 9F.
図９ａを参照すると、本発明の一実施例に係るプリント回路基板の製造工程は、デタッチコア基板５０を準備するステップを含むことができる。
デタッチコア基板５０には、コア金属層５１の両面に離型金属層５３、５５を積層することができる。
離型金属層５３と離型金属層５５が分離されることによりコア金属層５１を除去でき、回路パターンが形成された離型金属層５５をエッチングにより除去することにより、回路パターンの形成後にデタッチコア基板５０が除去されることができる。
Referring to FIG. 9 a, a printed circuit board manufacturing process according to an embodiment of the present invention may include preparing a detached core board 50.
In the detached core substrate 50, release metal layers 53 and 55 can be laminated on both surfaces of the core metal layer 51.
The core metal layer 51 can be removed by separating the release metal layer 53 and the release metal layer 55, and the detached metal layer 55 on which the circuit pattern is formed is removed by etching, so that the detached core is formed after the circuit pattern is formed. The substrate 50 can be removed.
図９ｂを参照すると、本発明の一実施例に係るプリント回路基板の製造工程は、回路パターン２０を形成するために、デタッチコア基板５０上に感光性フィルム７０を積層するステップを含むことができる。
感光性フィルム７０は、露光、現像工程を経て回路パターンが形成される部分を除去することができる。感光性フィルム７０を用いて露光、現像する工程は、公知の技術を用いることができる。
Referring to FIG. 9 b, the printed circuit board manufacturing process according to an embodiment of the present invention may include a step of laminating a photosensitive film 70 on the detached core substrate 50 to form the circuit pattern 20.
The photosensitive film 70 can remove a portion where a circuit pattern is formed through an exposure and development process. A known technique can be used for the process of exposing and developing using the photosensitive film 70.
感光性フィルム７０の除去された部分には、バリアー層３０を形成することができる。
バリアー層３０は、スパッタ（ｓｐｕｔｔｅｒ）工程等のメッキ工程を用いて形成することができる。
バリアー層３０の厚さは、１ｎｍ〜１００ｎｍ範囲で形成することができ、この厚さに制限されることはない。
A barrier layer 30 can be formed on the removed portion of the photosensitive film 70.
The barrier layer 30 can be formed using a plating process such as a sputtering process.
The thickness of the barrier layer 30 can be formed in the range of 1 nm to 100 nm, and is not limited to this thickness.
図９ｃを参照すると、本発明の一実施例に係るプリント回路基板の製造工程は、バリアー層３０上にシード層４０を形成するステップを含むことができる。
シード層４０は、回路パターン２０とバリアー層３０との間の密着力を高めるために形成される層であって、無電解銅メッキ又は電解銅メッキ工程により形成されることができる。
Referring to FIG. 9 c, a printed circuit board manufacturing process according to an embodiment of the present invention may include forming a seed layer 40 on the barrier layer 30.
The seed layer 40 is a layer formed to increase the adhesion between the circuit pattern 20 and the barrier layer 30 and may be formed by an electroless copper plating process or an electrolytic copper plating process.
図９ｄを参照すると、本発明の一実施例に係るプリント回路基板の製造工程は、シード層４０上に回路パターン２０を形成するステップを含むことができる。
回路パターン２０は、セミアディティブ法により形成することができ、その形成方法は制限されない。
Referring to FIG. 9 d, the manufacturing process of the printed circuit board according to the embodiment of the present invention may include forming a circuit pattern 20 on the seed layer 40.
The circuit pattern 20 can be formed by a semi-additive method, and the formation method is not limited.
図９ｅを参照すると、本発明の一実施例に係るプリント回路基板の製造工程は、感光性フィルム７０を除去するステップを含むことができる。
図９ｆを参照すると、本発明の一実施例に係るプリント回路基板の製造工程は、デタッチコア基板５０を除去するステップを含むことができる。
図９ｅを参照すると、本発明の一実施例に係るプリント回路基板の製造工程は、複数のバリアー層３０のうちの一部のバリアー層３０を除去するステップをさらに含むことができる。
Referring to FIG. 9E, the manufacturing process of the printed circuit board according to the embodiment of the present invention may include removing the photosensitive film 70.
Referring to FIG. 9f, the manufacturing process of the printed circuit board according to an embodiment of the present invention may include removing the detached core board 50.
Referring to FIG. 9 e, the printed circuit board manufacturing process according to an embodiment of the present invention may further include removing a part of the barrier layers 30 from the plurality of barrier layers 30.
複数のバリアー層３０のうちの一部のバリアー層３０を除去するステップにおいて、一部のバリアー層３０は、リセス・デプス（ｒｅｃｅｓｓ ｄｅｐｔｈ）を必要とする部分であって、一部のバリアー層３０を選択的にエッチングするか、ＣＺ及びＯＳＰ ｓｏｆｔ ｅｔｃｈｉｎｇによりリセス構造を形成することができる。
一部のバリアー層３０を除去するステップにおいて、選択的にバリアー層をエッチングすることにより、バリアー層または回路パターンがエッチングされることを最小化することができる。
In the step of removing a part of the plurality of barrier layers 30, the part of the barrier layers 30 is a part requiring a recess depth, and part of the barrier layers 30. Can be selectively etched, or a recess structure can be formed by CZ and OSP soft etching.
In the step of removing a part of the barrier layer 30, it is possible to minimize etching of the barrier layer or the circuit pattern by selectively etching the barrier layer.
本発明の一実施例に係るプリント回路基板は、絶縁層の一面に露出する回路パターン上にバリアー層を形成して、デタッチコア基板に形成された銅箔層を除去するためのエッチング液から回路パターンを保護することができる。
また、本発明の一実施例に係るプリント回路基板は、選択的にバリアー層を除去することにより、回路パターン上に形成されるバンプ等の構造物が短絡することを防止することができる。
A printed circuit board according to an embodiment of the present invention forms a circuit pattern from an etchant for forming a barrier layer on a circuit pattern exposed on one surface of an insulating layer and removing a copper foil layer formed on a detached core board. Can be protected.
In addition, the printed circuit board according to an embodiment of the present invention can prevent a structure such as a bump formed on the circuit pattern from being short-circuited by selectively removing the barrier layer.
以上、本発明の一実施例について説明したが、当該技術分野で通常の知識を有する者であれば特許請求の範囲に記載の本発明の思想から逸脱しない範囲内で、構成要素の付加、変更、削除または追加等で本発明を多様に修正及び変更することができ、これも本発明の権利範囲内に含まれるものといえよう。 Although one embodiment of the present invention has been described above, addition and modification of constituent elements are within the scope not departing from the spirit of the present invention as set forth in the appended claims, as long as the person has ordinary knowledge in the technical field. The present invention can be variously modified and changed by deletion, addition, etc., and it can be said that this is also included in the scope of the present invention.
１０ 絶縁層
２０ 回路パターン
３０ バリアー層
４０ シード層
１００、２００、３００、４００、５００、６００、７００、８００ プリント回路基板
DESCRIPTION OF SYMBOLS 10 Insulating layer 20 Circuit pattern 30 Barrier layer 40 Seed layer 100, 200, 300, 400, 500, 600, 700, 800 Printed circuit board
Claims (8)
前記絶縁層の内部に形成され、前記絶縁層に一面が露出するバリアー層と、
前記絶縁層の内部に形成され、前記バリアー層の他面に形成される回路パターンと、
を含むプリント回路基板。 An insulating layer;
A barrier layer formed inside the insulating layer and having one surface exposed to the insulating layer;
A circuit pattern formed inside the insulating layer and formed on the other surface of the barrier layer;
Including printed circuit board.
複数の前記回路パターン上に形成される複数の前記バリアー層のうちの一部のバリアー層が除去された請求項１または請求項２に記載のプリント回路基板。 A plurality of the barrier layers or the circuit patterns are formed,
The printed circuit board according to claim 1, wherein a part of the plurality of barrier layers formed on the plurality of circuit patterns is removed.
ニッケル（Ｎｉ）、クロム（Ｃｒ）、亜鉛（Ｚｎ）、チタン（Ｔｉ）、モリブデン（Ｍｏ）、金（Ａｕ）及び銀（Ａｇ）のうちの少なくともいずれか１種を含むか、これらの ２種以上の合金により形成される請求項１から請求項３の何れか一項に記載のプリント回路基板。 The barrier layer is
Contains at least one of nickel (Ni), chromium (Cr), zinc (Zn), titanium (Ti), molybdenum (Mo), gold (Au) and silver (Ag), or two of these The printed circuit board as described in any one of Claims 1-3 formed with the above alloy.
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| KR20220067356A (en) * | 2020-11-17 | 2022-05-24 | 주식회사 엔피테크놀로지 | Manufacturing method of flexible printed circuit board |
| KR20220067355A (en) * | 2020-11-17 | 2022-05-24 | 주식회사 엔피테크놀로지 | Manufacturing method of double side type flexible printed circuit board |
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| KR20220098528A (en) | 2021-01-04 | 2022-07-12 | 삼성전기주식회사 | Printed circuit board |
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