JP2018019070A - Electronic component built-in substrate - Google Patents

Abstract

An object of the present invention is to provide an electronic component built-in substrate capable of suppressing the influence of an external force on the electronic component. An electronic component-embedded substrate (1) includes a substrate (10) having a wiring layer (11) and an insulating layer (12) laminated on the wiring layer (11); An electronic component 20 having a second electrode layer 21B) and a dielectric layer 22 provided between a pair of electrode layers, and a stress relaxation layer 30 provided on the wiring layer 11 side with respect to the insulating layer 12 in the stacking direction At least a part of the end of the electronic component 20 on the wiring layer 11 side is in contact with the stress relaxation layer 30 in the stacking direction, and the end of the electronic component 20 on the insulating layer 12 side in the stacking direction At least a portion thereof is in contact with the insulating layer 12, and the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the electrode layer (second electrode layer 21B) located on the wiring layer 11 side. [Selection drawing] Fig. 1

Description

  The present invention relates to an electronic component built-in substrate.

  Along with the downsizing of electronic components, the electronic components used for the electronic component built-in substrate are also required to be downsized including a reduction in height. For example, Patent Document 1 and Patent Document 2 describe a thin film capacitor having a small total thickness and suitable for embedding in an electronic component built-in substrate.

JP 2008-34417 A JP 2008-34418 A

  However, in the case of a capacitor with a reduced height as described above, when an external force generated when the electronic component built-in substrate is handled is applied to the capacitor, the dielectric layer of the capacitor may be deformed.

  The present invention has been made in view of the above, and an object of the present invention is to provide an electronic component built-in substrate capable of suppressing the electronic component from being affected by external force.

  In order to achieve the above object, an electronic component built-in substrate according to one embodiment of the present invention includes a wiring layer and a substrate having an insulating layer laminated with respect to the wiring layer, and the substrate embedded in the substrate in the stacking direction. An electronic component having a pair of electrode layers extending in a crossing direction and a dielectric layer provided between the pair of electrode layers, and a stress relaxation layer provided on the wiring layer side with respect to the insulating layer in the stacking direction In the stacking direction, at least part of the end of the electronic component on the wiring layer side is in contact with the stress relaxation layer, and in the stacking direction, at least part of the end of the electronic component on the insulating layer side is insulated. The Young's modulus of the stress relaxation layer that is in contact with the layer is lower than the Young's modulus of the electrode layer located on the wiring layer side.

  In the electronic component built-in substrate, at least a part of the end portion on the wiring layer side of the electronic component is in contact with the stress relaxation layer. Since the Young's modulus of this stress relaxation layer is lower than the Young's modulus of the electrode layer located on the wiring layer side, the external force applied to the electronic component is relaxed by the stress relaxation layer. Therefore, it is possible to suppress the electronic component from being affected by an external force.

  In one embodiment, the stress relaxation layer includes a first stress relaxation layer having insulation and a second stress relaxation layer having conductivity, and the second stress relaxation layer is an electrode layer positioned on the wiring layer side. On the other hand, it may be provided on the wiring layer side. In this case, the first stress relaxation layer is disposed at a location where insulation is required, such as between the electrode layer located on the wiring layer side and the wiring layer, and the wiring layer side with respect to the electrode layer located on the wiring layer side The second stress relaxation layer can be arranged at a location where conductivity is required. Thereby, since the contact area of a stress relaxation layer and an electronic component can be enlarged, the external force added to an electronic component is further relieved. Therefore, it is possible to further suppress the electronic component from being affected by the external force.

  An electronic component built-in substrate according to one embodiment of the present invention includes a wiring layer and a substrate having an insulating layer laminated with respect to the wiring layer, and a pair of components that are built in the substrate and extend in a direction intersecting with the lamination direction of the substrates. An electronic component having a dielectric layer provided between the electrode layer and the pair of electrode layers, and an insulating stress relaxation layer provided on the wiring layer side with respect to the insulating layer in the stacking direction; In the stacking direction, at least part of the end of the electronic component on the wiring layer side is in contact with the stress relaxation layer, and in the stacking direction, at least part of the end of the electronic component on the insulating layer side is in contact with the insulating layer. The Young's modulus of the stress relaxation layer is lower than the Young's modulus of the electrode layer located on the wiring layer side.

  In the electronic component built-in substrate, at least a part of one end portion in the stacking direction of the electronic components located on the wiring layer side is in contact with the stress relaxation layer. Since the Young's modulus of this stress relaxation layer is lower than the Young's modulus of the electrode layer located on the wiring layer side, the external force applied to the electronic component is relaxed by the stress relaxation layer. Therefore, it is possible to suppress the electronic component from being affected by an external force. In addition, since the stress relaxation layer has an insulating property, even if the electronic component is deformed by an external force, the stress relaxation layer insulates the electrode layer located on the wiring layer side from other components. Can keep.

  An electronic component built-in substrate according to one embodiment of the present invention includes a wiring layer and a substrate having an insulating layer laminated with respect to the wiring layer, and a pair of components that are built in the substrate and extend in a direction intersecting with the lamination direction of the substrates. An electronic component having a dielectric layer provided between the electrode layer and the pair of electrode layers, and a conductive stress relaxation layer provided on the wiring layer side with respect to the electrode layer located on the wiring layer side, The Young's modulus of the stress relaxation layer is lower than the Young's modulus of the electrode layer located on the wiring layer side.

  In the electronic component built-in substrate, the stress gap layer is provided on the wiring layer side of the electrode layer located on the wiring layer side. Since the Young's modulus of the stress gap layer is lower than the Young's modulus of the electrode layer, the external force applied to the electronic component is relaxed by the stress gap layer. Therefore, deformation of the dielectric layer of the electronic component due to external force can be suppressed. Further, since the stress gap layer has conductivity, it is possible to suppress the electronic component from being affected by external force while maintaining electrical connection with the electrode layer.

  In one form, at least a part of the electronic component may be embedded in the wiring layer, and the stress relaxation layer may be exposed from the wiring layer side of the electronic component built-in substrate. According to this configuration, since at least a part of the electronic component is embedded in the wiring layer, the dimension in the stacking direction of the electronic component built-in substrate can be reduced.

  In one form, a stress relaxation layer and an electronic component may be laminated | stacked in order with respect to a wiring layer, and the stress relaxation layer may be in contact with the wiring layer. According to this configuration, by forming the stress relaxation layer between the electronic component and the wiring layer, it is possible to suppress the electronic component from being particularly affected by the external force from the stacking direction of the electronic component and the stress relaxation layer. Can do. When the stress relaxation layer has conductivity, the electrode layer and the wiring layer can be electrically connected via the stress relaxation layer.

  In one form, the Young's modulus of the stress relaxation layer may be lower than the Young's modulus of the wiring layer. According to this configuration, since the Young's modulus of the stress relaxation layer is lower than the Young's modulus of the wiring layer, the external force applied to the electronic component can be further relaxed when the electronic component is laminated on the wiring layer. it can. Therefore, it can suppress effectively that an electronic component receives the influence of external force. In particular, deformation of the dielectric layer of the electronic component due to external force can be effectively suppressed.

  In one form, the Young's modulus of the stress relaxation layer may be lower than the Young's modulus of the insulating layer. According to this configuration, since the Young's modulus of the stress relaxation layer is lower than the Young's modulus of the insulating layer, the external force applied to the electronic component can be further relaxed. Therefore, it can suppress effectively that an electronic component receives the influence of external force.

  ADVANTAGE OF THE INVENTION According to this invention, the electronic component built-in board | substrate which can suppress that an electronic component receives the influence of external force is provided.

1 is a cross-sectional view schematically showing an electronic component built-in substrate according to a first embodiment of the present invention. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is sectional drawing which shows schematically the board | substrate with a built-in electronic component which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is sectional drawing which shows schematically the board | substrate with a built-in electronic component which concerns on 3rd Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is sectional drawing which shows schematically the board | substrate with a built-in electronic component which concerns on 4th Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown in FIG. It is sectional drawing which shows roughly the modification of the electronic component built-in board | substrate shown in FIG. It is sectional drawing which shows roughly the other modification of the electronic component built-in board | substrate shown in FIG. It is sectional drawing which shows roughly the modification of the electronic component built-in board | substrate shown in FIG.

  Hereinafter, various embodiments will be described in detail with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same or an equivalent part, and the overlapping description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing an electronic component built-in substrate according to a first embodiment of the present invention. An electronic component built-in substrate 1 shown in FIG. 1 is a substrate used for a communication terminal, for example. As shown in FIG. 1, the electronic component built-in substrate 1 includes a substrate 10, an electronic component 20 built in the substrate 10, and a stress relaxation layer 30. The substrate 10 includes a wiring layer 11 and an insulating layer 12 stacked on the wiring layer 11. The electronic component 20 is built in the substrate 10 and includes a pair of first electrode layers 21A and second electrode layers 21B extending in a direction crossing the stacking direction in which the wiring layer 11 and the insulating layer 12 are stacked. It has an electrode layer and a dielectric layer 22 provided between the pair of electrode layers. Here, “the electronic component 20 is“ built in ”the substrate 10” means a state in which the electronic component 20 is not exposed from the main surface (main surface 10 a or main surface 10 b) of the substrate 10.

  The stress relaxation layer 30 of the electronic component built-in substrate 1 is provided on the wiring layer 11 side with respect to the insulating layer 12 along the stacking direction. In the stacking direction, at least a part of one end portion (second electrode layer 21B) of the electronic component 20 located on the wiring layer 11 side is in contact with the stress relaxation layer 30, and other electronic components 20 located on the insulating layer 12 side. At least a part of the end portion (first electrode layer 21 </ b> A) is in contact with the insulating layer 12. Here, the “end portion” is a portion near the end face of the first electrode layer 21A or the second electrode layer 21B in the stacking direction, and a direction intersecting the end face of the first electrode layer 21A or the second electrode layer 21B ( It also includes side surfaces extending in the stacking direction).

  In addition, the electronic component built-in substrate 1 includes a connection terminal 40 that is electrically connected to the first electrode layer 21 </ b> A of the electronic component 20. In the present embodiment, an opening 13 is provided in the wiring layer 11, and the electronic component 20 is disposed in the opening 13. As a result, at least a part of the electronic component 20 is embedded in the wiring layer 11. Here, the “state in which at least a part is embedded in the wiring layer 11” of the electronic component 20 means a state in which the electronic component 20 and the wiring layer 11 overlap in the stacking direction.

  The substrate 10 is a so-called multilayer circuit board, and the pair of main surfaces 10a and 10b are both ends in the stacking direction of the wiring layer 11 and the insulating layer 12, respectively. The main surface 10 a is an end surface on the insulating layer 12 side of the substrate 10, and the main surface 10 b is an end surface on the wiring layer 11 side of the substrate 10. The wiring layer 11 is made of a conductive material such as copper (Cu), for example. The wiring layer 11 is provided with an opening 13 for arranging the electronic component 20. The insulating layer 12 is made of an insulating material such as an epoxy resin, a polyimide resin, an acrylic resin, or a phenol resin. In addition, it is preferable that the insulating material which comprises the insulating layer 12 is a material from which hardness changes with specific processes, such as a thermosetting resin or a photocurable resin, for example. The insulating layer 12 is also provided so as to fill the gap between the electronic component 20 and the opening 13 in the opening 13 of the wiring layer 11. The total thickness of the substrate 10 can be, for example, about 40 μm to 1000 μm. Moreover, the thickness of the wiring layer 11 can be about 2 μm to 40 μm, and the thickness of the insulating layer 12 can be about 1 μm to 200 μm. In addition, the whole thickness of the board | substrate 10, the thickness of the wiring layer 11, and the thickness of the insulating layer 12 are not specifically limited.

  The electronic component 20 is a low-profile capacitor having a first electrode layer 21A, a second electrode layer 21B, and a dielectric layer 22 provided between the first electrode layer 21A and the second electrode layer 21B. . Each of the first electrode layer 21A and the second electrode layer 21B is divided into a plurality of pieces. In the present embodiment, the first electrode layer 21A is divided into five. The second electrode layer 21B is divided into three. In the present embodiment, the case where the electronic component 20 is a so-called TFCP (Thin Film Capacitor) in which the first electrode layer is formed of a metal thin film and the dielectric layer 22 is formed of a dielectric film will be described. The electronic component 20 has a total thickness of three layers of about 5 μm to 650 μm, the thickness of the first electrode layer 21A is about 0.1 μm to 50 μm, the thickness of the dielectric layer 22 is about 0.05 μm to 100 μm, The thickness of the second electrode layer 21B can be about 5 μm to 500 μm.

  As the material of the first electrode layer 21A and the second electrode layer 21B, the main component is nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), an alloy containing these metals, or an intermetal A material that is a compound is preferably used. However, the material of the first electrode layer 21A and the second electrode layer 21B is not particularly limited as long as it is a conductive material. In the present embodiment, a case will be described in which the first electrode layer 21A has copper as a main component and the second electrode layer 21B has nickel as a main component. The term “main component” means that the proportion of the component is 50% by mass or more. Moreover, as an aspect of the 1st electrode layer 21A and the 2nd electrode layer 21B, the case where it is the laminated body structure which consists of 2 or more types besides the case where an alloy and an intermetallic compound are formed is included. For example, the electrode layer may be formed as a two-layer structure in which a Cu thin film is provided on a Ni thin film. Further, when pure Ni is used as the first electrode layer 21A and / or the second electrode layer 21B, the purity of the Ni is preferably 99.99% or more. Further, in the case of an alloy containing Ni, metals included as metals other than Ni are platinum (Pt), palladium (Pd), iridium (Ir), rhodium (Rh), ruthenium (Ru), osmium (Os), It is preferable to use at least one selected from the group consisting of rhenium (Re), tungsten (W), chromium (Cr), tantalum (Ta), silver (Ag), and copper (Cu). The Young's modulus of the material used for the second electrode layer 21B is, for example, about 10 GPa to 250 GPa.

The dielectric layer 22 is made of a perovskite-based dielectric material. Here, as the perovskite-based dielectric material in the present embodiment, BaTiO ₃ (barium titanate), (Ba _1-x Sr _x ) TiO ₃ (barium strontium titanate), (Ba _1-x Ca _x ) TiO 2. ₃ , PbTiO ₃ , Pb (Zr _x Ti _1-x ) O ₃ and other (strong) dielectric materials having a perovskite structure, and Pb (Mg _1/3 Nb _2/3 ) O ₃ A composite perovskite relaxor type ferroelectric material is included. Here, in the perovskite structure and the perovskite relaxor type dielectric material, the ratio of the A site to the B site is usually an integer ratio, but may be intentionally shifted from the integer ratio in order to improve the characteristics. In order to control the characteristics of the dielectric layer 22, the dielectric layer 22 may appropriately contain an additive substance as a subcomponent.

  The stress relaxation layer 30 is provided on the wiring layer 11 side with respect to the insulating layer 12 along the stacking direction, and the end surface of the second electrode layer 21B of the electronic component 20 on the wiring layer 11 side (the lower side in the drawing). And a part on the side of the wiring layer 11 on the side of the wiring layer 11. Further, the stress relaxation layer 30 is provided in the opening 13 of the wiring layer 11 and is exposed from the main surface 10 b on the wiring layer 11 side of the substrate 10. Further, the stress relaxation layer 30 is provided up to a height position overlapping the second electrode layer 21 </ b> B of the electronic component 20 in the stacking direction of the substrate 10. In the present embodiment, the stress relaxation layer 30 is provided with a plurality of (for example, three) openings 31 corresponding to each of the divided second electrode layers 21B, and the end surfaces of the second electrode layers 21B are open. 31 is exposed. The electronic component 20 is electrically connected to an external electronic component, wiring, or the like via the second electrode layer 21 </ b> B exposed from the opening 31. By having such a structure, the stress relaxation layer 30 is also provided on the wiring layer 11 side with respect to the second electrode layer 21B.

  The stress relaxation layer 30 may be in contact with at least a part of the end portion of the second electrode layer 21B in the stacking direction of the substrate 10, but the second electrode layer 21B in the stacking direction as in the electronic component built-in substrate 1 may be used. It is preferable to contact both the end face and the side face that intersects the end face and continues to the end face. In the present embodiment, the stress relaxation layer 30 is also provided between the divided second electrode layers 21 </ b> B and between the second electrode layer 21 </ b> B and the wiring layer 11. With such a structure, not only the external force in the stacking direction of the substrate 10 but also the external force from a direction different from the stacking direction can be reduced. In addition, since the stress relaxation layer 30 has an insulating property, it is possible to reliably suppress a short circuit between the divided second electrode layers 21B or between the second electrode layer 21B and the wiring layer 11. .

  Although the material of the stress relaxation layer 30 will not be specifically limited if it is an insulating material, For example, nonelectroconductive resin (Non Conductive Paste: NCP) etc. are used suitably. Moreover, although the Young's modulus of the stress relaxation layer 30 can be 0.1 GPa-50GPa, for example, it is comprised with the material which has a Young's modulus lower than the Young's modulus of the 2nd electrode layer 21B of the electronic component 20. . Further, the Young's modulus of the material constituting the stress relaxation layer 30 is lower than any of the other members of the electronic component 20 (the first electrode layer 21A and the dielectric layer 22), the wiring layer 11, and the insulating layer 12. preferable. From the viewpoint of improving the durability of the electronic component built-in substrate 1, the stress relaxation layer 30 is preferably not only in contact with the electronic component 20 but also physically bonded. Therefore, it is more preferable to use a material whose hardness changes such as a thermosetting resin or a photocurable resin for the stress relaxation layer 30.

  The connection terminal 40 is provided corresponding to each of the divided first electrode layers 21A, and is electrically connected to the first electrode layer 21A. In the present embodiment, an example in which five connection terminals 40 are provided is shown. Each of the connection terminals 40 includes a via 41 penetrating the insulating layer 12 between the main surface 10a of the substrate 10 and the first electrode layer 21A, a terminal portion 42 exposed from the main surface 10a continuously to the via 41, have. The first electrode layer 21 </ b> A is electrically connected to an external electronic component or wiring via the connection terminal 40.

  Next, a method for manufacturing the electronic component built-in substrate 1 will be described with reference to FIGS. 2-4 is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown by FIG. 2 to 4 show a method of manufacturing one electronic component built-in substrate 1, but actually, after forming a plurality of electronic component built-in substrates 1 on one wafer, each electronic component is formed. Separated into the built-in substrate 1. Accordingly, FIGS. 2 to 4 show an enlarged part of one wafer.

  First, as shown in FIG. 2A, a wafer W as a base material is prepared, and a wiring layer 11 is formed on the wafer W. The material of the wafer W is not specifically limited, For example, a Si wafer etc. can be used. The wiring layer 11 is formed by plating, for example. In addition, you may prepare the wafer W in which the wiring layer 11 was formed previously.

  Next, as shown in FIG. 2B, an opening 13 for embedding the electronic component 20 is formed in the wiring layer 11. A general photolithography technique can be used to form the opening 13. Specifically, after applying a photoresist on the wiring layer 11, an actinic ray such as UV light is irradiated through a photomask. Next, development is performed to remove the portion of the photoresist where the opening 13 is to be formed. Thereafter, the wiring layer 11 is etched using the photoresist as a mask. After the etching of the wiring layer 11 is completed, the photoresist is removed. The material of the mask is not particularly limited, and a metal thin film such as chromium (Cr) or tungsten (W) may be used instead of the photoresist. Also, the etching method of the wiring layer 11 is not particularly limited, and a known wet etching process or dry etching process can be used.

  Next, as shown in FIG. 2C, a stress relaxation layer 30 is formed in the opening 13. When the stress relaxation layer 30 is formed of a material that changes in hardness, such as a thermosetting resin or a photocurable resin, an uncured resin material is disposed in the opening 13. The resin material is left uncured in order to embed the electronic component 20 in a later process.

  Next, as shown in FIG. 3A, the electronic component 20 is disposed in the opening 13. The electronic component 20 including the first electrode layer 21A, the dielectric layer 22, and the second electrode layer 21B can be manufactured by a known method. The electronic component 20 is arranged in a state where at least a part thereof is embedded in the uncured stress relaxation layer 30. Thereafter, the uncured stress relaxation layer 30 is cured. As a result, the electronic component 20 is embedded in the opening 13 and the stress relaxation layer 30, and the electronic component 20 and the stress relaxation layer 30 are physically bonded.

  Next, an insulating layer 12 is formed on the wiring layer 11 as shown in FIG. The insulating layer 12 is formed, for example, by applying an uncured thermosetting resin and then curing it by heating. The insulating layer 12 may be formed by applying an uncured photocurable resin and then curing it by irradiating with light of a specific wavelength. By this step, the insulating layer 12 is laminated on the wiring layer 11, the resin constituting the insulating layer 12 is filled between the opening 13 and the electrodes, and the electronic component 20 and the stress relaxation layer 30 are formed by the insulating layer 12. It will be in the sealed state.

  Next, as shown in FIG. 4A, a plurality of openings 14 corresponding to the first electrode layers 21 </ b> A of the electronic component 20 are formed in the insulating layer 12. For example, dry etching using a patterned photoresist as a mask can be used to form the opening 14. Through this step, each of the first electrode layers 21 </ b> A of the electronic component 20 is exposed from the opening 14.

  Next, as shown in FIG. 4B, the conductive layer 15 for forming the connection terminals 40 is formed. The conductive layer 15 is formed by plating, for example. By this step, the conductive layer 15 is formed on the insulating layer 12, the plurality of openings 14 are filled with the conductive layer 15, and the vias 41 of the plurality of connection terminals 40 are formed.

  Next, as shown in FIG. 4C, the conductive layer 15 is patterned by etching or the like to form the terminal portions 42 of the plurality of connection terminals 40 from the conductive layer 15. By this step, a plurality of connection terminals 40 are formed.

  Finally, the wafer W is removed, and an opening 31 is formed in the stress relaxation layer 30 by etching or the like. By this step, the second electrode layer 21 </ b> B of the electronic component 20 is exposed from the opening 31. Thereafter, by dividing into pieces by dicing or the like, an electronic component built-in substrate 1 as shown in FIG. 1 is obtained.

  As described above, in the electronic component built-in substrate 1, at least a part of the second electrode layer 21 </ b> B located on the wiring layer 11 side of the electronic component 20 is in contact with the stress relaxation layer 30. Since the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the second electrode layer 21 </ b> B located on the wiring layer 11 side, the external force applied to the electronic component 20 is relaxed by the stress relaxation layer 30. Therefore, deformation of the dielectric layer 22 due to the electronic component 20 being affected by external force can be suppressed.

  The stress relaxation layer 30 has an insulating property. Thus, even when the electronic component 20 is deformed by an external force, the stress relaxation layer 30 can maintain insulation between the second electrode layer 21B layer located on the wiring layer 11 side and other components.

  In the electronic component built-in substrate 1, the electronic component 20 having a reduced height as described above is used. In this way, when the electronic component 20 is reduced in height, the dielectric layer 22 is easily affected by external forces. In particular, it is considered that the wiring layer 11 has a higher Young's modulus than the insulating layer 12, and an external force from the wiring layer 11 side is likely to directly affect the dielectric layer 22. Therefore, out of the pair of electrode layers sandwiching the dielectric layer 22, the wiring layer 11 side is in contact with the end surface in the stacking direction of the second electrode layer 21B provided on the wiring layer 11 side, that is, the second electrode layer 21B side. By providing the stress relaxation layer 30 on the surface, particularly when an external force is applied along the direction in which the substrate 10 and the electronic component 20 are laminated, the stress relaxation layer 30 can appropriately relax the external force. As described above, when the stress relaxation layer 30 is provided on the wiring layer 11 side of the end face of the electronic component 20 (end face of the second electrode layer 21B), the electronic component is produced during manufacture and handling of the electronic component-embedded substrate 1. The deformation of the dielectric layer 22 due to the influence of the external force 20 can be suppressed.

  Further, the Young's modulus of the stress relaxation layer 30 can be made lower than the Young's modulus of the insulating layer 12. Thus, when the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the insulating layer 12, the external force applied to the electronic component 20 can be further relaxed. Therefore, deformation of the dielectric layer 22 due to the electronic component 20 being affected by external force can be effectively suppressed.

  If the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the second electrode layer 21B, the electronic component 20 can be suppressed from being influenced by external force. The difference from the Young's modulus of the two-electrode layer 21B is preferably 50 GPa or more. Further, the difference between the Young's modulus of the stress relaxation layer 30 and the Young's modulus of the insulating layer 12 is preferably 1 GPa or more. Due to the difference in Young's modulus, the external force can be relaxed more suitably by the stress relaxation layer 30.

  At least a part of the electronic component 20 is embedded in the opening 13 of the wiring layer 11, and the stress relaxation layer 30 is exposed from the wiring layer 11 side of the substrate 10 (the main surface 10 b of the substrate 10). Thus, since at least a part of the electronic component 20 is embedded in the wiring layer 11, the dimension in the stacking direction of the electronic component built-in substrate 1 can be reduced.

(Second Embodiment)
Next, an electronic component built-in substrate 2 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view schematically showing an electronic component built-in substrate according to a second embodiment of the present invention. Similar to the electronic component built-in substrate 1, the electronic component built-in substrate 2 includes a substrate 10, an electronic component 20, and a stress relaxation layer 30. The electronic component built-in substrate 2 is different from the electronic component built-in substrate 1 in that the stress relaxation layer 30 and the electronic component 20 are sequentially laminated on the wiring layer 11. Further, since the electronic component 20 is laminated on the wiring layer 11, the wiring layer 11 is divided into a plurality of parts corresponding to the divided second electrode layer 21B of the electronic component 20. In the electronic component built-in substrate 2, the stress relaxation layer 30 is provided so as to fill between the second electrode layer 21 </ b> B and the wiring layer 11, and is provided so as to fill a gap between the divided wiring layers 11. Yes. In the present embodiment, the second electrode layer 21B is divided into three, and the wiring layer 11 is also divided into at least three corresponding to the respective second electrode layers 21B.

  Moreover, between the 2nd electrode layer 21B and the wiring layer 11, the connection member 50 which has electroconductivity, for example is provided, respectively, and the 2nd electrode layer 21B and the wiring layer 11 are electrically connected. Thereby, the second electrode layer 21 </ b> B of the electronic component 20 is electrically connected to an external electronic component or wiring via the connection member 50 and the wiring layer 11. As shown in FIG. 5, when the connection member 50 is smaller than the second electrode layer 21B when viewed in the stacking direction, the stress relaxation layer 30 is disposed on the end face side of the second electrode layer 21B. That is, the stress relaxation layer 30 is provided so as to fill between the second electrode layer 21 </ b> B and the wiring layer 11. Note that the second electrode layer 21B and the wiring layer 11 may be directly electrically connected without the connection member 50 interposed therebetween. When the second electrode layer 21B and the wiring layer 11 are directly electrically connected, the second electrode layer 21B or the wiring layer is provided so that the stress relaxation layer 30 is provided between the second electrode layer 21B and the wiring layer 11. The shape of 11 is changed from the shape shown in FIG.

  Then, with reference to FIGS. 6-8, the manufacturing method of the electronic component built-in board | substrate 2 is demonstrated. 6 to 8 are views for explaining a method of manufacturing the electronic component built-in substrate shown in FIG. 6 to 8 show a method of manufacturing one electronic component built-in substrate 2, actually, after forming a plurality of electronic component built-in substrates 2 on a single wafer, each electronic component is formed. Separated into the built-in substrate 2. Accordingly, FIGS. 6 to 8 show an enlarged part of one wafer.

  As shown in FIG. 6A, a wafer W to be a base material is prepared, and a wiring layer 11 is formed on the wafer W. The material of the wafer W is not specifically limited, For example, a Si wafer etc. can be used. The wiring layer 11 is formed by plating, for example. In addition, you may prepare the wafer W in which the wiring layer 11 was formed previously.

  Next, as shown in FIG. 6B, the wiring layer 11 is divided into a plurality of parts by etching or the like. For the etching of the wiring layer 11, for example, a patterned photoresist or a metal thin film can be used as a mask. By this step, the wiring layer 11 is in a state of being divided corresponding to the second electrode layer 21B of the electronic component 20 disposed later.

  Next, as illustrated in FIG. 6C, the connection member 50 is formed on the divided wiring layer 11. By this step, the connection member 50 is laminated on each of the divided wiring layers 11. The material constituting the connection member 50 may be any material as long as it has conductivity.

  Next, as shown in FIG. 7A, the electronic component 20 is stacked on the connection member 50. The electronic component 20 is arranged in an aligned state so that the position of the divided second electrode layer 21 </ b> B corresponds to the position of each connection member 50. Thereby, the second electrode layer 21 </ b> B is electrically connected to the connection member 50 and the wiring layer 11.

  Next, as shown in FIG. 7B, a stress relaxation layer 30 is formed. The stress relaxation layer 30 is formed by, for example, applying an uncured thermosetting resin or photocurable resin and then curing it. By this step, the resin constituting the stress relaxation layer 30 is filled in gaps such as between the second electrode layers 21B and between the second electrode layer 21B and the wiring layer 11. As a result, the stress relaxation layer 30 and the electronic component 20 are sequentially stacked on the wiring layer 11.

  Next, as shown in FIG. 8A, the insulating layer 12 is formed. The insulating layer 12 is formed, for example, by applying an uncured thermosetting resin and then curing it by heating. The insulating layer 12 may be formed by applying an uncured photocurable resin and then curing it by irradiating with light of a specific wavelength. By this step, the insulating layer 12 is formed, and a resin constituting the insulating layer 12 is filled in a gap such as between the electrodes of the electronic component 20. As a result, the electronic component 20 and the stress relaxation layer 30 are sealed by the insulating layer 12.

  Next, as illustrated in FIG. 8B, a plurality of openings 14 corresponding to the divided first electrode layers 21 </ b> A of the electronic component 20 are formed in the insulating layer 12. For example, dry etching using a patterned photoresist as a mask can be used to form the opening 14. Through this step, each of the divided first electrode layers 21A of the electronic component 20 is exposed from the opening 14.

  Next, as shown in FIG. 8C, the conductive layer 15 for forming the connection terminals 40 is formed. The conductive layer 15 is formed by plating, for example. By this step, the conductive layer 15 is formed on the insulating layer 12, the plurality of openings 14 are filled with the conductive layer 15, and the via 41 of the connection terminal 40 is formed.

  Finally, the conductive layer 15 is patterned by etching or the like to form the terminal portions 42 of the plurality of connection terminals 40 from the conductive layer 15. By this step, a plurality of connection terminals 40 are formed. Thereafter, by dividing into pieces by dicing or the like and removing the wafer W, an electronic component built-in substrate 2 as shown in FIG. 5 is obtained.

  As described above, also in the electronic component built-in substrate 2, at least a part of one end portion (second electrode layer 21 </ b> B) in the stacking direction of the electronic component 20 located on the wiring layer 11 side is in contact with the stress relaxation layer 30. Yes. Since the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the second electrode layer 21 </ b> B located on the wiring layer 11 side, the external force applied to the electronic component 20 is relaxed by the stress relaxation layer 30. Therefore, even when the stress relaxation layer 30 and the electronic component 20 have a structure in which the electronic component 20 is sequentially laminated with respect to the wiring layer 11, deformation of the dielectric layer 22 due to the influence of the external force on the electronic component 20 is suppressed. can do.

  In the electronic component built-in substrate 2, it is preferable that the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the wiring layer 11. Thus, when the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the wiring layer 11, the external force applied to the electronic component 20 can be further relaxed. Therefore, deformation of the dielectric layer 22 due to the electronic component 20 being affected by external force can be effectively suppressed.

(Third embodiment)
Next, an electronic component built-in substrate 3 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 9 is a cross-sectional view schematically showing an electronic component built-in substrate according to a third embodiment of the present invention. As shown in FIG. 9, the electronic component built-in substrate 3 includes a substrate 10, an electronic component 20 built in the substrate 10, and a stress relaxation layer 30 (stress gap layer). The electronic component built-in substrate 3 is different from the electronic component built-in substrate 1 in that the stress relaxation layer 30 has conductivity. The stress relaxation layer 30 is provided on the wiring layer 11 side with respect to the second electrode layer 21B of the electronic component 20, and is in contact with the second electrode layer 21B. The stress relaxation layer 30 is disposed in the opening 13 of the wiring layer 11 and is exposed from the main surface 10 b of the substrate 10 on the wiring layer 11 side.

  The stress relaxation layer 30 is made of, for example, a conductive material such as a solder alloy or silver (Ag). Thereby, the second electrode layer 21 </ b> B is electrically connected to an external electronic component or wiring via the stress relaxation layer 30. In the electronic component built-in substrate 3 as well, from the viewpoint of improving durability, it is preferable that the stress relaxation layer 30 is not only electrically connected to the electronic component 20 but also physically connected. . Accordingly, the stress relaxation layer 30 is preferably a material whose hardness changes. Also from the above viewpoint, the solder alloy is preferably used as the stress relaxation layer 30.

  In the present embodiment, the stress relaxation layer 30 is also divided into three corresponding to the second electrode layer 21B. As described above, the stress relaxation layer 30 has a shape corresponding to the second electrode layer. FIG. 9 shows a case where the area of the stress relaxation layer 30 is slightly smaller than the area of the second electrode layer 21B when viewed in the stacking direction. With such a structure, it is possible to improve the durability against pressure in the vertical direction (stacking direction) applied from the stress relaxation layer 30 to the dielectric layer 22 of the electronic component built-in substrate 3. The stress relaxation layer 30 is fixed on the surface with the second electrode layer 21B. Since the stress relaxation layer 30 is smaller than the second electrode layer 21B, it has an allowance extending in the plane of the second electrode layer 21B. When pressure in the vertical direction is applied, the stress relaxation layer 30 is deformed in the direction of the outer edge of the second electrode layer 21B and releases the pressure in the vertical direction in the horizontal direction (plane direction). At this time, if there is an allowance extending in the plane of the second electrode layer 21 </ b> B, the possibility that the electrical characteristics are impaired due to the contact between the stress relaxation layers 30 after the deformation is lowered. However, a problem that may occur due to contact between the stress relaxation layers 30 after deformation is that the Young's modulus of the stress relaxation layer 30 described later is set to an appropriate value, or the electronic component 20 and the opening 13 are formed by the insulating layer 12. Filling the gap can also be prevented by these two means. Therefore, as shown in FIG. 9, when viewed in the stacking direction, the area of the stress relaxation layer 30 does not have to be smaller than the area of the second electrode layer 21B, and may be the same area. The area of the stress relaxation layer 30 may be larger than the area of the second electrode layer 21B.

  The Young's modulus of the stress relaxation layer 30 can be, for example, about 5 GPa to 120 GPa, but is made of a material having a Young's modulus lower than that of the second electrode layer 21B. Moreover, the dimension of the stress relaxation layer 30 in the stacking direction of the substrate 10 can be 2 μm to 50 μm.

  Next, with reference to FIGS. 10-12, the manufacturing method of the electronic component built-in board | substrate 3 is demonstrated. 10 to 12 are views for explaining a method of manufacturing the electronic component built-in substrate shown in FIG. 10 to 12 show a method of manufacturing one electronic component built-in substrate 3, but actually, after forming a plurality of electronic component built-in substrates 3 on one wafer, each electronic component is formed. Separated into the built-in substrate 3. Therefore, FIGS. 10 to 12 show an enlarged part of one wafer.

  First, as shown in FIG. 10A, a wafer W as a base material is prepared, and a wiring layer 11 is formed on the wafer W. The material of the wafer W is not specifically limited, For example, a Si wafer etc. can be used. The wiring layer 11 is formed by plating, for example. In addition, you may prepare the wafer W in which the wiring layer 11 was formed previously.

  Next, as shown in FIG. 10B, an opening 13 for embedding the electronic component 20 is formed in the wiring layer 11. A general photolithography technique can be used to form the opening 13. Specifically, after applying a photoresist on the wiring layer 11, an actinic ray such as UV light is irradiated through a photomask. Next, development is performed to remove the portion of the photoresist where the opening 13 is to be formed. Thereafter, the wiring layer 11 is etched using the photoresist as a mask. After the etching of the wiring layer 11 is completed, the photoresist is removed. The material of the mask is not particularly limited, and a metal thin film such as chromium (Cr) or tungsten (W) may be used instead of the photoresist. Also, the etching method of the wiring layer 11 is not particularly limited, and a known wet etching process or dry etching process can be used.

  Next, as shown in FIG. 10C, the stress relaxation layer 30 is formed in the opening 13. The stress relaxation layer 30 is formed at a position corresponding to the second electrode layer 21B of the electronic component 20 to be embedded later. The stress relaxation layer 30 can be formed by, for example, a printing method, a transfer method, or a conductive film laminating method.

  Next, as shown in FIG. 11A, the electronic component 20 is disposed in the opening 13. The electronic component 20 including the first electrode layer 21A, the dielectric layer 22, and the second electrode layer 21B can be manufactured by a known method. The electronic component 20 is arranged in an aligned state so that the position of the divided second electrode layer 21 </ b> B corresponds to the position of each stress relaxation layer 30. Thereby, the second electrode layer 21 </ b> B is electrically connected to the stress relaxation layer 30. In the case where the stress relaxation layer 30 is a material whose hardness changes, such as a solder alloy, the electronic component 20 is disposed before the stress relaxation layer 30 is cured, and the stress relaxation layer 30 is cured, whereby the electronic component 20. And the stress relaxation layer 30 can be physically connected.

  Next, as shown in FIG. 11B, an insulating layer 12 is formed on the wiring layer 11. The insulating layer 12 is formed, for example, by applying an uncured thermosetting resin and then curing it by heating. The insulating layer 12 may be formed by applying an uncured photocurable resin and then curing it by irradiating with light of a specific wavelength. By this step, the insulating layer 12 is laminated on the wiring layer 11, the resin constituting the insulating layer 12 is filled between the opening 13 and the electrodes, and the stress relaxation layer 30 and the electronic component 20 are formed by the insulating layer 12. It will be in the sealed state.

  Next, as shown in FIG. 12A, a plurality of openings 14 corresponding to the first electrode layers 21 </ b> A of the electronic component 20 are formed in the insulating layer 12. For example, dry etching using a patterned photoresist as a mask can be used to form the opening 14. Through this step, each of the first electrode layers 21 </ b> A of the electronic component 20 is exposed from the opening 14.

  Next, as shown in FIG. 12B, the conductive layer 15 for forming the connection terminals 40 is formed. The conductive layer 15 is formed by plating, for example. By this step, the conductive layer 15 is formed on the insulating layer 12, the plurality of openings 14 are filled with the conductive layer 15, and the vias 41 of the plurality of connection terminals 40 are formed.

  Finally, the conductive layer 15 is patterned by etching or the like to form the terminal portions 42 of the plurality of connection terminals 40 from the conductive layer 15. By this step, a plurality of connection terminals 40 are formed. Thereafter, the substrate is separated into pieces by dicing or the like and the wafer W is removed to obtain the electronic component built-in substrate 3 as shown in FIG.

  As described above, also in the electronic component built-in substrate 3, the stress relaxation layer 30 is provided on the wiring layer 11 side of the second electrode layer 21 </ b> B located on the wiring layer 11 side of the substrate 10. Since the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the second electrode layer 21 </ b> B, the external force applied to the electronic component 20 is relaxed by the stress relaxation layer 30. Therefore, deformation of the dielectric layer 22 of the electronic component 20 due to external force can be suppressed. Further, since the stress relaxation layer 30 has conductivity, it is possible to suppress deformation of the dielectric layer 22 of the electronic component 20 due to external force while maintaining electrical connection with the second electrode layer 21B.

  In the electronic component built-in substrate 3, the electronic component 20 having a reduced height as described above is used. In this way, when the electronic component 20 is reduced in height, the dielectric layer 22 is easily affected by external forces. In particular, it is considered that the wiring layer 11 has a higher Young's modulus than the insulating layer 12, and an external force from the wiring layer 11 side is likely to directly affect the dielectric layer 22. Therefore, by providing the stress relaxation layer 30 on the wiring layer 11 side with respect to the second electrode layer 21B provided on the wiring layer 11 side among the pair of electrode layers sandwiching the dielectric layer 22, in particular, the substrate 10 and the electronic component When an external force is applied along the stacking direction 20, the stress relaxation layer 30 can moderate the external force suitably. Therefore, it is possible to suppress the dielectric layer 22 from being deformed by an external force when the electronic component built-in substrate 3 is manufactured and handled.

  If the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the second electrode layer 21B, the deformation of the electronic component 20 due to external force can be suppressed, but the Young's modulus of the stress relaxation layer 30 and the second electrode layer The difference from the Young's modulus of 21B is preferably 50 GPa or more. Thus, when the difference in Young's modulus is 50 GPa or more, the external force can be relaxed more suitably by the stress relaxation layer 30.

  At least a part of the electronic component 20 is embedded in the opening 13 of the wiring layer 11, and the stress relaxation layer 30 is exposed from the wiring layer 11 side of the substrate 10 (the main surface 10 b of the substrate 10). Thereby, the second electrode layer 21 </ b> B and an external component can be electrically connected via the stress relaxation layer 30. In addition, since at least a part of the electronic component 20 is embedded in the wiring layer 11, the dimension in the stacking direction of the electronic component built-in substrate 3 can be reduced.

(Fourth embodiment)
Next, an electronic component built-in substrate 4 according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a cross-sectional view schematically showing an electronic component built-in substrate according to a fourth embodiment of the present invention. Similar to the electronic component built-in substrate 3, the electronic component built-in substrate 4 includes a substrate 10, an electronic component 20, and a stress relaxation layer 30 having conductivity. The electronic component built-in substrate 4 is different from the electronic component built-in substrate 3 in that the stress relaxation layer 30 and the electronic component 20 are sequentially laminated on the wiring layer 11, and the divided second electrode of the electronic component 20 is provided. The wiring layer 11 is divided into a plurality of parts corresponding to the layer 21B. In the present embodiment, the second electrode layer 21B is divided into three, and the wiring layer 11 is also divided into at least three corresponding to the respective second electrode layers 21B. Thereby, the second electrode layer 21 </ b> B of the electronic component 20 is electrically connected to an external electronic component or wiring via the stress relaxation layer 30 and the wiring layer 11.

  Then, with reference to FIGS. 14-16, the manufacturing method of the electronic component built-in board | substrate 4 is demonstrated. 14-16 is a figure for demonstrating the manufacturing method of the electronic component built-in board | substrate shown by FIG. 14 to 16 show a method of manufacturing one electronic component built-in substrate 4, actually, after forming a plurality of electronic component built-in substrates 4 on one wafer, each electronic component is formed. Separated into the built-in substrate 4. Accordingly, FIGS. 14 to 16 show an enlarged part of one wafer.

  As shown in FIG. 14A, a wafer W to be a base material is prepared, and a wiring layer 11 is formed on the wafer W. The material of the wafer W is not specifically limited, For example, a Si wafer etc. can be used. The wiring layer 11 is formed by plating, for example. In addition, you may prepare the wafer W in which the wiring layer 11 was formed previously.

  Next, as shown in FIG. 14B, the wiring layer 11 is divided into a plurality of parts by etching or the like. For the etching of the wiring layer 11, for example, a patterned photoresist or a metal thin film can be used as a mask. By this step, the wiring layer 11 is in a state of being divided corresponding to the second electrode layer 21B of the electronic component 20 disposed later.

  Next, as shown in FIG. 14C, the stress relaxation layer 30 is formed on the divided wiring layer 11. The stress relaxation layer 30 is formed by, for example, a printing method, a transfer method, or a conductive film laminating method. By this step, the stress relaxation layer 30 is laminated on each of the divided wiring layers 11.

  Next, as shown in FIG. 14A, the electronic component 20 is laminated on the stress relaxation layer 30. The electronic component 20 is arranged in an aligned state so that the position of the divided second electrode layer 21 </ b> B corresponds to the position of each stress relaxation layer 30. Thereby, the second electrode layer 21 </ b> B is electrically connected to the stress relaxation layer 30.

  Next, as shown in FIG. 14B, the insulating layer 12 is formed. The insulating layer 12 is formed, for example, by applying an uncured thermosetting resin and then curing it by heating. The insulating layer 12 may be formed by applying an uncured photocurable resin and then curing it by irradiating with light of a specific wavelength. By this step, the insulating layer 12 is formed, and the resin constituting the insulating layer 12 is filled in gaps such as between the divided wiring layers 11 and between the electrodes of the electronic component 20. As a result, the stress relaxation layer 30 and the electronic component 20 are sealed by the insulating layer 12.

  Next, as shown in FIG. 15A, a plurality of openings 14 corresponding to the divided first electrode layers 21 </ b> A of the electronic component 20 are formed in the insulating layer 12. For example, dry etching using a patterned photoresist as a mask can be used to form the opening 14. Through this step, each of the divided first electrode layers 21A of the electronic component 20 is exposed from the opening 14.

  Next, as shown in FIG. 15B, the conductive layer 15 for forming the connection terminals 40 is formed. The conductive layer 15 is formed by plating, for example. By this step, the conductive layer 15 is formed on the insulating layer 12, the plurality of openings 14 are filled with the conductive layer 15, and the via 41 of the connection terminal 40 is formed.

  Finally, the conductive layer 15 is patterned by etching or the like to form the terminal portions 42 of the plurality of connection terminals 40 from the conductive layer 15. By this step, a plurality of connection terminals 40 are formed. Thereafter, by dividing into pieces by dicing or the like and removing the wafer W, an electronic component built-in substrate 2 as shown in FIG. 13 is obtained.

  As described above, also in the electronic component built-in substrate 4, the stress relaxation layer 30 is provided on the wiring layer 11 side of the second electrode layer 21B positioned on the wiring layer 11 side. Since the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the second electrode layer 21 </ b> B, the external force applied to the electronic component 20 is relaxed by the stress relaxation layer 30. Therefore, deformation of the dielectric layer 22 of the electronic component 20 due to external force can be suppressed. Further, since the stress relaxation layer 30 has conductivity, it is possible to suppress deformation of the dielectric layer 22 of the electronic component 20 due to external force while maintaining electrical connection with the second electrode layer 21B.

  In addition, the stress relaxation layer 30 and the electronic component 20 are sequentially stacked on the wiring layer 11, and the stress relaxation layer 30 is in contact with the wiring layer 11. Thereby, the second electrode layer 21 </ b> B and the wiring layer 11 can be electrically connected via the stress relaxation layer 30.

  In the electronic component built-in substrate 4, it is preferable that the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the wiring layer 11. Thus, when the Young's modulus of the stress relaxation layer 30 is lower than the Young's modulus of the wiring layer 11, the external force applied to the electronic component 20 can be further relaxed. Therefore, deformation of the dielectric layer 22 of the electronic component 20 due to external force can be effectively suppressed.

  As mentioned above, although embodiment of this invention has been described, this invention is not limited to said embodiment, A various change can be made.

  For example, the electronic component incorporated in the electronic component built-in substrate is not limited to the electronic component 20, and may have a structure different from that of the electronic component 20. FIG. 17 is a cross-sectional view schematically showing an electronic component built-in substrate 5 according to a modification of the electronic component built-in substrate 1 shown in FIG. As shown in FIG. 17, the electronic component built-in substrate 5 is different from the electronic component built-in substrate 1 in that an electronic component 60 is incorporated instead of the electronic component 20, and no opening is provided in the stress relaxation layer 30. Is a point.

  The electronic component 60 includes a pair of electrode layers (first electrode layer 61A, second electrode layer 61B) and a dielectric layer 62 disposed between the first electrode layer 61A and the second electrode layer 61B, A layer 63 is further provided. The second electrode layer 61B, the dielectric layer 62, and the first electrode layer 61A are laminated on the base material layer 63 in this order. The base material layer 63 is made of, for example, a semiconductor material such as silicon (Si). In the electronic component 60, the second electrode layer 61B is electrically connected to an external electronic component or wiring from the insulating layer 12 side, not the wiring layer 11 side. In the electronic component built-in substrate 5 in which the electronic component 60 is incorporated, the stress relaxation layer 30 is provided so as to cover the end of the electronic component 60 on the wiring layer 11 side, that is, the base material layer 63. In the electronic component built-in substrate 5, there is no need to ensure electrical connection with the second electrode layer 61B of the electronic component 60 on the wiring layer 11 side, and an opening for electrical connection of the second electrode layer 61B is provided in the stress relaxation layer. Therefore, the contact area between the stress relaxation layer 30 and the electronic component 60 can be increased. Therefore, it is possible to effectively suppress deformation of the dielectric layer 62 due to the electronic component 60 being affected by external force.

  The stress relaxation layer 30 of the electronic component built-in substrate includes a first stress relaxation layer 30A having insulation and a second stress relaxation layer 30B having conductivity for the purpose of further relaxing external force. Also good. FIG. 18 is a cross-sectional view schematically showing an electronic component built-in substrate 6 according to a modification of the electronic component built-in substrate 1 shown in FIG. As shown in FIG. 18, the electronic component built-in substrate 6 is different from the electronic component built-in substrate 1 in that it is in contact with at least a part of one end portion (second electrode layer 21B) of the electronic component 20 and has a first insulating property. It is provided with a stress relaxation layer 30A and a conductive second stress relaxation layer 30B provided on the wiring layer 11 side of the second electrode layer 21B, that is, in the opening 31 of the first stress relaxation layer 30A. is there. Specifically, the first stress relaxation layer 30A is in contact with both the end surface of the second electrode layer 21B in the stacking direction and the side surface that intersects the end surface and continues to the end surface, and is divided. It is provided between 21B and between the second electrode layer 21B and the wiring layer 11. One end of the second stress relaxation layer 30B is in contact with the second electrode layer 21B, and the other end is exposed from the main surface 10b of the substrate 10. As a result, the second electrode layer 21B of the electronic component 20 can be electrically connected to an external electronic component, wiring, or the like via the second stress relaxation layer 30B.

  The material of the first stress relaxation layer 30A is, for example, a non-conductive resin (Non Conductive Paste) in the same manner as the stress relaxation layer 30 (stress relaxation layer 30 having insulating properties) in the electronic component built-in substrate 1 and the electronic component built-in substrate 2. : NCP) is preferably used. Further, the Young's modulus of the first stress relaxation layer 30A can be set to 0.1 GPa to 50 GPa, for example.

  The material of the second stress relaxation layer 30B is, for example, a solder alloy or silver (Ag), like the stress relaxation layer 30 (stress relaxation layer 30 having conductivity) in the electronic component built-in substrate 3 and the electronic component built-in substrate 4. It is comprised by the material which has conductivity. Further, the Young's modulus of the material constituting the second stress relaxation layer 30B is lower than the Young's modulus of the second electrode layer 21B, and can be set to 5 GPa to 120 GPa, for example. It is preferable that it is lower than Young's modulus. Further, the thickness of the second stress relaxation layer 30B can be set to, for example, about 2 μm to 50 μm.

  As described above, when the stress relaxation layer 30 includes the first stress relaxation layer 30A and the second stress relaxation layer 30B, the contact area between the stress relaxation layer 30 and the electronic component 20 can be increased. Specifically, as shown in FIG. 18, the first stress relaxation layer 30A is disposed at a location where insulation is required, such as between the second electrode layer 21B located on the wiring layer 11 side and the wiring layer 11. The second stress relaxation layer 30B can be disposed at a location where conductivity is required such as the wiring layer 11 side with respect to the second electrode layer 21B located on the wiring layer 11 side. As described above, since the contact area between the stress relaxation layer 30 and the electronic component 20 can be increased, the electronic component 20 can be connected to the external force while ensuring the electrical connection between the second electrode layer 21B and the external electronic component. It is possible to further effectively suppress deformation of the dielectric layer 22 due to the influence of the above.

  Further, even when the electronic component 20 includes the plurality of second electrode layers 21B, a single stress relaxation layer may be provided so as to cover all of the end portions of the electronic component 20 on the wiring layer 11 side. FIG. 19 is a cross-sectional view schematically showing an electronic component built-in substrate 7 according to a modification of the electronic component built-in substrate 6 shown in FIG. As shown in FIG. 19, the electronic component built-in substrate 7 is different from the electronic component built-in substrate 6 in that one kind of stress relaxation layer 70 is used to connect between the plurality of second electrode layers 21B and the second electrode layer 21B and the wiring. The layer 11 is insulated and the second electrode layer 21B is electrically connected to an external electronic component or the like.

  As the stress relaxation layer 70, for example, an anisotropic conductive film having conductivity in the stacking direction and insulating in a direction crossing the stacking direction can be used. Also in such an electronic component built-in substrate 7, since the contact area between the stress relaxation layer 70 and the electronic component 20 can be increased, the electrical connection between the second electrode layer 21B and an external electronic component is ensured. However, it is possible to more effectively suppress deformation of the dielectric layer 22 due to the electronic component 20 being affected by external force.

  In the above embodiment, the stress relaxation layer 30 is provided up to a height position overlapping the second electrode layer 21 </ b> B of the electronic component 20 in the stacking direction of the substrate 10. ) Can be changed as appropriate as long as a part of the end portion of the first electrode layer 21A of the electronic component 20 is in contact with the insulating layer 12. For example, the stress relaxation layer 30 may be provided thicker than the wiring layer 11 or may be provided so as not to overlap with the second electrode layer 21B and to be in contact with only the end face of the second electrode layer 21B in the stacking direction. Also good. In addition, from the viewpoint of relieving external force, the stress relaxation layer 30 is preferably provided thick, and may be provided up to a height position overlapping the first electrode layer 21A, for example.

  Moreover, the stress relaxation layer 30 should just be in contact with at least one part of the edge part by the side of the wiring layer 11 of the electronic component 20. FIG. In the above embodiment, the case where a part of the stress relaxation layer 30 is in contact with the end surface on the second electrode layer 21B side of the electronic component 20 has been described. However, the stress relaxation layer 30 is the end surface of the second electrode layer 21B. The structure which is not touching and is in contact with the side surface continuous from the end face may be used. In this case, the stress relaxation layer 30 is not provided on the wiring layer 11 side of the end face of the electronic component 20 (end face of the second electrode layer 21B). Even in this case, the stress relaxation layer 30 is not provided. Since it can prevent the external force from a direction different from the stacking direction from affecting the electronic component 20, it is possible to suppress the electronic component from being influenced by the external force.

  In the above-described embodiment, the electronic component 20 is built in the substrate 10 so that the first electrode layer 21A of the electronic component 20 is on the insulating layer 12 side and the second electrode layer 21B is on the wiring layer 11 side. However, the electronic component 20 may be incorporated in the substrate 10 such that the second electrode layer 21B is on the insulating layer 12 side and the first electrode layer 21A is on the wiring layer 11 side.

  Further, when the stress relaxation layer 30 has an insulating property (the first embodiment and the second embodiment), the stress relaxation layer 30 (or the first stress relaxation layer 30A) overlaps the electronic component 20 in the stacking direction of the substrate 10. Although it is preferable to be at the height position, the height (thickness) of the stress relaxation layer 30 can be changed as appropriate.

  In the third embodiment and the fourth embodiment (when the stress relaxation layer 30 has conductivity), the case where the electronic component 20 and the stress relaxation layer 30 are in contact has been described. Another layer having conductivity may be provided between the relaxing layer 30 and the relaxation layer 30. However, in this case, it is necessary to have a shape corresponding to the shape of the second electrode layer 21B of the electronic component 20.

  In the above-described embodiment, an example in which each of the first electrode layer 21A and the second electrode layer 21B is divided into a plurality of parts for the electronic component 20 in the electronic component built-in substrate has been described. And the shape of the 2nd electrode layer 21B is not limited to the said embodiment, It can change suitably.

  1, 2, 3, 4, 5, 6, 7 ... electronic component built-in substrate, 10 ... substrate, 10a, 10b ... main surface, 11 ... wiring layer, 12 ... insulating layer, 13 ... opening, 20, 60 ... electronic component 21A ... 1st electrode layer, 21B ... 2nd electrode layer, 22 ... Dielectric layer, 30, 70 ... Stress relaxation layer, 30A ... 1st stress relaxation layer, 30B ... 2nd stress relaxation layer, 40 ... Connection terminal, 50: Connection member.

Claims (8)

A substrate having a wiring layer and an insulating layer laminated to the wiring layer;
An electronic component having a pair of electrode layers built in the substrate and extending in a direction crossing the stacking direction of the substrates, and a dielectric layer provided between the pair of electrode layers;
A stress relaxation layer provided on the wiring layer side with respect to the insulating layer in the stacking direction,
In the stacking direction, at least a part of the end of the electronic component on the wiring layer side is in contact with the stress relaxation layer,
In the stacking direction, at least a part of the end portion of the electronic component on the insulating layer side is in contact with the insulating layer,
The electronic component built-in substrate, wherein a Young's modulus of the stress relaxation layer is lower than a Young's modulus of the electrode layer located on the wiring layer side. The stress relaxation layer includes a first stress relaxation layer having insulation and a second stress relaxation layer having conductivity,
2. The electronic component built-in substrate according to claim 1, wherein the second stress relaxation layer is provided on the wiring layer side with respect to the electrode layer located on the wiring layer side. A substrate having a wiring layer and an insulating layer laminated to the wiring layer;
An electronic component having a pair of electrode layers built in the substrate and extending in a direction crossing the stacking direction of the substrates, and a dielectric layer provided between the pair of electrode layers;
In the stacking direction, provided on the wiring layer side with respect to the insulating layer, comprising a stress relaxation layer having insulation,
In the stacking direction, at least a part of the end of the electronic component on the wiring layer side is in contact with the stress relaxation layer,
In the stacking direction, at least a part of the end portion of the electronic component on the insulating layer side is in contact with the insulating layer,
The electronic component built-in substrate, wherein a Young's modulus of the stress relaxation layer is lower than a Young's modulus of the electrode layer located on the wiring layer side. A substrate having a wiring layer and an insulating layer laminated to the wiring layer;
An electronic component having a pair of electrode layers built in the substrate and extending in a direction crossing the stacking direction of the substrates, and a dielectric layer provided between the pair of electrode layers;
A stress relieving layer provided on the wiring layer side with respect to the electrode layer located on the wiring layer side and having conductivity;
The electronic component built-in substrate, wherein a Young's modulus of the stress relaxation layer is lower than a Young's modulus of the electrode layer located on the wiring layer side. At least a portion of the electronic component is embedded in the wiring layer;
5. The electronic component built-in substrate according to claim 1, wherein the stress relaxation layer is exposed from the wiring layer side of the electronic component built-in substrate. The stress relaxation layer and the electronic component are sequentially laminated with respect to the wiring layer,
The electronic component built-in substrate according to claim 1, wherein the stress relaxation layer is in contact with the wiring layer.   The electronic component built-in substrate according to claim 6, wherein a Young's modulus of the stress relaxation layer is lower than a Young's modulus of the wiring layer.   The electronic component built-in substrate according to claim 1, wherein a Young's modulus of the stress relaxation layer is lower than a Young's modulus of the insulating layer.

Images