JP2018018903A - Semiconductor device - Google Patents

Abstract

Kind Code: A1 An electric field in the vicinity of an outer peripheral edge of a field plate electrode is relaxed. SOLUTION: In a semiconductor device, a floating electrode is in contact with a surface of a semiconductor substrate within an outer withstand voltage region, an interlayer insulating film covers the surface of the semiconductor substrate within the outer withstand voltage region and the floating electrode, and a surface electrode is provided. A field plate electrode electrically connected to is arranged on the interlayer insulating film, and an outer peripheral side end of the field plate electrode is arranged above the floating electrode. [Selection drawing] Fig. 2

Description

  The technology disclosed in this specification relates to a semiconductor device.

  The semiconductor device of Patent Document 1 includes a semiconductor substrate, a front surface electrode, and a back electrode. The surface electrode is in contact with the semiconductor substrate at the center of the surface of the semiconductor substrate. The semiconductor substrate has an element region in contact with the surface electrode and an outer peripheral region outside the element region. In the element region, a Schottky barrier diode (hereinafter sometimes referred to as SBD) is provided. The surface of the outer peripheral region is covered with an interlayer insulating film. A field plate electrode is provided on the interlayer insulating film. The field plate electrode is electrically connected to the surface electrode. When a reverse voltage is applied to the SBD, the potential difference between the front electrode and the back electrode increases. At this time, the outer peripheral end surface of the semiconductor substrate has substantially the same potential as the back electrode. For this reason, in the outer peripheral region, a potential difference is generated in the direction from the outer peripheral end surface of the semiconductor substrate toward the surface electrode (that is, in the lateral direction). If the field plate electrode does not exist, the electric field concentrates near the outer peripheral edge of the surface electrode, and the breakdown voltage of the semiconductor device is lowered. On the other hand, the presence of the field plate electrode relaxes the electric field in the vicinity of the outer peripheral edge of the surface electrode and improves the breakdown voltage of the semiconductor device.

  In Patent Document 1, a semiconductor element in which an SBD is provided in the element region is described. However, a semiconductor element other than the SBD in the element region (for example, a rectifying element such as a pn diode, or a switching element such as an FET or IGBT). Even when the device is provided, the electric field relaxation effect by the field plate electrode can be obtained.

JP 2009-077686 A

  By providing the field plate electrode as in Patent Document 1, the electric field in the vicinity of the outer peripheral edge of the surface electrode is relaxed. On the other hand, the electric field concentrates in the vicinity of the outer peripheral edge of the field plate electrode. Therefore, the present specification provides a technique for relaxing the electric field in the vicinity of the outer peripheral edge of the field plate electrode.

  A semiconductor device disclosed in the present specification includes a semiconductor substrate, a surface electrode in contact with the surface of the semiconductor substrate, a back electrode in contact with the back surface of the semiconductor substrate, a field plate electrode, a floating electrode, and an interlayer It has an insulating film. The semiconductor substrate has an element region overlapping with a contact surface between the surface electrode and the semiconductor substrate when viewed in plan along the thickness direction of the semiconductor substrate, and an outer peripheral breakdown voltage region around the element region. Yes. The element region includes a semiconductor element that can be energized between the front electrode and the back electrode. The floating electrode is in contact with the surface in the outer peripheral withstand voltage region and is insulated from the surface electrode. The interlayer insulating film covers the surface in the outer peripheral withstand voltage region and the floating electrode. The field plate electrode is disposed on the interlayer insulating film and is electrically connected to the surface electrode. An end portion on the outer peripheral side of the field plate electrode is disposed on the floating electrode.

  In this semiconductor device, the outer peripheral end of the field plate electrode is disposed above the floating electrode. Since the potential is constant inside the floating electrode, it is difficult for a potential difference to occur even in the upper part thereof. Therefore, in this semiconductor device, the electric field in the vicinity of the outer peripheral end of the field plate electrode is relaxed.

1 is a plan view of a semiconductor device 10 of Example 1. FIG. Sectional drawing of the semiconductor device 10 in the II-II line | wire of FIG. FIG. 3 is a cross-sectional view corresponding to FIG. 2 of a semiconductor device 110 according to a second embodiment.

A semiconductor device 10 according to the first embodiment illustrated in FIGS. The semiconductor substrate 12 is made of a wide gap semiconductor (for example, GaN, Ga ₂ O ₃ , SiC, etc.). As shown in FIG. 2, the semiconductor substrate 12 has a cathode region 32 and a drift region 34. The cathode region 32 is an n-type region having a high n-type impurity concentration. The cathode region 32 is exposed on the back surface 12 b of the semiconductor substrate 12. The drift region 34 is an n-type region having a low n-type impurity concentration. The drift region 34 is disposed on the cathode region 32. The drift region 34 is exposed on the surface 12 a of the semiconductor substrate 12.

  As shown in FIG. 2, a first metal layer 14 a, a second metal layer 14 b, a plurality of floating electrodes 18, an interlayer insulating film 22, and a protective insulating film 24 are provided on the surface 12 a of the semiconductor substrate 12. In FIG. 1, illustration of the interlayer insulating film 22 and the protective insulating film 24 is omitted. In FIG. 1, the first metal layer 14a and the floating electrode 18 are indicated by hatching. Moreover, the dotted line of FIG. 1 has shown the outline of the 2nd metal layer 14b.

  As shown in FIGS. 1 and 2, the first metal layer 14 a is disposed at the center of the surface 12 a of the semiconductor substrate 12. The first metal layer 14 a is in Schottky contact with the drift region 34. Hereinafter, a range overlapping with the contact surface between the first metal layer 14a and the semiconductor substrate 12 (that is, the drift region 34) when viewed in plan along the thickness direction of the semiconductor substrate 12 is referred to as an element region 40. Further, a range outside the element region 40 (a range between the element region 40 and the outer peripheral end face 12 c of the semiconductor substrate 12) is referred to as an outer peripheral region 42. The cathode region 32 and the drift region 34 described above are distributed across the element region 40 and the outer peripheral region 42.

  The plurality of floating electrodes 18 are provided on the surface 12 a of the semiconductor substrate 12 in the outer peripheral region 42. Each floating electrode 18 has a ring shape surrounding the first metal layer 14a in multiple layers. Each floating electrode 18 is separated from the first metal layer 14a and the second metal layer 14b. The plurality of floating electrodes 18 are separated from each other. The potential of each floating electrode 18 is floating. The width of each floating electrode 18 is the widest on the inner peripheral side and narrower on the outer peripheral side. Further, the interval between two adjacent floating electrodes 18 is the narrowest on the inner peripheral side, and becomes wider on the outer peripheral side. Each floating electrode 18 is in Schottky contact with the drift region 34. Hereinafter, the innermost floating electrode 18 is referred to as a floating electrode 18a, and the other floating electrodes 18 are referred to as floating electrodes 18b.

  The interlayer insulating film 22 covers the surface 12 a of the semiconductor substrate 12 in the outer peripheral region 42 and each floating electrode 18.

  The second metal layer 14b is made of a metal different from the first metal layer 14a. The second metal layer 14b is disposed on the first metal layer 14a. Further, the outer peripheral portion of the second metal layer 14 b is disposed on the interlayer insulating film 22. A field plate electrode 20 (hereinafter referred to as FP electrode 20) is configured by the second metal layer 14b on the interlayer insulating film 22. Hereinafter, the first metal layer 14a and the portion of the second metal layer 14b stacked on the first metal layer 14a are referred to as a surface electrode 16. The outer peripheral end 21 of the FP electrode 20 is disposed above the innermost floating electrode 18a. The width W1 of the portion of the floating electrode 18a that overlaps with the FP electrode 20 is narrower than the width W2 of the portion of the floating electrode 18a that does not overlap with the FP electrode 20.

  The protective insulating film 24 covers the interlayer insulating film 22 and the FP electrode 20 in the outer peripheral region 42.

  A back electrode 30 is provided on the back surface 12 b of the semiconductor substrate 12. The back electrode 30 covers substantially the entire area of the back surface 12 b of the semiconductor substrate 12. The back electrode 30 is in ohmic contact with the cathode region 32.

  Next, the operation of the semiconductor device 10 will be described. In the element region 40 of the semiconductor device 10, a Schottky barrier diode (hereinafter referred to as SBD) is formed by the front electrode 16, the drift region 34, the cathode region 32, and the back electrode 30. The front electrode 16 functions as an anode electrode, and the back electrode 30 functions as a cathode electrode. When a forward voltage (a voltage at which the front electrode 16 has a higher potential than the back electrode 30) is applied between the front electrode 16 and the back electrode 30, the surface passes through the Schottky interface between the front electrode 16 and the drift region 34. A current flows from the electrode 16 to the back electrode 30. That is, a current flows from the front electrode 16 to the back electrode 30 through the drift region 34 and the cathode region 32. That is, SBD is turned on.

  When the applied voltage between the front electrode 16 and the back electrode 30 is switched from a forward voltage to a reverse voltage (a voltage at which the back electrode 30 has a higher potential than the front electrode 16), the current stops and the SBD is turned off. Then, since a reverse voltage is applied to the Schottky interface between the surface electrode 16 and the drift region 34, a depletion layer spreads in the drift region 34 from the Schottky interface. The depletion layer extends over substantially the entire drift region 34. As the drift region 34 is depleted, a potential difference is generated in the drift region 34. In the element region 40, since the drift region 34 is sandwiched between the front electrode 16 and the back electrode 30 in the vertical direction, a potential difference is generated in the vertical direction in the depleted drift region 34. Further, the outer peripheral end surface 12 c of the semiconductor substrate 12 has substantially the same potential as the back electrode 30. For this reason, in the outer periphery area | region 42, an electrical potential difference arises in a horizontal direction (direction which goes to an inner peripheral side from an outer peripheral side).

  Here, a case where the floating electrode 18 is not present will be considered. If the floating electrode 18 is not present, the electric field concentrates in the vicinity of the outer peripheral end 21 of the FP electrode 20 when a reverse voltage is applied. For this reason, an avalanche current is easily generated in the drift region 34 in the vicinity of the outer peripheral end 21 of the FP electrode 20. Further, the electric field is increased on the surface of the protective insulating film 24 in the vicinity of the outer peripheral end 21 of the FP electrode 20. When the electric field is increased at this position, a discharge (so-called creeping discharge) tends to occur from the back electrode 30 to the front electrode 16 along the surface of the protective insulating film 24 and the outer peripheral end surface 12c of the semiconductor substrate 12. As described above, when the floating electrode 18 is not present, electric field concentration occurs in the vicinity of the outer peripheral end 21 of the FP electrode 20 and the breakdown voltage of the semiconductor device is lowered.

  On the other hand, in the semiconductor device 10 according to the first embodiment, the innermost floating electrode 18 a exists below the outer peripheral end 21 of the FP electrode 20. Since the floating electrode 18a is a conductor, there is no potential difference inside it. For this reason, the potential difference hardly occurs in the lateral direction even above the floating electrode 18a, and the concentration of the electric field on the outer peripheral end 21 of the FP electrode 20 is suppressed. Further, when the floating electrode 18a is provided, the electric field is easily concentrated in the vicinity of the outer peripheral end 19 of the floating electrode 18a. However, the degree of electric field concentration on the outer peripheral end 19 of the floating electrode 18a is smaller than the degree of electric field concentration on the outer peripheral end 21 of the FP electrode 20 when the floating electrode 18a is not present. In Example 1, the width W2 of the floating electrode 18a that does not overlap with the FP electrode 20 is wider than the width W1 of the portion of the floating electrode 18a that overlaps with the FP electrode 20. For this reason, the outer peripheral end 19 of the floating electrode 18 a is separated from the outer peripheral end 21 of the FP electrode 20. Thus, the electric field is further relaxed by increasing the distance between the portions where the electric field is likely to concentrate. Furthermore, in Example 1, the some floating electrode 18b is provided in the outer peripheral side of the floating electrode 18a. For this reason, the electric field concentrates on each of the outer peripheral ends of the plurality of floating electrodes 18 including the floating electrode 18a, and the concentrated portions of the electric field are dispersed. For this reason, the peak value of the electric field in the outer peripheral region 42 can be reduced. When there are a plurality of floating electrodes 18, the electric field tends to concentrate near the outer peripheral end of the floating electrode 18 toward the inner peripheral side. On the other hand, as in the first embodiment, the distance between two floating electrodes 18 that are adjacent to each other on the inner peripheral side is narrowed to further suppress electric field concentration near the outer peripheral end of the floating electrode 18 on the inner peripheral side. can do. Further, as in the first embodiment, by increasing the width of the inner peripheral floating electrode 18, electric field concentration near the outer peripheral end of the inner peripheral floating electrode 18 can be further suppressed. Further, since the electric field does not concentrate so much on the outer peripheral side, the semiconductor device 10 can be downsized by reducing the width of the floating electrode 18.

  As described above, in the semiconductor device 10 according to the first embodiment, electric field concentration in the outer peripheral region 42 is suppressed. For this reason, the semiconductor device 10 has a high breakdown voltage.

  FIG. 3 is a cross-sectional view of the semiconductor device 110 according to the second embodiment. In the semiconductor device 110 according to the second embodiment, the innermost floating electrode 18a is provided on the surface 12a of the semiconductor substrate 12 as in the first embodiment, and a plurality of floating electrodes at the outer peripheral side than the floating electrode 18a are provided. 18 b is provided on the surface of the interlayer insulating film 22. Of the floating electrodes 18b on the interlayer insulating film 22, the innermost floating electrode is disposed so as to overlap the outer peripheral end 19 of the floating electrode 18a. According to this configuration, electric field concentration at the outer peripheral end 19 of the floating electrode 18a can be suppressed. In the plurality of floating electrodes 18b, the width of the floating electrode 18b is wider toward the inner peripheral side, and the interval between two adjacent floating electrodes 18b is narrower toward the inner peripheral side. According to this configuration, electric field concentration in the vicinity of the floating electrode 18 on the inner peripheral side can be reduced. As described above, the electric field concentration in the outer peripheral region 42 can be reduced also by the configuration of the second embodiment.

  As described above, according to the configuration of the second embodiment, electric field concentration in the outer peripheral region 42 is suppressed. For this reason, the semiconductor device 110 has a high breakdown voltage.

Note that when the semiconductor substrate is made of a material such as GaN or Ga ₂ O ₃ that makes it difficult to form a p-type region, it is difficult to reduce electric field concentration by the p-type region. Since the structure of Examples 1 and 2 can relax the electric field by the floating electrode, it can also be used in a material in which it is difficult to form a p-type region.

  Further, in Examples 1 and 2, by making the relative dielectric constant of the interlayer insulating film 22 higher than the relative dielectric constant of the semiconductor substrate 12, in the vicinity of the outer peripheral ends of the surface electrode 16, the FP electrode 20, and the plurality of floating electrodes 18. Electric field concentration can be further suppressed. Further, in Examples 1 and 2, by making the relative dielectric constant of the protective insulating film 24 higher than the relative dielectric constant of the semiconductor substrate 12, in the vicinity of the outer peripheral ends of the surface electrode 16, the FP electrode 20, and the plurality of floating electrodes 18. Electric field concentration can be further suppressed. In this case, it is more effective that the relative dielectric constant of the protective insulating film 24 is higher than the relative dielectric constant of the interlayer insulating film 22.

  In the first and second embodiments, the case where the SBD is provided in the element region has been described. However, other semiconductor elements may be provided in the element region. For example, a pn diode may be provided in the element region. In Examples 1 and 2, a pn diode can be formed in the element region by providing a p-type region in ohmic contact with the surface electrode. Also in the pn diode, when a reverse voltage is applied, electric field concentration in the outer peripheral region is suppressed by the floating electrode. Further, for example, a MOSFET or IGBT may be provided in the element region. In the case of a MOSFET, the front electrode can be a source electrode and the back electrode can be a drain electrode. In the case of an IGBT, the front electrode can be an emitter electrode and the back electrode can be a collector electrode. In the case of MOSFET or IGBT, the electric field concentration in the outer peripheral region is suppressed by the floating electrode when these elements are in the off state.

  The embodiments have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical usefulness by achieving one of them.

DESCRIPTION OF SYMBOLS 10: Semiconductor device 12: Semiconductor substrate 14a: 1st metal layer 14b: 2nd metal layer 16: Surface electrode 18: Floating electrode 20: Field plate electrode 22: Interlayer insulating film 24: Protective insulating film 30: Back surface electrode 32: Cathode Region 34: Drift region 40: Element region 42: Peripheral region

Claims (1)

A semiconductor device,
A semiconductor substrate;
A surface electrode in contact with the surface of the semiconductor substrate;
A back electrode in contact with the back surface of the semiconductor substrate;
A field plate electrode;
A floating electrode;
Interlayer insulation film,
Have
The semiconductor substrate has an element region overlapping with a contact surface between the surface electrode and the semiconductor substrate when viewed in plan along the thickness direction of the semiconductor substrate, and an outer peripheral breakdown voltage region around the element region. And
The element region has a semiconductor element that can be energized between the front electrode and the back electrode,
The floating electrode is in contact with the surface in the outer peripheral pressure-resistant region and insulated from the surface electrode;
The interlayer insulating film covers the surface and the floating electrode in the outer peripheral breakdown voltage region;
The field plate electrode is disposed on the interlayer insulating film, and is electrically connected to the surface electrode;
The outer peripheral end of the field plate electrode is disposed on the floating electrode.
Semiconductor device.