JP2018018864A - Semiconductor element mounting substrate, semiconductor device, and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a semiconductor element mounting substrate and a semiconductor device capable of increasing the number of pins, miniaturizing, and high-density mounting, and a method of manufacturing the same. A semiconductor element mounting area provided in a predetermined area on the front side of a conductive substrate, an internal terminal portion provided around the semiconductor element mounting area and including the flat surface on the front side, and the internal terminal An external terminal portion provided apart from the portion and including the flat surface on the front side, and a first wiring for electrically connecting the internal terminal portion and the external terminal portion on at least the flat surface on the front surface side Part, a second wiring part electrically connecting the internal terminal part and the external terminal part, and having a height lower than the flat surface on the front side, and at least a surface of the conductive substrate. And a recessed area provided in a region other than the semiconductor element mounting region, the internal terminal portion, the external terminal portion, the first wiring portion, and the second wiring portion. [Selection diagram] Fig. 1

Description

  The present invention relates to a semiconductor element mounting substrate, a semiconductor device, and manufacturing methods thereof.

  In recent years, as represented by mobile phones and the like, downsizing and thinning of electronic devices have been promoted. For this reason, high density, small size, light weight, and high density mounting on a circuit board are also achieved for semiconductor devices used in such electronic devices.

  Conventionally, in a semiconductor device, a conductive substrate is etched or pressed to produce a lead frame, a semiconductor element is mounted on the lead frame, connection is made by wire bonding or the like, and then the whole is covered with a sealing resin. A semiconductor device was manufactured.

  However, for the purpose of downsizing and high density arrangement, a type of semiconductor device in which the conductive substrate is removed after resin sealing has been proposed.

  In such a semiconductor device, a resist mask subjected to predetermined patterning is formed on both surfaces of a conductive base material, and a conductive metal is provided as a plating layer on the base material exposed from the resist mask by plating. Then, by using the plating layer on the surface side as a mask, half-etching from the surface side forms a die pad portion for mounting a semiconductor element and a lead portion for external connection, and by removing the resist mask, a semiconductor element mounting substrate First form.

  Then, the semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, and the conductive substrate at a predetermined position is removed by etching using the plating layer on the back side as a mask, thereby the die pad portion. And the semiconductor device which separated the lead part is produced.

  For example, Patent Document 1 discloses a semiconductor device that removes such a conductive substrate.

  Further, in Patent Document 2 in which these semiconductor devices are miniaturized and thinned and at the same time advanced in high-density mounting, a method such as removing the substrate after sealing the above wiring layer with a sealing resin, A Fan-In type semiconductor device in which an external terminal is also arranged below the die pad portion is disclosed. As a result, a plurality of rows of external terminal portions can be arranged, and the number of pins has been increased.

JP 2007-150372 A JP 2013-80957 A

  However, in the semiconductor device described in Patent Document 2, it is necessary to arrange a wiring portion that connects the internal terminal portion and the external terminal portion, and there is a limit to disposing a plurality of wiring portions between the external terminal portions. For this reason, for example, a TAB (Tape Automated Bonding) tape in which a copper foil is laminated on a tape base material such as a polyimide tape is used in a multi-pin semiconductor device having an external terminal portion exceeding 200 pins instead of a conductive substrate. . Since the polyimide tape is expensive and the manufacturing process is complicated, there is a problem that the cost is higher than that of a semiconductor device using a conductive substrate.

  Therefore, the present invention has been made in view of the above problems, and in a semiconductor device in which a semiconductor element is mounted on a substrate for mounting a semiconductor element, and a die pad portion and a lead portion are separated by etching from the back surface after resin sealing. An object of the present invention is to provide a semiconductor element mounting substrate and a semiconductor device, and a method of manufacturing the same, which can have a larger number of pins, a smaller size, and a higher density mounting than in the past.

In order to achieve the above object, a semiconductor element mounting substrate according to one embodiment of the present invention includes a semiconductor element mounting region provided in a predetermined region on the surface side of a conductive substrate,
An internal terminal portion provided around the semiconductor element mounting region and including a flat surface on the surface side;
An external terminal portion provided apart from the internal terminal portion and including a flat surface on the surface side;
A first wiring portion that electrically connects the internal terminal portion and the external terminal portion on at least the flat surface on the surface side;
Electrically connecting the internal terminal portion and the external terminal portion, a second wiring portion provided with a height lower than the flat surface on the surface side;
At least a semiconductor element mounting region on the surface side of the conductive substrate, the internal terminal portion, the external terminal portion, the recessed region provided in a region other than the first wiring portion and the second wiring portion, Have.

  According to the present invention, it is possible to provide a semiconductor element mounting substrate and a semiconductor device that can be multi-pinned, miniaturized, and mounted with high density.

It is a figure which shows an example of the board | substrate for semiconductor element mounting which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the wiring part of the board | substrate for semiconductor element mounting which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the manufacturing method of the wiring part of the board | substrate for semiconductor element mounting which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows an example of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device which concerns on the modification of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows an example of the board | substrate for a Fan-In type semiconductor element mounting which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows an example of the Fan-In type semiconductor device which concerns on the 2nd Embodiment of this invention. It is the figure which showed an example of the Fan-In type semiconductor device of this invention. It is the figure which showed the series of processes of the first half of an example of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the figure which showed a series of processes of the latter half of an example of the manufacturing method of the semiconductor element mounting substrate which concerns on the 1st Embodiment of this invention. It is a figure which shows a series of processes of the first half of an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows a series of processes of the latter half of an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

[First Embodiment]
<Semiconductor element mounting substrate>
A semiconductor element mounting substrate according to a first embodiment of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing an example of a semiconductor element mounting substrate (hereinafter also referred to as “lead frame”) according to the first embodiment of the present invention. In FIG. 1, not a cross section along the wiring portion 50 but a cross section cut along a line intersecting the wiring portion 50 is shown.

  As shown in FIG. 1, a semiconductor element mounting substrate 100 according to the first embodiment is connected to a conductive substrate 10, a semiconductor element mounting portion 22 functioning as a semiconductor element mounting region 20, and an electrode of the semiconductor element. An internal terminal portion 30 for connecting to the external device (not shown), a wiring portion 50 for electrically connecting the internal terminal portion 20 and the external terminal portion 40, a first It has a depression region 60, a second depression region 70, a surface plating layer 80, and a back plating layer 81. The entire portion below the semiconductor element mounting region 20 may be called a die pad portion.

  Note that, depending on the pattern, there is a pattern in which the semiconductor element mounting portion 22 is not manufactured after the semiconductor element mounting area 20 is secured. That is, in the present embodiment, it is not essential to provide the semiconductor element mounting portion 22, and it is only necessary to secure the semiconductor element mounting area 20 on which the semiconductor element can be mounted. For example, the substrate for mounting a semiconductor element of the present invention has a semiconductor mounting region 20 and a semiconductor device such as a Fan-In type in which the external terminal portion 40 is disposed on the lower surface of the semiconductor element, or an internal terminal portion by flip chip bonding. The present invention can also be applied to a semiconductor device in which an electrode of a semiconductor element is directly bonded to 30. Hereinafter, in the first embodiment, the semiconductor element mounting substrate 100 having a pattern with the semiconductor element mounting portion 22 will be described.

  The material of the conductive substrate 10 is not particularly limited as long as conductivity is obtained. For example, copper or a copper alloy may be used. In order to dissolve and remove a predetermined portion of the conductive substrate 10 after sealing the resin, generally, copper or a copper alloy that can be selectively dissolved and removed is often used.

  In the semiconductor element mounting substrate 100 according to the first embodiment, the constituent portions of the semiconductor element mounting portion 22, the internal terminal portion 30, and the external terminal portion 40 are left unprocessed without the conductive substrate 10 being etched. It consists of a flat area. On the other hand, the first dent region 60 and the second dent region 70 (hereinafter simply referred to as “dent regions 60, 70”) are formed by etching the conductive substrate 10 from the surface side. The remaining portion of the conductive substrate 10 after etching, that is, the lower region of the recessed regions 60 and 70 constitutes the back surface connecting portion 11. Further, a surface plating layer 80 is formed by electroplating on the surface of the semiconductor element mounting portion 22 and the internal terminal portion 30, and the back surface of the semiconductor element mounting portion 22 and the external terminal portion 40 is also back electroplated. A plating layer 81 is formed.

  The internal terminal portion 30 and the external terminal 40 are electrically connected by the wiring portion 50 and further connected by the back surface connecting portion 11 formed by etching the conductive substrate 10. Further, the semiconductor element mounting portion 22 is connected to the inner and outer terminal portions 30 and 40 and the wiring portion 50 by the back surface connecting portion 11.

  The surface plating layer 80 is formed on at least the surface of the internal terminal portion 30. When the semiconductor element mounting portion 22 is formed, the surface plating layer 80 may also be formed on the surface of the semiconductor element mounting portion 22. The type of plating metal used for the surface plating layer 80 is not particularly limited, but is selected in consideration of the following points.

  Since the uppermost surface of the surface plating layer 80 of the internal terminal portion 30 includes a portion functioning as an internal electrode connected by wire bonding to the electrode of the semiconductor element, a plating metal suitable for connection of a bonding wire or the like is selected. For example, in the case of an Au wire, Ag plating, Au plating, Pd plating, or the like is preferable.

  The back plating layer 81 is formed at least on the external terminal portion 40. When the semiconductor element mounting portion 22 is formed, the back plating layer 81 may also be formed on the back surface of the semiconductor element mounting portion 22. Since the back surface plating layer 81 of the external terminal portion 40 includes a portion that functions as an external electrode connected to an external device, a plating metal suitable for connection to the external device is selected. For connection to an external device, since there are generally many solder-based alloys such as solder balls, Au (gold) plating, Pd plating, etc., which have good solder wettability and good bondability with solder, are preferable.

  Furthermore, since the surface plating layer 80 and the back surface plating layer 81 are generally formed by performing electroplating simultaneously, the same plating configuration is desirable. For example, multi-layer plating in which Ni, Pd, and Au are laminated in this order from the contact surface of the conductive substrate 10 to the outside may be used.

  Further, the types of plating of the front plating layer 80 and the back plating layer 81 may be different. For example, the surface may be Ag plating with good bonding properties, and the back surface may be laminated plating in which Ni, Pd, and Au are laminated in order of good solder wettability.

  Note that a plating layer such as the external terminal back surface plating layer 43 is not formed on the back surfaces of the internal terminal portion and the wiring portion.

  In areas corresponding to portions other than the semiconductor element mounting portion 22, the internal terminal portion 30, the external terminal portion 40, and the wiring portion 50 of the conductive substrate 10, recessed regions 60 and 70 are provided by etching from the surface side.

  By forming the recessed regions 60 and 70, the semiconductor element mounting portion 22, the internal terminal portion 30, the external terminal portion 40, and the wiring portion 50 are formed. Further, since the back surface side of the conductive substrate 10 is not etched and no depression is formed, the back surface side is connected with the entire material surface.

  In addition, about the back surface connection part 11, a semiconductor element mounting part, an internal terminal part, and an external terminal part are each removed by an etching process from a back surface side using a back surface plating layer as a mask after mounting a semiconductor element and resin-sealing. Make it independent.

  Here, the depth of the recessed regions 60 and 70 to be provided is from 1/2 of the plate thickness of the conductive substrate 10 to -0.03 mm.

  If the depth of the dent is less than 1/2 of the plate thickness, the amount of etching processing after resin sealing increases, the etching time becomes longer, and the etching solution etches a part of the plating layer. It tends to occur. If the plate thickness exceeds -0.03 mm, the formed back surface connecting metal portion becomes thin, and there is a possibility that deformation defects may occur during conveyance. The plate thickness is preferably -0.05 mm to plate thickness -0.03 mm.

  Next, the wiring part which is a feature of the present invention will be described with reference to FIGS. FIG. 2 is a diagram showing an example of a wiring portion of the semiconductor element mounting substrate according to the first embodiment of the present invention. FIG. 2A is an enlarged view showing an example of the wiring portion of the present invention. FIG. 2B is an enlarged view showing an example of a conventional wiring section.

  As shown in FIG. 2B, the conventional wiring part 250 is formed to have a certain width on the same surface as the upper surfaces of the internal terminal part 230 and the external terminal part 240. The wiring part 250 is configured to electrically connect the external terminal part 240 and the internal terminal part 230. Since the internal terminal portion 230 is connected to the electrode of the semiconductor element by a bonding wire or the like, it is disposed around the semiconductor element. The external terminal portions 240 are generally arranged in one row around the outer shape of the semiconductor device. However, due to the increase in the number of pins, a plurality of rows such as two rows and three rows may be arranged around the outer shape. Further, as will be described later, Fan-In in which a die pad portion is not formed, a semiconductor element mounting area is secured, a semiconductor element is mounted with an insulating adhesive, and the like, and an external terminal is also disposed on the lower surface of the semiconductor element. There is also a type. In this type, external terminals are arranged in a matrix. For this reason, the external terminal part 240 and the internal terminal part 230 are electrically connected by the wiring part 250. At this time, conventionally, for example, as disclosed in Patent Document 2, the wiring portion 250 secures a certain width, and a plurality of wiring portions 250 are formed between the external terminal portions 240. The width of the wiring part 250 is 0.06 mm to 0.15 mm, although it is affected by the depth of the depression from the surface side. With the miniaturization of semiconductor devices or the increase in the number of pins, there is a demand for reducing the width of the wiring portion 250. However, 0.06 mm or more is necessary to secure the width of the wiring portion 250 in the etching process. If the width is less than 0.06 mm, the adhesion between the resist mask and the conductive substrate is reduced, and the etching process is performed. There is a high possibility that the wiring portion 250 cannot be processed normally.

  The inventor has found the present invention as a result of trial and error. A part of the wiring part 50 that connects the external terminal part 40 and the internal terminal part 30 of the semiconductor element mounting substrate 100 according to the first embodiment of the present invention is on the surface side on which the surface plating layer 80 is formed. The inner terminal portion 30 is formed lower than the height. Further, the cross-sectional shape perpendicular to the longitudinal direction (extending direction) of the wiring part 50 formed lower than the height of the internal terminal part 30 has a convex shape protruding toward the surface on which the surface plating layer 80 is formed. doing.

  Conventionally, as shown in Patent Document 1, when forming a surface plating layer as a mask at the time of recess processing by etching from the surface side for forming the shape of the internal terminal portion 230 and the external terminal portion 240, the wiring portion A plating layer is also required on 250, and a flat portion is also required on the lower wiring portion 250. Although details will be described later, in the manufacturing process of the semiconductor element mounting substrate 100 according to the first embodiment of the present invention, the surface plating layer is not used as a mask at the time of the recess processing from the front side, but for the recess processing. Use a special resist. Thereby, it is not necessary to form the surface plating layer 80 on the wiring part 50. In the present invention, as shown in FIG. 2A, the wiring part 50 is formed lower than the height of the internal terminal part 30. And the cross-sectional shape orthogonal to the longitudinal direction of the wiring part 50 is convex on the surface side. The internal terminal part 30 and the external terminal part 40 are connected by a wiring part 50 having a convex cross section. By forming the wiring part 50 in such a protruding shape with a sharp tip, the flat part on the upper surface of the wiring part 250, which has been conventional, is eliminated, and the wiring part pitch can be reduced accordingly. The width of the conventional wiring portion 250 is 0.06 mm to 0.15 mm, and the wiring portion pitch can be reduced accordingly. In addition, since the height of the internal terminal part 30 is the same as the height of the semiconductor element mounting part 22 and the external terminal part 40, naturally the height of the wiring part 50 is the semiconductor element mounting part 22 and the external terminal part 40. Lower than height.

  The wiring part 50 of the semiconductor element mounting substrate 100 according to the first embodiment is manufactured by the method shown in FIG.

  FIG. 3 is a diagram showing an example of a method for manufacturing a wiring portion of the semiconductor element mounting substrate according to the first embodiment of the present invention. FIG. 3A is an enlarged view showing the wiring portion before etching. FIG. 3B is an enlarged view showing the initial stage of etching of the wiring portion. FIG. 3C is an enlarged view showing the middle stage of etching of the wiring portion. FIG. 3D is an enlarged view showing completion of etching of the wiring portion.

  When a flat portion is formed in the conventional wiring portion 250, a resist mask slightly larger than the width of the flat portion is produced. This is because the etching is performed not only on the lower side but also in the lateral direction during etching, so that the lower side of the end portion of the resist mask is also removed. Therefore, in the present invention, using this, an etching rate control resist 172 is formed in the wiring portion 50 as shown in FIG. Next, as shown in FIG. 3B, etching is started from the surface side. In FIG. 3C, the etching process proceeds also in the lateral direction, and the flat part at the upper part of the wiring part disappears. In FIG. 3D, the etching is completed, and the wiring portion 50 is formed lower than the height of the internal terminal portion 30, and a convex pointed shape is formed on the upper surface. In FIG. 3D, the tip of the convex shape has an acute angle, but the apex has a curved surface shape because it is etched. From the upper surface of the internal terminal portion 30, it is preferably formed 0.01 to 0.03 mm lower. If it is less than 0.01 mm, the tip portion remains in a needle shape, which may drop off and cause a problem. Further, if the thickness exceeds 0.03 mm, the thickness of the wiring portion becomes thin when the semiconductor device is formed, and there is a possibility of causing problems such as use interruption lines. Furthermore, the adhesiveness with the sealing resin is lowered.

  In the present invention, the etching rate control resist 172 formed on the wiring portion 50 is important. The etching rate control resist 172 is disposed along the longitudinal direction of the 50 parts of the wiring. The width of the etching rate control resist 172 is set so that the height of the wiring portion 50 is lower than the upper surface of the internal terminal portion 30. Note that the height of the wiring portion 50 is appropriately adjusted depending on the concentration of the etching solution, the discharge pressure of the etching solution, and the like. Further, the width of the etching rate control resist 172 is also affected by the size of the area where the recess processing is performed on both sides of the wiring portion 50. In the case of being densely packed, the width is narrowed because the etching solution is difficult to rotate, and in the case where both sides are wide, the width is widened because the etching rate is increased. Considering these, the width of the etching rate control resist 172 is set so that a uniform convex shape can be formed in the longitudinal direction of the wiring portion 50.

  In addition, the wiring part 250 of the prior art may be formed as long as there is a sufficient area for performing recess processing on both sides of the wiring part 50 and a flat part can be provided on the upper surface of the wiring part 50. The wiring portion 50 formed lower than the height of the internal terminal portion 30 may be formed at a location where the interval between the external terminal portion 40 or the internal terminal portions 30 is narrow, and it is not necessarily required to be formed at a location where the interval is wide. . Therefore, a part of the wiring portion has a projection shape with a sharp tip as described above.

<Semiconductor Device of First Embodiment>
Next, a semiconductor device using the above-described semiconductor element mounting substrate 100 as a lead frame will be described with reference to FIG. FIG. 4 is a cross-sectional view showing an example of a semiconductor device according to the first embodiment of the present invention. In FIG. 4, a cross-sectional view cut along a line that intersects the wiring portion 50 is shown instead of a cross-section along the wiring portion 50.

  In the semiconductor device 200 according to the first embodiment of the present invention, the semiconductor element 110 is mounted in the semiconductor element mounting region 20 using the semiconductor element mounting substrate 100 described above.

  In FIG. 4, a case where the semiconductor element mounting portion 22 is formed and the semiconductor element 110 is mounted thereon will be described. There is a type in which the semiconductor mounting area 20 is secured and the semiconductor element mounting portion 22 is not formed. For example, a Fan-In type semiconductor device in which the external terminal portion 40 is disposed on the lower surface of the semiconductor element 110 or a flip-chip bonded semiconductor device.

  A semiconductor element 110 is mounted on the semiconductor element mounting portion 22, and an electrode (not shown) of the semiconductor element 110 and a surface plating layer 80 formed on the upper surface of the internal terminal portion 30 are electrically connected by a bonding wire 120 or the like. Has been. The internal terminal part 30 and the external terminal part 40 are connected via the wiring part 50. A back plating layer 81 is formed on the back surface of the external terminal portion 40.

  Furthermore, the surfaces of the semiconductor element 110, the bonding wire 120, the internal terminal portion 30, the external terminal portion 40, and the wiring portion 50 are sealed with the first resin 130 and are entirely covered.

  Thereafter, the sealed semiconductor element mounting substrate 100 is etched from the back side to form the external terminal portion 40, the internal terminal portion 30, and the wiring portion 50, and the external terminal portion 40, the internal terminal portion 30, and the wiring. Each part 50 is made independent.

  In this etching process, the terminals 30, 40, and 50 are separated and independent by etching the back surface connecting portion 11 in the lead frame of FIG. Further, since this etching process is performed using the back plating layer 81 as a mask, the external terminal part 40 having the back plating layer 81 is not etched from the back side, but the internal terminal part 30 and the wiring part 50 are provided on the back plating layer 81. Since is not formed, it is etched from the back surface to form a thin portion. The semiconductor element mounting portion 22 is the same as the external terminal portion 40 when the back plating layer 81 is formed, and is a thin portion similar to the internal terminal portion 30 when the back plating layer 81 is not formed. FIG. 4 shows a case where the semiconductor element mounting portion 22 includes a back plating layer 81.

  That is, the semiconductor element mounting portion 22 and the external terminal portion 40 have the original thickness of the conductive substrate 10. On the other hand, the internal terminal part 30 is thinner than the thickness of the semiconductor element mounting part 22 and the external terminal part 40 by etching from the back side. Since the wiring portion 50 is etched from the back surface in the same manner as the internal terminal portion 30, the bottom surface has substantially the same height as the internal terminal portion 30. The reason for being substantially the same is that the difference in etching is taken into account. If the etching amount is the same, the bottoms of the wiring part 50 and the internal terminal part 40 have the same height, and both the bottoms are on the same horizontal plane. In addition, as described above, the heights of the upper surfaces of the semiconductor element mounting portion 22, the internal terminal portion 30, and the external terminal portion 40 are the same, but the apex (tip) of the wiring portion 50 is the semiconductor element mounting portion 22, It is lower than the upper surfaces of the terminal portion 30 and the external terminal portion 40 and lower than the upper end of the recessed region 60. The upper surfaces of the semiconductor element mounting portion 22, the internal terminal portion 30, and the external terminal portion 40 are the same height as the upper end of the recessed region 60, which is the same surface as a flat surface that is an unprocessed surface of the conductive substrate 10. It is. The semiconductor element mounting part 22, the internal terminal part 30, the external terminal part 40, and the wiring part 50 of the semiconductor device 200 according to the first embodiment have the dimensions and arrangement relationships as described above in the height direction. With this configuration, a narrow-pitch semiconductor device 200 is realized.

  The side surface of the back surface plating layer 81 of the external terminal portion 40, the side surface of the external terminal portion 40, the back surface of the internal terminal portion 30 and the wiring portion 50 are covered with the second sealing resin 140, and the back surface plating layer of the external terminal portion 40 81 and the back plating layer 81 of the semiconductor element mounting portion 22 are exposed from the second resin 140. This exposed surface is for connection with an external device.

  The internal terminal portion 30 and the wiring portion 50 are thin portions as described above, and are not exposed from the second sealing resin portion 103, and there is no risk of contact with an external device. The first resin 130 and the second resin 140 may be of the same type or different types. FIG. 4 shows an example where the first resin 130 and the second resin 140 are different. In addition, the second resin 140 may be molded in the same manner as the first resin 130, or the second resin 140 is installed so that the back surface side of the semiconductor device 200 faces upward. A thin insulating thin film may be formed by dropping the resin 140.

  FIG. 5 is a cross-sectional view showing a semiconductor device 201 according to a modification of the semiconductor device 200 according to the first embodiment of the present invention. In the semiconductor device 201 according to the modified example, the second resin on the back surface side is made of the same type of resin 130 as the first resin 130 on the front surface side, and the second resin on the back surface side is molded as well as the first resin 130. This is an example of molding.

  A feature of the semiconductor devices 200 and 201 according to the first embodiment of the present invention is that at least a part of the wiring portion 50 that connects the internal terminal portion 30 and the external terminal portion 40 is formed from the upper surface of the internal terminal portion 20. It is formed on the lower side. Since the semiconductor devices 200 and 201 according to the first embodiment are manufactured using the above-described semiconductor element mounting substrate 100, the wiring part 50 is formed below the upper surface of the internal terminal part 30. Further, after mounting the semiconductor element 110 and sealing with the first resin 130, the back surface connecting portion 11 is etched to separate the semiconductor element mounting portion 22 and the terminals 30 and 40 from each other. Here, the wiring part 50 has a substantially triangular cross-sectional shape perpendicular to the wiring longitudinal direction. The substantially triangular shape is formed so that the height is about 0.1 mm and the base length is about 0.1 mm.

  The depth of the etching process is equal to the thickness of the back surface connecting portion 11 of the semiconductor element mounting substrate 100, but this thickness is preferably 0.03 mm to 0.05 mm. If the thickness of the back surface connecting portion 11 is less than 0.03 mm, the strength of the semiconductor element mounting substrate 100 itself becomes weak, causing problems such as conveyance. On the other hand, when the thickness of the back surface connecting portion 11 exceeds 0.05 mm, after the front surface side is sealed with the first resin 130, the amount of etching from the back surface side increases, and the variation during etching increases. If it does so, the location which cannot fully secure the thickness of the wiring part 50 will generate | occur | produce, and problems, such as a use interruption line, may be caused. When manufacturing the semiconductor devices 200 and 201 according to the first embodiment of the present invention, it is important to appropriately manage the etching amount from the back surface after sealing the front surface side with the first resin 130.

  Further, the wiring portion 50 has a convex shape on the upper surface, and since it is easy to drop off from the first resin 130 only by sealing from the front surface side, the wiring portion 50 is sealed from the back surface side by the second resin 140. Also good. Sealing from the back side with the second resin 140 can prevent the wiring part 50 from falling off.

  If there are sufficient areas on both sides of the wiring part 50 and a flat part can be provided on the upper surface of the wiring part 50, the wiring part 250 of the prior art may be formed. The wiring portion 50 formed lower than the height of the internal terminal portion 30 is at least in the region when the wiring portion 50 needs to be arranged in a region where the interval between the external terminal portion 40 or the internal terminal portions 30 is narrow. Is formed. Therefore, a part of the wiring portion has the above-described shape.

[Second Embodiment]
Next, a semiconductor element mounting substrate according to a second embodiment of the present invention will be described with reference to FIGS.

  The embodiment described so far is an example of a fan-out type in which the semiconductor element 110 is mounted on the semiconductor element mounting portion 22 and the external terminal portion 40 is disposed outside the semiconductor element mounting region 20.

  In contrast to the Fan-Out type, the semiconductor element mounting substrate 101 according to the second embodiment secures the semiconductor element mounting region 20a and arranges the external terminal portion 40 on the lower surface of the semiconductor element as shown in FIG. This is an example of the Fan-In type as shown.

  FIG. 8 is a diagram illustrating an example of a Fan-In type semiconductor device. FIG. 8A is a plan view of the Fan-In type semiconductor device, and FIG. 8B is a partially enlarged view of a portion A surrounded by a broken line in FIG. FIG. 8A shows a planar configuration in which an FI external terminal (external terminal arranged below the semiconductor element) 40a is provided in the semiconductor element mounting region 20a. As described above, in the Fan-In type semiconductor device, the internal terminal portion 30 is disposed around (outside) the semiconductor element mounting region 20 a, but the external terminal portions 40 and 40 a are separated from the internal terminal portion 30. What is necessary is just to arrange | position not only as the external terminal part 40 outside the internal terminal part 30, but inside the internal terminal part 30, and is also arrange | positioned as the FI external terminal 40a also in the semiconductor element mounting area | region 20. FIG. Note that, as shown in FIG. 8B, the wiring portion 50 is electrically connected to the internal terminal portion 30 and the external terminal portions 40 and 40a in the same manner as the Fan-Out type.

<Semiconductor element mounting substrate>
FIG. 6 is a cross-sectional view showing an example of a Fan-In type semiconductor element mounting substrate 101 according to the second embodiment. The Fan-In type semiconductor element mounting substrate 101 according to the second embodiment has an FI external terminal portion 40a disposed below the semiconductor element. The upper surface of the FI external terminal portion 40a functions as the semiconductor element mounting region 20a. A back plating layer 81a is formed on the lower surface (back surface) of the FI external terminal portion 40a.

  The semiconductor element mounting substrate 101 according to the second embodiment of the present invention does not have the dedicated semiconductor element mounting region 20 formed of the semiconductor element mounting portion 22, and includes a plurality of FI external terminal portions 40a including the back plating layer 81a. The semiconductor element 110 is mounted across the surface of the plurality of FI external terminal portions 40a. Therefore, the semiconductor element mounting region 20a shown in FIG. 6 constitutes a part of the entire semiconductor element mounting region 20a. The back plating layer 81a of the FI external terminal portion 40a is used for connection to an external device as in the case of the external terminal 40, and the other forms are the same as those of the semiconductor element mounting substrate 100 according to the first embodiment. The structure is adopted. The FI external terminal portion 40a may be referred to as a semiconductor element mounting portion 40a because the upper surface constitutes the semiconductor element mounting region 20a and has a function as a semiconductor element mounting portion.

  Thus, the semiconductor element mounting substrate of the present invention can also be applied to the Fan-In type semiconductor element mounting substrate 101. Even in this case, the internal terminal portion 30 and the external terminal portion 40 are electrically connected to the wiring portion 50 having a height lower than that of the internal terminal portion 30, and the internal terminal portion 30 and the FI external terminal portion 40a are connected to each other. The wiring part 50 whose height is lower than that of the internal terminal part 30 is electrically connected. Thereby, even if it is an area | region where the space | interval of the internal terminal parts 30 or the space | interval of the external terminal parts 40 and 40a is narrow, the internal terminal part 30 and the external terminal parts 40 and 40a generate malfunctions, such as a short circuit. It can be securely connected without any problems.

<Semiconductor device>
FIG. 7 is a cross-sectional view illustrating an example of a Fan-In type semiconductor device according to the second embodiment. As shown in FIG. 7, the semiconductor device 202 according to the second embodiment has an FI external terminal portion 40a, and the semiconductor element mounting region 20a on the upper surface thereof is interposed with an insulating adhesive 150 or the like. A semiconductor element 110 is mounted. Note that the semiconductor element 110 is mounted so as to straddle the plurality of FI external terminal portions 40a as described above.

  The semiconductor device 202 according to the second embodiment shown in FIGS. 7 and 8 includes a plurality of FI external terminal portions 40a including a back plating layer 81a in the semiconductor element mounting region 20a, and the plurality of FI external terminal portions 40a. The semiconductor element 101 is mounted using an insulating adhesive 150 or the like so as to straddle each semiconductor element mounting region 20a, and has a fixed structure. Then, the electrode 111 of the semiconductor element 110 is connected to the surface plating layer 80 of the internal terminal portion 30, and the front side and the back side are sealed with the first resin 130 and the second resin 140. Since the portion (back surface plating layers 81 and 81a) responsible for connection is also provided on the back surface immediately below the semiconductor element 110, the structure corresponds to miniaturization and high-density mounting of the semiconductor device 202.

<Manufacturing method of semiconductor element mounting substrate>
Next, as a method for manufacturing the semiconductor element mounting substrate of the present invention, a method for manufacturing the semiconductor element mounting substrate 100 according to the first embodiment will be described with reference to FIGS.

  The semiconductor devices 200 and 201 according to the first embodiment are Fan-Out type semiconductor devices, which form the semiconductor element mounting portion 22 on which the semiconductor element 110 is mounted, and the back plating layer 81 of the semiconductor element mounting portion 22. An example in which the FI external terminal 40a is exposed from the second resin 140 will be described, but an example in which the FI external terminal 40a is arranged on the lower surface of the semiconductor element 110 as in the Fan-In type according to the second embodiment will be sequentially described.

  In the following description, the same constituent elements as those described above are denoted by the same reference numerals as those described above, and the description thereof is omitted.

(Conductive substrate preparation process)
FIG. 9 is a diagram showing a series of steps in the first half of an example of the method for manufacturing the semiconductor device 100 according to the first embodiment.

  FIG. 9A is a diagram illustrating an example of a preparation process for preparing a conductive substrate. In the step of preparing the conductive substrate, the conductive substrate 10 is prepared. The material of the conductive substrate 10 is not particularly limited as long as conductivity is obtained, but a Cu alloy is generally used.

(First resist coating step)
FIG. 9B is a diagram illustrating an example of the first resist coating process. The first resist is used as a mask resist for the front plating layer and the back plating layer.

  In the first resist coating step, both surfaces of the conductive substrate 10 are coated with a resist 160. As the resist 160 to be used, a conventional method such as laminating a dry film resist or applying a liquid resist to both surfaces of the conductive substrate 10 can be used.

(First exposure / development process)
FIG. 9C is a diagram showing an example of the first exposure / development process. In the first exposure step, exposure masks (not shown) are placed above and below the first resist 160 in an exposure apparatus (not shown), and exposure is performed by irradiating with ultraviolet light (not shown). I do. In addition, the pattern of an exposure mask is produced so that the surface plating layer 80 may be formed in the surface side, and the back surface plating layer 81 may be formed in the back surface side. When the semiconductor element mounting portion 22 is formed, a pattern is formed so that the back plating layer 81 is also formed on the back surface side of the semiconductor element mounting portion 22. Thereby, an unexposed portion is formed in the resist 160.

  After the exposure, in the first developing step, the unexposed portion of the resist 160 is removed, and an opening 161 is formed. Thereby, a part of the conductive substrate 10 is exposed from the opening 161. Thus, the resist 160 having the opening 161 is configured as the plating masks 162 and 163.

  In the case where the FI external terminal portion 40a and the like are disposed under the semiconductor element mounting region 20a without forming the semiconductor element mounting portion 22, a mask pattern in which the back plating layer 81a and the like are disposed is produced.

(Plating / first resist removal process)
FIG. 9D is a diagram illustrating an example of the plating / first resist removing step. In the plating process, the resist 160 formed with the opening 161 formed in the first development process shown in FIG. 9C is used as the plating masks 162 and 163 and is not covered with the plating masks 162 and 163. The opening 161 is plated to form a surface plating layer 80 on the front side and a back plating layer 81 on the back side.

  Thereafter, the resist 160 formed as the plating masks 162 and 163 is peeled and removed. The first resist stripping may be performed using, for example, a liquid resist stripper. By the first resist peeling, the resist 160 is removed, and the conductive substrate 10 is in a state where the surface plating layer 80 and the back surface plating layer 81 are formed.

(Second resist coating step)
FIG. 10 is a diagram showing a series of steps in the latter half of the example of the method for manufacturing the semiconductor element mounting substrate 100 according to the first embodiment of the present invention.

  FIG. 10A is a diagram illustrating an example of the second resist coating process. In the second resist coating step, both surfaces of the conductive substrate 10 are covered with the resist 170 in a state where the surface plating layer 80 and the back surface plating layer 81 are formed on the conductive substrate 10. As the resist 170, a conventional method such as laminating a dry film resist or applying a liquid resist can be used as in the first resist coating step described with reference to FIG.

(Second exposure / development process)
FIG. 10B shows an example of the second exposure / development process. In the second exposure step, exposure masks (not shown) are placed above and below the resist 170 in an exposure apparatus (not shown), and exposure is performed with ultraviolet light (not shown). A front-side exposure mask (not shown) used in the second exposure step covers the internal terminal portion 30 and the semiconductor element mounting portion 22 on which the surface plating layer 80 of the conductive substrate 10 is formed, and external terminals. About the area | region which forms the part 40, and the area | region which forms a wiring part, the pattern of the predetermined opening part 171 is formed and covered so that a predetermined shape may be formed. On the back side, a pattern covering the entire surface is formed.

  A speed control resist pattern 172 is formed at a location where the wiring portion 50 is to be formed. The pattern size position and the like are as described above. Note that a pattern of the resist 170 having a width wider than that of the speed control resist pattern 172 is formed at a portion where the wiring portion 250 having a flat surface as in the related art is formed.

  Next, in the second development step, the unexposed portion is removed, and a resist 170 having an opening 171 is formed as an etching mask 173.

(Etching process)
FIG.10 (c) is a figure which shows an example of the etching process etched from the surface. In the etching process, the surface of the conductive substrate 10 is etched with an etching solution using the resist 170 having the opening 171 formed in FIG. Form. Thereby, the semiconductor element mounting part 22, the internal terminal part 30, the external terminal part 40, and the back surface connection part 11 are formed.

  In the Fan-In type, the semiconductor element mounting portion 22 is not formed, and the FI external terminal portion 40a and the like are formed under the semiconductor element mounting region 20a.

(Second resist removal step)
FIG. 10D is a step of removing the second resist. The second resist removal may be performed using, for example, a liquid resist remover. Thereafter, if necessary, the sheet may be cut into a predetermined size.

  With the above manufacturing method, the semiconductor element mounting substrate 100 according to the first embodiment of the present invention is completed.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device using the semiconductor element mounting substrate of the present invention will be described with reference to FIGS.

  FIG. 11 is a diagram showing a series of steps in the first half of an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention, which is the method for manufacturing the semiconductor device shown in FIG.

(Semiconductor element mounting process)
FIG. 11A is a diagram illustrating an example of a semiconductor element mounting process. In the semiconductor element mounting step, the semiconductor element 110 is mounted on the semiconductor element region 20 of the semiconductor element mounting substrate 100. Here, when the semiconductor element mounting portion 22 is present, the semiconductor element 110 is mounted using Ag paste or the like. FIG. 11A shows an example in which the semiconductor element 110 is mounted on the semiconductor element mounting portion 22.

  On the other hand, when the FI external terminal portion 40a is disposed under the semiconductor element 110, the semiconductor element 110 is mounted via an insulating adhesive layer, for example, an insulating adhesive 150 (see FIG. 7).

  When the FI external terminal portion 40a and the wiring portion 50 are disposed in the semiconductor element region 20a, the semiconductor element 110 is mounted thereon.

(Wire bonding process)
FIG. 11B is a diagram illustrating an example of a wire bonding process. In the wire bonding step, the electrode 111 of the semiconductor element 110 and the surface plating layer 80 of the internal terminal portion 30 are electrically connected using a bonding wire 120 or the like.

(First resin sealing step)
FIG. 11C is a diagram illustrating an example of the first resin sealing step. In the first resin sealing step, the surface of the back surface connecting portion 11 including the semiconductor element 110, the bonding wire 120, the internal terminal portion 30, the external terminal portion 40, the wiring portion 50, and the semiconductor element mounting portion 22 is the first surface. The resin 130 is sealed.

(Etching step after first resin sealing)
FIG. 12 is a diagram illustrating a series of steps in the latter half of the example of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

  FIG. 12A is a diagram illustrating an example of an etching process after resin sealing. In the etching process after resin sealing, etching is performed using the back plating layer as a mask from the lower (back side) direction not sealed with the first resin 130. Thereby, it divides | segments separately for every terminal and will be in an independent state, respectively.

(Second resin sealing step)
FIG. 12B is a diagram illustrating an example of the second resin sealing step. In the second resin sealing step, the side surfaces of the external terminal portion 40 and the semiconductor element mounting portion 22, the back surfaces of the internal terminal portion 30 and the wiring portion 50, and the like are sealed with the second resin 140. However, the back surface plating layer 81 of the external terminal portion 40 and the back surface plating layer 81 of the semiconductor element mounting portion 22 are exposed from the second resin 140 and function as external connection terminals.

  Finally, the semiconductor device 200 according to the first embodiment of the present invention is completed by cutting into a predetermined size of the semiconductor device 200.

[Example]
Hereinafter, the present invention will be described in detail using examples.

[Example 1]
(Conductive substrate preparation process)
A Cu plate (Furukawa Electric Co., Ltd .: EFTEC64-T) having a plate thickness of 0.2 mm was processed as a conductive substrate into a long plate shape having a width of 140 mm.

(First resist coating step)
Next, a photosensitive dry film resist having a thickness of 0.025 mm was attached to both surfaces of the conductive substrate.

(First exposure / development process)
Next, on the front side, the surface plating layer of the internal terminal part and the position where the surface plating layer of the die pad part is to be formed. On the back side, the back side plating layer of the external terminal part and the back plating layer of the die pad part are formed. A glass mask (exposure mask) in which a desired pattern was formed at the position to be covered was placed on the front and back surfaces in an aligned state, and both surfaces were exposed to ultraviolet light through the glass mask.

  Then, the development process which melt | dissolves the uncured dry film resist which was interrupted | blocked with ultraviolet irradiation with the sodium carbonate solution was performed, and the opening part was formed in the dry film resist.

(Plating / first resist removal process)
Next, the dry film was dissolved and plating was performed on the opening where the metal surface of the conductive substrate was exposed. The plating was formed by stacking Ni plating of 3.0 μm, Pd plating of 0.1 μm, and Au plating of about 0.04 μm in this order.

  Thereafter, the dry film resist was peeled off with a sodium hydroxide solution. Thereby, the plating layer was formed on the front and back surfaces of the conductive substrate.

(Second resist coating step)
Next, a photosensitive dry film resist having a thickness of 0.025 mm was attached to both surfaces of the conductive substrate having the plating layers formed on the front and back surfaces as described above.

(Second exposure / development process)
After coating the resist, a dry film is used as an exposure mask using a glass mask with a surface plating layer on the surface and a pattern in which the internal terminal part, external terminal part and wiring part are formed, and a pattern covering the entire surface on the back surface. It was covered with a resist and exposed to ultraviolet light. A part of the wiring part was formed with a desired pattern so that a speed control resist was formed. The size, position, and the like of the speed control resist in the wiring portion were appropriately set in consideration of the etching conditions, the shape and arrangement of the internal terminals and the external terminals, and the like.

  Then, the development process which melt | dissolves the uncured dry film resist which was interrupted | blocked with ultraviolet irradiation with the sodium carbonate solution was performed, and the opening part was formed in the dry film resist.

(Etching process)
Next, it was masked with the prepared resist, and etched from the surface side with a ferric chloride solution to form a recessed region having a depth of 0.15 mm on the conductive substrate. By this etching process, an internal terminal portion, an external terminal portion, a semiconductor element mounting portion, a back surface connection portion, a wiring portion having a flat portion, and a wiring portion having a convex shape were formed. The tip of the convex part of the wiring part was formed at a position 0.02 mm lower than the upper surface of the internal terminal part.

(Second resist removal step)
Next, the dry film resist was peeled off with a sodium hydroxide solution.

  Then, the board | substrate for semiconductor element mounting which concerns on a present Example was obtained by cut | disconnecting to a predetermined dimension.

  Next, using the manufactured semiconductor element mounting substrate, a semiconductor device was manufactured according to the following procedure.

(Semiconductor element mounting and wire bonding process)
Using the above-mentioned semiconductor element mounting substrate, mounting the semiconductor element using Ag paste on the die pad surface plating layer of the semiconductor element mounting substrate, and connecting the electrode part of the semiconductor element and the internal terminal surface plating layer by wire bonding did.

(First resin sealing step and etching step after resin sealing)
Thereafter, the surface on which the semiconductor element is mounted is sealed with the first resin, and the back surface connecting portion is etched using the back surface plating layer of the external terminal portion and the back surface plating layer of the semiconductor element mounting portion as a mask, and the external terminal Each part was made independent.

(Second resin sealing step)
Thereafter, the external terminal portion was sealed with the second resin. The same resin was used for the first resin and the second resin. Finally, the semiconductor device was completed by cutting to a predetermined semiconductor device size.

[Example 2]
<Semiconductor element mounting substrate>
The substrate for mounting a semiconductor element according to the second embodiment forms a semiconductor element mounting region without forming a die pad portion in the “first exposure / development process” and the “second exposure / development process” in the first embodiment. A substrate for mounting a semiconductor element was produced using an exposure mask having a pattern in which an external terminal having a back plating layer is arranged immediately below the position.

<Semiconductor device>
A semiconductor device was manufactured using the semiconductor element mounting substrate manufactured as described above.

  Specifically, in the fabrication of the semiconductor element mounting substrate, in Example 1, when forming the first resist pattern, the die pad portion is not disposed, and the internal terminal surface plating layer and the external terminal back surface plating layer are disposed. When forming the second resist pattern and forming the second resist pattern, a pattern was prepared in which the internal terminal portion, the external terminal portion, and the wiring portion were disposed without disposing the die pad portion on the surface side.

  Furthermore, in the manufacture of the semiconductor device, in the semiconductor element mounting process, the semiconductor elements are mounted and fixed on the surfaces of the plurality of external terminal portions immediately below the semiconductor element mounting region using an insulating adhesive.

  Other manufacturing conditions are the same as those in Example 1.

<Evaluation>
Regarding the semiconductor devices manufactured in Example 1 and Example 2, energization was confirmed between the internal terminal part and the external terminal part before sealing with the second resin, and the wiring part was connected. Was confirmed. Further, when the completed semiconductor device was cut and a cross-sectional shape orthogonal to the longitudinal direction of the wiring portion was confirmed, it was substantially triangular. Further, since the width of the flat portion in the conventional wiring portion is about 0.06 mm to 0.1 mm, the pitch between the external terminal portions can be narrowed by about 0.06 mm to 0.15 mm. It was.

  As described above, according to the present example, according to the semiconductor element mounting substrate and the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, the electrical connection is ensured while the pitch between the external terminal portions is narrowed. It was shown that it can be secured.

  The preferred embodiments and examples of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments and examples, and the above-described embodiments and examples can be performed without departing from the scope of the present invention. Various modifications and substitutions can be made to the embodiments.

DESCRIPTION OF SYMBOLS 10 Conductive substrate 20, 20a Semiconductor element mounting area 22 Semiconductor element mounting part 30 Internal terminal part 40, 40a External terminal part 50 Wiring part 60, 70 Indented area 80 Surface plating layer 81, 81a Back surface plating layer 100, 101 Semiconductor element mounting Substrate 110 Semiconductor element 120 Bonding wire 130, 140 Resin 200, 201, 202 Semiconductor device

Claims (10)

A semiconductor element mounting region provided in a predetermined region on the surface side of the conductive substrate;
An internal terminal portion provided around the semiconductor element mounting region and including a flat surface on the surface side;
An external terminal portion provided apart from the internal terminal portion and including a flat surface on the surface side;
A first wiring portion that electrically connects the internal terminal portion and the external terminal portion on at least the flat surface on the surface side;
Electrically connecting the internal terminal portion and the external terminal portion, a second wiring portion provided with a height lower than the flat surface on the surface side;
At least a semiconductor element mounting region on the surface side of the conductive substrate, the internal terminal portion, the external terminal portion, the recessed region provided in a region other than the first wiring portion and the second wiring portion, A substrate for mounting semiconductor elements.   The semiconductor element mounting substrate according to claim 1, wherein a tip of the second wiring portion has a convex shape.   3. The semiconductor element mounting substrate according to claim 1, wherein a plating layer is provided on a surface of the internal terminal portion and on a back surface of the external terminal portion.   The board | substrate for semiconductor element mounting of Claim 3 with which the said plating layer was provided in both surfaces of the said semiconductor element mounting area | region. A semiconductor element mounting portion made of a metal material and having a first thickness and a surface being a semiconductor element mounting region;
The metal material is provided around the semiconductor element mounting portion, has a second thickness that is smaller than the first thickness, and has a surface that is the same height as the surface of the semiconductor element mounting region. An internal terminal,
An external terminal portion made of the metal material, provided apart from the internal terminal portion, having the first thickness, and a surface having the same height as the surface of the semiconductor element mounting region,
Made of the metal material, provided between the internal terminal portion and the external terminal portion so as to electrically connect the internal terminal portion and the external terminal portion, and having the second thickness, A first wiring portion having a surface that is the same height as the surface of the semiconductor element mounting region;
The metal material is provided between the internal terminal portion and the external terminal portion so as to electrically connect the internal terminal portion and the external terminal portion, and has a height lower than the second thickness. A second wiring portion having a bottom surface that is substantially the same height as the bottom surface of the internal terminal portion;
A semiconductor element mounted on the semiconductor element mounting region;
Connection means for electrically connecting the electrode of the semiconductor element and the surface of the internal terminal portion;
Except for the back surface of the semiconductor element mounting portion and the back surface of the external terminal portion, the semiconductor element mounting portion, the internal terminal portion, the external terminal portion, the first wiring portion, the second wiring portion, and the semiconductor element And a resin that seals the connection means.   The semiconductor device according to claim 5, wherein a plating layer is provided on the front surface of the internal terminal portion and the back surface of the external terminal portion.   The semiconductor element mounting portion also functions as the external terminal portion, and is electrically connected to the internal terminal portion via the first wiring portion or the second wiring portion. Semiconductor device. A plating layer forming step of forming a plating layer in a region where the internal terminal portion on the surface of the conductive substrate is to be formed and a region where the external terminal portion is formed on the back surface;
A region to form a semiconductor element mounting region on a surface of the conductive substrate, a region to form the internal terminal portion, a region to form the external terminal portion, the internal terminal portion, and the A masking step of covering a region where a wiring part to be electrically connected to an external terminal part is to be formed, and a whole back surface of the conductive substrate with a mask;
Etching both sides of the conductive substrate covered with the mask, and forming an indentation region in a region not covered with the mask, and
The mask that covers a region where a wiring portion that electrically connects the internal terminal portion and the external terminal portion is formed has a shape along the extending direction of the wiring portion, and in the etching step, A first mask having a first width capable of maintaining a flat surface on the surface of the conductive substrate, and a second mask having a second width on which the flat surface on the surface of the conductive substrate is also etched. A method for manufacturing a semiconductor element mounting substrate, comprising: a mask.   The method for manufacturing a semiconductor element mounting substrate according to claim 8, wherein in the step of forming the plating layer, the plating layer is also formed on both surfaces of a region where the semiconductor element mounting region is to be formed. Mounting a semiconductor element on the semiconductor element mounting region of the semiconductor element mounting substrate manufactured by the method for manufacturing a semiconductor element mounting substrate according to claim 8 or 9,
Electrically connecting the electrode of the semiconductor element and the surface of the internal terminal using a connecting means;
Sealing the entire surface of the semiconductor element mounting substrate with a first resin;
Etching the back surface of the semiconductor element mounting substrate using the plating layer as a mask;
Sealing the back surface of the semiconductor element mounting substrate with a second resin except for the plating layer on the back surface.

Images