JP2018014373A - FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF, DISPLAY ELEMENT, DISPLAY DEVICE, AND SYSTEM - Google Patents

Abstract

A field effect transistor including a step of forming a source electrode and a drain electrode by wet etching a metal film made of any one of Ti, a Ti alloy, or a laminate containing Ti or a Ti alloy on a glass substrate. In the manufacturing method, cracks and disconnections are less likely to occur in the semiconductor layer formed on the source electrode and the drain electrode. A method for manufacturing a field effect transistor according to the present invention is a method for manufacturing a field effect transistor having a glass substrate, wherein Ti, Ti alloy, or a laminate including Ti or Ti alloy is formed on the glass substrate. A source electrode and a drain electrode are formed from the metal film by a process of forming a metal film made of any of the above and wet etching, and a groove is formed in the glass substrate other than the region where the source electrode and the drain electrode are formed. Forming a buried layer in the trench, and forming a semiconductor layer on the source electrode, the drain electrode, and the buried layer. [Selection] Figure 2

Description

  The present invention relates to a field effect transistor, a manufacturing method thereof, a display element, a display device, and a system.

  A field effect transistor (FET) is easy to manufacture and integrate as compared with a bipolar transistor because it has a low gate current and a planar structure. Therefore, FETs are indispensable elements in integrated circuits used in current electronic devices. For example, an active matrix in which field effect transistors are arranged in a matrix is used as a driving circuit for a display such as a liquid crystal display. It has been.

  As wiring in the active matrix, it is common to use a structure in which low resistance Al and a barrier metal are laminated. Although Mo is generally used as the barrier metal, attention has been focused on Ti that enables cost reduction and high resistance to chemicals and heat.

  Ti, Ti alloy, or a laminate containing Ti or Ti alloy can be patterned by dry etching using a chlorine-based gas, but the risk of chlorine-based gas is high, the environmental load is large, and the apparatus to be used is There are disadvantages such as being expensive, which is not preferable. Therefore, in order to enable patterning by wet etching, an etchant containing a fluorine compound has been developed (see, for example, Patent Document 1).

  However, the etchant containing the fluorine compound dissolves the glass substrate. Therefore, when a metal film made of Ti, Ti alloy, or a laminate containing Ti or Ti alloy is formed on the glass substrate, when the metal film is wet etched to form the source electrode and the drain electrode, A groove is formed. Therefore, when forming a semiconductor layer on the source electrode and the drain electrode, it is necessary to form the semiconductor layer from the source electrode and the drain electrode to a deep position in the groove. As a result, the semiconductor layer is cracked or disconnected. There is a problem that it is easy.

  The present invention is a field effect type including a step of forming a source electrode and a drain electrode by wet etching a metal film made of any one of Ti, Ti alloy, or a laminate containing Ti or Ti alloy on a glass substrate. In a method for manufacturing a transistor, an object is to make a semiconductor layer formed over a source electrode and a drain electrode less likely to be cracked or disconnected.

  The method for producing a field effect transistor is a method for producing a field effect transistor having a glass substrate, and is composed of any one of Ti, Ti alloy, and a laminate containing Ti or Ti alloy on the glass substrate. Forming a metal film; and forming a source electrode and a drain electrode from the metal film by wet etching, and forming a groove in the glass substrate other than the region where the source electrode and the drain electrode are formed And a step of forming a buried layer in the trench, and a step of forming a semiconductor layer on the source electrode, the drain electrode, and the buried layer.

  According to the disclosed technique, the method includes wet etching a metal film made of any one of Ti, Ti alloy, or a laminate including Ti or Ti alloy on a glass substrate to form a source electrode and a drain electrode. In the method for manufacturing a field effect transistor, it is possible to prevent cracks and disconnections from occurring in a semiconductor layer formed over a source electrode and a drain electrode.

1 is a cross-sectional view illustrating a field effect transistor according to a first embodiment. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the field effect transistor according to the first embodiment; FIG. 6 is a diagram (No. 2) for exemplifying the manufacturing process of the field effect transistor according to the first embodiment; It is sectional drawing which illustrates the field effect transistor which concerns on a comparative example. It is sectional drawing which illustrates the field effect transistor which concerns on the modification 1 of 1st Embodiment. It is a figure which illustrates the manufacturing process of the field effect transistor which concerns on the modification 1 of 1st Embodiment. 6 is a cross-sectional view illustrating a field effect transistor according to Modification 2 of the first embodiment; FIG. It is a figure which illustrates the manufacturing process of the field effect transistor which concerns on the modification 2 of 1st Embodiment. It is a block diagram which shows the structure of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 1) of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 2) of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 3) of the television apparatus in 2nd Embodiment. It is explanatory drawing of the display element in 2nd Embodiment. It is explanatory drawing of organic EL in 2nd Embodiment. It is explanatory drawing (the 4) of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 1) of the other display element in 2nd Embodiment. It is explanatory drawing (the 2) of the other display element in 2nd Embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

<First Embodiment>
[Structure of field effect transistor]
1A and 1B are cross-sectional views illustrating the field effect transistor according to the first embodiment. FIG. 1A is an overall view, and FIG. 1B is a partially enlarged view of a portion A in FIG. FIG.

  Referring to FIG. 1, a field effect transistor 10 includes a glass substrate 11, a source electrode 12, a drain electrode 13, a buried layer 14, a semiconductor layer 15, a gate insulating layer 16, and a gate electrode 17. A top-gate / bottom-contact field effect transistor. The field effect transistor 10 is a typical example of a semiconductor device according to the present invention.

  In this embodiment, for the sake of convenience, the gate electrode 17 side is the upper side or one side, and the glass substrate 11 side is the lower side or the other side. Further, the surface on the gate electrode 17 side of each part is the upper surface or one surface, and the surface on the glass substrate 11 side is the lower surface or the other surface. However, the field effect transistor 10 can be used upside down, or can be arranged at an arbitrary angle. The planar view refers to viewing the object from the normal direction of the upper surface of the glass substrate 11, and the planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the glass substrate 11. .

There is no restriction | limiting in particular as a shape of a glass substrate 11, a structure, and a magnitude | size, According to the objective, it can select suitably. There is no restriction | limiting in particular as a material of the glass substrate 11, Although it can select suitably according to the objective, For example, an alkali free glass, a silica glass, etc. are mentioned. More specifically, it may be glass such as SiO ₂ , GeO ₂ , B ₂ O ₃ , P ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , V ₂ O ₅ , Sb ₂ O ₅ , Li A multicomponent glass further containing ₂ O, Na ₂ O, K ₂ O, MgO, BaO, CaO, SrO, BaO or the like may be used.

A source electrode 12 and a drain electrode 13 are formed on the glass substrate 11. More specifically, the source electrode 12 is formed on a convex portion 11y having a substantially trapezoidal cross section formed on the glass substrate 11. As shown in FIG. 1B, the bottom angle on the drain electrode 13 side of the lower bottom of the convex portion 11y is θ ₁ in a cross-sectional view. Further, the cross-sectional shape of the source electrode 12 is also substantially trapezoidal, and the bottom angle of the lower bottom of the source electrode 12 on the drain electrode 13 side is θ ₁ . Further, the extended surface of the source electrode 12 side end of the upper surface of the buried layer 14, the angle between the drain electrode 13 side surface of the source electrode 12 is theta _2.

Similarly, the drain electrode 13 is formed on the convex portion 11z having a substantially trapezoidal cross section formed on the glass substrate 11. In cross section, the base angle of the source electrode 12 of the lower bottom of the convex portion 11z is substantially the same angle ₁ and theta (where, for convenience, the theta _3). Further, the cross-sectional shape of the drain electrode 13 is also substantially trapezoidal, and the base angle of the lower base of the drain electrode 13 on the source electrode 12 side is also substantially the same as θ ₁ . The angle formed between the extended surface of the upper surface of the buried layer 14 on the drain electrode 13 side and the side surface of the drain electrode 13 on the source electrode 12 side is substantially the same as θ ₂ (here, for the sake of convenience, θ ₄ And).

Here, θ ₁ (≈θ ₃ ) can be set to about 50 to 70 degrees, for example, and θ ₂ (≈θ ₄ ) is equal to or less than θ ₁ (≈θ ₃ ). The value of θ ₂ (≈θ ₄ ) can be appropriately adjusted by selecting a material for forming the buried layer 14 in the manufacturing process described later. In the example of the present embodiment, θ ₁ (≈θ ₃ ) is about 60 degrees and θ ₂ (≈θ ₄ ) is about 50 degrees.

  The source electrode 12 and the drain electrode 13 are electrodes for taking out current in response to application of a gate voltage to the gate electrode 17. Note that the source electrode 12 and the drain electrode 13 and the wiring connected to the source electrode 12 and the drain electrode 13 may be formed in the same layer.

  The material of the source electrode 12 and the drain electrode 13 is any one of Ti, Ti alloy, or a laminated body containing Ti or Ti alloy. Specifically, Ti, TiN, Ti / Al / Ti laminate, Ti / Cu / Ti laminate, TiN / Al / TiN laminate, TiN / Cu as materials of the source electrode 12 and the drain electrode 13 are used. / TiN laminate and the like.

  There is no restriction | limiting in particular as an average film thickness of the source electrode 12 and the drain electrode 13, Although it can select suitably according to the objective, 20 nm-1 micrometer are preferable and 50 nm-500 nm are more preferable.

  Grooves 11x are formed in the glass substrate 11 other than the region where the source electrode 12 and the drain electrode 13 are formed. That is, in the glass substrate 11, the region other than the convex portion 11y where the source electrode 12 is formed and the convex portion 11z where the drain electrode 13 is formed is the groove 11x. The depth of the groove 11x (the distance between the surface of the glass substrate 11 in contact with the source electrode 12 and the drain electrode 13 (the upper surface of the protrusion 11y and the protrusion 11z) and the bottom of the groove 11x) is, for example, about 10 to 500 nm. can do.

A buried layer 14 is formed in the groove 11x. The material of the buried layer 14 is not particularly limited as long as it is an insulating material, and can be appropriately selected according to the purpose. As the material of the buried layer 14, for example, a spin-on glass material having planarity can be used. To be specific, SiO ₂ and BPSG (Boron Phosphor Silicate Glass), it is possible to use PSG (Phosphor Silicate Glass) or the like.

  The buried layer 14 preferably further contains an alkaline earth metal element. This is because the inclusion of the alkaline earth metal element makes it possible to control the linear expansion coefficient of the buried layer 14 and to avoid problems such as cracks and peeling due to a subsequent thermal process.

For example, when the buried layer 14 is made of only SiO ₂ , the linear expansion coefficient is smaller than that of the surrounding layers (semiconductor layer 15 or the like). Therefore, by adding an alkaline earth metal element to increase the linear expansion coefficient of the buried layer 14 and adjusting it to a value close to the linear expansion coefficient of the surrounding layers, the semiconductor layer 15 and the like are cracked by the thermal process in the subsequent process. And peeling can be prevented.

  In addition, when the film thickness of the source electrode 12 and the drain electrode 13 is A, the depth of the groove 11x is B, and the minimum film thickness of the buried layer 14 is C, it is preferable that B <C <A + B is satisfied.

  The semiconductor layer 15 is formed on the source electrode 12, the drain electrode 13, and the buried layer 14. The semiconductor layer 15 may be formed so as to cover at least part of the source electrode 12 and the drain electrode 13. The semiconductor layer 15 located between the source electrode 12 and the drain electrode 13 becomes a channel region. There is no restriction | limiting in particular as an average film thickness of the semiconductor layer 15, Although it can select suitably according to the objective, 1 nm-500 nm are preferable, 5 nm-100 nm are more preferable, and 5 nm-50 nm are especially preferable.

  There is no restriction | limiting in particular as a material of the semiconductor layer 15, According to the objective, it can select suitably, For example, a silicon semiconductor, an oxide semiconductor, an organic semiconductor etc. are mentioned. Examples of the silicon semiconductor include polycrystalline silicon (p-Si) and amorphous silicon (a-Si). As examples of the oxide semiconductor, In—Ga—Zn—O, I—Z—O, In—Mg—O, and the like can be given. Examples of the organic semiconductor include pentacene. Among these, an oxide semiconductor is preferably used.

  The gate insulating layer 16 is provided between the semiconductor layer 15 and the gate electrode 17. The gate insulating layer 16 covers the entire semiconductor layer 15 and part of the source electrode 12, the drain electrode 13, and the buried layer 14. The gate insulating layer 16 is a layer for insulating the source electrode 12 and the drain electrode 13 from the gate electrode 17. There is no restriction | limiting in particular as an average film thickness of the gate insulating layer 16, Although it can select suitably according to the objective, 50 nm-1000 nm are preferable and 100 nm-500 nm are more preferable.

The material of the gate insulating layer 16 is not particularly limited and may be appropriately selected depending on the purpose, for _example, SiO 2, SiN material and being used already widely mass production of such _x, La _{2 O} 3, Examples thereof include high dielectric constant materials such as HfO ₂ and organic materials such as polyimide (PI) and fluorine-based resin.

  There is no restriction | limiting in particular as a formation method of the gate insulating layer 16, According to the objective, it can select suitably, For example, vacuum film-forming methods, such as sputtering, chemical vapor deposition (CVD), and atomic layer deposition (ALD) , Printing methods such as spin coating, die coating, and ink jet.

  The gate electrode 17 is stacked on the semiconductor layer 15 via the gate insulating layer 16. The gate electrode 17 is an electrode for applying a gate voltage. There is no restriction | limiting in particular as a material of the gate electrode 17, Although it can select suitably according to the objective, For example, aluminum, gold | metal | money, platinum, palladium, silver, copper, zinc, nickel, chromium, tantalum, molybdenum, titanium Such metals, alloys thereof, mixtures of these metals, and the like can be used. In addition, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide, and niobium oxide, composite compounds thereof, mixtures thereof, and the like may be used. There is no restriction | limiting in particular as an average film thickness of the gate electrode 17, Although it can select suitably according to the objective, 40 nm-2 micrometers are preferable, and 70 nm-1 micrometer are more preferable.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be described. 2 and 3 are diagrams illustrating the manufacturing process of the field effect transistor according to the first embodiment.

  First, in the step shown in FIG. 2A, a glass substrate 11 is prepared, and a metal film 120 made of Ti, Ti alloy, or a laminate containing Ti or Ti alloy is formed on the glass substrate 11. Film. The material and thickness of the glass substrate 11 can be appropriately selected as described above. Further, from the viewpoint of cleaning the surface of the glass substrate 11 and improving adhesion, pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning is preferably performed.

  The method for forming the metal film 120 is not particularly limited and may be appropriately selected depending on the purpose. Examples thereof include a sputtering method, a vacuum deposition method, a dip coating method, a spin coating method, and a die coating method. it can. There is no restriction | limiting in particular in the average film thickness of the metal film 120, Although it can select suitably according to the objective, 20 nm-1 micrometer are preferable and 50 nm-500 nm are more preferable.

  Next, in the step shown in FIG. 2B, the source electrode 12 and the drain electrode 13 are formed from the metal film 120 by wet etching.

  Specifically, for example, a photoresist is applied on the metal film 120, and a resist pattern that covers portions to be the source electrode 12 and the drain electrode 13 is formed by pre-baking, exposure by an exposure apparatus, and development. Then, the metal film 120 in a region not covered with the resist pattern is removed by wet etching, and then the resist pattern is removed.

  An etchant used for wet etching is not particularly limited, but an etchant containing hydrogen fluoride or ammonium fluoride is preferably used. Furthermore, an acid such as nitric acid, sulfuric acid, hydrogen peroxide solution, and acetic acid may be included as necessary.

  In the wet etching, overetching is performed in order to reliably form the source electrode 12 and the drain electrode 13, but during the overetching, the glass substrate 11 other than the region where the source electrode 12 and the drain electrode 13 are formed is dissolved. To do.

  Thereby, the convex part 11y whose cross-sectional shape is substantially trapezoid shape is formed in the glass substrate 11, and the source electrode 12 is formed on the convex part 11y. Further, a convex portion 11z having a substantially trapezoidal cross section is formed on the glass substrate 11, and a drain electrode 13 is formed on the convex portion 11z. Further, a groove 11x is formed in the glass substrate 11 other than the region where the source electrode 12 and the drain electrode 13 are formed. Although the depth of the groove 11x depends on the material of the glass substrate 11, the etching solution, the etching time, etc., it is about 10 to 500 nm.

  Next, in the process shown in FIGS. 2C and 2D, the buried layer 14 is formed in the groove 11x. First, in the step shown in FIG. 2C, the buried layer forming coating solution 140 is applied onto the trench 11x, the source electrode 12, and the drain electrode 13 by spin coating or the like. The embedded layer forming coating solution 140 is, for example, a spin-on-glass forming coating solution, and preferably contains at least an organic solvent and a silane compound. The buried layer forming coating solution 140 preferably further contains an alkaline earth metal compound.

  Next, in the step shown in FIG. 2D, the buried layer forming coating solution 140 is baked to form the buried layer 14. The coating liquid 140 for forming the buried layer is formed on the groove 11x, the source electrode 12, and the drain electrode 13 after the coating process. However, since the viscosity decreases during the firing process, the coating liquid 140 for the buried layer is formed on the source electrode 12 and the drain electrode 13. From the inside to the groove 11x, and the groove 11x can be embedded.

  Here, if the maximum step of the source electrode 12 and the drain electrode 13 is X nm and the maximum step of the buried layer 14 after firing is Y nm, the planarization rate P of the buried layer is “P [%] = (XY) / X × 100 ″. From the viewpoint of easy embedding of the groove 11x, the planarization rate P is preferably 50% or more.

  The maximum level difference (X nm) between the source electrode 12 and the drain electrode 13 is the difference in height (film thickness) between the highest and lowest portions of the surface of the source electrode 12 and the drain electrode 13. Further, the maximum step (Ynm) of the buried layer 14 after firing is the difference in height between the highest portion and the lowest portion of the surface of the buried layer 14 after firing. These X and Y values can be determined by a stylus type step meter (for example, Alpha-Step IQ, manufactured by KLA Tencor Japan).

  As shown in FIG. 2D, when the buried layer 14 (baked buried layer forming coating solution 140) remains on the source electrode 12 and the drain electrode 13 after the firing step, FIG. The entire surface of the buried layer 14 is etched back in the step shown in FIG. Thereby, the buried layer 14 on the source electrode 12 and the drain electrode 13 can be removed, and the surfaces of the source electrode 12 and the drain electrode 13 can be exposed.

  At this time, when the film thickness of the source electrode 12 and the drain electrode 13 is A, the depth of the groove 11x is B, and the minimum film thickness of the buried layer 14 is C, etching back is performed so as to satisfy B <C <A + B. Is preferred. This is because the trench 11x is sufficiently filled with the buried layer 14 to reduce the step between the upper surface of each of the source electrode 12 and the drain electrode 13 and the upper surface of the buried layer 14.

  Next, in the step shown in FIG. 3B, the semiconductor layer 15 is formed on the source electrode 12, the drain electrode 13, and the buried layer 14. A method for forming the semiconductor layer 15 is not particularly limited and may be appropriately selected depending on the purpose. For example, (i) after film formation on the entire surface of the source electrode 12, the drain electrode 13, and the buried layer 14. And a method of patterning by photolithography, and (ii) a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, and gravure. As the film forming process (i), a vacuum film forming process such as sputtering, or a process of baking after coating by spin coating, die coating, slit coating or the like is applicable. The material and thickness of the semiconductor layer 15 can be appropriately selected as described above.

  Next, in the step shown in FIG. 3C, the gate insulating layer 16 that covers the entire semiconductor layer 15 and part of the source electrode 12, the drain electrode 13, and the buried layer 14 is formed on the glass substrate 11. Form. There is no restriction | limiting in particular as a method of forming the gate insulating layer 16, According to the objective, it can select suitably, For example, a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method, Examples thereof include a film forming process by a vacuum process such as an atomic layer deposition (ALD) method, a solution process such as a dip coating method, a spin coating method, and a die coating method. Another example includes a step of directly forming a desired shape by a printing process such as inkjet, nanoimprint, or gravure. The material and thickness of the gate insulating layer 16 can be appropriately selected as described above.

  Next, in the step shown in FIG. 3D, a gate electrode 17 is formed on the gate insulating layer 16. First, a metal film to be the gate electrode 17 is formed on the gate insulating layer 16. The method for forming the metal film to be the gate electrode 17 is not particularly limited and may be appropriately selected depending on the purpose. For example, sputtering, vacuum deposition, dip coating, spin coating, die coating, etc. Can be mentioned.

  Next, the gate electrode 17 having a predetermined shape can be formed by patterning the formed metal film by photolithography and etching. The material and thickness of the metal to be the gate electrode 17 can be appropriately selected as described above.

  Through the above steps, the top-gate / bottom-contact field effect transistor 10 shown in FIG. 1 can be manufactured.

  FIG. 4 is a cross-sectional view illustrating a field effect transistor according to a comparative example. Referring to FIG. 4, the field effect transistor 10 </ b> X according to the comparative example is different from the field effect transistor 10 in that it does not have the embedded layer 14.

  Without the buried layer 14 as in the field effect transistor 10X, it is necessary to form a thin semiconductor layer 15 on the order of nm from the source electrode 12 and the drain electrode 13 to a deep position in the trench 11x. The layer 15 is likely to be cracked or disconnected. When cracks or disconnections occur in the semiconductor layer 15, transistor characteristics such as mobility are deteriorated or the transistor does not operate.

  On the other hand, in the present embodiment, a metal film 120 made of any one of Ti, Ti alloy, or a laminate including Ti or Ti alloy is formed on the glass substrate 11, and the metal is formed by wet etching. A source electrode 12 and a drain electrode 13 are formed from the film 120. Then, a buried layer 14 is formed in the groove 11x formed in the glass substrate 11 located around the source electrode 12 and the drain electrode 13 during overetching during wet etching.

  Thereby, since the semiconductor layer 15 can be formed on the source electrode 12, the drain electrode 13, and the buried layer 14, the semiconductor layer 15 is formed in the groove unlike the case where the buried layer 14 is not provided as in the comparative example. It is not necessary to form a deep position in 11x. As a result, cracks and disconnections are less likely to occur in the semiconductor layer 15, and transistor characteristics such as mobility can be improved. This effect becomes more prominent as the semiconductor layer 15 becomes thinner.

Further, by adjusting the flattening rate of the buried layer 14, an angle θ formed by the extended surface of the upper surface of the buried layer 14 on the side of the source electrode 12 and the side surface of the source electrode 12 on the side of the drain electrode 13 in the sectional view ₂ can be set to a base angle θ ₁ or less on the drain electrode 13 side at the bottom of the convex portion 11y. As a result, in the portion from the source electrode 12 to the buried layer 14, it is possible to suppress a sharp shape change of the semiconductor layer 15, and to further reduce the possibility that the semiconductor layer 15 is cracked or disconnected. The same effect is also obtained on the drain electrode 13 side.

<Modification of First Embodiment>
The modification of the first embodiment shows an example in which the value of θ ₂ is different from that of the first embodiment. In the modification of the first embodiment, the description of the same components as those of the already described embodiments may be omitted.

  FIG. 5 is a cross-sectional view illustrating a field effect transistor according to Modification 1 of the first embodiment. FIG. 5A is an overall view, and FIG. 5B is A in FIG. It is the elements on larger scale of a part. The field effect transistor shown in FIG. 5 is a typical example of the semiconductor device according to the present invention.

The field effect transistor 10 </ _b > A shown in FIG. 5 has θ ₂ smaller than that of the field effect transistor 10. In the example of the present embodiment, θ ₁ is about 60 degrees and θ ₂ is about 30 degrees.

  The field-effect transistor 10A can be manufactured by the same process as the field-effect transistor 10, but in the present embodiment, as the embedded layer forming coating solution 140 used in the process shown in FIG. A spin-on-glass forming coating solution having a flattening rate lower than that of the first embodiment is used. The planarization rate of the coating liquid 140 for forming the buried layer used in the present embodiment can be about 50%, for example.

  Thus, when the buried layer forming coating solution 140 is baked, as shown in FIG. 6A, the buried layer 14 having a lower planarization rate than that in FIG. 2D can be formed. After that, as shown in FIG. 6B, the entire buried layer 14 remaining on the source electrode 12 and the drain electrode 13 is etched back after the baking step, so that the buried layer on the source electrode 12 and the drain electrode 13 is etched back. 14 is removed. Then, by performing the same steps as in FIGS. 3B to 3D, the field effect transistor 10A is completed.

  7A and 7B are cross-sectional views illustrating a field effect transistor according to Modification 2 of the first embodiment. FIG. 7A is an overall view, and FIG. 7B is A in FIG. It is the elements on larger scale of a part. The field effect transistor shown in FIG. 7 is a typical example of the semiconductor device according to the present invention.

The field effect transistor 10 </ _b > B illustrated in FIG. 7 has a larger θ ₂ than the field effect transistor 10. In the example of the present embodiment, θ ₁ is about 60 degrees and θ ₂ is about 60 degrees.

  The field effect transistor 10B can be manufactured by the same process as the field effect transistor 10. In this embodiment, after forming the source electrode 12 and the drain electrode 13 in the step shown in FIG. 8A, the embedded layer forming coating solution 140 is applied in the step shown in FIG. As the coating liquid 140, a spin-on-glass forming coating liquid having a higher planarization rate than that of the first embodiment is used. The planarization rate of the coating liquid 140 for forming the buried layer used in the present embodiment can be about 90%, for example. Since the coating liquid 140 for forming the buried layer having a high flattening rate has a low viscosity, it can be applied only in the groove 11 x without being applied on the source electrode 12 and the drain electrode 13.

  By performing baking after the step shown in FIG. 8B to form the buried layer 14, and then performing the same steps as in FIG. 3B to FIG. 3D without performing etch back, the field effect is obtained. The type transistor 10B is completed.

Thus, the planarization rate of the buried layer 14 can be changed by appropriately selecting the planarization rate of the coating liquid 140 for forming the buried layer. That is, θ ₂ can be reduced relative to θ ₁ , θ ₁ and θ ₂ can be made equal, or can be selected as appropriate according to the purpose.

<Example 1>
In Example 1, a top gate / bottom contact type field effect transistor 10 was fabricated.

-Formation of source electrode 12 and drain electrode 13-
First, the source electrode 12 and the drain electrode 13 were formed on the glass substrate 11. Specifically, a metal film 120 was formed on the glass substrate 11 by DC sputtering. As the metal film 120, a Ti / Al / Ti laminated film was used, and was formed on the glass substrate 11 so that the average film thickness was about 30 nm / 100 nm / 30 nm.

Thereafter, a photoresist was applied on the metal film 120, and a resist pattern was formed by pre-baking, exposure using an exposure apparatus, and development. Further, by immersing in an etching solution containing ammonium fluoride adjusted to about 35 ° C., the metal film 120 in the region where the resist pattern was not formed was dissolved and removed. Over-etching was about 50%. During the over-etching, the glass substrate 11 was dissolved by about 40 nm, and the grooves 11x were formed. Finally, by removing the resist pattern, the source electrode 12 and the drain electrode 13 were formed. Θ ₁ (see FIG. 1) was about 60 °.

-Formation of buried layer 14-
Next, a buried layer 14 for filling the groove 11x was formed. Specifically, a spin-on-glass material having a planarization rate of about 70% was prepared as the embedded layer forming coating solution 140. Then, a buried layer forming coating solution 140 was applied onto the trench 11x, the source electrode 12, and the drain electrode 13 by spin coating. The buried layer forming coating solution 140 is a spin on glass forming coating solution containing at least an organic solvent and a silane compound.

After applying the filling layer forming coating solution 140, the groove 11x was filled with the SiO ₂ film by baking at about 400 ° C. for about 1 hour. The average film thickness of the SiO ₂ film on the trench 11 x was 250 nm, and the buried layer 14 was also formed on the source electrode 12 and the drain electrode 13.

Subsequently, the entire surface of the buried layer 14 was etched back with a mixed gas of CF ₄ and O _2, and SiO ₂ was etched by 130 nm to remove the buried layer 14 on the source electrode 12 and the drain electrode 13. Θ ₂ (see FIG. 1) was about 50 °.

-Formation of the semiconductor layer 15-
Next, the semiconductor layer 15 was formed on the source electrode 12, the drain electrode 13, and the buried layer 14. Specifically, an Mg—In-based oxide (In ₂ MgO ₄ ) film was formed by DC sputtering so that the average film thickness was about 10 nm. Thereafter, a photoresist was applied onto the Mg—In-based oxide film, and a resist pattern was formed by pre-baking, exposure using an exposure apparatus, and development.

  Further, the Mg—In-based oxide film in the region where the resist pattern was not formed was removed by RIE. Thereafter, by removing the resist pattern, a semiconductor layer 15 made of an oxide semiconductor and forming a channel between the source electrode 12 and the drain electrode 13 was formed.

-Formation of gate insulating layer 16-
Next, a gate insulating layer 16 that covers the entire semiconductor layer 15 and part of the source electrode 12, the drain electrode 13, and the buried layer 14 was formed on the glass substrate 11. Specifically, the SiO ₂ film was formed by RF sputtering so that the average film thickness was about 300 nm. Thereafter, a photoresist was applied on the SiO ₂ film, and a resist pattern was formed by pre-baking, exposure using an exposure apparatus, and development. Further, the SiO ₂ film in the region where the resist pattern was not formed was removed by RIE. Then, the gate insulating layer 16 was formed by removing the resist pattern.

-Formation of gate electrode 17-
Next, a gate electrode 17 was formed on the gate insulating layer 16. Specifically, a Mo / Al / Mo laminated film was formed by DC sputtering so that the average film thickness was about 30 nm / 100 nm / 30 nm. Thereafter, a photoresist was applied on the Mo / Al / Mo laminated film, and a resist pattern was formed by pre-baking, exposure with an exposure apparatus, and development. Further, the Mo / Al / Mo laminated film in the region where the resist pattern was not formed was removed by RIE. Thereafter, the gate electrode 17 was formed by removing the resist pattern. Finally, the field effect transistor 10 was completed by applying a heat treatment at 300 ° C.

  Then, transistor performance evaluation was implemented about the obtained field effect transistor 10 using the semiconductor parameter analyzer apparatus (Agilent Technology company make, semiconductor parameter analyzer B1500A). Specifically, the source / drain voltage Vds was set to 10 V, the gate voltage was changed from Vg = −15 V to +15 V, the source / drain current Ids and the gate current | Ig | were measured, and the current-voltage characteristics were evaluated. Then, the mobility was calculated in the saturation region of the evaluated current-voltage characteristics.

<Example 2>
In the second embodiment, the top gate / bottom contact type field effect transistor shown in FIG. 5 is the same as the first embodiment except that the material of the buried layer 14 is a spin-on-glass material having a planarization rate of about 50%. 10A was produced. Θ ₂ (see FIG. 5) was about 50 °. Further, after the completion of the field effect transistor 10A, the mobility of the field effect transistor 10A was measured.

<Example 3>
In Example 3, the material of the buried layer 14 is a spin-on-glass material having a flattening rate of about 90%, and the same method as in Example 1 is used except that the entire surface etchback in the process of forming the buried layer 14 is omitted. The top gate / bottom contact type field effect transistor 10B shown in FIG. Θ ₂ (see FIG. 7) was about 60 °. Further, after the completion of the field effect transistor 10B, the mobility of the field effect transistor 10B was measured.

<Comparative example>
In the comparative example, the field effect transistor 10X shown in FIG. 4 was produced in the same manner as in Example 1 except that the buried layer 14 was not formed.

  <Summary of results>

結果を表１にまとめた。表１に示すように、実施例１で作製した電界効果型トランジスタは移動度が５．７ｃｍ^２／Ｖｓであり、良好なトランジスタ特性を示した。又、実施例２で作製した電界効果型トランジスタは移動度が６．１ｃｍ^２／Ｖｓであり、良好なトランジスタ特性を示した。又、実施例３で作製した電界効果型トランジスタは移動度が５．９ｃｍ^２／Ｖｓであり、良好なトランジスタ特性を示した。なお、平坦化率やθ_２の値による移動度の顕著な差は見られなかった。

The results are summarized in Table 1. As shown in Table 1, the field-effect transistor manufactured in Example 1 had a mobility of 5.7 cm ² / Vs, and showed good transistor characteristics. In addition, the field-effect transistor manufactured in Example 2 had a mobility of 6.1 cm ² / Vs, and showed good transistor characteristics. In addition, the field-effect transistor manufactured in Example 3 had a mobility of 5.9 cm ² / Vs and exhibited good transistor characteristics. In addition, the remarkable difference of the mobility by the flattening rate and the value of (theta) ₂ was not seen.

On the other hand, the field effect transistor 10X produced in the comparative example had a mobility of 1 cm ² / Vs or less, which was significantly lower than those of Examples 1 to 3. This is because, in the field effect transistor 10X in which the buried layer 14 is not formed, the thin semiconductor layer 15 on the order of nm is formed from the source electrode 12 and the drain electrode 13 to a deep position (bottom surface) in the trench 11x. It is thought that the crack etc. produced in 15 and the mobility fell.

  In other words, by forming the buried layer 14, it is possible to make it difficult for the semiconductor layer 15 to be cracked or disconnected, and to improve transistor characteristics such as mobility.

<Second Embodiment>
In the second embodiment, an example of a display element, an image display device, and a system using the field effect transistor according to the first embodiment is shown. In the second embodiment, description of the same components as those of the already described embodiments may be omitted.

(Display element)
The display element according to the second embodiment includes at least a light control element and a drive circuit that drives the light control element, and further includes other members as necessary. The light control element is not particularly limited as long as it is an element that controls the light output according to the drive signal, and can be appropriately selected according to the purpose. For example, an electroluminescence (EL) element, an electrochromic (EC) ) Elements, liquid crystal elements, electrophoretic elements, electrowetting elements and the like.

  The drive circuit is not particularly limited as long as it has the field effect transistor according to the first embodiment, and can be appropriately selected according to the purpose. There is no restriction | limiting in particular as another member, According to the objective, it can select suitably.

  Since the display element according to the second embodiment includes the field effect transistor according to the first embodiment, transistor characteristics such as mobility are good. As a result, high quality display can be performed.

(Image display device)
The image display device according to the second embodiment includes at least a plurality of display elements according to the second embodiment, a plurality of wirings, and a display control device. It has a member. The plurality of display elements are not particularly limited as long as they are the display elements according to the plurality of second embodiments arranged in a matrix, and can be appropriately selected according to the purpose.

  The plurality of wirings are not particularly limited and can be appropriately selected depending on the purpose as long as the gate voltage and the image data signal can be individually applied to each field effect transistor in the plurality of display elements.

  The display control device is not particularly limited as long as the gate voltage and signal voltage of each field effect transistor can be individually controlled via a plurality of wirings according to image data, and is appropriately selected according to the purpose. can do. There is no restriction | limiting in particular as another member, According to the objective, it can select suitably.

  Since the image display device according to the second embodiment includes the display element including the field effect transistor according to the first embodiment, it is possible to display a high-quality image.

(system)
The system according to the second embodiment includes at least an image display device according to the second embodiment and an image data creation device. The image data creation device creates image data based on the image information to be displayed, and outputs the image data to the image display device.

  Since the system includes the image display device according to the second embodiment, the image information can be displayed with high definition.

  Hereinafter, the display element, the image display apparatus, and the system according to the second embodiment will be specifically described.

  FIG. 9 shows a schematic configuration of a television apparatus 500 as a system according to the second embodiment. In addition, the connection line in FIG. 9 shows the flow of a typical signal and information, and does not show all the connection relations of each block.

  A television apparatus 500 according to the second embodiment includes a main controller 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, and a DA converter (DAC). 512, audio output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, image display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541 A hard disk device 542, an optical disk device 543, an IR light receiver 551, a communication control device 552, and the like.

  The main control device 501 controls the entire television device 500 and includes a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program written in a code readable by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

  The tuner 503 selects a preset channel broadcast from the broadcast waves received by the antenna 610. The ADC 504 converts the output signal (analog information) of the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information from the ADC 504.

  The TS decoder 506 performs TS decoding on the output signal of the demodulation circuit 505 and separates audio information and video information. The audio decoder 511 decodes the audio information from the TS decoder 506. The DA converter (DAC) 512 converts the output signal of the audio decoder 511 into an analog signal.

  The audio output circuit 513 outputs the output signal of the DA converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video / OSD synthesis circuit 522 synthesizes the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

  The video output circuit 523 outputs the output signal of the video / OSD synthesis circuit 522 to the image display device 524. The OSD drawing circuit 525 includes a character generator for displaying characters and figures on the screen of the image display device 524, and a signal including display information in response to an instruction from the operation device 532 or the IR light receiver 551. Generate.

  The memory 531 temporarily stores AV (Audio-Visual) data and the like. The operating device 532 includes an input medium (not shown) such as a control panel, for example, and notifies the main controller 501 of various information input by the user. The drive IF 541 is a bi-directional communication interface, and is compliant with ATAPI (AT Attachment Packet Interface) as an example.

  The hard disk device 542 includes a hard disk and a drive device for driving the hard disk. The drive device records data on the hard disk and reproduces data recorded on the hard disk. The optical disk device 543 records data on an optical disk (for example, DVD) and reproduces data recorded on the optical disk.

  The IR light receiver 551 receives the optical signal from the remote control transmitter 620 and notifies the main controller 501 of it. The communication control device 552 controls communication with the Internet. Various information can be acquired via the Internet.

  The image display device 524 includes a display 700 and a display control device 780 as shown in FIG. 10 as an example. As shown in FIG. 11 as an example, the display 700 includes a display 710 in which a plurality of (here, n × m) display elements 702 are arranged in a matrix.

  In addition, as shown in FIG. 12 as an example, the display 710 includes n scanning lines (X0, X1, X2, X3,..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction, in the Y-axis direction M current supply lines (Y0i, Y1i, Y2i, Y3i,..., Ym-1i) arranged at equal intervals along the line. The display element 702 can be specified by the scan line and the data line.

  As shown in FIG. 13 as an example, each display element 702 includes an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a color-compatible 32-inch display. The size is not limited to this.

  As shown in FIG. 14 as an example, the organic EL element 750 includes an organic EL thin film layer 740, a cathode 712, and an anode 714.

The organic EL element 750 can be disposed beside a field effect transistor, for example. In this case, the organic EL element 750 and the field effect transistor can be formed on the same substrate. However, it is not limited to this, For example, the organic EL element 750 may be arrange | positioned on a field effect transistor. In this case, since the gate electrode needs to be transparent, the gate electrode was added with ITO (Indium Tin Oxide), In ₂ O ₃ , SnO ₂ , ZnO, Ga added ZnO, Al. A transparent oxide having conductivity such as SnO ₂ to which ZnO or Sb is added is used.

In the organic EL element 750, Al is used for the cathode 712. Note that an Mg—Ag alloy, an Al—Li alloy, ITO, or the like may be used. ITO is used for the anode 714. Note that a conductive oxide such as In ₂ O ₃ , SnO ₂ , or ZnO, an Ag—Nd alloy, or the like may be used.

  The organic EL thin film layer 740 includes an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. A cathode 712 is connected to the electron transport layer 742, and an anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

  As shown in FIG. 13, the drive circuit 720 includes two field effect transistors 810 and 820 and a capacitor 830. The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to one terminal of the capacitor 830.

  The capacitor 830 is for storing the state of the field effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

  The field effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. The drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

  Therefore, when the field effect transistor 810 is turned on, the organic EL element 750 is driven by the field effect transistor 820.

  As an example, the display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG.

  The image data processing circuit 782 determines the brightness of the plurality of display elements 702 in the display 710 based on the output signal of the video output circuit 523. The scanning line driving circuit 784 individually applies voltages to the n scanning lines in accordance with an instruction from the image data processing circuit 782. The data line driving circuit 786 individually applies voltages to the m data lines in accordance with an instruction from the image data processing circuit 782.

  As is clear from the above description, in the television apparatus 500 according to the present embodiment, the video decoder 521, the video / OSD synthesis circuit 522, the video output circuit 523, and the OSD drawing circuit 525 constitute an image data creation apparatus. ing.

  In the above description, the light control element is an organic EL element. However, the present invention is not limited to this, and a liquid crystal element, an electrochromic element, an electrophoretic element, or an electrowetting element may be used.

  For example, when the light control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 16, the current supply line in the display element 703 is not necessary.

  In this case, as shown in FIG. 17 as an example, the drive circuit 730 is configured by only one field effect transistor 840 similar to the field effect transistor (810, 820) shown in FIG. Can do. In the field effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Note that reference numerals 762 and 772 in FIG. 17 denote a counter electrode (common electrode) of the capacitor 760 and the liquid crystal element 770, respectively.

  In the above embodiment, the case where the system is a television apparatus has been described. However, the present invention is not limited to this. In short, the image display device 524 may be provided as a device for displaying images and information. For example, a computer system in which a computer (including a personal computer) and an image display device 524 are connected may be used.

  In addition, an image display device 524 is provided as a display means in a portable information device such as a mobile phone, a portable music playback device, a portable video playback device, an electronic BOOK, a PDA (Personal Digital Assistant), or an imaging device such as a still camera or a video camera. Can be used. Further, the image display device 524 can be used as a display unit for various information in a mobile system such as a car, an aircraft, a train, and a ship. Furthermore, the image display device 524 can be used as a display unit for various information in a measurement device, an analysis device, a medical device, and an advertising medium.

  The preferred embodiments and the like have been described in detail above, but the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope described in the claims. Variations and substitutions can be added.

DESCRIPTION OF SYMBOLS 10, 10A, 10B Field effect transistor 11 Glass substrate 11x Groove 11y, 11z Convex part 12 Source electrode 13 Drain electrode 14 Embedded layer 15 Semiconductor layer 16 Gate insulating layer 17 Gate electrode 120 Metal film 140 Coating liquid for embedded layer formation

JP 2007-67367 A

Claims (13)

A method of manufacturing a field effect transistor having a glass substrate,
Forming a metal film made of Ti, Ti alloy, or a laminate containing Ti or Ti alloy on a glass substrate;
Forming a source electrode and a drain electrode from the metal film by wet etching, and forming a groove in the glass substrate other than the region where the source electrode and the drain electrode are formed;
Forming a buried layer in the groove;
Forming a semiconductor layer on the source electrode, the drain electrode, and the buried layer, and a method of manufacturing a field effect transistor. The step of forming the buried layer includes a step of applying a filling layer forming coating solution to at least the groove;
The method for producing a field effect transistor according to claim 1, further comprising: baking the coating liquid for forming the buried layer.   3. The electric field according to claim 2, wherein the step of forming the buried layer includes a step of exposing the surface of the source electrode and the drain electrode by etching back the fired coating liquid for forming the buried layer. Method for producing effect transistor.   4. The method of manufacturing a field effect transistor according to claim 2, wherein the coating liquid for forming the buried layer includes an organic solvent and a silane compound.   5. The method of manufacturing a field effect transistor according to claim 4, wherein the coating liquid for forming the buried layer contains an alkaline earth metal compound. A field effect transistor having a glass substrate,
A source electrode and a drain electrode made of any one of Ti, Ti alloy, or a laminate containing Ti or Ti alloy formed on a glass substrate;
Grooves formed in the glass substrate other than the region where the source electrode and the drain electrode are formed;
A buried layer formed in the groove;
A field effect transistor comprising: the source electrode, the drain electrode, and a semiconductor layer formed on the buried layer.   7. The relation of B <C <A + B is satisfied, where A is the film thickness of the source electrode and the drain electrode, B is the depth of the groove, and C is the minimum film thickness of the buried layer. The field effect transistor described. The source electrode is formed on the first convex part having a trapezoidal cross-sectional shape formed on the glass substrate,
In cross section, the bottom angle of the drain electrode side of the lower base of the first convex portion is theta _1, and the extension surface of the source electrode side end of the upper surface of said buried layer, said drain electrode of said source electrode The angle formed with the side surface is θ ₂ , θ ₂ is θ ₁ or less,
The drain electrode is formed on the second convex part having a trapezoidal cross-sectional shape formed on the glass substrate,
In a cross-sectional view, the base angle on the source electrode side of the lower base of the second convex portion is θ ₃ , an extended surface of the drain electrode side end of the upper surface of the buried layer, and the source electrode side of the drain electrode the angle between the side surface is theta _4, the field-effect transistor according to claim 6 or 7, characterized in that theta ₄ is theta ₃ or less.   The field effect transistor according to claim 6, wherein the buried layer contains an alkaline earth metal compound. A drive circuit;
A light control element whose light output is controlled in accordance with a drive signal from the drive circuit;
Have
The display device, wherein the drive circuit drives the light control element by the field effect transistor according to claim 6.   The display device according to claim 10, wherein the light control element is an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoretic element, or an electrowetting element. A display device in which a plurality of display elements according to claim 10 or 11 are arranged in a matrix,
A display control device for individually controlling each of the display elements;
A display device comprising: A display device according to claim 12,
An image data creation device for supplying image data to the display device;
The system characterized by having.

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