JP2018011216A - Sound data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To switch a word clock between synchronized clocks without muting sound data to be outputted and without noise caused by a phase difference.SOLUTION: When switching a clock to be outputted in a state where a selector 220 selects and outputs a sampling clock S-x, into a sampling clock Sd-y (x,y=0 to n and x≠y), a control part 208 causes a selector 207 of a supply part 204 to select an SRC part 206. Synchronously to a sampling clock CKo that the selector 220 is outputting, the SRC part 206 generates and outputs a sample in timing deviated from timing of the clock just by a phase adjustment value Tb defining a phase difference Ta between the sampling clock S-x and a sampling clock S-y as an initial value. The control part 208 decreases the phase adjustment value Tb with the lapse of time.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a sound data processing apparatus.

  2. Description of the Related Art Conventionally, in various sound data processing apparatuses that output digital sound signals (referred to as “sound data”) such as a digital mixer, sound data is input from an external device. Further, as described in Patent Document 1, there is also known a device that inputs sound data accompanied by a word clock (timing information) from a plurality of external devices.

Patent Document 1 discloses that a digital sound processing apparatus selects any one sound data supply source, generates a sampling clock based on a word clock supplied from the supply source, and outputs a clock for outputting the sound data. Describes a sound data processing device to be supplied to a DSP (digital signal processing unit).
Separately, in Patent Document 2 and Patent Document 3, a sample of sound data and a sample at the midpoint of the next sample are obtained by using an interpolation operation such as Lagrange interpolation. An inter-sample interpolation technique for calculating from previous and subsequent samples is described. Patent Document 3 describes a sample rate conversion technique that uses this interpolation to convert an input sample sequence into an output sample sequence having a different sampling frequency.

Japanese Patent No. 3760483 Japanese Patent Publication No.59-17838 Japanese Patent No. 3221041

  However, in the conventional sound data processing apparatus described in Patent Document 1, when the selection of the word clock used for generating the sampling clock that defines the output timing of the sound data is changed, the sound data is generated from the newly selected word clock. There is a problem that a certain amount of time is required for the sampling clock to be stabilized. For this reason, the sound data output timing fluctuates while the sampling clock is unstable. Therefore, if the selection of the word clock is changed, the sound data is output for a certain period of time until the sampling clock becomes stable. Had to be muted (squeezing the level so that no sound could be heard).

  In this regard, for each input unit that receives sound data, a PLL (phase lock loop) unit that generates sampling clock candidates based on the word clock transmitted together with the sound data is provided, and the sound data is output from each candidate. If a sampling clock that defines the timing is selected, it can be improved to some extent. This is because the sampling clock candidates have already been stably generated at the selected time.

When the sound data processing apparatus having this configuration receives a plurality of word clocks synchronized with each other, the phases do not coincide with each other among the plurality of candidates generated by the plurality of PLLs. This is because the phases of word clocks followed by the candidates are different from each other. For this reason, when the user changes the selection of the candidate, the sampling clock fluctuates due to the phase difference between the candidates, and noise is generated in the output sound data.
Therefore, when a PLL unit is provided for each sound data input unit, even if a plurality of candidates are generated from a plurality of word clocks synchronized with each other, it is a short period when the selection is changed between these candidates. There is a problem that the sound data output must be muted. Note that it is common in professional audio equipment to synchronize the word clocks (or sampling clocks) of multiple devices. In that case, sound data can be transmitted between these devices without sample rate conversion.

  In such a situation, the present invention does not mute the output sound data when the switching of the word clock used for generating the clock signal that defines the output timing of the sound data is switching between the clocks to which it synchronizes. In addition, it is an object of the present invention to be able to perform without noise caused by the phase difference.

  In order to achieve the above object, a sound data processing apparatus according to the present invention includes a receiving unit that receives sound data, a first PLL unit that generates a first clock signal based on a first word clock, and the first word clock. A second PLL unit that generates a second clock signal based on a second word clock synchronized with the first clock signal, and first outputs the first clock signal, and then outputs an output clock signal in response to a first switching instruction. A clock output unit for switching to a two-clock signal, and a phase difference for outputting a phase difference between the first clock signal and the second clock signal in response to the switching, and then reducing the phase difference to be output as time elapses The sound data corresponding to the sound data received by the output unit and the receiving unit is associated with the reproduction timing indicated by the clock signal output by the clock output unit. In a sound data processing apparatus including a sound data output unit that outputs to a subsequent stage, a clock signal output from the clock output unit by interpolating a sample of sound data received by the reception unit into the sound data output unit Is provided with an interpolation output unit that generates a sample with a timing shifted by the phase difference output from the phase difference output unit and outputs the sample in synchronization with the clock signal output from the clock output unit.

  In such a sound data processing device, the sound data received by the receiving unit is synchronized with the first word clock, and the sound data output unit further includes a sample of the sound data received by the receiving unit. Are sequentially stored and output in synchronization with the clock signal output from the clock output unit, and the storage output unit outputs the first clock signal while the clock output unit outputs the first clock signal. Select and output a sample, after the switching of the clock output unit, until the phase difference output by the phase difference output unit becomes zero, select and output the sample output by the interpolation output unit, After that, it is preferable to provide an output selection unit that selects and outputs the sample output from the storage output unit.

Furthermore, a third PLL unit that generates a third clock signal based on a third word clock that is not synchronized with the first clock is provided, and the clock selection unit first outputs the first clock signal, and then the second clock signal. In response to the switching instruction, the output clock signal is switched to the third clock signal, and the phase difference output unit outputs a phase difference of zero in response to the clock output unit outputting the third clock. The output selection unit mutes the output of the sound data for a predetermined period in response to the clock output unit outputting the third clock signal, and then selects and outputs the sample output by the interpolation output unit. It is good to do so.
Further, the sound data received by the receiving unit is not synchronized with the first word clock, and the sound data output unit continuously outputs the samples output by the interpolation output unit to the subsequent stage. May be.
In addition to being realized as an apparatus as described above, the present invention can be realized in any form such as a method, a system, a program, and a recording medium recording the program.

  According to the configuration of the present invention as described above, in the sound data processing device, the switching of the word clock used for generating the clock signal that defines the output timing of the sound data is switching between the clocks to which it synchronizes. In addition, the sound data to be output can be performed without muting and without noise caused by the phase difference.

FIG. 1 is a diagram showing a hardware configuration example of a digital mixer which is an embodiment of a sound data processing apparatus of the present invention. It is a figure which shows the structure of the sound signal input part shown in FIG. 1 in detail. It is a figure which shows the timing of sampling clock CKo and the sound data output at the time of the selection switching of the sampling clock in the sound signal input part shown in FIG. It is a figure which shows the example of the sample output as sound data, and its output timing in case there is no switching of a sampling clock. It is a figure which shows the sample output as sound data when the sampling clock is switched, and its output timing. It is a figure which shows typically the condition of control of the supply part which a control part performs when there exists switching of a sampling clock. It is a figure which shows the example of a clock frequency table. It is a figure which shows the example of a clock source selection screen. 3 is a flowchart of an operation executed when the control unit of the sound signal input unit illustrated in FIG. 2 detects selection of a sampling clock. FIG. 9 is a flowchart of a first phase adjustment operation started in step S14 of FIG. 10 is a flowchart of a second phase adjustment operation started in step S15 of FIG.

Hereinafter, embodiments for carrying out the present invention will be specifically described with reference to the drawings.
[Embodiment: FIGS. 1 to 10]
First, a digital mixer which is an embodiment of a sound data processing apparatus of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the digital mixer.
As shown in FIG. 1, the digital mixer 10 includes a CPU 11, a ROM 12, a RAM 13, a display 14, an operator 15, a sound signal input unit 20, a signal processing unit (DSP) 21, and a sound signal output unit 22. They are connected by a bus 16. The sound signal processing apparatus has a function of performing various signal processing on the sound signal received by the receiving unit through a plurality of signal processing channels (ch) and outputting the processed signal, and samples the sound signal received by the receiving unit. This is a sound data processing device that outputs in synchronization with a clock signal to be described later.

  The CPU 11 is a control means for controlling the operation of the entire digital mixer 10 and controls required hardware by executing a required program stored in the ROM 12. This allows the sound signal input unit 20 and the sound signal output unit 22 to input / output sound signals and other data, display on the display unit 14, operation detection of the operating element 15, and parameter settings according to the detected operation. Various functions such as value change and display change are realized.

The ROM 12 is a nonvolatile storage unit that stores a control program executed by the CPU 11. The ROM 12 may be constituted by a flash memory which is a rewritable nonvolatile storage means.
The RAM 13 is a storage means for storing data to be temporarily stored and used as a work memory for the CPU 11.

The display unit 14 is a display unit that displays various information according to control by the CPU 11, and can be configured by, for example, a liquid crystal panel (LCD) or a light emitting diode (LED). In the example described here, the digital mixer 10 includes an LCD having a size capable of displaying at least the clock source selection screen 300 shown in FIG.
The operation element 15 is for accepting a user operation on the digital mixer 10 and can be constituted by various keys, buttons, a rotary encoder, a slider, and the like. A touch panel laminated on the LCD serving as the display 14 can also be used.

The sound signal input unit 20 has at least a function of inputting digital sound data from an external device, and includes a plurality of receiving units that receive the sound data together with a word clock accompanying the sound data.
Although the format and procedure of this word clock differs depending on the transmission method of sound data, the timing of finally reproducing each sample of the sound data transmitted along with the sound data by a digital-analog converter (DAC) ( Timing information). The entity of the word clock varies depending on the system. In some cases, the sample reproduction timing is indicated by the change timing of the electric signal. In other cases, the reproduction timing is indicated by the timing at which the packet containing the sample is received. In some cases, numerical values indicate the sample playback timing. The word clock (in a broad sense) is a broader concept than the “narrow word clock” in which one clock per sample. In other words, in a broad word clock, there are cases where one cycle of the word clock is subdivided to generate the reproduction timing (sample cycle) of each sample.

That is, when transmitting sound data of a plurality of consecutive samples in one packet as in CobraNet (trademark) or Dante (trademark), the cycle indicated by the word clock is not the reproduction timing for each sample. , The reproduction timing for every n samples (n is an integer of 2 or more).
Each sample of sound data is subjected to various signal processing required, and then at the reproduction timing indicated by the word clock (more precisely, in synchronization with the sampling clock generated from the word clock). It is converted into an analog sound signal and output.
In this specification, when “word clock” is described without distinguishing between narrow sense and broad sense, this “wide sense word clock” is indicated.

In addition, the sound signal input unit 20 inputs a word clock acquired by the receiving unit for each digital sound signal receiving unit, and generates a sampling clock S (a candidate for the sampling clock CKo) from the word clock. A circuit 203 is provided.
The sound signal sampling clock CKo is a clock that defines the reproduction timing of the sound signal when the sound signal is reproduced as it is or after the sound signal is processed by the DSP 21 or the like in units of sample periods. In this digital mixer 10, since the generated clock S and clock CKo are also used for serial transmission and sample rate conversion, high accuracy is required, and the clock signal of integer part 5 bits + decimal part 12 bits is used. The sampling clock CKo is expressed. One count in the integer part indicates an output period for one sample (period for one clock of the word clock). The decimal part 12 bits are generated according to the clock generated by the master PLL circuit 203 at a frequency of 4096 times the word clock.

  The sound signal input unit 20 has a function of inputting an analog sound signal and a word clock supplied from an external clock source in addition to a function of generating the sampling clock S, and a sampling clock CKo supplied to the DSP 21 and the sound signal output unit 22. A function for selecting from a plurality of candidates is provided. These functions will be described later with reference to FIG.

  The DSP 21 performs signal processing on each sample of the sound data supplied from the sound signal input unit 20 in synchronization with a sample period defined by the sampling clock CKo supplied from the sound signal input unit 20. A function of outputting subsequent sound data to the sound signal output unit 22 is provided. Note that the DSP 21 does not need to operate in exact synchronization with the sampling period, and the quality of the signal processing of the DSP 21 is not affected by the quality of the sampling clock CKo.

  For example, in the case of a digital mixer, the signal processing executed by the DSP 21 is an input patch process for supplying any of a plurality of sound data supplied from the outside via the sound signal input unit 20 to a plurality of input channels. Input channel processing for performing various ch signal processing such as level adjustment, frequency characteristic adjustment, effect addition, etc., and mixing the sound data after processing of each input channel to a plurality of mixing buses Processing, output channel processing for performing various channel signal processing on the output channel corresponding to the mixing bus for the sound data mixed in each mixing bus, and output sound processing after processing for each output channel as output channel It includes output processing for outputting to the output port of the associated sound signal output unit 22.

  The sound signal output unit 22 has a function of converting each sample of sound data processed by the DSP 21 into an analog sound signal at a reproduction timing defined by the sampling clock CKo, and outputting the sample to the outside by the internal DAC. Prepare. In addition, the sound signal output unit 22 converts the reproduction timing indicated by the sampling clock CKo into a word clock at the internal transmission unit and adds it to the sound data processed by the DSP 21, and converts the digital sound data by various transmission methods. It also has a function to send output to external equipment.

  Even when the sound data is transmitted to another device as digital, it is finally converted into an analog sound signal at a reproduction timing indicated by the added word clock at some point of the transmission destination. Considering this point, even when digitally transmitting to another device, the sampling clock CKo can be said to “show the reproduction timing of the sound data sample”. As the output destination or transmission destination of the sound data, various devices such as a sound generation device such as a powered speaker, a recording device, and another sound signal processing device are conceivable. When an audio network is used, the sound signal output unit 22 can output the sound signal via the same network that the sound signal input unit 20 uses to receive the sound signal.

In the digital mixer 10 having the above configuration, one of the characteristic points is the configuration of the sound signal input unit 20. Therefore, the configuration of the sound signal input unit 20 will be described in detail below with reference to FIG.
As shown in FIG. 2, the sound signal input unit 20 receives a plurality of (here, n) digital sound signal receiving units 200-that receive sound data and the accompanying word clock via cables of various transmission methods. 1-200-n (the number specifying the individual after the hyphen is called a “subscript”, and thereafter, when there is no need to specify the individual, a code without a subscript is used. The same shall apply to the above). The sound signal input unit 20 also includes a word clock input unit 210 that receives a word clock signal (word clock in a narrow sense).

Among these, each i-th (where 1 ≦ i ≦ n) receiving unit 200-i includes a carrier clock recovery unit 201-i and a data recovery unit 202-i. The sound signal input unit 20 is provided with a master PLL circuit 203-i and a supply unit 204-i corresponding to each receiving unit 200. The supply unit 204-i includes a first-in first-out (FIFO) 205-i and a sampling rate SRC (sampling rate).
Conversion) section 206-i and selector 207-i. In the drawing, numbers i corresponding to the receiving units 200-i are appended as subscripts to the reference numerals of these units. The same applies to sound data D, word clock W, and sampling clock S described later.
The sound signal input unit 20 also includes a control unit 208 and a selector 220.

  Among these, the carrier clock recovery unit 201-i has a function of generating a carrier clock synchronized with each bit of the bit string signal from the waveform of the bit string signal of the transmission method input from the outside through a cable of various transmission methods. Prepare. The carrier clock recovery unit 201-i can be configured by a PLL circuit having good followability to the bit rate specified by the transmission method. Since the frequency stability of this PLL circuit is not so high, a carrier clock generated by a PLL circuit for a transmission system other than the audio transmission line cannot be used as a sampling clock. Even if the carrier clock is generated by the PLL circuit for the audio transmission line, it is possible to obtain a higher quality word clock through the master PLL.

  The data recovery unit 202-i regenerates a bit string from the waveform of the bit string signal of each transmission method using the carrier clock generated by the carrier clock reproduction part 201-i, and further generates sound data D-i of each sample from the bit string. The function to take out. More specifically, the waveform of the bit string signal is latched at the timing indicated by the carrier clock, the value of each bit of the transmitted bit string is determined, and an algorithm according to the transmission method is used to determine the value of each bit from the bit string. Extract sound data.

  For example, in the case of an audio transmission line, if data of the number of bits corresponding to one sample is extracted from the bit string for every predetermined number of bits, it becomes sound data of each sample. If the transmission method uses a packet, first, a frame is extracted from the bit string based on the bit pattern of the preamble, the packet is extracted from the frame, and further, the data of the sound signal area of the packet is extracted. Sample sound data can be obtained.

The data recovery unit 202-i is provided with a circuit such as an FPGA (Field Programmable Gate Array) for performing an extraction operation according to the transmission method to be used. You may enable it to perform extraction operation according to one transmission method selected from a plurality of transmission methods.
Then, the data recovery unit 202-i supplies the sound data Di extracted from the received sound signal to both the FIFO 205-i and the SRC unit 206-i of the corresponding supply unit 204-i. At this time, if sound data for a plurality of channels is extracted, the sound data is supplied separately for each channel.
In addition, the data recovery unit 202-i uses the master PLL circuit 203 as the reception timing of the packet including the sound data, the time stamp attached to the sound data, and the like as the word clock Wi indicating the reproduction timing of the sound data sample. -Supply to i.

  The master PLL circuit 203-i is a PLL unit, and generates a highly stable sampling clock Si following the phase of the input word clock Wi. The master PLL circuit 203-i generates a clock having a frequency 4096 times the word clock (sample frequency), and generates a sampling clock Si as data of an integer part 5 bits + decimal part 12 bits counted according to the clock. To do. The master PLL circuit 203-i supplies the generated sampling clock S-i to the control unit 208 and the selector 220. Note that the period of the sampling clock Si is a period of one count of the integer part, and coincides with the sampling period of the word clock W except that the stability is different. How many times the sampling frequency is generated may be appropriately changed according to the purpose of use of the sampling clock Si.

  The supply unit 204-i is a sound data output unit, and based on each sample of the sound data input from the data recovery unit 202-i, the sound data corresponding to the sound data is reproduced at the reproduction timing indicated by the sampling clock CKo. A function of supplying a sample to the DSP 21 is provided. There are two supply functions, a buffer function and an SRC function.

  Of these, the FIFO 205-i serving as a storage output unit plays a buffer function. The FIFO 205-i is a buffer memory controlled by a first-in first-out (FIFO) algorithm, sequentially stores each sample of sound data input from the data recovery unit 202-i, and reproduces it indicated by the sampling clock CKo. The data is sequentially output to the selector 207-i at the timing.

  If there is a timing shift between the word clock Wi and the sampling clock CKo, the number of samples input to the FIFO 205-i and the number of samples output from the FIFO 205-i differ within a predetermined time by the shift. . Therefore, the time from when the sample is input to the FIFO 205-i until it is output, that is, the delay time of the sample due to the FIFO 205-i is different for each sample. However, there is no particular problem as long as the buffer does not overflow or become empty.

  On the other hand, the SRC unit 206-i which is an interpolation output unit bears the SRC function. The SRC unit 206-i synthesizes a virtual sample at an arbitrary timing of the sound data D-i from the input sound data D-i at the reproduction timing indicated by the sampling clock CKo, and outputs it to the selector 207-i. To do. This synthesis can be performed by a complementary operation using a Lagrangian function or a function obtained by applying a window function to the SINC function using samples before and after the timing (not limited to immediately before and after).

  At this time, if a sample of the reproduction timing is synthesized with each reproduction timing, the SRC unit 206-i substantially converts the sound data having a sample period different from the sampling clock CKo received by the reception unit 200-i into the sampling clock. The sound data having the same sample period as CKo can be converted, and each sample of the converted sound data can be output.

  Further, the SRC unit 206-i can synthesize and output a virtual sample at a timing shifted from the reproduction timing at each reproduction timing. Thus, in addition to the conversion of the sampling frequency, the phase of the sample output at each reproduction timing can be adjusted. The control unit 208 sets the SRC unit 206-i as a phase difference value at any time as to how much the sample at the timing shifted from the reproduction timing is to be synthesized by the SRC unit 206-i.

The selector 207-i has a function of selecting either the sound data output from the FIFO 205-i or the sound data output from the SRC unit 206-i and supplying the selected sound data to the subsequent DSP 21 as the sound data Di. . This selection is performed according to a control signal from the control unit 208, and the control unit 208 and the selector 207-i operate as an output selection unit.
Here, when the FIFO 205 is used, all the samples of the sound data extracted by the data recovery unit 202 are output after finely adjusting the output timing. When the SRC unit 206 is used, a sample generated by a complementary operation is output. However, in any case, the output sound data is sound data indicating (almost) the same sound as the sound indicated by the sound data extracted by the data recovery unit 202. This is referred to as outputting sound data corresponding to the received sound data.

  The control unit 208 has a function of controlling each supply unit 204 based on the sampling clock S supplied from each master PLL circuit 203-0 to n. Further, it has a function of controlling the selector 220 in accordance with an instruction from the CPU 11. These control functions may be realized by dedicated hardware, realized by software, or a combination thereof. Details of the control function will be described in detail with reference to FIG.

  The selector 220 is a clock output unit, which will be described in detail later, but selectively outputs one of a plurality of sampling clocks S supplied to the selector 220 in accordance with an instruction from the control unit 208. The selector 220 supplies the selected clock signal to the DSP 21 and the sound signal output unit 22 as a sampling clock CKo that defines the reproduction timing of each sample of the sound data. The selector 220 also supplies the sampling clock CKo to the supply units 204 corresponding to the reception units 200-1 to 200-n.

  In the sound signal input unit 20, the waveform shaping unit 211 of the word clock input unit 210 has a function of adjusting the waveform of the word clock signal (word clock in a narrow sense) input from the outside. The waveform shaping unit 211 can be configured by a filter or a comparator.

In the word clock signal whose waveform is adjusted, the voltage inversion timing indicates the sample reproduction timing, and is handled in the same manner as the word clock W output from the data recovery unit 202. This word clock is referred to herein as the word clock W-0 using the subscript “0”. The subscript “0” is also used for the master PLL circuit 203 corresponding to the word clock input unit 210.
The function of the master PLL circuit 203-0 is the same as that of the other master PLL circuit 203, and generates a highly stable sampling clock S-0 from the input word clock W-0.

  Next, a control operation executed by the control unit 208 in the sound signal input unit 20 described above will be described. One of the characteristic features of this control is that noise is not generated in the sound signal output from the sound signal output unit 22 when the sampling clock S selected by the selector 220 as the sampling clock CKo is changed. (Mute if noise is inevitable). The following description will focus on this point.

First, FIG. 3 is a diagram showing the timing of sampling clock CKo and sound data output when the selector 220 switches the sampling clock.
In FIG. 3, a sampling clock S before switching (first clock signal: S-x) and a sampling clock S after switching (second clock signal: S-y) indicate LSBs of integer parts, respectively. The signal rises at the timing when the decimal part becomes 0, and falls at the half of one cycle. Further, it is assumed that the sampling clock S-x and the sampling clock S-y are synchronized with each other (the sampling period is substantially the same) and are out of phase.

  Here, when switching the selection of the sampling clock S, the selector 220 holds the clock in a falling state after the sampling clock S-x before switching falls until the rising of the sampling clock S-y after switching. . For example, after the value of the decimal part is counted up to the upper limit value, it is held (held) as it is.

  Accordingly, if switching is performed immediately after time t1 when the sampling clock S-x rises, the sampling clock CKo output from the selector 220 falls with the sampling clock S-x at time t2, and does not rise thereafter at time t3. At time t4, the signal rises with the sampling clock S-y. For this reason, the phase of the sampling clock CKo is delayed by the phase difference Ta between the sampling clock S-x and the sampling clock S-y as the selection is switched.

On the other hand, each supply unit 204 outputs a sample of sound data in synchronization with the rising timing of the sampling clock CKo (integer part LSB). Accordingly, each supply unit 204 outputs the next sample P _{n + 1} at time t4 after outputting the sample P _n at time t1. For this reason, the output timing of the sample P _{n + 1} is delayed by Ta as compared with the case where there is no switching. Similarly, the signal processing in the DSP 21 and the output processing in the sound signal output unit 22 for the sample P _{n + 1} are also performed at a timing delayed by Ta. Therefore, if the sample P _{n + 1} is simply a sample at a timing one cycle after the sampling clock CKo from the sample P _n (a sample to be output at time t3), when the sample P _{n + 1} is finally output as a sound, Noise corresponding to the phase shift occurs.

Here, it is important that the timing of finally converting to sound by the DAC or the like is controlled by the sampling clock CKo, and the timing of each stage in the middle, such as the output timing of the supply unit 204, is as follows. It is sufficient if the sampling clock CKo is loosely synchronized.
The control unit 208 performs control to correct the sample output from each supply unit 204 immediately after switching using the SRC unit 206 so that this noise does not occur.

Next, this correction will be described with reference to FIGS. 4A and 4B.
4A and 4B are diagrams showing the relationship between the count number of the sampling clock CKo, the clock rise time, and the samples output from the supply unit 204 in synchronization with each count. FIG. 4A is an example when the sampling clock is not switched, and FIG. 4B is an example when the switching is performed in the second period. In both figures, the time is one cycle time of the sampling clock CKo (= one cycle time of the sampling clocks S-x and S-y) and “1” is the rise time of the first clock. Represents.

  The output sample indicates a sample to be output at time t when the sampling clock is not switched as P (t). This sample P (t) will be referred to as “sample at time t”. When the sampling period of the word clock W (= the period of the sampling clock S) received along with the sound data in a certain receiving unit 200 is equal to the period of the sampling clock CKo (this is assumed in the description up to FIG. 5). The sample P (t) where t is an integer can be obtained by reading out the sample written by the data recovery unit 202 as it is using the FIFO 205. The sample P (t) where t is not an integer can be generated using the SRC unit 206 by complementing the samples at integer timings before and after the t.

  First, in the case of FIG. 4A, since the sampling clock CKo is counted at equal intervals, the time progress is also “1” per clock. For this reason, the time of the output sample is also shifted by one period in accordance with it. Since t is always an integer, in order to perform such an output, the control unit 208 causes the selector 207 to select the sound data of the FIFO 205 and samples the sample written in the FIFO 205 by the data recovery unit 202. What is necessary is just to output synchronizing with the clock CKo.

  Next, in the case of FIG. 4B, the rising time of the sampling clock CKo immediately after switching (count number = 3) is “3.5”, which is later than usual by the phase difference Ta (in this example, 0.5). At this time, as shown in FIG. 4B, if the output sample is the sample P (3.5) at the rising time “3.5”, a plurality of samples corresponding to each rising timing of the sampling clock CKo are smoothly connected. Even when the sound is finally output, noise due to phase shift does not occur.

  When the control unit 208 instructs the selector 220 to switch the selection of the sampling clock for this output, the control unit 208 causes the selector 207 to select the sound data of the SRC unit 206 and causes the SRC unit 206 to count the next count of the sampling clock CKo. By setting the number Ct and the phase difference Ta (= initial value of the phase adjustment amount Tb), a sample at the time of Ct + Ta is generated and output in synchronization with the sampling clock CKo. Even in this case, the output of the sample is performed at the rising timing of the sampling clock CKo as in the case where there is no switching.

By the way, from this point of view, there is no problem from the viewpoint of noise prevention even if the count number Ct is advanced while the phase adjustment amount Tb is maintained. However, samples containing errors due to the interpolation calculation of the SRC unit 206 will continue to be output, which is not desirable in terms of sound quality.
Therefore, the control unit 208 performs an operation of gradually changing the phase adjustment amount Tb set in the SRC unit 206 to 0 over a certain period of time. Then, the SRC unit 206 synthesizes and outputs a sample P (Ct + Tb) at the timing of the count number Ct + phase adjustment amount Tb at each rising timing of the sampling clock CKo. The phase adjustment amount Tb may be set by the control unit 208 in the SRC unit 206 every clock or every predetermined clock. On the SRC unit 206 side, a constant value is subtracted from the initial value every clock or every predetermined clock. You may make it make it.

  Then, the control unit 208 causes the selector 207 to select the sound data of the FIFO 205 when the phase adjustment amount Tb reaches 0, and thereafter supplies the sound data from the FIFO 205 to the DSP 21. In the example of FIG. 4B, the phase adjustment amount Tb is decreased by “0.02” every clock, and becomes “0” at the 53rd count, and the FIFO 205 is selected from the 53rd count.

  In this way, if the phase of the output sample is shifted little by little at the SRC unit 206, the phase can be finally set to a desired value without causing noise in the output sound. You can go back to the selection. After that, the FIFO 205 can output the sample received by each receiving unit 200 to the DSP 21 as it is (shifted by the timing), thereby realizing high-quality sound output.

FIG. 5 schematically shows the control described with reference to FIG. 4B.
The graph in FIG. 5 shows the transition of the phase adjustment amount Tb, and “selected sound data” indicates which sound data of the FIFO 205 or the SRC unit 206 is selected by the selector 207 at each time.

  As shown in FIG. 5, when the control unit 208 causes the selector 220 to switch the selection of the sampling clock, the control unit 208 causes the selector 207 to select the sound data of the SRC unit 206 and sets the initial value of the phase adjustment amount Tb before and after the switching. A phase difference Ta between sampling clocks is set in the SRC unit 206. Thereafter, the control unit 208 gradually decreases the phase adjustment amount Tb as time elapses. When the phase adjustment amount Tb reaches zero, the control unit 208 causes the selector 207 to select the sound data of the FIFO 205 and thereafter continues as it is if there is no change in the sampling clock CKo.

  As a result, it is possible to prevent the influence of the phase fluctuation of the sampling clock CKo caused by the selection switching of the sampling clock from affecting the sound output from the sound signal output unit 22. Further, the use of the SRC unit 206 can be minimized and high-quality sound output can be performed.

  Next, the control operation at the time of switching the sampling clock executed by the control unit 208 will be described. In the following description, the case where the period of the sampling clock before and after the switching is different, or the case where the period is different between the word clock W accompanying the sound data received by the receiving unit 200 and the sampling clock CKo are also considered.

  In order to cope with these situations, the control unit 208 operates as a cycle detection unit, detects the cycle of each sampling clock S-0 to n, and registers the reciprocal thereof in the clock frequency table shown in FIG. In FIG. 6, “sampling clock ID” corresponds to the subscript of the sampling clock S in FIG. “Frequency” is the frequency of the corresponding sampling clock S, and “−” indicates no reception.

  FIG. 7 shows an example of a clock source selection screen for the CPU 11 to accept a sampling clock selection switching instruction from the user. The instruction received on this screen can also be considered as a selection switching instruction for the word clock (clock source) used for generating the clock signal. Based on the instruction received from this screen, the CPU 11 instructs the control unit 208 to switch sampling clock selection. Based on the instruction, control unit 208 causes selector 220 to select a sampling clock.

The clock source selection screen 300 of FIG. 7 includes buttons 301-0 corresponding to the word clock input unit 210 and buttons 301-1 to n corresponding to the receiving units 200-1 to 200-n, respectively. By operating a desired button 301, the user can instruct to select the sampling clock S supplied from the supply source corresponding to the button as the sampling clock CKo.
In FIG. 7, the fact that the button 301-2 is operated is indicated by hatching.

  Note that the phase adjustment described with reference to FIGS. 4B and 5 cannot be performed properly when the sampling clocks before and after switching are not synchronized (the sampling periods are substantially the same). For this reason, the CPU 11 displays a button 301-3 for selecting a sampling clock S-3 having a different period from the currently selected sampling clock S-2 based on the clock frequency table of FIG. This indicates that phase adjustment cannot be performed (mute is required when switching). Further, since a supply source that does not supply the sampling clock S cannot be selected, the CPU 11 displays an X mark indicating that on a button (here, button 301-4) corresponding to the supply source, and the button is displayed. The operation is disabled.

Next, FIGS. 8 to 10 are flowcharts of operations executed when the control unit 208 detects a sampling clock selection switching instruction from the CPU 11.
When detecting the switching instruction from the CPU 11, the control unit 208 first determines whether or not the period of the sampling clock S before and after switching is (almost) the same (synchronized) as shown in FIG. (S11). If they are the same (synchronized), the control unit 208 proceeds to step S12 and subsequent steps to perform the control described with reference to FIGS. 4B and 5. The switching instruction in this case corresponds to the first switching instruction.

  Here, the control unit 208 first detects the sampling clock phase difference Ta before and after switching (S12). Then, for each receiving unit 200, the control unit 208 determines whether the sampling cycle of the word clock W output from the receiving unit 200 is the same as the cycle of the sampling clock S-y after switching (whether or not they are synchronized). In response to (S13), the first phase adjustment operation (S14) or the second phase adjustment operation (S15) related to the corresponding supply unit 204 is started. Thereafter, the control unit 208 causes the selector 220 to select the sampling clock S-y after switching (S16), and ends the operation of FIG. As the first phase adjustment operation and the second phase adjustment operation, the control unit 208 can continuously perform the operations related to the plurality of supply units 204 after the operation of FIG.

On the other hand, when the periods are different in step S11 (when not synchronized), the sampling clock CKo after switching is not synchronized with the sound data, so the control unit 208 performs switching by the operations in step S17 and subsequent steps. The switching instruction in this case corresponds to the second switching instruction.
That is, the control unit 208 first mutes the output of sound data from each supply unit 204 (S17). This mute is to change the sample of the sound data output from the selector 207 to a sample indicating silence or an extremely low sound. In this state, noise caused by switching of the sampling clock can be ignored.

  Next, the control unit 208 causes the selector 220 to select the switched sampling clock S-y (S18). Then, the control unit 208 causes the selector 207 of the supply unit 204 corresponding to the reception unit 200 that outputs the (synchronized) word clock W having the same sampling period as the switched sampling clock S-y to select the sound data of the FIFO 205. Then, the selector 207 of the supply unit 204 corresponding to the other reception unit 200 that outputs the word clock W (not synchronized) having a different sample period is made to select the sound data of the SRC unit 206 (S19). For the latter, the setting necessary for converting the sample of the input sound data into the sample of the cycle of the sampling clock S-y after the switching is performed (a zero phase difference Ta is set in the SRC unit 206).

  Thereafter, after a predetermined time, the control unit 208 cancels the mute of the output of the sound data (S20) and ends the operation of FIG. Since the word clock W of each receiving unit 200 is already stable, the predetermined time here may be an extremely short time of about 1 to several seconds.

Next, FIG. 9 shows a flowchart of the first phase adjustment operation started in step S14 of FIG. This operation corresponds to the control described with reference to FIGS. 4B and 5. This processing is performed by paying attention to one of the supply units 204 in which the word clock of the receiving unit 200 is synchronized with both the sampling clock S-x before switching and the sampling clock S-y after switching. It is.
In the operation of FIG. 9, the control unit 208 sets the phase difference Ta detected in step S12 of FIG. 8 as the initial value of the phase adjustment amount Tb in the SRC unit 206 (S31), and the selector 207 of the supply unit 204 of interest. The sound data on the SRC unit 206 side is selected (S32). These two steps need to be performed while the same sample is being output from the supply unit 204. For example, in FIG. 3, it is performed until t3 after the switching operation. As a result, the sampling clock output from the selector 220 is held in the falling state during Ta (until t4), and the SRC unit 206 starts from the count value of the clock at the rising timing (t4) of the sampling clock CKo after switching. A sample at a time delayed by Tb is output.

Next, after the next sampling clock CKo rises (S33), the control unit 208 decreases the phase adjustment amount Tb set in the SRC unit 206 by a predetermined value (S34). This reduced phase adjustment amount is used for the interpolation calculation of the sample output from the SRC unit 206 at the next rising edge of the sampling clock CKo. If the phase adjustment amount Tb has not reached zero, the process is repeated (No in S35). If the phase adjustment amount Tb has reached zero, the control unit 208 causes the supply unit 204 to focus on the next rising edge of the sampling clock CKo. The selector 207 selects the FIFO 205 (S36), and the operation in FIG. After the operation in FIG. 9 is finished, the control unit 208 does not change the setting of the supply unit 204, but the supply unit 204 supplies the sample output from the FIFO 205 to the DSP 21 at each rising timing of the sampling clock CKo.
In FIG. 9, particularly in the operations of steps S31 and S34, the control unit 208 operates as a phase difference output unit.

Next, FIG. 10 shows a flowchart of the second phase adjustment operation started in step S15 of FIG. This operation is the same as steps S31 and S33 to S35 in FIG. 9, and therefore the step numbers also use the same numbers.
The supply unit 204 controlled by the second phase adjustment operation needs to use the SRC function continuously because the sampling cycle of the word clock W output from the corresponding receiving unit is different from the cycle of the sampling clock CKo (asynchronous). A supply unit 204 is provided. For this reason, it is different from the operation of FIG. 9 in that switching of the selector 207 is unnecessary. However, even in the operation of FIG. 10, the phase adjustment amount Tb is regarded as an offset amount, and the sample at the timing after the phase adjustment amount Tb is compared with the count value of the sampling clock CKo and the phase adjustment amount Tb later than the case of only the SRC function. If combined with 206, the phase shift with reference to the sampling clock CKo can be made zero without generating noise as in the operation of FIG. 9, and from another viewpoint, the latency as a sound data processing device is constant. It is possible to obtain an excellent effect that can be realized.

This is the end of the description of the embodiment, but it goes without saying that the configuration of the apparatus, the display content of the screen, the specific operation procedure, the transmission method to be used, and the like are not limited to those described in the above embodiment. is there.
For example, the timing at which the selector 207 selects the FIFO 205 may be not only the timing when the phase adjustment amount Tb reaches 0 or 1 clock, but also the timing when it reaches an arbitrary integral multiple of the period of the sampling clock CKo. There is no particular advantage in increasing the phase adjustment amount Tb (absolute value thereof), but it can be considered as a variation. In addition, it is not essential to select the FIFO 205 immediately after reaching the integral multiple, and it may be possible to select the FIFO 205 after a short time.

In addition to the above, the CPU 11 may automatically determine which sampling clock S is to be selected by the selector 220 on some basis. For example, a sampling clock having a frequency within a predetermined range and the smallest fluctuation width is selected.
In the embodiment described above, it is not essential to provide the word clock input unit 210. Conversely, a plurality of word clock input units 210 may be provided, a word clock may be input from a plurality of external devices, and a sampling clock generated based on the word clock may be a candidate for selection in the selector 220. Of course, the number of digital sound signal receivers 200 is arbitrary.

  Further, the number of bits of the sampling clock CKo is not limited to that of the above-described embodiment. The integer part only needs to have the number of bits corresponding to the amount of data to be buffered in the FIFO 205 or the SRC part 206, and the decimal part only needs to have the number of bits corresponding to the required resolution. In addition, the timing for performing various processes such as the output timing of the sample has been described as being performed at the clock rise (integer part count-up) timing, but is not limited thereto. You may synchronize with the timing of arbitrary phases. Regardless of the phase, it is output in association with the reproduction timing indicated by the sampling clock CKo. As long as the output sample and the reproduction timing are associated with each other, the output timing does not necessarily coincide with the reproduction timing.

In addition to the digital mixer, the present invention also receives timing information of the digital sound signal and the accompanying word clock, generates a clock signal based on the timing information, and controls timing of signal processing and sound data output. The present invention can be applied to a sound signal processing apparatus used for the above. For example, it can be applied to effectors, recorders, amplifiers, synthesizers, etc., and it can receive sound signal input from the outside and supply it to a specific device or network, or a sound signal received from a specific device or network The present invention can also be applied to a signal output device that outputs to the outside or a powered speaker.
In addition, the configurations and modifications described above can be applied in appropriate combinations within a consistent range.

  As is apparent from the above description, according to the present invention, when the switching of the word clock used for generating the clock signal that defines the output timing of the sound data is switching between the clocks that synchronize, the output It is possible to realize a sound data processing apparatus that can perform the sound data without mute and without noise caused by the phase difference.

10: Digital mixer, 11: CPU, 12: ROM, 13: RAM, 14: Display, 15: Operator, 16: System bus, 20: Sound signal input unit, 21: Signal processing unit (DSP), 22: Sound signal output unit, 200: Digital sound signal reception unit, 201: Carrier clock reproduction unit, 202: Data recovery unit, 203: Master PLL circuit, 204: Supply unit, 205: FIFO, 206: SRC unit, 207, 220: Selector, 210: Word clock input unit, 211: Waveform shaping unit, 300: Clock source selection screen, 301: Button, D: Sound data, CKo, S: Sampling clock, Ta: Phase difference, Tb: Phase adjustment amount, W : Word clock

Claims (4)

A receiver for receiving sound data;
A first PLL unit for generating a first clock signal based on the first word clock;
A second PLL unit for generating a second clock signal based on a second word clock synchronized with the first word clock;
First, a clock output unit that outputs the first clock signal and then switches the output clock signal to the second clock signal in response to a first switching instruction;
A phase difference output unit that outputs a phase difference between the first clock signal and the second clock signal in response to the switching, and then reduces a phase difference that is output as time elapses;
A sound data processing apparatus comprising: a sound data output unit that outputs sound data corresponding to sound data received by the receiving unit to a subsequent stage in association with a reproduction timing indicated by a clock signal output from the clock output unit; ,
The sound data output unit interpolates the sample of the sound data received by the reception unit, so that a sample at a timing shifted from the clock signal output by the clock output unit by the phase difference output by the phase difference output unit is obtained. The sound data processing apparatus comprising: an interpolation output unit that generates and outputs in synchronization with a clock signal output from the clock output unit. The sound data processing device according to claim 1,
The sound data received by the receiver is synchronized with the first word clock,
The sound data output unit further includes:
A storage output unit that sequentially stores samples of sound data received by the reception unit, and sequentially outputs in synchronization with a clock signal output by the clock output unit;
While the clock output unit outputs the first clock signal, the sample output from the storage output unit is selected and output, and after the switching of the clock output unit, the phase difference output unit outputs the sample. An output selection unit that selects and outputs the sample output by the interpolation output unit until the phase difference becomes zero, and then selects and outputs the sample output by the storage output unit. A characteristic sound data processing apparatus. The sound data processing device according to claim 2, further comprising:
A third PLL for generating a third clock signal based on a third word clock that is not synchronized with the first clock;
The clock selection unit first outputs the first clock signal, and then switches the output clock signal to the third clock signal in response to a second switching instruction.
The phase difference output unit outputs a phase difference of zero in response to the clock output unit outputting a third clock,
The output selection unit mutes the output of the sound data for a predetermined period in response to the clock output unit outputting the third clock signal, and then selects and outputs the sample output by the interpolation output unit. A sound data processing apparatus. The sound data processing device according to claim 1,
The sound data received by the receiving unit is not synchronized with the first word clock,
The sound data processing device, wherein the sound data output unit continuously outputs the sample output by the interpolation output unit to a subsequent stage.

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