JP2018011149A - A / D conversion circuit, signal readout circuit, and image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A / D conversion circuit and a signal readout circuit in which the number of times a pulse is generated with respect to a signal (charge amount or voltage) does not vary even if the threshold voltage of an inverter or a comparator constituting the circuit varies in production. And provide an image sensor. SOLUTION: A capacitance is provided between a voltage detection node into which a signal is input and a multi-stage inverting circuit for generating a pulse, and a predetermined capacitance is provided between both electrodes of the capacitance before the voltage detection node is reset. It is characterized by giving a potential difference ΔV = VTH-Vshort between the threshold voltage (VTH) and the voltage (Vshort) when the input terminal and output terminal of the first-stage inverting circuit of the multi-stage inverting circuit are short-circuited. To do. [Selection diagram] Fig. 1

Description

  The present invention relates to an A / D (analog / digital) conversion circuit, a signal readout circuit, and an image sensor, and more particularly, a circuit that performs A / D conversion on a photoelectrically converted signal (charge amount or voltage) in each pixel of the image sensor. And a signal readout circuit and an image sensor using the same.

  Conventionally, an image sensor (solid-state imaging device) processes a photoelectrically converted signal (charge amount or voltage) as an analog signal. However, the signal is A / D (analog / digital) converted in the image sensor to be digital. By outputting as data, the dynamic range of photoelectric conversion can be expanded and the processing of the output signal can be facilitated.

  For example, in a CMOS image sensor or the like, an image sensor for column parallel signal processing of a method in which an A / D conversion circuit is shared for each column of pixels arranged in an array in the vertical and horizontal directions is manufactured. However, in such a configuration in which A / D conversion processing of pixels in a single row is performed by a single A / D conversion circuit, as the resolution of the image sensor increases (that is, as the number of pixels per row increases). ), The time required for the A / D conversion processing is prolonged, and it has become difficult to perform signal processing for all pixels within the time of one frame rate in moving image processing.

  Therefore, for the purpose of reducing the noise of the image sensor and speeding up the processing, an image of a pixel parallel signal processing method in which an A / D conversion circuit is provided in each pixel and a photoelectrically converted signal can be output in parallel for all pixels. Sensors have been proposed. The pixel parallel signal processing image sensor can solve the trade-off between the number of scanning lines and the frame rate, which is a drawback of the conventional column parallel signal processing image sensor. Therefore, it is researched as a promising candidate for the future high performance image sensor. It is being advanced. Among them, the image sensor described in Non-Patent Document 1 includes a circuit called a 1-bit A / D conversion circuit (1 bit ADC), and the amount of light that can be input is not limited by the storage capacity of the photodiode. It is said that the dynamic range of the image sensor can be significantly improved.

  The operation of the readout circuit of the image sensor proposed in Non-Patent Document 1 will be described below. FIG. Although a circuit is illustrated in FIG. 3, for the sake of simplicity, transistors (Tr1, Tr3, Tr4) that are not essential to the circuit operation, and a circuit in which details of a feedback circuit and a counter including them are omitted (FIG. 9) Will be described.

  FIG. 9 shows a signal readout circuit using a conventional 1-bit A / D conversion circuit (1 bit ADC) described in Non-Patent Document 1.

The readout circuit includes a photodiode (PD) 10 as a photoelectric conversion element, a reset transistor (T _R ) 20 for applying a reset voltage V _RST to the electrode of the photodiode 10, an inverter circuit (inverter chain) 30, And the counter 40. The inverter circuit 30 is a multi-stage inverting circuit in which inverters (Inv_1, Inv_2,... Inv_n), which are inverting circuits, are connected in an odd number of stages, and the potential of the voltage detection node (N _PD ) 11 of the photodiode 10 is the first stage inverter. (Inv_1). The output of the inverter circuit 30 is input to the counter 40 as the output (ADC_OUT) of the A / D conversion circuit and is applied to the gate electrode of the reset transistor 20. The counter 40 counts the number of pulses of the 1-bit A / D converter circuit output (ADC_OUT), and outputs it, for example, as an 8-bit counter output.

  Next, the operation of the signal readout circuit of the image sensor in FIG. 9 will be described.

(1) A description will be given from the time when the reset of the photodiode is released. That is, in a state where the potential of the photodiode (PD) 10 is reset (≈V _RST ), the input of the first stage inverter (Inv_1) is High and the output is Low, and the output of the second stage inverter (Inv_2) is High, It is assumed that the output of the final stage inverter (Inv_n), that is, the A / D conversion circuit output (ADC_OUT) is Low, and the reset transistor (T _R ) 20 is in an OFF state. [Initialization status]

(2) When light enters the photodiode 10, electrons generated by photoelectric conversion accumulate in the photodiode 10, and the potential of the electrode (voltage detection node N _PD ) 11 of the photodiode 10 decreases.

(3) When the voltage of the voltage detection node (N _PD ) 11 of the photodiode 10 reaches the inversion threshold voltage of the first-stage inverter (Inv_1), the output of the inverter (Inv_1) is inverted to High. The inverters are connected in n stages (n is an odd number), and the outputs are sequentially inverted and transmitted, and the output of the inverter (Inv_n) in the final stage, that is, the A / D conversion circuit output (ADC_OUT) becomes High. The reason why the inverters are connected not in one stage but in n stages is to stabilize the circuit operation by utilizing the delay caused by the n-stage inverter. Of the n-stage inverters, a comparator can be used instead of the first-stage inverter (Inv_1).

(4) When the A / D conversion circuit output (ADC_OUT) becomes High, the reset transistor 20 is turned on, the reset voltage V _RST is applied to the electrode of the photodiode 10, and the photodiode 10 is reset again. The

  (5) When the photodiode 10 is reset, the input of the first-stage inverter (Inv_1) is High, the A / D conversion circuit output (ADC_OUT) is Low, and the process returns to (1).

  Thereafter, the above (1) to (5) are repeated, and the output of the inverter circuit (inverter chain) 30 repeats High and Low. If the amount of light incident on the photodiode 10 is large, the potential change of the photodiode 10 is accelerated, and the inversion timing of the inverter circuit 30 is accelerated. Therefore, the number of pulses proportional to the amount of light is generated in the A / D conversion circuit output (ADC_OUT) within one frame period of the image.

  The counter 40 sequentially accumulates pulses, and after the end of one frame period, the counter output is read and the count is reset.

  In this A / D conversion circuit, the photodiode (PD) is reset a plurality of times in one frame period, and the number of resets (corresponding to the number of pulses) is output, so that the photodiode (PD) as in the conventional image sensor The dynamic range can be improved to the range counted by the counter without being limited by the storage capacity.

  In the prototype of Non-Patent Document 1, the counter 40 has 8 bits, but the read circuit using a 1-bit A / D converter circuit (1-bit ADC) has a capacity of 18 to 19 at an operation of 60 fields / second. It is said that a dynamic range of bits can be realized.

  Attempts have also been made to realize an image sensor provided with a signal readout circuit using this 1-bit A / D conversion circuit in each pixel by a three-dimensional integrated circuit (Non-patent Document 2).

F. Andoh et.al, “A Digital Pixel Image Sensor for Real-Time Readout”, IEEE Transaction on electron devices, (2000), vol. 47, No. 11, pp. 2123-2127 M. Goto et.al, “Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A / D Converters Developed by Direct Bonding of SOI Layers”, IEEE Transaction on electron devices, (2015), Vol.62, No.11, pp.3530-3535

  As described above, in the 1-bit A / D converter circuit (1-bit ADC), a pulse is output when the potential of the photodiode changes from the reset voltage due to light incidence and exceeds the threshold voltage of the inverter or comparator, The pulse output frequency (number of pulse occurrences) is the signal output. However, since the threshold voltages of the inverter and the comparator are different values due to manufacturing variations and the like, even if the same signal (charge amount or voltage) is generated, the number of pulses generated is different for each pixel. However, there is a problem that fixed pattern noise appears.

  Therefore, the object of the present invention, which has been made in view of the above problems, is that even if manufacturing variations occur in the inverters and comparators that constitute the circuit, variations occur in the number of pulses generated for signals (charge amount or voltage). The object is to provide an A / D conversion circuit, a signal readout circuit, and an image sensor.

In order to solve the above problems, an A / D conversion circuit according to the present invention is an A / D (analog / digital) conversion circuit that generates a pulse corresponding to a signal, and the signal is input to the pulse. A voltage detection node that is reset based on an odd number of inversion circuits, an output that is inverted based on an input voltage, the multi-stage inversion circuit that generates the pulse, the voltage detection node, and the multi-stage inversion circuit; Before the voltage detection node is reset, a predetermined threshold voltage (V _TH ) between the two electrodes of the capacitor and the first stage of the multi-stage inverting circuit. A potential difference ΔV = V _TH −V _short between the voltage (V _short ) when the input terminal and the output terminal of the inverting circuit are short-circuited is provided.

  In order to solve the above problems, an A / D conversion circuit according to the present invention is an A / D (analog / digital) conversion circuit that generates a pulse corresponding to a signal, and the voltage to which the signal is input. A detection node; reset means for resetting the voltage of the voltage detection node; threshold voltage setting means for setting the voltage of the voltage detection node to a predetermined threshold voltage; and an odd number of inverting circuits. A multi-stage inversion circuit that generates the pulse by inverting the output based on the voltage applied, a short-circuit means for short-circuiting an input terminal and an output terminal of the first-stage inversion circuit of the multi-stage inversion circuit, the voltage detection node, and the multi-stage A capacitor connected between the inverter circuit, a first delay circuit for delaying an output of the A / D converter circuit and operating the threshold voltage setting means and the short-circuit means; and Output Cast by, characterized by comprising a second delay circuit for operating said reset means.

  In the A / D conversion circuit, the first-stage inverting circuit is preferably formed of an inverter or a comparator.

  In the A / D conversion circuit, the voltage detection node is preferably an electrode of a photodiode.

  In the A / D conversion circuit, the voltage detection node is a floating diffusion, and a transfer transistor is provided between the photodiode and the floating diffusion, and the gate of the transfer transistor includes the A / D It is preferable that a NOR logic result of the output of the conversion circuit, the output of the first delay circuit, and the output of the second delay circuit is input.

  In order to solve the above problems, a signal readout circuit according to the present invention includes the A / D conversion circuit and a counter that counts pulses output from the A / D conversion circuit.

  In order to solve the above problems, an image sensor according to the present invention is characterized in that the pixel is provided with the signal readout circuit.

  According to the A / D conversion circuit of the present invention, the number of pulses generated for a signal can be made constant even if manufacturing variations occur in inverters and comparators constituting the circuit. Further, according to the signal readout circuit and the image sensor of the present invention, the output characteristics of the pixels can be made uniform even if manufacturing variations occur in the inverters and comparators that constitute each pixel.

1 is a diagram illustrating an A / D conversion circuit according to a first embodiment. 3 is a timing chart illustrating an operation of the A / D conversion circuit according to the first exemplary embodiment. It is a figure explaining the capacitor | condenser voltage of the A / D conversion circuit of Example 1, and the operating point of an inverter. 6 is a diagram illustrating an A / D conversion circuit according to a second embodiment. FIG. 12 is a timing chart illustrating an operation of the A / D conversion circuit according to the third embodiment. FIG. 10 is a diagram illustrating an A / D conversion circuit according to a fourth embodiment. 10 is a timing chart illustrating an operation of the A / D conversion circuit according to the fourth embodiment. It is a conceptual diagram of the image sensor (solid-state image sensor) of this invention. It is a figure which shows the signal read-out circuit using the conventional A / D conversion circuit.

(Embodiment 1)
Embodiments of the present invention will be described below. First, a 1-bit A / D conversion circuit according to the first embodiment of the present invention will be described.

FIG. 1 shows an A / D conversion circuit (1-bit ADC) according to a first embodiment of the present invention. The A / D conversion circuit includes a voltage detection node (N _PD ) 11 that collects signal charges from the photodiode (PD) 10, a reset transistor (T _R ) 20, a short-circuit transistor (T _S ) 21, and a threshold. A value setting transistor (T _TH ) 22, an inverter circuit (inverter chain) 30, a first delay circuit (Delay 1) 41, a second delay circuit (Delay 2) 42, and a capacitor (C) 50 are provided.

Among them, the basic configuration of the photodiode (PD) 10, the voltage detection node (N _PD ) 11, the reset transistor (T _R ) 20, and the inverter circuit (inverter chain) 30 is the conventional one shown in FIG. This is the same as the bit type A / D conversion circuit.

The reset transistor (T _R ) 20 applies a reset voltage V _RST to the node (N _PD ) 11 (electrode of the photodiode (PD) 10) by turning on (conducting). Thus, the reset transistor (T _R ) 20 functions as a reset unit.

  The inverter circuit (inverter chain) 30 is a multi-stage inverting circuit in which inverters (Inv_1, Inv_2,... Inv_n) as inverting circuits are connected in an odd number of stages. Here, for simplicity, the number of inverter stages is The inverter (Inv_1) 31, the first-stage inverter (Inv — 2) 32, and the third-stage inverter (Inv — 3) 33 have a three-stage configuration. Each inverter is composed of, for example, a CMOS inverter. The threshold voltage of the inverter is easily affected by variations in the manufacturing process. For example, the power supply voltage of each of the inverters 31 to 33 is set to 1.8 V, and the inversion threshold voltage is set to about 0.9 V, which is a half thereof can do. The output of the inverter circuit 30 becomes the output (ADC_OUT) of the A / D conversion circuit.

The short-circuit transistor (T _S ) 21 is connected to the input and output of the first stage inverter (Inv — 1) 31 of the inverter circuit 30, and is made conductive by a signal applied to the gate. And short the output terminals. That is, the short-circuit transistor (T _S ) 21 functions as a short-circuit means.

The threshold setting transistor (T _TH ) 22 is turned on (conducted) by a signal applied to the gate, and sets the potential of the voltage detection node (N _PD ) 11 to a predetermined threshold voltage V _TH . That is, the threshold setting transistor (T _TH ) 22 and the threshold voltage source function as threshold voltage setting means. This threshold voltage V _TH can be set from the outside and becomes a threshold voltage at which the A / D conversion circuit is inverted, as will be described later. Note that V _RST > V _TH , and the sensitivity (frequency of output pulses) of the signal readout circuit can be adjusted by the difference between the reset voltage V _RST and the threshold voltage V _TH . For example, the threshold voltage V _TH Can be set to about 1.0V to 1.5V.

The capacitor (C) 50 is connected between the voltage detection node (N _PD ) 11 and the input of the first-stage inverter (Inv_1) 31. As will be described later, the voltage held in the capacitor (C) 50 compensates for variations in the threshold voltage of the inverter 31.

The first delay circuit (Delay 1) 41 outputs the output (ADC_OUT) of the A / D conversion circuit with a delay of a predetermined time (ΔT). The output node (D 1) is connected to the input of the second delay circuit (Delay 2) 42 and the gates of the short-circuit transistor (T _S ) 21 and the threshold setting transistor (T _TH ) 22.

The second delay circuit (Delay 2) 42 further delays the output of the first delay circuit (Delay 1) 41 by a predetermined time (ΔT) and outputs it. The output node (D2) is connected to the gate of the reset transistor (T _R ) 20. In this embodiment, as a result, the output pulse (ADC_OUT) is applied to the gate of the reset transistor (T _R ) 20 with a time delay of 2ΔT.

  The operation of this A / D conversion circuit will be described with reference to the timing chart of FIG. 2, the capacitor voltage of FIG. 3, and the operating point of the inverter.

(1) The operation will be described from the state (time t1) when the output (ADC_OUT) of the A / D conversion circuit becomes High. The first delay circuit (Delay 1) 41 outputs a waveform delayed by a time ΔT from the circuit output (ADC_OUT). Therefore, the output node (D1) of the first delay circuit 41 becomes High at time t2 after ΔT. Since the output node (D1) is connected to the gate of the shorting transistor (T _S ) 21 and the gate of the threshold setting transistor (T _TH ) 22, the shorting transistor (T _S ) 21 and the shorting transistor (T _S ) 21 are connected at time t2. The threshold setting transistor (T _TH ) 22 is turned on, and the voltage across the capacitor (C) 50 is V _TH on the voltage detection node (N _PD ) 11 side and V _{short on} the inverter 31 side as shown in FIG. become.

Here, the voltage V _short is a voltage when the input voltage and the output voltage are equal in the input / output characteristics of the inverter (Inv_1) 31, as shown in FIG. When the short-circuit transistor (T _S ) 21 is turned on, the input terminal and the output terminal of the inverter (Inv_1) 31 are short-circuited. Therefore, the operating point of the inverter (Inv_1) 31 becomes A, and this voltage (V _short ) Input voltage and output voltage are fixed. The voltage V _short is substantially equal to the threshold voltage when the inverter (Inv_1) 31 is inverted. At this time, the potential difference ΔV between both ends of the capacitor (C) 50 (between both electrodes) is V _TH −V _short .

The inverter circuit 30 is designed so that the circuit output (ADC_OUT) becomes Low when the output of the first-stage inverter (Inv_1) 31 becomes the voltage V _short at time t2. In order to avoid that the circuit output (ADC_OUT) becomes the voltage V _short that is neither High nor Low at the time t2 to t3, it is desirable to adjust the threshold values of the inverters 32 and 33 in the subsequent stage. For example, as shown in FIG. 3 (3), in the input / output characteristics of the second stage inverter (Inv_2) 32, the inverter (Inv_2) 32 is set so that the output becomes High when the input voltage is V _short. The threshold voltage (input voltage when the output changes from High to Low) is set to be slightly higher than that of the first-stage inverter (Inv_1) 31.

Alternatively, the inverter (Inv_2) 32 has the same configuration as the first-stage inverter (Inv_1) 31, and the input voltage is V _short in the input / output characteristics of the third-stage inverter (Inv_3) 33 as shown in FIG. The threshold voltage of the inverter (Inv_3) 33 is set to be slightly lower than that of the inverter (Inv_1) 31 and the inverter (Inv_2) 32 so that the output becomes Low when

  With the above operation, when the output node (D1) of the first delay circuit (Delay 1) 41 becomes High at time t2, the delay time of the inverters 32 and 33 is small, so that the output (ADC_OUT) becomes Low quickly. As a result, the pulse width of the output (ADC_OUT) of the A / D conversion circuit is ΔT.

(2) The second delay circuit (Delay 2) 42 outputs a waveform delayed by time ΔT from the first delay circuit (Delay 1) 41. Accordingly, the node D2 becomes High at time t3. The output node of the second delay circuit 42 (D2), because they are connected to the gate of the reset transistor (T _R) 20, a reset transistor (T _R) 20 becomes conductive at time t3. Further, since the pulse width of the output of the A / D converter circuit (ADC_OUT) is ΔT, the node D1 becomes Low at time t3, the threshold setting transistor (T _TH ) 22 becomes OFF (OFF), and the voltage The detection node (N _PD ) 11 becomes the reset voltage V _RST . Therefore, the voltage on the left side (voltage detection node (N _PD ) 11 side) of the capacitor (C) 50 becomes the reset voltage V _RST as shown in FIG. At this time, the node on the right side (inverter 31 side) of the capacitor (C) 50 is floating because the short-circuit transistor (T _S ) 21 is off (OFF), so the capacitor (C) 50 maintains the potential difference ΔV. The voltage on the right side becomes V _RST −ΔV = V _RST −V _TH + V _short .

The operating point A ′ of the inverter (Inv_1) 31 at this time is shown in FIG. The voltage on the right side of the capacitor (C) 50 becomes the input of the inverter, and the output of the inverter (Inv_1) 31 becomes Low. However, V _RST > V _TH . The circuit output (ADC_OUT) remains low and does not change.

(3) At time t4, the output node (D2) of the second delay circuit 42 becomes Low, the reset transistor (T _R ) 20 is turned off (OFF), and the reset is completed. Henceforth, the photodiode (PD) 10 starts accumulating electric charges, and the voltage of the voltage detection node (N _PD ) 11 of the photodiode (PD) 10 decreases according to the amount of light. The voltage across the capacitor (C) 50 at time t5 during the accumulation period is shown in FIG. 3 (7), and the operating point A ″ of the inverter (Inv_1) 31 is shown in FIG. 3 (8). The voltage (signal voltage) of (N _PD ) 11 is V _Sig .

(4) When the signal voltage V _Sig becomes lower than the threshold voltage V _{TH at} time t6, the inverter (Inv_1) 31 to the inverter (Inv_3) 33 are sequentially inverted, and the output (ADC_OUT) of the A / D conversion circuit is It becomes High and returns to the state of (1).

As described above, in the 1-bit type A / D conversion circuit of the present invention, the input terminal and the output terminal of the first stage inverter are short-circuited, and the voltage changed from the short-circuit voltage is detected and a pulse is output. It is possible to cancel the threshold variation and perform an A / D conversion operation. Further, the inversion voltage of the A / D conversion circuit and its sensitivity can be set from the outside by the threshold voltage V _TH and the reset voltage V _RST .

FIG. 4 shows an A / D conversion circuit (1 bit ADC) according to the second embodiment of the present invention. In the A / D conversion circuit of FIG. 1, a comparator (Comp) 60 is used instead of the first stage inverter 31 of the inverter circuit (inverter chain) 30 which is a multistage inverting circuit. Here, a comparator (Comp) 60 compares the input voltage with the reference voltage (V _REF), the input voltage is the reference voltage (V _REF) high when the output becomes Low than, than the reference voltage (V _REF) Since it is a circuit whose output becomes High when it is low, it functions as a kind of inverting circuit.

The operation of the A / D conversion circuit is substantially the same as the circuit operation described with reference to FIGS. 1 to 3, and the input terminal of the comparator (Comp) 60 is turned on when the short-circuit transistor (T _S ) 21 is turned on. Since the output terminal is short-circuited, the input voltage and the output voltage are fixed to the voltage (V _short ) when the input voltage and the output voltage of the comparator (Comp) 60 become equal. After this, as in the first embodiment, in order to detect the voltage changed from the _short- circuit voltage (V _short ) and output a pulse, the characteristics of the individual comparators and variations in the reference voltage (V _REF ) are canceled. A / D conversion operation can be performed.

  The A / D conversion circuit according to the third embodiment of the present invention is obtained by adding a delay circuit to stabilize the circuit operation in the A / D conversion circuit of FIG. 1 or FIG.

At time t3 in the time chart of FIG. 2, it is avoided that the threshold voltage V _TH and the reset voltage V _RST are temporarily applied to the voltage detection node (N _PD ) 11 on the left side of the capacitor (C) 50. For this purpose, a third delay circuit (Delay 3) (not shown) is inserted between the second delay circuit (Delay 2) 42 and the gate of the reset transistor (T _R ) 20.

The time chart at that time is shown in FIG. By adding the third delay circuit (Delay 3), the reset transistor (T _R ) 20 is turned on (ON) more time than the threshold setting transistor (T _TH ) 22 is turned off (OFF). Delayed by ΔT. Thereby, the time for applying the threshold voltage V _TH and the reset voltage V _RST can be separated, and a more reliable A / D conversion operation can be realized. The same effect can be obtained by increasing the delay time of the second delay circuit (Delay 2) 42 instead of adding the third delay circuit (Delay 3).

  FIG. 6 illustrates an A / D conversion circuit (1 bit ADC) according to the fourth embodiment of the present invention. A characteristic part of the A / D conversion circuit of this embodiment is that it has a floating diffusion (FD) for accumulating signal charges generated in the photodiode.

  The charge generated in the photodiode (PD) is transferred to the floating diffusion (FD), which has a smaller capacity than the photodiode, and the voltage of the floating diffusion (FD) is detected to increase the detection sensitivity of the signal charge. it can.

A circuit configuration will be described. The A / D conversion circuit of FIG. 6 has a configuration in which a floating diffusion (FD) 12, a transfer transistor (T _TX ) 23, and a NOR circuit 70 are added to the A / D conversion circuit of FIG. The electrode of (FD) 12 becomes the voltage detection node (N _FD ) 13.

  The photodiode (PD) 10 as a photoelectric conversion element is constituted by, for example, an embedded photodiode having a small dark current. Note that the form of the photoelectric conversion element is not limited to this, and an element having a photoelectric conversion function, such as a normal PN junction photodiode formed on the substrate surface, a MOS photodiode, or a thin film photodiode, may be used. Anything can be used.

  The floating diffusion (FD) 12 is composed of, for example, a diffusion region formed on a semiconductor substrate and functions as a storage capacitor (capacitor). Connected in parallel with the photodiode 10, signal charges generated by photoelectric conversion in the photodiode 10 are accumulated. By making the capacitance of the floating diffusion (FD) 12 smaller than that of the photodiode 10, the light detection sensitivity can be increased. For example, by setting the capacitance to 1 / N of the photodiode capacitance (for example, N is 10 to 50), the voltage due to the accumulated charge can be increased N times. The structure of the floating diffusion (FD) 12 may be a capacitance of other structure besides the PN junction capacitance formed of the diffusion region, and the parasitic capacitance without actively forming the capacitive element. It is also possible to use.

The potential of the floating diffusion (FD) 12 appears at the voltage detection node (N _FD ) 13 and connects the node (N _FD ) 13 to the capacitor (C) 50.

The transfer transistor (T _TX ) 23 functions as a transfer gate that transfers the signal charge generated by the photodiode (PD) 10 to the floating diffusion (FD) 12. The transfer transistor (T _TX ) 23 is subjected to ON / OFF control by applying an output pulse of a NOR circuit 70 described later to the gate thereof.

The reset transistor (T _R ) 20 applies a reset voltage V _RST to the node (N _FD ) 13 of the floating diffusion (FD) 12 by turning on (conducting).

The input of the NOR circuit 70 includes an output (ADC_OUT) of the A / D conversion circuit, an output node (D1) of the first delay circuit (Delay 1) 41, and an output node (D2) of the second delay circuit (Delay 2) 42. Are connected, and the NOR logic result of these three outputs is applied to the gate of the transfer transistor (T _TX ) 23 as the output (TX) of the NOR circuit 70. The functions and operations of the other configurations are the same as those in FIG.

  The operation of the A / D conversion circuit in FIG. 6 will be described with reference to the timing chart in FIG.

When the output (ADC_OUT) of the A / D conversion circuit becomes High at time t1, the output (TX) of the NOR circuit 70 becomes Low, the transfer transistor (T _TX ) 23 turns off, and the photodiode (PD ) 10 is separated from the floating diffusion (FD) 12.

At time t2 after ΔT, the output node (D1) of the first delay circuit 41 becomes High, and the short-circuit transistor (T _S ) 21 and the threshold setting transistor (T _TH ) 22 become conductive. As a result, the node (N _FD ) 13 of the floating diffusion (FD) 12 becomes the threshold voltage V _TH , the input / output voltage of the inverter 31 becomes V _short , and the voltage across the capacitor (C) 50 is as shown in FIG. )become that way.

Thereafter, at time t3, the reset transistor (T _R ) 20 is turned on, and the threshold setting transistor (T _TH ) 22 is turned off (OFF), so that the node (N _FD ) of the floating diffusion (FD) 12 13 is the reset voltage V _RST .

Further, at time t4, the output (TX) of the NOR circuit 70 becomes High, the transfer transistor (T _TX ) 23 becomes conductive, and the photodiode (PD) 10 and the floating diffusion (FD) 12 are connected. Thereafter, signal charges are accumulated in the floating diffusion (FD) 12, and a pulse is generated in the same manner as in FIG. 1 due to the relationship between the voltage of the floating diffusion (FD) 12 and the threshold voltage V _TH . D conversion operation is performed.

From the above operation, the photodiode (PD) 10 is reset from the floating diffusion (FD) 12 (t1 to t4), and the floating diffusion (FD) 12 is reset and the initial voltage is set to the capacitor (C) 50. Etc. can be performed. The charges generated during this period are accumulated in the photodiode (PD) 10 and transferred to the floating diffusion (FD) 12 after the transfer transistor (T _TX ) 23 is turned on. There is no loss and more accurate charge detection can be performed.

In the circuit of FIG. 6, a third delay circuit (Delay 3) (not shown) is further added between the second delay circuit (Delay 2) 42 and the gate of the reset transistor (T _R ) 20. 5, a pulse waveform having a time difference is generated at the same timing as in FIG. 5, so that a short-circuit transistor (T _S ) 21, a threshold setting transistor (T _TH ) 22, a reset transistor (T _R ) 20, and a transfer transistor If the timing at which (T _TX ) 23 is turned ON / OFF is separated, a more reliable A / D conversion operation can be realized.

  Although the present invention has been described on the assumption of a circuit that detects electrons, it is obvious that a circuit that detects holes can also be realized by changing the type of the transistor and the sign of the power supply voltage with the same circuit configuration. is there.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is a signal readout circuit that can be used for an image sensor or the like.

  A counter (see FIG. 9) is added to the 1-bit A / D converter circuit (1-bit ADC) of the first to fourth examples described in Embodiment 1, and the output pulse (ADC_OUT) is counted. A signal readout circuit can be configured.

  That is, a signal (charge amount or voltage) photoelectrically converted by the photodiode (PD) 10 of each pixel of the image sensor can be read as a counter output. The number of bits of the counter can be set as appropriate. For example, by using a 16-bit counter, signals can be read with high accuracy in a wide dynamic range.

  By using the 1-bit A / D conversion circuit of the present invention for a photoelectric conversion signal readout circuit of an image sensor, variations in threshold values of inverters and comparators are compensated, and the same signal ( It can be designed such that the number of pulses generated with respect to (charge amount or voltage) is constant.

  Although the image sensor has been described as an example so far, the A / D conversion circuit (1 bit ADC) and the signal readout circuit of the present invention are not limited to the image sensor, but can be a fine region such as an array type pressure sensor or a fingerprint sensor. The present invention can also be applied to sensors that need to perform digital signal processing every time, and general integrated circuits.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. FIG. 8 shows a conceptual diagram of an image sensor (solid-state imaging device) 100 as Embodiment 3 of the present invention.

  The image sensor 100 in FIG. 8 is a pixel parallel signal processing image sensor in which each pixel outputs digital data.

  In the sensor area 101 of the image sensor 100, pixels 103 are arranged vertically and horizontally. Each pixel 103 includes a signal processing circuit therein, and includes a photodiode (PD) 104 as a photoelectric conversion element and an A / D conversion circuit (ADC) that converts the amount of signal charge from the photodiode 104 into digital data. ) 105 and a counter 106 that counts the number of pulses of the A / D conversion circuit output (ADC_OUT) and outputs the counted number of bits as data. The A / D conversion circuit of each pixel 103 is the A / D conversion circuit of any one of the first to fourth embodiments. In FIG. 8, the photodiode 104, the A / D conversion circuit 105, and the counter 106 are arranged in a plane in the pixel 103. However, these elements may be stacked and realized as a three-dimensional integrated circuit. good.

  The output from each pixel is processed by the output processing circuit 102 and output as imaging data of digital data. In the output processing circuit 102, for example, data from each pixel 103 is once stored in a buffer memory and then sequentially read out. Further, the output data of all the pixels can be sequentially scanned and output by a scanning circuit (not shown), and any appropriate reading process can be performed.

  In the image sensor 100 of the present invention, each pixel 103 includes the A / D conversion circuit according to any one of the first to fourth embodiments, and can compensate for variations in the characteristics of the inverter and the comparator of each pixel. And the uniformity of detection sensitivity can be improved.

  Although the present invention has been described based on the drawings and examples, it should be noted that those skilled in the art can easily make various modifications and corrections based on the present disclosure. Therefore, it should be noted that these variations and modifications are included in the scope of the present invention. For example, the functions and the like included in each means can be rearranged so as not to be logically contradictory, and a plurality of means and steps can be combined into one or divided.

10 Photodiodes 11 and 13 Voltage detection node 12 Floating diffusion 20 Reset transistor 21 Short-circuit transistor 22 Threshold setting transistor 23 Transfer transistor 30 Inverter circuits 31 to 33 Inverter 40 Counter 41 First delay circuit 42 Second delay circuit 50 Capacitance 60 Comparator 70 NOR circuit 100 Image sensor 101 Sensor region 102 Output processing circuit 103 Pixel 104 Photodiode 105 A / D conversion circuit 106 Counter

Claims (7)

An A / D (analog / digital) conversion circuit that generates a pulse in response to a signal,
A voltage detection node that receives the signal and is reset based on the pulse;
A multi-stage inverting circuit that consists of an odd number of inverting circuits, the output is inverted based on the input voltage, and generates the pulse;
A capacitor connected between the voltage detection node and the multi-stage inverting circuit;
Before the voltage detection node is reset, a predetermined threshold voltage (V _TH ) and the input terminal and the output terminal of the first stage inverting circuit of the multistage inverting circuit are short-circuited between both electrodes of the capacitor. An A / D conversion circuit characterized in that a potential difference ΔV = V _TH −V _short with respect to the voltage (V _short ) when applied is given. An A / D (analog / digital) conversion circuit that generates a pulse in response to a signal,
A voltage detection node to which the signal is input;
Resetting means for resetting the voltage of the voltage detection node;
Threshold voltage setting means for setting the voltage of the voltage detection node to a predetermined threshold voltage;
A multi-stage inverting circuit that consists of an odd number of inverting circuits, the output is inverted based on the input voltage, and generates the pulse;
Short-circuit means for short-circuiting the input terminal and the output terminal of the first-stage inverter circuit of the multi-stage inverter circuit,
A capacitor connected between the voltage detection node and the multi-stage inverting circuit;
A first delay circuit for delaying the output of the A / D conversion circuit and operating the threshold voltage setting means and the short-circuit means;
An A / D conversion circuit comprising: a second delay circuit that delays the output of the first delay circuit and operates the reset means. The A / D conversion circuit according to claim 1 or 2,
The A / D converter circuit characterized in that the first-stage inverting circuit is constituted by an inverter or a comparator. In the A / D conversion circuit according to any one of claims 1 to 3,
The A / D conversion circuit, wherein the voltage detection node is an electrode of a photodiode. The A / D conversion circuit according to claim 2,
The voltage detection node is a floating diffusion, and a transfer transistor is provided between the photodiode and the floating diffusion;
A NOR logic result of the output of the A / D conversion circuit, the output of the first delay circuit, and the output of the second delay circuit is input to the gate of the transfer transistor. / D conversion circuit.   6. A signal readout circuit comprising: the A / D conversion circuit according to claim 1; and a counter that counts pulses output from the A / D conversion circuit. An image sensor comprising the signal readout circuit according to claim 6 in each pixel.

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