JP2018010005A - IC chip test apparatus, IC chip test method, and IC chip test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC chip test device and method, as well as a test system that optimize a frequency of test data, shorten a testing time, and can improve test quality and yield.SOLUTION: An IC chip test device, which inputs a scan pattern to a scan object IC, compares an output value to be output with an expected value, and inspects presence or absence of a defect of the IC chip on the basis of a comparison result, comprises a shift frequency retrieve unit that shifts a usable shift frequency of two more scan sections 1202 and 1204 included in a scan pattern set to a scan path 1210, and retrieves a shift frequency of which a scan test results in PASS or FAIL. The shift frequency retrieval unit is configured to retrieve the shift frequency by increasing or decreasing the shift frequency so as to be different from at least one scan section of other scan sections to be shifted to the scan path, or setting the shift frequency to a different shift frequency.SELECTED DRAWING: Figure 12

Description

  The present invention relates to an IC chip test apparatus, an IC chip test method, and an IC chip test system.

  The contents described in this part merely provide background information according to the present embodiment, and do not constitute the prior art.

  The most common method for testing an IC chip is to apply test data to the input of the IC chip, and compare the output value of the IC chip with a predetermined predicted value (Expected Value) or a predicted result (Expected Result). That is. (For example, refer to Patent Document 1). However, in the case of an IC chip including a sequential circuit having a storage element (Storage Element) such as a flip-flop, a desired value is applied to the flip-flop in the IC chip from the outside. It is not easy to detect the value of the flip-flop from the outside.

  The scan design method is one of design for test (DFT) methods that are used to increase the controllability and the observability of a circuit. Using the scan design method, ATPG (Automatic Test Pattern Generator), which is software that automatically generates a test pattern based on circuit structural information, has a small fault size (Fault Coverage) despite its small size. Test data can be obtained.

  In other words, scan design is a combination of sequential circuits (combinational logic) during scan testing, allowing the circuit to be easily controlled and observed from outside the chip, and minimizing the size of test data via ATPG. can do. Test data obtained via scan design and ATPG software is composed of at least one scan pattern. The scan pattern can have an order during a scan test.

  The general scan test process is as follows.

  (1) Apply main input test data to the main input port of the IC chip.

  (2) A scan activation signal is applied to the scan activation port, and the IC chip is set to the scan mode.

  (3) The scan pattern is shifted into the scan input port (Shift-In), and the scan pattern is loaded into the flip-flop on the scan path. In this specification, shifting a scan pattern into a scan input port or shifting out an output from a scan output port may be collectively referred to as “shifting”. Further, the time interval (that is, the period) shift frequency for shifting the scan pattern when the scan pattern is shifted in has a reciprocal relationship. The scan pattern loaded in the scan path is applied to the combinational circuit. After the scan pattern is applied to the combinational circuit, the result output from the main output port is compared with the predicted main output value. If the comparison results are different, the IC chip is determined to be defective.

  (4) A scan deactivation signal is applied to the scan activation port to switch the IC chip from the scan mode to the functional mode. When the clock signal is applied in the functional mode, the flip-flop captures the output value of the combinational circuit. Such an operation is called a scan capture, and the mode at this time is called a scan capture mode.

  (5) A scan activation signal is applied to the scan activation port to switch the IC chip from the functional mode to the scan mode again.

  (6) The value captured by the flip-flop on the scan path is shifted out (Shift-Out) via the scan output port and unloaded.

  (7) The unloaded output pattern is compared with the predicted pattern known in advance to determine whether the IC chip can operate normally. Here, the predicted pattern is a scan pattern that is output via the scan output port after applying the main input test data and the scan pattern when the IC chip is normal and performing the scan capture operation. A value known in advance or a predicted result pattern. If the comparison result in step (3) is the same and the comparison result in step (7) is the same, the test result is normal (PASS), so the IC chip is a good product, otherwise, the IC chip Is a defective product. Test normal (PASS) means a case where it is determined that there is no abnormality in the IC chip (Fault-Free), and test failure (FAIL) means a case where it is determined that there is an abnormality in the IC chip.

  The scan test is roughly divided into a stuck-at-fault test and a delay fault test. Fixed fault means a state in which a certain signal line on the IC chip is not intended to be fixed to a logic 0 (Logic 0) or logic 1 (Logic 1) value, and a delay fault is defined on the IC chip. It means a state in which the specification of the IC chip cannot be satisfied due to a delay time when a signal value is transmitted via a certain signal line or path.

  The delay fault test includes a transition delay test and a path delay test, and is also referred to as an at-speed test. The transition delay test tests whether a transition delay time problem of a signal value of 0-to-1 or 1-to-0 exists in a specific node (Node) or signal line on the IC chip. is there. The path delay test tests whether a transition delay time problem of a signal value of 0-to-1 or 1-to-0 exists in a specific signal path on the IC chip.

  As a typical method for performing the delay fault test, there are a launch-on-capture method and a launch-on-shift method. These methods are also used for the delay fault test. The load pattern is shifted in on the scan path, and the unload operation is shifted out in the delay fault test result captured in the flip-flop on the scan path.

Korean Patent Publication No. 10-2012-0102876

  In the case of such a scan test, a clock pulse for shifting by the number of flip-flops on the scan path is necessary. Therefore, there is a problem that it takes a long time to perform the shift-in and shift-out operations. However, the frequency of the clock signal for shifting to the scan path in order to shorten the test time, that is, the shift frequency cannot be simply increased.

  For example, simply increasing the scan shift frequency may cause an overkill problem that determines a non-defective product as a defective product due to power consumption or a critical path delay time problem.

  Furthermore, not only deep sub-micron (DSM) micro manufacturing process and low power manufacturing process, but also low power design reduces the power of the IC chip, while power supply noise against the operating frequency of the IC chip. The impact of is getting bigger.

  In particular, since the IC chip generates more switching operation in the scan mode than in the function mode, an additional delay of the signal line generated due to power supply noise due to the switching operation may cause a delay test overkill. There is a limit to simply increasing the shift frequency.

  Further, the signal integrity problem due to interference between signal lines on the IC chip (Signal Crosstalk) has become more important as the DSM micro-process progresses. Inter-signal line interference may be further deteriorated by a switching operation frequently generated in the scan mode. Therefore, an additional delay that occurs in the signal line due to interference between the signal lines during the delay test may cause a delay test overkill.

  Further, when searching for the shift frequency based on the power consumption value of the scan pattern, even if the power consumption value does not exceed the specification of the IC chip, excessive circuit switching operation to the IC chip and variations in the manufacturing process due to the characteristics of the scan test A scan test error problem due to IR-Drop or Ground-Bounce may occur due to the influence of (Process Variation).

  For example, when a delay test using a scan pattern is performed, an IR-Drop, that is, a voltage drop, may cause an additional delay in a specific signal line, which causes a delay test overkill. There is a possibility of waking up.

  Even when the power consumption of the scan pattern exceeds the specification of the IC chip, the problem of IR-Drop or Ground-Bounce may not occur depending on the manufacturing process and design characteristics of the IC chip. Therefore, there is a limit to search for the optimum shift frequency for the IC chip only by the power consumption value.

  Furthermore, when searching for the maximum shift frequency using only the power consumption value of the scan pattern, even if the power consumption value does not exceed the specification of the IC chip, the problem of critical path timing occurs on the scan path due to the raised shift frequency. There is a case.

  Further, when the shift frequency is increased, a problem of timing of the critical path occurs on the scan path, but a logical problem due to the scan pattern may not occur. In other words, a false critical path may occur in a specific scan shift cycle depending on the state of the bit value on the critical path of the scan path.

  For example, if two consecutive logic-0 bit values are shifted and stored in two flip-flops forming a critical path on the scan path and then shifted at a high shift frequency, the critical path starts. There may be a critical path delay time problem where the signal for the logic-0 bit value stored in the flip-flop cannot reach the next flip-flop within the normal time. However, a false critical path may occur in which a logical problem of the bit values stored in the two flip-flops forming the critical path by the shift operation does not occur.

  In addition, low power IC chips using multiple voltage island or voltage domain or region techniques provide high voltage in design areas where high speed performance is required, and relative in other areas. Since a low voltage is supplied to the power supply, the power consumption allowed varies depending on the voltage region.

  At least one embodiment of the present invention has been made to meet the above-described conventional requirements, and optimizes the frequency of test data, shortens test time, and improves test quality and yield. It is an object of the present invention to provide an IC chip test apparatus, an IC chip test method, and an IC chip test system.

  In at least one embodiment of the present invention, a scan pattern is input to a scan path via a scan input port of an IC chip including a test target circuit, and an output value output via the scan output port is set in advance. In an IC chip test apparatus for performing a scan test for comparing with a predicted value and inspecting for the presence or absence of an IC chip based on a comparison result, it can be used among at least two scan sections included in a scan pattern set. The shift frequency search unit includes a shift frequency search unit that searches for a shift frequency in which a target scan section to be searched for a shift frequency is shifted to the scan path and a scan test result is normal or a failure is detected. Search shift frequency for the target scan section The scan test results when the shift frequency of the target scan section is increased or decreased to be different from at least one of the other scan sections shifted to the scan path, or set to a different shift frequency. Provided is an IC chip test apparatus that searches for a shift frequency at which is normal or a shift frequency at which it is a failure.

  In at least one embodiment of the present invention, the shift frequency search unit increases or decreases the shift frequency of the target scan section while searching for a shift frequency that can be used for the target scan section. The shift frequency of the region that changes to or the region that normally changes from failure is searched.

In at least one embodiment of the present invention, the shift frequency search unit may obtain the first scan obtained using the first shift frequency for the target scan section when searching for a shift frequency usable for the target scan section. When the result of the test and the result of the second scan test obtained using a second shift frequency different from the first shift frequency for any one scan section before the target scan section are normal The first shift frequency is determined as a usable shift frequency for the target scan section.
In at least one embodiment of the invention, the IC chip comprises a chip on a wafer or a packaged chip.

  In at least one embodiment of the present invention, a scan pattern is input to a scan path via a scan input port of an IC chip including a test target circuit, and an output value output via the scan output port is set in advance. In an IC chip test apparatus for performing a scan test that compares a predicted value and inspects whether there is a defect in an IC chip based on a comparison result, a first scan pattern including a first scan section is shifted to a scan path of the IC chip. A second test step for performing a test by shifting the second scan pattern including the second scan section after the first scan section and the second scan section after the first scan section to the scan path, and performing the test on the second scan section A shift frequency search unit for searching for usable shift frequencies, The frequency search unit shifts the first scan section to the scan path at the first shift frequency in the first test process, and scans the second scan section at the second shift frequency different from the first shift frequency in the second test process. Shift to the path, and when searching for an available shift frequency for the second scan section, if both the test result in the first test step and the test result in the second test step are normal, the second shift frequency is An IC chip test apparatus is provided that determines a usable shift frequency for a second scan section.

  In at least one embodiment of the invention, the first scan section is a first scan pattern or part of a first scan pattern, and the second scan section is a second scan pattern or part of a second scan pattern. is there.

  In at least one embodiment of the present invention, the shift frequency search unit may search at least one of the other scan sections that shift the second shift frequency to the scan path when searching for an available shift frequency for the second scan section. Search for available shift frequencies for the second scan section, increasing or decreasing differently from the scan section, or setting to a different shift frequency.

  In at least one embodiment of the invention, the IC chip comprises a chip on a wafer or a packaged chip.

  In at least one embodiment of the present invention, a scan pattern is input to a scan path via a scan input port of an IC chip including a test target circuit, and an output value output via the scan output port is set in advance. At least two or more scans included in a scan pattern set in an IC chip test method used in an IC chip test apparatus for performing a scan test that compares a predicted value and inspects whether there is a defect in an IC chip based on a comparison result A shift frequency search step of searching for a shift frequency in which a scan test result is normal or a failure by shifting a target scan section, which is a target for searching for an available shift frequency, to a scan path among the sections. , Shift frequency search process, target scan When searching for the shift frequency for a specific scan section, the shift frequency of the target scan section is increased or decreased differently from at least one of the other scan sections that shift to the scan path, or set to a different shift frequency. Thus, an IC chip test method including a step of searching for a shift frequency at which a scan test result is normal or a failure is provided.

  In at least one embodiment of the present invention, the shift frequency search process may cause the scan test result to fail from normal to normal while increasing or decreasing the shift frequency of the target scan section when searching for available shift frequencies for the target scan section. And searching for the shift frequency of the region that changes to normal or the region that normally changes from failure.

  In at least one embodiment of the present invention, the shift frequency search step includes a first scan obtained using the first shift frequency for the target scan section when searching for a usable shift frequency for the target scan section. When the result of the test and the result of the second scan test obtained using a second shift frequency different from the first shift frequency for any one scan section before the target scan section are normal Determining the first shift frequency as an available shift frequency for the target scan section.

  In at least one embodiment of the invention, the IC chip comprises a chip on a wafer or a packaged chip.

  In at least one embodiment of the present invention, a scan pattern is input to a scan path via a scan input port of an IC chip including a test target circuit, and an output value output via the scan output port is set in advance. In an IC chip test method used in an IC chip test apparatus for performing a scan test for comparing with a predicted value and inspecting the presence or absence of a defect of an IC chip based on a comparison result, a first scan pattern including a first scan section is represented by an IC. Performing a first test process for performing a test by shifting to a scan path of the chip and a second test process for performing a test by shifting a second scan pattern including a second scan section after the first scan section to the scan path. , Find the available shift frequency for the second scan section A shift frequency search step for shifting the first scan section to the scan path at the first shift frequency in the first test step, and the second scan section as the first shift frequency in the second test step. Both the process of shifting to the scan path with a different second shift frequency and the search result of the first test process and the test result of the second test process when searching for an available shift frequency for the second scan section. If normal, determining a second shift frequency as an available shift frequency for the second scan section.

  In at least one embodiment of the invention, the first scan section is a first scan pattern or part of a first scan pattern, and the second scan section is a second scan pattern or part of a second scan pattern. is there.

  In at least one embodiment of the present invention, the shift frequency search step includes at least one of the other scan sections that shift the second shift frequency to the scan path when searching for an available shift frequency for the second scan section. Searching for available shift frequencies for the second scan section, increasing or decreasing differently from the scan section, or setting to a different shift frequency.

  In at least one embodiment of the invention, the IC chip comprises a chip on a wafer or a packaged chip.

  In at least one embodiment of the present invention, a tester body for controlling a scan test of an IC circuit, a host computer including a processor built in the tester body or provided outside the tester body, and a tester An IC chip test system comprising a test head electrically connected to a main body for inputting a test data signal to an IC circuit and an IC chip test apparatus according to at least one embodiment of the present invention.

  In at least one embodiment of the invention, the host computer includes an IC chip test device.

  In at least one embodiment of the present invention, a computer-readable recording medium storing a program for executing an IC chip test method according to at least one embodiment of the present invention is provided.

  In at least one embodiment of the present invention, the IC chip test method according to at least one embodiment of the present invention is executed, and information on the shift frequency determined as the usable shift frequency for each target scan section is obtained. A computer-readable recording medium for storage is provided.

  In at least one embodiment of the present invention, a target scan used to perform an IC chip test method according to at least one embodiment of the present invention to search for usable shift frequencies for each target scan section. A computer-readable recording medium for storing test data including sections is provided.

  According to at least one embodiment of the present invention, when the IC chip is tested, the shift frequency is increased considering only the power consumption or the critical path delay time for each scan pattern, scan section, or scan group. In addition, there is an effect that it is possible to provide an optimum shift frequency capable of reducing the scan test time while solving the problem of overkill in which a non-defective product is determined as a defective product by the overshift frequency.

  Further, in the test of the IC chip, there is an effect that an optimum shift frequency can be provided in consideration of the influence of power supply noise, interference between signal lines, and the like.

  In addition, when testing IC chips, the effects of IR-Drop or Ground-Bounce due to excessive circuit switching operations due to scan tests, manufacturing process variations, fine manufacturing processes, low-power manufacturing processes, or low-power designs are reflected. There is an effect that an optimum shift frequency can be provided.

  Further, in the test of the IC chip, the effect of the timing of the critical path on the scan path that may occur when the shift frequency is increased is taken into consideration, and an optimum shift frequency can be provided.

  Furthermore, when testing the IC chip, if the critical path of the scan path is false (False) due to the bit value on the scan path, the critical timing constraint is ignored and the IC chip can operate normally. Thus, it is possible to maximize the scan shift frequency and minimize the test time.

  Further, when the IC chip is tested, the use of a higher shift frequency can be achieved by the Don't Care bit on the scan pattern set. The don care bit means a bit that does not affect the result of the scan test.

  In addition, when testing an IC chip, a low power IC chip using a multiple voltage island (Voltage Island) or voltage domain (Region Domain or Region) method reflects the power consumption allowed for each voltage island or voltage region. As a result, the optimum shift frequency can be provided.

  Furthermore, since the circuit design information of the IC chip is not required when searching for the optimum shift frequency associated with the scan pattern or scan section used in the test of the IC chip, the chip can be obtained without the circuit design information of the IC chip. There is an effect that it is possible to provide an optimum shift frequency for each scan pattern or each scan section only by a set of scan patterns. The scan section is composed of all or part of the scan pattern.

  Furthermore, when an IC chip is tested, a scan pattern in which power consumption or current consumption in each scan section is greater than or equal to a predetermined shift frequency, such as a nominal frequency, is initially assigned to all scan sections. Alternatively, when the process of searching for the optimum shift frequency for the scan section is performed, the processing time can be shortened compared to the method of searching for the optimum shift frequency for each of the entire scan pattern or scan section. .

  Further, when testing an IC chip, the test time is increased in order to solve the problem of fail hole (fail hole) in which an abnormal test failure occurs within a shift frequency range where the test result should be normal. There is an effect that it can be suppressed. In order to solve the problem of the fail hole, it is possible to prevent the failure detection rate (Fault Coverage) of the chip from decreasing or the field escape (Field Escape) problem to occur.

  Furthermore, a stress or burn-in test that further accelerates chip aging can reduce test time and improve test quality. In addition, the time required for the stress or burn-in test can be accurately predicted, and the quality of the stress or burn-in test can be accurately predicted.

  Further, it is possible to obtain the information for improving the yield through the test of the IC chip or to increase the yield.

It is the schematic which shows an example of the IC chip to which the scan design method is applied. 1 is a block diagram showing a configuration of an IC chip test system according to at least one embodiment of the present invention. 1 is a block diagram showing a configuration of an IC chip test system according to at least one embodiment of the present invention. It is the schematic which shows an example of the scan pattern which concerns on the at least 1 Example of this invention. FIG. 5 is a schematic diagram illustrating a test data dividing method according to at least one embodiment of the present invention. FIG. 5 is a schematic diagram illustrating a test data dividing method according to at least one embodiment of the present invention. FIG. 5 is a schematic diagram illustrating a test data dividing method according to at least one embodiment of the present invention. FIG. 5 is a schematic diagram illustrating a test data dividing method according to at least one embodiment of the present invention. FIG. 5 is a schematic diagram illustrating a test data dividing method according to at least one embodiment of the present invention. 6 is a graph showing a relationship between the number of scan sections and a reduction rate of scan test time according to at least one embodiment of the present invention. FIG. 6 is a schematic diagram illustrating an example in which a shift frequency is assigned to each scan section in order to minimize the test time of an IC chip according to at least one embodiment of the present invention. FIG. 6 is a schematic diagram illustrating an example of searching for a shift frequency in order to minimize a test time of an IC chip according to at least one embodiment of the present invention. FIG. 6 is a schematic diagram illustrating an example of a pattern input to a scan path in order to determine a shift frequency according to at least one embodiment of the present invention. FIG. 6 is a schematic diagram illustrating an example of a pattern input to a scan path in order to determine a shift frequency according to at least one embodiment of the present invention. FIG. 6 is a schematic diagram illustrating an example of a pattern input to a scan path in order to determine a shift frequency according to at least one embodiment of the invention. 6 is a graph illustrating an example of a method for searching for a usable shift frequency of a scan pattern according to at least one embodiment of the present invention. 6 is a graph illustrating a case where a test result of another scan pattern is unsuccessful when increasing or decreasing a shift frequency of a scan pattern to be searched for an optimum shift frequency according to at least one embodiment of the present invention. It is the schematic which shows an example regarding the structure of the scanning pattern required in order to obtain the optimal shift frequency which concerns on at least 1 Example of this invention, a scan section, and shift frequency information. It is the schematic which shows an example regarding the structure of the scanning pattern required in order to obtain the optimal shift frequency which concerns on at least 1 Example of this invention, a scan section, and shift frequency information. It is the schematic which shows an example regarding the structure of the scanning pattern required in order to obtain the optimal shift frequency which concerns on at least 1 Example of this invention, a scan section, and shift frequency information. It is the schematic which shows an example of the method of producing | generating the data for a search which concerns on the at least 1 Example of this invention. It is the schematic which shows an example of the method of producing | generating the data for a search which concerns on the at least 1 Example of this invention. It is the schematic which shows an example of the method of producing | generating the data for a search which concerns on the at least 1 Example of this invention. It is the schematic which shows an example of the method of producing | generating the data for a search which concerns on the at least 1 Example of this invention. It is the schematic which shows an example of the method of producing | generating the data for a search which concerns on the at least 1 Example of this invention. It is the schematic which shows an example of the method of producing | generating the data for a search which concerns on the at least 1 Example of this invention. It is the schematic which shows an example of the method of producing | generating the data for a search which concerns on the at least 1 Example of this invention. It is the schematic which shows an example of the method of producing | generating the data for a search which concerns on the at least 1 Example of this invention. 5 is a flowchart illustrating an example method for minimizing chip test time according to at least one embodiment of the present invention. 6 is a flowchart illustrating an example of a method for determining an optimum shift frequency for each scan section in order to minimize the time of chip test according to at least one embodiment of the present invention. 5 is a flowchart illustrating an example of a more specific process of a method for minimizing a chip test time according to at least one embodiment of the present invention. 6 is a flowchart illustrating an example of specific steps for grasping whether a test is normal or failed in a method for minimizing a chip test time according to at least one embodiment of the present invention. 5 is a flowchart illustrating an example method for minimizing chip test time according to at least one embodiment of the present invention. 1 is a block diagram showing a configuration of an apparatus for minimizing a test time of an IC chip according to at least one embodiment of the present invention. 6 is a schematic diagram illustrating an example of a method for searching or determining an optimal shift frequency of a plurality of scan sections in parallel according to at least one embodiment of the present invention. FIG. 5 is a schematic diagram illustrating an example of a method for rearranging scan patterns in order to minimize the time for testing an IC chip according to at least one embodiment of the present invention. 1 is a block diagram showing a configuration of a burn-in test system according to at least one embodiment of the present invention. 1 is a block diagram showing a configuration of a burn-in test system according to at least one embodiment of the present invention. FIG. 6 is a schematic diagram illustrating an example of the influence of temperature on an IC chip when performing a burn-in test using a single scan shift frequency according to at least one embodiment of the present invention. FIG. 6 is a schematic diagram illustrating an example of the influence of temperature on an IC chip when a burn-in test is performed using an optimum shift frequency for each scan pattern according to at least one embodiment of the present invention. It is a thermal image which shows the heat_generation | fever state of an IC chip at the time of the scan shift operation | movement when not optimizing the shift frequency according to a scan section, and when it optimizes. It is a graph which shows an example of the power consumption which generate | occur | produces during the burn-in test before adjusting the power consumption of test data. It is a graph which shows an example of the power consumption which generate | occur | produces during the burn-in test after adjusting the power consumption of test data. 6 is a flowchart illustrating an example of a method for searching for an optimal shift frequency for each scan section in order to minimize the burn-in test time according to at least one embodiment of the present invention. 1 is a block diagram illustrating an example of an apparatus for minimizing burn-in test time according to at least one embodiment of the present invention. It is the table | surface which compared the experimental result with respect to the shift frequency optimized using the shift frequency and shift frequency increase / decrease method when approaching the critical power consumption of an IC chip with respect to each scan pattern. It is a graph which shows an example of the test fail hole which may occur in the case of a test of an IC chip. 6 is a graph illustrating an example method for solving a test fail hole problem according to at least one embodiment of the present invention. 3 is a flowchart illustrating an example method for solving a test fail hole problem according to at least one embodiment of the present invention. 6 is a graph illustrating an example method for solving a test fail hole problem according to at least one embodiment of the present invention. 5 is a graph illustrating an example of a method for searching for a shift frequency for reducing test time and improving yield according to at least one embodiment of the present invention.

  Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings. In assigning reference numerals to constituent elements in each drawing, the same constituent elements are assigned the same reference numerals as much as possible even if they are shown on different drawings. Further, in describing the embodiments of the present invention, when it is determined that a specific description related to a known configuration or function can diminish the gist of the present invention, a detailed description thereof will be omitted.

  Furthermore, terms such as first, second, A, B, (a), (b) can be used in describing the components of the present invention. Such terms are for distinguishing the constituent elements from other constituent elements, and the essence and order of the constituent elements are not limited by the terms. Throughout the specification, “including” or “comprising” a certain component does not exclude other components but includes other components unless specifically stated to the contrary. It means that you can. In addition, terms such as “unit” and “module” described in the specification mean a unit for processing at least one function or operation, and such a processing unit is hardware, software, or hardware and software. It can be realized by a combination.

  FIG. 1 is a schematic diagram illustrating an example of an IC chip (100) to which a scan design method is applied.

  As shown in FIG. 1, the IC chip (100) includes a combinational circuit (110) and a sequential circuit (Sequential Logic). The sequential circuit is composed of a plurality of flip-flops (120, 130, 140). Each of the flip-flops (120, 130, 140) can be configured in various ways including a scan flip-flop of a multiplexer (MUX) type.

  The IC chip (100) has a main input (PI: Primary Input) port (150), a main output (PO: Primary Output) port (152), a scan activation (SE: Scan Enable) port (160), and a scan input port. (162), a clock input port (164), a scan output port (166), and the like. The scan activation port (160) and the clock input port (164) are connected to the flip-flops (120, 130, 140). Each flip-flop (120, 130, 140) is connected to the combinational circuit (110), outputs the value stored in each flip-flop to the combinational circuit (110), and is output from the combinational circuit (110). Receives the value as input.

  The main input port (150) and the main output port (152) are ports for inputting and outputting data in the normal operation process of the IC chip.

  The scan activation port (160) is a port for inputting a scan activation signal or a scan deactivation signal. The scan activation signal or the scan deactivation signal causes the IC chip to enter a normal mode (or a functional mode) in which a normal operation is performed, or to enter a scan mode for testing the IC chip.

  The scan input port (162) is a port for inputting a scan pattern for testing the IC chip (100), and the scan output port (166) is a port for outputting a test result based on the scan pattern. . A bit pattern output via the scan output port is referred to as an output scan pattern, an output pattern, or a scan test result pattern.

  The clock input port (164) shifts and loads the scan pattern input via the scan input port (162) to the flip-flop (120, 130, 140) or the combination of the combination circuit (110). This is a port for inputting a clock signal that performs a trigger function so that the output can be captured and stored in the flip-flops (120, 130, 140). For example, the signal is triggered by a rising edge (Rising Edge) or a falling edge (Falling Edge) of a clock signal input through the flip-flops (120, 130, 140) and the clock input port (164).

  A path (a path indicated by a dotted line) connected from the scan input port (162) to the scan output port (166) through a plurality of flip-flops (120, 130, 140) is a scan chain (Scan Chain) or a scan path (Sacn Path). ). Although a single scan path is shown in FIG. 1, a plurality of scan paths can be used.

  In the functional mode, the combinational circuit (110) performs an operation of receiving data input via the main input port (150) and outputting the result via the main output port (152). In the functional mode, the flip-flops (120, 130, 140) receive the output value of the combinational circuit (110) by a clock signal, and this operation is called a scan capture at the time of a scan test.

  In the scan mode, each bit of the scan pattern is sequentially shifted in (Shift-In) into the flip-flops (120, 130, 140) existing on the scan path by the clock signal, and is also shifted through the scan output port (166). Out (Shift-Out). Here, shifting the scan pattern into the flip-flop (120, 130, 140) is referred to as “load”, and the value stored in the flip-flop (120, 130, 140) is the scan output port (166). ) Is referred to as unloading.

  For example, if the number of flip-flops (120, 130, 140) on the scan path in the IC chip is three, the length of each scan pattern is the same 3-bit length as the number of flip-flops on the scan path. The 3-bit scan pattern is sequentially shifted into the flip-flops (120, 130, 140) on the scan path by the clock signal.

  That is, if a value is stored in the flip-flop at the rising edge of the clock signal, the first bit of the scan pattern is stored in the first flip-flop (140) at the rising edge of the first clock signal. The output value of the first flip-flop (140) is stored in the second flip-flop (130) at the rising edge of the first clock signal, and the second bit value of the scan pattern is stored in the first flip-flop (140). Stored. At the rising edge of the third clock signal, the output value of the second flip-flop (130) is stored in the third flip-flop (120), and the output value of the first flip-flop (140) is the second flip-flop. (130), and the first bit value of the scan pattern is stored in the first flip-flop (140). Accordingly, one scan pattern is loaded into the flip-flops (120, 130, 140) on the scan path by three clock signals. Similarly, the values of the flip-flops (120, 130, 140) on the scan path are unloaded via the scan output port (166) by three clock signals.

  Hereinafter, the scan test process will be described more specifically.

  (1) Main input test data is applied to the main input port (150) of the IC chip (100).

  (2) A scan activation signal is applied to the scan activation port (160) to set the IC chip (100) to the scan mode.

  (3) The scan pattern is shifted into the scan input port (162), and the scan pattern is loaded into the flip-flops (120, 130, 140) on the scan path. The scan pattern loaded in the scan path is applied to the combinational circuit (110). After the scan pattern is applied to the combinational circuit (110), the result output through the main output port (152) is compared with the predicted main output value. If the comparison result is different, the IC chip is regarded as a defective product. judge.

  (4) A scan deactivation signal is applied to the scan activation port (160) to switch the IC chip (100) from the scan mode to the functional mode. When a clock signal is applied in the functional mode, the flip-flop (120, 130, 140) captures the output value of the combinational circuit (110). Such an operation is called a scan capture, and the mode at this time is called a scan capture mode.

  (5) A scan activation signal is applied to the scan activation port (160), and the IC chip (100) is switched from the functional mode to the scan mode again.

  (6) Then, the values captured by the flip-flops (120, 130, 140) on the scan path are unloaded by shifting out the values via the scan output port (166).

  (7) The unloaded output pattern is compared with the predicted pattern known in advance to determine whether the IC chip (100) can operate normally. Here, the predicted pattern is a scan pattern output via the scan output port (166) after applying the main input test data and the scan pattern and performing the scan capture operation when the IC chip (100) is normal. , The value you know before the test or the expected result pattern. If the comparison result in step (3) is the same and the comparison result in step (7) is the same, the test result is normal (PASS), so the IC chip is a good product, otherwise, the IC chip Is a defective product. Test normal (PASS) means a case where it is determined that there is no abnormality in the IC chip (Fault-Free), and test failure (FAIL) means a case where it is determined that there is an abnormality in the IC chip.

  2 and 3 are block diagrams showing the configuration of an embodiment of an IC chip test system called ATE (Automatic Test Equipment) to which the present invention is applied.

  As shown in FIGS. 2 and 3, the IC chip test system includes a host computer (200, 300), a tester body (210, 310), a test head (220, 320), and an interface board (230, 330). A device under test (DUT) set on the interface board (230, 330) for testing is an IC on a wafer or a packaged IC chip. If the DUT is an IC chip on a wafer, it further comprises a prober (350). Hereinafter, an IC circuit, an IC chip on a wafer, a packaged IC chip, and the like are referred to as an IC chip or a chip for convenience of explanation.

  The tester body (210, 310) controls the entire scan test. For example, the tester body (210, 310) controls general processes such as setup for DUT test, generation of electrical signals for DUT test, observation and measurement of DUT test result signals. The tester body (210, 310) can be realized by a computer including a central processing unit (CPU), a memory, a hard disk, a user interface, etc., and supplies power to the DUT (240, 340) according to an embodiment. A device power supply device (Device Power Supply) may be further included.

  The tester body (210, 310) controls a digital signal processor (DSP) (not shown) and a test head (220, 320) for processing various digital signals, and sends signals to the DUT (240, 340). Dedicated hardware such as controller and signal generator, software, firmware, or the like. The tester bodies (210, 310) are also called mainframes or servers.

  The host computer (200, 300) is a computer such as a personal computer or a workstation, and is a device that allows a user to execute a test program, control a test process, and analyze a test result. Generally, the host computer (200, 300) includes a CPU, a storage device such as a memory or a hard disk, a user interface, and the like, and is connected to the tester main body (210, 310) by wired or wireless communication. The host computer (200, 300) includes dedicated hardware, software, firmware and the like for controlling the test. In the present embodiment, the host computer (200, 300) and the tester main body (210, 310) are separately illustrated, but the host computer (200, 300) and the tester main body (210, 310) are realized by one apparatus. You can also.

  DRAM, SRAM, flash memory, or the like can be used as the memory of the tester body (210, 310) or the host computer (200, 300). The memory can store a program and data for performing a DUT test.

  The software or firmware of the tester body (210, 310) or host computer (200, 300) is a device driver program for a scan test, an OS (Operating System) program, a program for performing a DUT test, and a setup for the DUT test. , Stored in the memory in the form of an instruction code (Instruction Code) for generating a signal for the DUT test, observing and analyzing the DUT test result signal, and executed by the CPU.

  Therefore, the scan pattern is applied to the DUT by such a program. Furthermore, DUT test and test result reporting and analysis data can be obtained automatically through a program. Various languages such as C, C ++, Java and the like can be used as a language used in the program. The program can be stored in a recording device such as a hard disk, a magnetic tape, or a flash memory.

  The CPU of the tester main body (210, 310) or the host computer (200, 300) is a processor, and executes software or program code stored in the memory. For example, when a user command is received via a user interface such as a keyboard or a mouse, the CPU analyzes the user command, performs the corresponding work via software or a program, and then outputs the result to a speaker, printer, monitor, etc. Provide to users through the user interface.

  The user interface of the tester body (210, 310) or the host computer (200, 300) allows information to be exchanged between the user and the device and commands to be transmitted. For example, there are interface devices for user input such as a keyboard, a touch screen, and a mouse, and output interface devices such as a speaker, a printer, and a monitor.

  The test head (220, 320) includes a channel for transferring an electrical signal between the tester body (210, 310) and the DUT (240, 340). Interface boards (230, 330) are provided on the test heads (220, 320). An interface board used for a packaged IC chip is called a normal load board, and an interface board used for testing an IC chip on a wafer is called a normal probe card.

  In at least one embodiment of the present invention, the host computer (200, 300) includes an IC chip test device (250, 360).

  An IC chip test apparatus (250, 360) according to at least one embodiment of the present invention is a target scan which is a target for searching for a usable shift frequency among at least two scan sections included in a scan pattern set. A shift frequency search unit (251, 361) is provided for searching for a shift frequency where the section is shifted to the scan path and the result of the scan test is normal or unsuccessful.

  In the IC chip test apparatus (250, 360) according to at least one embodiment of the present invention, the shift frequency search unit (251, 361) determines the shift frequency of the target scan section when searching for the shift frequency for the target scan section. Find the shift frequency at which the scan test result is normal or unsuccessful, increasing or decreasing differently than at least one of the other scan sections shifting to the scan path, or setting it to a different shift frequency To do.

  In the IC chip test apparatus (250, 360) according to at least one embodiment of the present invention, the shift frequency search unit (251, 361) is configured to search for a shift frequency that can be used for the target scan section. While increasing or decreasing the shift frequency, the shift frequency is searched for the region where the scan test result changes from normal to failure or from the failure to normal.

  In the IC chip test apparatus (250, 360) according to at least one embodiment of the present invention, the shift frequency search unit (251, 361) may search the target scan section when searching for a shift frequency usable for the target scan section. The result of the first scan test obtained using the first shift frequency and the second scan frequency different from the first shift frequency for any one scan section before the target scan section. The first shift frequency is determined as a usable shift frequency for the target scan section when both of the obtained second scan test results are normal.

  An IC chip test apparatus (250, 360) according to at least one embodiment of the present invention includes a first test process for performing a test by shifting a first scan pattern including a first scan section to a scan path of an IC chip, and a first test process. Shift for searching for a usable shift frequency for the second scan section by executing a second test step of performing a test by shifting the second scan pattern including the second scan section after the first scan section to the scan path. A frequency search unit (251, 361) is provided.

  In the IC chip test apparatus (250, 360) according to at least one embodiment of the present invention, the shift frequency search unit (251, 361) uses the first scan section as a scan path at the first shift frequency in the first test process. Shifting, shifting the second scan section to the scan path at a second shift frequency different from the first shift frequency in the second test step, and searching for an available shift frequency for the second scan section in the first test step When both the test result and the test result in the second test step are normal, the second shift frequency is determined as a usable shift frequency for the second scan section.

  In the IC chip test apparatus (250, 360) according to at least one embodiment of the present invention, the first scan section is the first scan pattern or a part of the first scan pattern, and the second scan section is the second scan section. It is a part of the scan pattern or the second scan pattern.

  In the IC chip test apparatus (250, 360) according to at least one embodiment of the present invention, the shift frequency search unit (251, 361) may search the second shift frequency when searching for a usable shift frequency for the second scan section. Can be increased or decreased differently from at least one of the other scan sections shifting to the scan path, or set to a different shift frequency to find an available shift frequency for the second scan section. To do.

  An IC chip test method according to at least one embodiment of the present invention includes a scan path that scans a target scan section that is a target for searching for a usable shift frequency among at least two scan sections included in a scan pattern set. And a shift frequency search step of searching for a shift frequency where the scan test result is normal or unsuccessful.

  In the test method of an IC chip according to at least one embodiment of the present invention, the shift frequency search step includes another scan section that shifts the shift frequency of the target scan section to the scan path when searching for the shift frequency for the target scan section. And increasing or decreasing differently from at least one scan section, or setting to a different shift frequency, and searching for a shift frequency at which a scan test result is normal or unsuccessful.

  In the method of testing an IC chip according to at least one embodiment of the present invention, the shift frequency search step performs a scan while increasing or decreasing the shift frequency of the target scan section when searching for a usable shift frequency for the target scan section. A step of searching for a shift frequency of a region where a result of the test changes from normal to failure or a region where the test result changes from failure to normal.

  In the IC chip testing method according to at least one embodiment of the present invention, the shift frequency search step uses the first shift frequency for the target scan section when searching for a shift frequency usable for the target scan section. And the result of the second scan test obtained using a second shift frequency different from the first shift frequency for any one scan section before the target scan section. Determining a first shift frequency as an available shift frequency for the target scan section when both are normal.

  An IC chip test method according to at least one embodiment of the present invention includes a first test step of performing a test by shifting a first scan pattern including a first scan section to a scan path of the IC chip, and the first scan section and thereafter. A shift frequency search step of searching for a usable shift frequency for the second scan section by executing a second test step of performing a test by shifting the second scan pattern including the second scan section to the scan path. Prepare.

  In the IC chip test method according to at least one embodiment of the present invention, the shift frequency search step shifts the first scan section to the scan path at the first shift frequency in the first test step, and the second test step shifts the first scan section to the scan path. The test result and the second test in the first test step when the two scan sections are shifted to the scan path at a second shift frequency different from the first shift frequency, and the available shift frequencies for the second scan section are searched. Determining a second shift frequency as an available shift frequency for the second scan section when both test results in the process are normal.

  In the IC chip testing method according to at least one embodiment of the present invention, the first scan section is the first scan pattern or a part of the first scan pattern, and the second scan section is the second scan pattern or the second scan pattern. Part of a two-scan pattern.

  In the method for testing an IC chip according to at least one embodiment of the present invention, the shift frequency search step includes a step of shifting the second shift frequency to the scan path when searching for an available shift frequency for the second scan section. Searching for an available shift frequency for the second scan section, increasing or decreasing different from at least one of the scan sections, or setting to a different shift frequency.

  2 and 3, it is described that the IC chip test apparatus (250, 360) is included in the host computer (200, 300). However, this is merely an example, and a separate computer having a processor is used as the IC. It includes a chip test device (250, 360), and can be connected to a host computer (200, 300) or a tester body (210, 310) to perform a function.

  The IC chip test system shown in FIGS. 2 and 3 is only an example for deepening the understanding of the present invention. Therefore, the respective configurations are integrated to be realized as an integrated type, or one configuration is composed of a plurality of configurations. Various design changes are possible depending on the embodiment.

  The scan pattern means a bit pattern input to the scan path or a bit pattern output from the scan path for performing a scan test.

  The bit length of the scan pattern is the bit pattern length necessary for one scan test operation. For example, the bit length of the scan pattern may be the same as the bit length of the bit pattern shifted to the scan path until the scan capture operation is performed. Alternatively, the bit length of the scan pattern may be the same as the number of bit storage elements (Storage Elements) such as flip-flops on the scan path. The bit length of the scan pattern is not limited to the above description, and can be set in various forms by the scan test circuit.

  The embodiment of the present invention can be applied not only to the IC chip shown in FIG. 1 but also to various types of chips that shift in a bit pattern in a scan path and shift out an output pattern from the scan path.

  For example, the embodiments of the present invention may be applied to various types of chips including circuits that can perform an operation of shifting a scan pattern into a scan path, a scan capture operation, and an operation of shifting out a captured bit pattern. it can.

  FIG. 4 is a schematic view showing an example of a scan pattern applicable to the chip test according to at least one embodiment of the present invention.

  As shown in FIG. 4, the shift-in and shift-out operations are performed simultaneously in order to reduce the time required for performing the shift-in operation and the shift-out operation in the scan mode. That is, loading and unloading operations are performed simultaneously.

  For example, when the input pattern K (430) is shifted in and loaded into the scan path via the scan input port, the test result according to the input pattern K-1 (400) is simultaneously shifted out and unloaded via the scan output port. Is done. At this time, the unloaded output pattern is compared with the predicted pattern K-1 (440) for the input pattern K-1 (400). In general, the prediction pattern K-1 (440) and the input pattern K (430) for the input pattern K-1 (400) can be managed in pairs as test data or a file.

  In at least one embodiment of the present invention, an input pattern K (430) and an input pattern K− that are shifted in through a scan input port in order to perform a scan test with overlapping shift-in and shift-out operations (Overlapping). The prediction pattern for 1 (400) is managed in pairs. In this way, the scan patterns can have an order with respect to each other. In some embodiments, the scan pattern can be rearranged in various ways without order.

  In at least one embodiment of the present invention, when the first scan pattern is shifted into the scan path, the output pattern shifted out at the same time is the Don't Care pattern or the scan path state due to reset of the test target chip. Value.

  As another method for minimizing the scan test time, there are a method for reducing the total number of scan patterns for the scan test and a method for increasing the scan shift speed.

  Here, increasing the scan shift speed means increasing the shift frequency of shift-in or shift-out of the scan pattern or shortening the cycle of the shift frequency. On the other hand, lowering the scan shift speed means lowering the shift frequency or increasing the period of the shift frequency. Furthermore, optimizing the scan shift speed means optimizing the shift frequency or optimizing the period of the shift frequency.

  Since the increase or decrease of the shift frequency is substantially the same as the decrease or increase of the period of the shift frequency, in the following, for convenience of explanation, a method for minimizing the scan test time mainly from the viewpoint of increase or decrease of the shift frequency. Will be described. Therefore, in the following, even if there is no explicit description, an increase or decrease in frequency may be equated with a decrease or increase in frequency period, and conversely, an increase or decrease in frequency period is a frequency. May be equated with a decrease or increase of. Hereinafter, the frequency period is also simply referred to as a period.

  5 through 9 are schematic diagrams illustrating various examples of a method for dividing test data into at least one scan section in order to minimize chip test time according to at least one embodiment of the present invention.

  As shown in FIG. 5, the bit pattern of the test data (500) shifted to the scan path for the IC chip test is divided into a plurality of scan sections (510, 512, 514, 516, 518). (510, 512, 514, 516, 518) By determining another optimum shift frequency and applying it to the scan test, the scan test time can be shortened.

  In at least one embodiment of the present invention, the bit pattern of the test data (500) can be composed of a plurality of scan patterns as shown in FIG.

  As shown in FIG. 6, a plurality of scan patterns can be used for testing an IC chip. The scan section can be composed of at least one scan pattern or a part of the scan pattern, and by determining the optimum shift frequency for each scan section and applying it to the scan test, the scan test time can be reduced. It can be shortened more.

  In the first embodiment, the scan section 600 includes one scan pattern and corresponds to the scan pattern on a one-to-one basis. That is, the scan pattern becomes a scan section as it is.

  In the second embodiment, the scan section (610) may include two scan patterns. The number of scan patterns included in the scan section can be changed according to the embodiment.

  In the third embodiment, the scan section 620 may include a part of the first scan pattern and a part of the second scan pattern.

  In the fourth embodiment, the scan section (630) may be composed of a part of one scan pattern.

  In the fifth embodiment, one scan pattern can be divided into two scan sections (640, 650). The number of scan sections included in one scan pattern can be changed according to the embodiment.

  The test data can be divided into any form of scan sections (600, 610, 520, 630, 640, 650) according to various embodiments, and can be divided by applying two or more of these embodiments. it can. For example, as shown in FIG. 6, the test data composed of N scan patterns includes a first scan section (600) including one scan pattern, a second scan section (610) including two scan patterns, one It can be divided into a third scan section (640) and a fourth scan section (650) including a part of one scan pattern.

  As shown in FIG. 7, a section having the same and continuous bit values in the bit pattern of the test data (700) can be divided into scan sections (702, 704, 706, 708, 710). When the same bit value is continuously shifted to the scan path, the scan path bit value switching operation (Switching Activities) is reduced, and power consumption is reduced. Therefore, a high shift frequency is applied to a scan section having continuous bit values. Can be assigned.

  For example, the test data (700) includes at least one scan section (702, 704, 706) on the basis of a boundary in which the bit value changes from 0 to 1 or from 1 to 0 in the bit pattern of the test data (700). , 708, 710). Furthermore, M (M is an integer) bits can be divided into one scan section (720, 722) within a bit pattern interval (710) in which bit values of 0 or 1 are continuous.

  Furthermore, if the length of the section having the same and continuous bit value in the bit pattern of the test data is shorter than a predetermined length, at least two sections (702, 704) are divided without dividing this section as a scan section. It can be divided into one scan section (703).

  As shown in FIG. 8, the scan section (810) can be divided into a plurality of sub scan sections (812, 814) again. For example, the scan section (810) having a relatively low shift frequency among the optimum shift frequencies searched for by the scan sections (810, 820) is divided again into a plurality of sub-scan sections (812, 814). 812, 814), the optimum shift frequency can be searched again.

  As shown in FIG. 9, the test data is considered in consideration of an expected time (hereinafter referred to as “estimated required time”) required to search for an optimum shift frequency applied to each scan section of the test data (900, 910). Can determine the number of scan sections to divide. The larger the number of scan sections, the longer the expected time required to search for the optimum shift frequency of the entire scan section. The expected required time can be calculated by a preset mathematical expression that represents the relationship between the number of scan sections and the expected required time.

  In the example shown in FIG. 9, if there is a restriction of A time to search for the optimum shift frequency, the number N of scan sections that divide the test data (900) so that the expected required time is less than A time is It is decided. If there is a constraint on B (A> B) time to search for the optimum shift frequency, the number of scan sections M (N>) that divide the test data (910) so that the estimated required time is less than B time. M) is determined.

  When the number of test data (900) to be divided is determined to be N, the test data (900) is determined and divided into N scan sections. For example, a method of dividing the test data (900) into N scan sections having equal bit lengths, and dividing a section having the same and consecutive bit values as shown in FIG. Various methods such as a method of dividing until the number of N becomes N can be applied.

In order to calculate the estimated required time, the following information can be used.
-Start frequency for searching for the optimal shift frequency-End frequency for searching for the optimal shift frequency-Frequency increase / decrease unit for searching for the optimal shift frequency-Frequency for searching for the optimal shift frequency Increase / decrease method (continuous increase / decrease or binary search method)
・ Number of scan patterns included in test data (SPN)
-Scan pattern bit length (SBL)
・ Methods and criteria for dividing test data into scan sections (divided by a fixed bit length unit, divided by a fixed number, or divided based on a boundary where the bit value changes)
・ Number of scan sections (SSN)
-The performance of the device that executes the method of searching for the optimum shift frequency (for example, processor performance (CPU speed, etc.), memory and hard disk capacity and speed, etc.)
・ Other margin time considering the data input / output time of the device that executes the method of searching for the optimum shift frequency

  In at least one embodiment of the present invention, when a method of sequentially increasing from a start frequency to an end frequency is used when searching for an optimal shift frequency, an example of a mathematical formula for calculating an estimated required time is as follows: It is as follows.

(Equation 1)
Estimated required time (T) = SSN * SPN * SBL * SFP * FN
Here, SSN is the number of scan sections, SPN is the number of scan patterns, SBL is the bit length of the scan pattern, SFP is the cycle of the shift frequency, and FN is the shift frequency for searching for the optimum shift frequency per scan section. This represents the number of increases.

  Given the expected time required by Equation 1, the number of scan sections that satisfy this can be determined.

  FIG. 10 is a graph showing the relationship between the number of scan sections and the reduction rate of the scan test time according to at least one embodiment of the present invention.

  As shown in FIG. 10, the number of scan sections divided in the test data can be determined using the transition information of the scan test time reduction rate according to the number of scan sections and the scan section division method. As the number of scan sections in which the shift frequency is optimized increases, the time reduction rate of the scan test using the test data increases.

  In FIG. 10, the vertical axis represents the scan test time when using a single shift frequency for the entire test data versus the reduction rate of the scan test time when using the optimum shift frequency for each scan section. The horizontal axis represents the number of scan sections in which the shift frequency is optimized.

  The greater the number of scan sections that divide the test data, the shorter the average bit length of the scan section. The shorter the bit length of the scan section, the higher the optimum shift frequency, and the scan test time can be further shortened.

  The various methods of dividing the scan section discussed above are examples for deepening the understanding of the present invention, and the present invention is not limited to the methods shown in FIGS. Needless to say, various methods for dividing the test data can be applied in addition to the methods shown in FIGS.

  FIG. 11 is a schematic diagram illustrating an example in which a shift frequency is assigned to each scan section in order to minimize the test time of the IC chip according to at least one embodiment of the present invention.

  As shown in FIG. 11, a plurality of shift frequencies are assigned to each scan section. In the case of a conventional scan test, a single shift frequency that can normally shift all scan patterns of test data to the scan path of the IC chip is used. Such a single shift frequency is also referred to as a nominal shift frequency.

  In general, the nominal frequency is a shift frequency used when a scan pattern is created by ATPG software or a shift frequency slightly adjusted based on this, and all scan patterns for testing an IC chip are included in the scan path of the IC chip. A single frequency that can be shifted normally and a relatively low frequency (eg, about 5 MHz).

  Therefore, if the nominal frequency is used as it is for several thousand to several tens of thousands of scan patterns constituting the test data, it takes a considerable amount of time for the scan test. This significantly affects the market entry time (Time-to-Market). For example, if it takes 2 seconds to test one IC chip, it takes about 5,556 hours, or about 231 days, to test 10 million chips sequentially. Even if several chips are tested at the same time using an expensive apparatus, a relatively long test time is required. Usually, an IC chip test service provider charges the cost based on the number of test devices used and the test time, so that the time required for the chip test greatly affects the cost of the chip.

  In order to solve such a problem, if the nominal shift frequency is simply increased, the power consumption that occurs when the scan pattern is shifted in or out may be out of the range of power consumption allowed by the IC chip. It may not be possible to perform a normal scan test. Furthermore, an overkill problem may occur in which a non-defective product is determined to be a defective product due to a critical path delay time problem, an effect of power supply noise, an interference effect between signal lines, and the like depending on the overshift frequency. This will affect the yield and cost which are very important in the mass production of IC chips.

  Therefore, the embodiment of the present invention does not apply a single shift frequency such as a nominal shift frequency to the entire scan pattern, but assigns an optimal shift frequency that can be normally shifted to the scan path for each scan section. . The process of searching for the optimum shift frequency for each scan section will be described in more detail with reference to FIG. The optimal shift frequency means the maximum shift frequency that can be used for the scan section or a lower shift frequency.

  In the example shown in FIG. 11, the shift frequency A is assigned to the scan section 1, and the shift frequency B is assigned to the scan section 2. Similarly to the scan section 1, the shift frequency A is assigned to the scan section 3. In this manner, each scan section is assigned the same shift frequency or different shift frequencies.

  For example, when one scan pattern is divided into a plurality of scan sections, a plurality of shift frequencies are assigned to one scan pattern. Referring to FIG. 6, two scan sections (640, 650) belonging to one scan pattern are assigned different shift frequencies. That is, two shift frequencies are assigned to one scan pattern.

  Scan sections assigned shift frequencies can be integrated into section groups in some embodiments. For example, the second scan section and the third scan section can be set as a section group, and a lower shift frequency or less of the shift frequencies A and B of each scan section can be assigned to the section group.

  The application of main input test data to the main input port in the scan test process and the observation of the test result from the main output after inputting the scan pattern to the scan path are applied and applied to the chip test process of the following embodiments. May not be.

  FIG. 12 is a schematic diagram illustrating an example of searching for a shift frequency in order to minimize the test time of an IC chip according to at least one embodiment of the present invention.

  First, the relationship between the input pattern, scan section, scan pattern, and output pattern will be described.

  The input patterns (1202, 1204, 1206) are bit patterns input to the scan path (1210). In FIG. 12, the shift frequency is determined. The scan section K has a one-to-one correspondence with the input pattern K (1204). The bit pattern located before or after the input pattern K (1204) including the scan section K (hereinafter referred to as “target scan section K”) for which the optimum shift frequency is to be searched or determined is an auxiliary scan for the target scan section. It can be referred to as a section or auxiliary bit pattern.

(Input pattern when scan section and scan pattern correspond one-to-one)
When the target scan section K (1204) has a one-to-one correspondence with the scan pattern M, the input pattern K-1 (1202), the input pattern K (1204), and the input pattern K + 1 (1206) are each the scan pattern M-1. , The scan pattern M and the scan pattern M + 1 can correspond one-to-one.

(Output pattern K when scan section and scan pattern correspond one-to-one)
When the target scan section K (1204) has a one-to-one correspondence with the scan pattern M, the output pattern of the scan path (1210) for the target scan section K (1204) is the output pattern K of the scan path (1210) for the scan pattern M. This corresponds to (1224). The output pattern K (1224) is a pattern in which the scan capture result pattern or the scan pattern M for the target scan section K (1204) is output as it is from the scan path.

(Output pattern K-1 when scan section and scan pattern correspond one-to-one)
When the target scan section K (1204) has a one-to-one correspondence with the scan pattern M, the scan path output pattern for the input pattern K-1 (1202) is the scan path output pattern K-1 (1222) for the scan pattern M-1. ) The output pattern K-1 (1222) is a pattern in which the scan capture result for the scan pattern M-1 or the scan pattern M-1 is output as it is from the scan path.

(Output pattern K + 1 when scan section and scan pattern correspond one-to-one)
When the target scan section K (1204) has a one-to-one correspondence with the scan pattern M, the scan path output pattern for the input pattern K + 1 (1206) is the scan path output pattern K + 1 for the scan pattern M + 1. The output pattern K + 1 is a pattern in which the scan capture result for the scan pattern M + 1 or the scan pattern M + 1 is output as it is from the scan path.

(Input patterns K-1, K + 1 when the scan section is a part of the scan pattern)
For example, as shown in FIG. 14, when the target scan section K (1204) is a part of the scan pattern M, the input pattern K-1 (1202) is scanned from the scan pattern M-1 and the scan pattern M. A part other than K (1204) can be included. The input pattern K + 1 can include a part other than the scan section K (1204) from the scan pattern M + 1 and the scan pattern M.

(Output pattern K when the scan section is part of the scan pattern)
As shown in FIG. 14, when the target scan section K (1204) is a part of the scan pattern M, the output pattern K (1224) of the scan path for the target scan section K (1204) is the target scan section K ( 1204) or a scan capture result pattern for a scan pattern M including a scan section K. Alternatively, the output pattern K (1224) is a pattern in which the scan section K (1204) is output as it is from the scan path or a scan pattern M that includes the scan section K (1204) is output as it is from the scan path. .

(Output patterns K-1, K + 1 when the scan section is a part of the scan pattern)
When the target scan section K (1204) is a part of the scan pattern M as shown in FIG. 14, the output pattern K-1 (1222) of the scan path for the input pattern K-1 (1202) is the scan pattern. This is an output pattern for M-1 or an output pattern for a part of scan pattern M-1 and scan pattern M. Further, the output pattern K + 1 of the scan path for the input pattern K + 1 (1206) is an output pattern for the scan pattern M + 1 or an output pattern for a part of the scan pattern M + 1 and the scan pattern M. In another example, the output pattern of the scan path for a part of the scan pattern M included in the input pattern K-1 (1202) or the input pattern K + 1 (1206) is a scan including the target scan section K (1204). This is reflected in the output pattern of the scan path for the pattern M. In still another example, the output pattern corresponding to the input pattern K-1 (1202) or the input pattern K + 1 (1206) is a pattern in which the input pattern K-1 (1202) or the input pattern K + 1 (1206) is output as it is from the scan path. It is.

(When the scan section spans multiple scan patterns)
For example, as shown in FIG. 15, the target scan section K (1204) may span a plurality of scan patterns. In such a case, the input pattern K-1 (1202) includes a portion obtained by excluding the portion of the target scan section K (1204) from the scan pattern M-1, and the input pattern K + 1 (1206) is the target from the scan pattern M + 1. A portion excluding the portion of the scan section K (1204) is included. In this case, the optimum shift frequency is searched for each part of the target scan section K (1204) applied to each scan pattern, and the optimum shift frequency assigned to the target scan section K (1204) is determined. be able to.

  The above examples are merely examples for deepening the understanding of the present invention, and the present invention is not limited thereto. Further, as described with reference to FIGS. 5 to 10, the scan pattern can be divided into various types of scan sections, and the input pattern K and the input pattern K positioned before and after the scan section are divided according to the division form of the scan section. The form of −1 or input pattern K + 1 can also be changed appropriately. That is, the input pattern K-1 (1202) or the input pattern K + 1 (1206) can be composed of at least one scan section.

  FIG. 12 shows an example for minimizing the scan test time when the shift-in and the shift-out described with reference to FIG. 4 are performed in an overlapping manner. FIG. 12 is for explaining an example according to at least one embodiment of the present invention. Needless to say, the present invention is not limited to the case where the shift-in and the shift-out described with reference to FIG. 4 are performed simultaneously. .

  In the IC chip scan test, the test result pattern (1220) for the input pattern (1200) is compared with the predicted pattern (1230) to determine whether the test result is normal. That is, after the input pattern (1200) is loaded onto the scan path (1210), the result pattern (1220) obtained by performing the capture operation is unloaded, or the input pattern is loaded and then unloaded without the capture operation. Then, the prediction pattern (1230) and the unloaded result pattern (1220) are compared to determine whether the test is normal.

  In at least one embodiment of the present invention, to optimize the shift frequency for a scan pattern or scan section, the target scan pattern or target scan section is shifted simultaneously (or sequentially) when the target scan pattern or target scan section is shifted into the scan path. Check if the output pattern is normal. For example, even if the target scan pattern target scan section is normally shifted into the scan path at the increased shift frequency, an error may occur in the test result pattern for the input pattern before being shifted out at the increased shift frequency. It is.

  In the example shown in FIG. 12, in order to confirm whether the scan section K (1204), which is the target for determining the current shift frequency, is normally shifted into the scan path at the specific shift frequency, the input pattern K-1 (1202 ) And the input pattern K + 1 (1206) can be used together. That is, the input pattern K-1 (1202) that can initialize the scan path with a certain bit pattern before the target scan section K (1204) is repeatedly input to the scan path (1210) can be used. Further, every time the output pattern of the scan path for the kth scan section (1204) is repeatedly shifted, the input pattern K + 1 (1206) shifted into the scan path with a constant bit pattern can be used.

  When the target scan section K (1204) has a one-to-one correspondence with the scan pattern M, the input pattern K-1 (1202) is the scan pattern M used for the actual test located before the target scan section K (1204). This is a predicted pattern for a result pattern obtained by scan capture after loading 1 or scan pattern M-1 into the scan path.

  In another example, when the target scan section K (1204) is a part of the scan pattern M as shown in FIG. 14, the input pattern K-1 (1202) is positioned before the target scan section K (1204). In addition, the scan pattern M-1 or the scan pattern M-1 used for the actual test is loaded into the scan path and then the predicted pattern for the result pattern obtained by scan capture is included. Furthermore, the input pattern K-1 (1202) includes a part other than the target scan section K (1204) from the scan pattern M. Here, a part other than the target scan section K (1204) from the scan pattern M is a part of the bit pattern used in the actual scan test.

  Further, the input pattern K-1 (1202) is preliminarily set such that it is mainly composed of bits 0 or 1 or mainly composed of consecutive bits 0 or 1 in order to reduce the scanning path switching operation. It is an arbitrary pattern.

  Furthermore, in another example, the input pattern K-1 (1202) includes at least one scan section as shown in FIG.

  When the target scan section K (1204) has a one-to-one correspondence with the scan pattern M, the (k + 1) th input pattern K + 1 (1206) is the scan pattern M + 1 used for the actual scan test located after the scan section K (1204). Alternatively, it is a predicted pattern for a result pattern obtained by scanning a scan pattern M + 1 after loading it onto the scan path.

  In still another example, when the target scan section K (1204) is a part of the scan pattern M as shown in FIG. 14, the input pattern K + 1 (1206) is actually located after the target scan section K (1204). A scan pattern M + 1 used for the scan test is included. Further, the input pattern K + 1 (1206) includes a part other than the target scan section K (1204) from the scan pattern M. Here, a part other than the target scan section K (1204) is a part of the bit pattern used in the actual scan test.

  In yet another example, the input pattern K + 1 (1206) is configured mainly by bits 0 or 1 in order to reduce the switching operation on the scan path, or mainly configured by consecutive bits 0 or 1 in advance. It is a set arbitrary pattern.

  In still another example, the input pattern K + 1 (1206) includes at least one scan section as shown in FIG.

  In the scan test, the input pattern located before the first scan section and after the last scan section is mainly composed of bit 0 or 1 in order to reduce the switching operation of the scan path, or consecutive bits 0. Alternatively, it is an arbitrary pattern set in advance such as mainly composed of 1. Furthermore, the input pattern located before the first scan section may be a value on the scan path when the test target chip is in the reset state.

  In at least one embodiment of the present invention, each of the input pattern K-1 (1202) or the input pattern K + 1 (1206) is composed of one or more scan sections, and the shift frequency of these sections is a target for determining the current shift frequency. It is possible to make no restriction on searching for the maximum shift frequency of the scan section K (1204).

  For example, it is assumed that the input pattern K-1 (1202) can be normally shifted into the scan path up to 30 MHz, and the target scan section K (1204) can be normally shifted into the scan path up to 50 MHz. When the input pattern K-1 (1202) and the target scan section K (1204) are sequentially shifted into the scan path at the same shift frequency while increasing the shift frequency, the maximum shift frequency that can be searched for the target scan section K (1204) Is limited to 30 MHz. This is because when the shift frequency exceeds 30 MHz, the output pattern and the prediction pattern for the input pattern K-1 (1202) may be different from each other. Further, even when the input pattern K + 1 (1206) can be normally shifted into the scan path up to a maximum of 30 MHz, the maximum shift frequency that can be searched for the target scan section K (1204) is limited to 30 MHz.

  Therefore, in order to avoid such a restriction, in at least one embodiment of the present invention, the input pattern K-1 (1202) or the shift frequency of the input pattern K-1 (1202) is set to a preset shift frequency ( In the above-described example, it is possible not to exceed 30 MHz).

  For example, the shift frequency of the input pattern K-1 (1202) or the input pattern K + 1 (1206) is fixed to a preset shift frequency (30 MHz in the above example), and the shift frequency of the target scan section K (1204) The maximum shift frequency that can be used for the target scan section K (1204) can be searched.

  In yet another example, the input pattern K-1 (1202), the target scan section K (1204), and the input pattern K + 1 (1206) are preset up to a shift frequency (30 MHz in the above example) together. When the shift frequency is increased and exceeds a preset shift frequency, only the shift frequency of the target scan section K (1204) can be increased.

  In other words, the shift frequency of the target scan section K (1204) and the shift frequencies of the other input patterns (1202, 1206) can be controlled to be different from each other. If the maximum allowable shift frequency of the input pattern K-1 (1202) or the input pattern K + 1 (1206) is higher than the maximum shift frequency of the target scan section K (1204), the target scan section K (1204) and other input patterns (1202) 1206) can be increased at the same frequency. Here, the preset shift frequency can be appropriately changed according to the embodiment, such as a nominal shift frequency, a shift frequency obtained by adjusting the nominal shift frequency, a value preset in the test apparatus by a program, or a value preset by the user. And is not limited to the above example.

  In at least one embodiment of the present invention, an optimal shift frequency is already determined for the input pattern K-1 (1202) or the input pattern K + 1 (1206) using the method according to at least one embodiment of the present invention. In such a case, the input pattern K-1 (1202) or the input pattern K + 1 (1206) can be shifted into the scan path by applying the optimum shift frequency or lower.

  For example, when the method according to at least one embodiment of the present invention is sequentially applied to a scan pattern, at least one of the input pattern K-1 is determined before the shift frequency of the target scan section K (1204) is determined. The optimal shift frequency for the above scan section may be determined first. Therefore, the apparatus for minimizing the scan test time uses the optimum shift frequency for each scan section of the input pattern K-1 (1202), and the nominal shift frequency or the nominal shift frequency for the input pattern K + 1 (1206). An adjusted shift frequency can be applied.

  Then, the input pattern (1202, 1204, 1206) is sequentially input onto the scan path (1210) while increasing the shift frequency of the target scan section K (1204), and the actual output pattern (1220) is the same as the predicted pattern (1230). It is judged whether it is. At this time, a scan capture operation may be performed on at least one of the input patterns (1202, 1204, 1206) as necessary.

  For example, a device that minimizes the scan test time uses the nominal shift frequency as the initial shift frequency, and increases the shift frequency in increments or decrements of the shift frequency preset in the device that minimizes the scan test time. That is, after the input pattern K-1 (1202) is loaded into the scan path by shifting in the preset shift frequency like the nominal frequency, the target scan section K (1204) is set to “initial shift frequency + increment unit”. And the test result (ie, output pattern K-1) (1222) of the input pattern K-1 (1202) is shifted out at the same time, and the known prediction pattern K-1 (1232) is shifted out. ) Is the same.

  At this time, the shift frequency preset for at least one scan section included in the input pattern K-1 (1202) or the input pattern K-1 (1202) is the same as that of the target scan section K (1204). It may be different from the initial shift frequency. The output pattern K (1224) obtained by shifting out the test result for the target scan section K (1204) simultaneously with the shift-in of the input pattern K + 1 (1206) again is the same as the known prediction pattern (1234). To compare. At this time, if the target scan section K (1204) is a part of the scan pattern as shown in FIG. 14, the input pattern K-1 (1202), the target scan section K (1204), and the input pattern K + 1 (1206). And the output pattern for each is as described above.

  In at least one embodiment of the present invention, the preset shift frequency described above may not constrain the search for the optimal shift frequency of the target scan section K (1204). In at least one embodiment of the present invention, the shift frequency of the input pattern K-1 (1202) or the input pattern K + 1 (1206) should not be increased or decreased with the shift frequency of the target scan section K (1204) or the target scan section. A frequency different from K (1204) can be used. At this time, a shift frequency that can normally input the scan section of the input pattern K-1 (1202) or the input pattern K + 1 (1206) to the scan path is used.

  In at least one embodiment of the present invention, the preset shift frequency may be a value obtained by adjusting the nominal shift frequency in addition to the nominal shift frequency, a value set in the apparatus by a program, or a value set by the user. However, the present invention is not limited to the above example.

  If the output pattern K-1 (1222) and the prediction pattern K-1 (1232) are the same, and the output pattern K (1224) and the prediction pattern K (1234) are the same, the current shift frequency is the target scan section K (1204). ) Is a usable shift frequency. The apparatus for minimizing the scan test time again increases the shift frequency for the target scan section K (1204) by a predetermined magnitude and similarly performs the process of inputting from the input pattern K-1 (1202) to the scan path. The step of comparing the output pattern (1220) and the predicted pattern (1230) is performed again.

  In this manner, the shift frequency for the target scan section K (1204) is continuously increased until the output pattern (1220) and the predicted pattern (1230) are not identical, and the shift frequency before that is below the target scan section K ( 1204) can be determined as the optimum shift frequency.

  The above-described embodiment mainly describes a method of searching for an optimal shift frequency by increasing the shift frequency. As another embodiment, the shift frequency is predicted as the output pattern (1220) of the target scan section K (1204). It is possible to search for a shift frequency at which the output pattern (1220) and the predicted pattern (1230) are the same while the pattern (1230) is repeatedly lowered from a different high frequency. Then, a shift frequency equal to or lower than the shift frequency at which the output pattern (1220) and the prediction pattern (1230) are the same can be determined as the optimum shift frequency of the target scan section K (1204).

  Furthermore, as an example of the shift frequency increase / decrease range when repeatedly comparing the output pattern and the predicted pattern for the scan section or scan pattern while increasing / decreasing the shift frequency, within the range set in the device that minimizes the scan test time When the output frequency (1220) and the predicted pattern (1230) are the same or different from each other, the increase or decrease of the shift frequency is stopped. In this case, the time required to search for the maximum shift frequency that can be used for each scan section can be reduced.

  Depending on the embodiment, various values other than the nominal frequency can be set as the initial shift frequency for searching for the optimum shift frequency for the target scan section K (1204). Furthermore, instead of increasing from a low shift frequency, it is possible to search for a shift frequency at which the output pattern and the prediction pattern are the same while decreasing the shift frequency, starting from a high shift frequency where the output pattern and the prediction pattern are different from each other. In addition, instead of sequentially increasing or decreasing the shift frequency of the target scan section K (1204), it may be changed in various ways through various algorithms to find the optimal shift frequency in a shorter time. Is possible.

  In at least one embodiment of the present invention, a binary search algorithm can be used. For example, if the shift frequency is 10 MHz and the test is normal and the test fails at 20 MHz, the next shift frequency is 15 MHz. If the test is normal, the test is performed between 15 MHz and 20 MHz. If the test is unsuccessful, the test is performed between 10 MHz and 15 MHz. The test normal means that the test target chip is determined as a non-defective product, and the test failure means that the test target chip is determined as a defective product.

Employing binary search has the effect of reducing the time required to search for a frequency that is a boundary between test normality and test failure or a frequency range that can be used in normal test, as compared to linear search (Linear Search). For example, when the maximum frequency of normal test is searched with the frequency increase / decrease number of N times using linear search, the maximum frequency of normal test can be searched with the number of times of log ₂ (N) when binary search is used. . The effect of reducing the search time required to search for the maximum frequency of normal test using binary search is more effective than the linear search method as the total number of scan sections and the unit value of the frequency increased or decreased by the test apparatus are smaller.

  In yet another example, an optimum frequency and cycle can be determined in consideration of a change margin of a voltage (Supply Voltage) supplied to the test target chip. For example, it is possible to quickly search for an optimal frequency or cycle within the range of the voltage supplied to the test target chip through the following steps.

Step 1
The apparatus for minimizing the scan test time searches the maximum shift frequency or the range of the shift frequency where the test result of the test data is normal for each voltage while changing the voltage supplied to the test target chip by a predetermined unit. That is, instead of searching for the shift frequency for each scan section into which the test data is divided, the maximum shift frequency or shift frequency range that can be used for the entire test data is searched.

Step 2
From the result in step 1, the apparatus that minimizes the scan test time selects a specific voltage to be supplied to the test target chip. Here, the specific voltage supplied to the test target chip is a voltage corresponding to the lowest shift frequency among the maximum shift frequencies by voltage searched in step 1 or a voltage adjacent thereto. In addition, a voltage to be supplied to the test target chip can be selected in consideration of a test setup, a manufacturing process, a test process, or the like.

Step 3
The apparatus for minimizing the scan test time supplies the specific voltage selected in step 2 to the test target chip. The apparatus that minimizes the scan test time grasps whether the test is normal or failed for each shift frequency while increasing or decreasing the shift frequency for each scan section while supplying a specific voltage.

Step 4
The apparatus for minimizing the scan test time searches or determines the optimum shift frequency for each scan section using the shift frequency information to which the result of the test normal or test failure for each scan section obtained in step 3 is mapped.

Step 5
The apparatus for minimizing the scan test time checks whether the test result is normal using the optimum shift frequency for each scan section searched or determined in step 4 while changing the voltage supplied to the test target chip.

  In at least one embodiment of the present invention, the voltage change range in step 5 may be the same as the voltage change range in step 1. Further, the voltage change range in step 5 may be a range in which the change range in step 1 is adjusted in consideration of a test setup, a manufacturing process, a test process, or the like. While changing the voltage within the voltage change range, it is confirmed whether the scan test result using the optimum shift frequency for each scan section searched or determined in step 4 is normal.

  If all the scan sections are tested normally within the voltage change range, the shift frequency is normally optimized. In addition, there may be various criteria for determining that the shift frequency is normally optimized for each scan section in consideration of a test setup, a manufacturing process, a test process, and the like. For example, a specific voltage may cause a test failure.

  If you have to search for the optimum frequency in consideration of the change margin of the voltage supplied to the chip under test, the method described above is based on the method of searching while changing the voltage and frequency for all scan sections. By using this method, it is possible to quickly search or determine the optimum shift frequency or the period of the shift frequency.

  For example, assuming that SN (number of scan sections) = 1,000, VN (voltage change count) = 10, and FN (frequency change count) = 10, consider the following case.

Case 1
Number of searches required to grasp test normality or test failure while changing voltage and frequency for all scan sections = SNxVNxFN = 100,000

Case 2
Number of searches required to grasp test normality or test failure using steps 1 to 5 described above = (step 1) VNxFN + (step 3) SNxFN + (step 5) VN = (VN + SN) xFN + VN = 10, 110

  It can be seen that the number of cases 2 is reduced to about 10% of case 1.

  The scan section K (1204) for searching for the optimum shift frequency may be composed of a part of the scan pattern M as shown in FIG. That is, the length of the target scan section K (1204) may be shorter than the length of the scan path. In such a case, the shift frequency of the portion excluding the target scan section K (1204) in the scan pattern M including the target scan section K (1204) is used to search for the optimum shift frequency of the target scan section K (1204). Avoid giving constraints.

  For example, the shift frequency of the portion excluding the target scan section K (1204) in the scan pattern M is not increased or decreased together with the shift frequency of the target scan section K (1204), or is different from the target scan section K (1204). Frequency can be used. In at least one embodiment of the present invention, as the shift frequency of the part excluding the target scan section K (1204) in the scan pattern M, the part excluding the target scan section K (1204) can be normally input to the scan path. A shift frequency can be used.

  In another example, the shift frequency applied to the portion excluding the target scan section K (1204) in the scan pattern M is equal to or lower than the nominal shift frequency or the portion excluding the target scan section K (1204). When an optimum shift frequency has already been determined using the method according to at least one embodiment, a preset shift frequency can be used so as to be equal to or less than the optimum shift frequency. For the target scan section K (1204), as described above, the optimum frequency is searched through the shift frequency increase / decrease. The preset shift frequency can be changed according to the embodiment, such as a value obtained by adjusting the nominal shift frequency, a value set in the apparatus by a program, or a value set by the user, and is not limited to the above example. .

  FIG. 12 shows a method of searching for the optimum shift frequency of the target scan section K (1204) using the input pattern K-1 (1202) together, but is not limited to this. According to the embodiment, only the output pattern of the scan path for the scan pattern including the target scan section K (1204) or the target scan section K (1204) may be compared with the predicted pattern to search or determine the optimum shift frequency.

(Comparison with output pattern prediction pattern for previous input pattern)
In at least one embodiment of the present invention, the input pattern K-1 (1202) located immediately before the target scan section K (1204) when searching or determining the optimum shift frequency of the target scan section K (1204). Or an output pattern for a scan pattern located immediately before the scan pattern including the target scan section K (1204) can be compared with the predicted pattern.

  For example, when the output pattern of the scan path for the target scan section K (1204) is the same as the predicted pattern and the output pattern for the input pattern K-1 (1202) is also the same as the predicted pattern, the target scan section K (1204) is changed. The shift frequency used when shifting to the scan path is a usable shift frequency of the target scan section K (1204).

  In another example, when the target scan section K (1204) is a part of the scan pattern as shown in FIG. 14, the output pattern K (1224) of the scan path for the scan pattern M including the target scan section K (1204) is When the output pattern K-1 (1222) of the scan path for the scan pattern M-1 that is the same as the predicted pattern K (1234) and is located before the scan pattern M is the same as the predicted pattern K-1 (1232), The shift frequency used when shifting the target scan section K (1204) to the scan path is a usable shift frequency of the target scan section K (1204).

  As described above, the reason why the output pattern (1222) and the predicted pattern (1232) for the input pattern (1202) positioned in front of the target scan section K (1204) is compared with the target scan section K (1204). This is because the output pattern of the scan path with respect to the input pattern (or a part of the input pattern) located before () is influenced by the shift-in frequency of the target scan section K (1204). Here, the shift-out output pattern with respect to the input pattern is obtained by performing a scan capture operation after an input pattern (or a part of the input pattern) positioned before the target scan section K (1204) is input to the scan path. It is a pattern that is output from the scan path without a pattern or scan capture operation.

  FIG. 16 is a graph illustrating an example of a method for searching for a usable shift frequency of a scan pattern according to at least one embodiment of the present invention. FIG. 17 is a graph showing a case where the test result of another scan pattern fails when increasing or decreasing the shift frequency of the scan pattern to be searched for the optimum shift frequency according to at least one embodiment of the present invention. It is.

  As shown in FIG. 16, the first scan pattern, the second scan pattern, and the third scan pattern are sequentially input to the scan path in order to search for the optimum shift frequency of the second scan pattern. In at least one embodiment of the present invention, a shift frequency (for example, 5 MHz) at which the first scan pattern can be normally input to the scan path is used for shifting in the first scan pattern. That is, the shift frequency at which the scan test result by the first scan pattern is normal is used for shifting the first scan pattern.

  When the shift frequency of the second scan pattern is sequentially increased from 5 MHz to 25 MHz, the test results of the first scan pattern and the second scan pattern are both normal. In this case, all shift frequencies of 25 MHz or less are shift frequencies that can be used for the second scan pattern.

  As shown in FIG. 17, when the shift frequency of the second scan pattern is increased to 30 MHz, the test result of the second scan pattern is normal, but the test result of the first scan pattern is unsuccessful. This is because the test result of the first scan pattern to be shifted out is affected by the shift frequency of the second scan pattern. Therefore, in at least one embodiment of the present invention, not only the second scan pattern to be searched for the optimum shift frequency but also the test result of the first scan pattern that is the input pattern before the second scan pattern is normal. The shift frequency in this case is a usable frequency of the second scan pattern.

  In some cases, the scan section that seeks the optimal shift frequency is part of the scan pattern. In such a case, as described above, not only the second scan pattern including the target scan section to be searched for the optimum shift frequency but also the shift frequency when the test result of the first scan pattern is normal is the target. This is the usable frequency of the scan section. For the bit pattern excluding the target scan section, a shift frequency capable of normally inputting the bit pattern to the scan path is used.

  The third scan pattern is normally shifted into the scan path, and at the same time, a shift frequency that can normally shift out the test result for the second scan pattern is used.

  In order to search for the optimum shift frequency of the scan section or to reduce the production test time of the chip, the first scan section and the second scan section which are adjacent to each other are sequentially input to the scan path of the chip. The scan test can be performed by making the shift frequency and the shift frequency of the second scan section different from each other. For example, the different shift frequencies used for the two scan sections are equal to or lower than the shift frequency at which the scan test using the two scan sections is normal.

  The scan test can be performed by setting the shift frequency of the second scan section higher or lower than the shift frequency of the first scan section for the first scan section and the second scan section adjacent to each other. At this time, when the test result for a fault-free (Fault-Free) chip is normal, the shift frequency below each of the two adjacent scan sections is used to shorten the chip mass production test time. That is, it is necessary to consider the influence of adjacent scan sections on each other during a scan test.

  For example, if the first scan section and the second scan section are scan patterns adjacent to each other, the influence of the shift frequency of the second scan section that is subsequently input is considered when the scan capture result by the first scan section is shifted out. Must. For example, when the scan capture result pattern is shifted out, the bit value of the result pattern may change depending on the shift frequency.

  In another example, when the first scan section and the second scan section that are adjacent to each other are included in one scan pattern, the shift of the second scan section that is subsequently shifted in when the first scan section is shifted in. The effect of frequency must be taken into account. For example, the bit value of the first scan section shifted in the scan path may change depending on the shift frequency of the second scan section.

  In yet another example, when the scan capture result of the first scan pattern shifted in before the second scan pattern including the first scan section and the second scan section is shifted out, the second scan pattern belonging to the second scan pattern The influence of the first scan section and the second scan section must be considered. If this effect is not taken into consideration, the scan test result for a chip having no failure may be a test failure during a mass production test.

(Consideration of output result for input pattern before or after target scan section to search for optimum shift frequency)
When searching or determining the optimum shift frequency of the target scan section, the scan located before or after the scan pattern including not only the target scan section but also the input pattern or the target scan section (1204) positioned before or after the target scan section. The output pattern of the scan path for the pattern is compared with the predicted pattern to grasp whether or not the normal test target IC chip is actually tested as normal.

  In at least one embodiment of the present invention, it is possible to search for the optimum shift frequency of the target scan section by repeating such a process while increasing or decreasing the shift frequency. At this time, the shift frequency with a normal test result is a usable shift frequency of the target scan section. The scan path output pattern for the target scan section is the pattern obtained by loading the target scan section into the scan path and then performing the capture operation, or the target scan section or the scan pattern that includes the target scan section is the scan capture operation It is a pattern output from the scan path without any.

(Consideration of output result for input pattern input after target scan section to search for optimum shift frequency)
In order to find or determine the optimal shift frequency, the output pattern of the scan path for the input pattern located after the target scan section or the scan pattern located after the scan pattern including the target scan section (1204) is also compared with the predicted pattern. Steps may be included.

  For example, when searching for the optimal shift frequency of the target scan section, the output pattern for the target scan section shifted out of the scan path affects the bit value of the input pattern shifted in immediately after the target scan section. May give. In another example, when searching or determining the optimum shift frequency of the target scan section, the output pattern for the scan pattern including the target scan section shifted out of the scan path is located immediately after the scan pattern including the target scan section. This may affect the bit value of the scan pattern shifted in.

(If the later pattern can affect the target scan section trying to find the optimal shift frequency)
When the output pattern of the scan path for the scan pattern including the target scan section or the target scan section is shifted out, the input pattern that is shifted in and positioned later affects the bit value of the output pattern of the target scan section There is.

(Consideration of shift frequency of later input pattern)
In order to reduce or eliminate the influence of the input pattern (or scan pattern), the input that is positioned and shifted in immediately after the output pattern of the scan path for the target scan section or the scan pattern including the target scan section is shifted out As the shift frequency of the pattern (or scan pattern), a shift frequency that can normally shift the input pattern (or scan pattern) that is positioned after the target scan section and is shifted in to the scan path can be used.

(Considering shift frequency of input pattern before or after)
When searching or determining the optimum shift frequency of the target scan section, the same or different shift frequency as the target scan section is used as the shift frequency of the input pattern (or part of the input pattern) located before or after the target scan section. Can be used. In this case, in at least one embodiment of the present invention, a shift frequency is used that allows the input pattern located before or after the target scan section to be normally shifted to the scan path.

  This is because the input pattern located before or after the target scan section to search for the currently available maximum shift frequency may constrain the maximum available shift frequency of the target scan section as described above. is there. For example, the maximum usable shift frequency of the input pattern located before or after the target scan section may be lower than the maximum usable shift frequency of the target scan section.

  18 to 20 are schematic diagrams illustrating an example of the configuration of a scan pattern, a scan section, and shift frequency information necessary for obtaining an optimum shift frequency according to at least one embodiment of the present invention.

  As shown in FIG. 18, a scan section is a scan pattern in which a usable shift frequency or an optimum shift frequency at which a chip can be normally tested is searched. Each scan pattern N + 1, scan pattern N + 2, and scan pattern N + 3 of the test data (1800) is a scan section to search for a usable shift frequency or an optimum shift frequency. FIG. 18 shows the configuration of the scan pattern, the scan section, and the shift frequency information necessary for searching or determining the usable shift frequency or the optimum shift frequency of each of the scan pattern N + 1, the scan pattern N + 2, and the scan pattern N + 3. Show.

  In at least one embodiment of the present invention, in FIG. 18, T1, T2, T3, and Target_T represent information related to a scan shift frequency or a scan shift frequency period. For convenience of explanation, a timing identifier (Timing Identifier) is used. Also referred to as timing set or timing information.

  In at least one embodiment of the present invention, the timing information is information related to the shift frequency or the period of the shift frequency, and may include or represent the shift frequency or the period of the shift frequency. Timing information can be used to identify or control a scan pattern or a scan section. For example, the test apparatus can increase or decrease the shift frequency or the shift frequency period of the scan pattern or scan section identified by the timing information.

  In FIG. 18, T <b> 1 represents information related to the shift frequency or the period of the shift frequency with respect to the scan pattern N and is timing information of the scan pattern N. In FIG. 18, Target_T for the scan pattern N + 1 represents information related to the shift frequency or the period of the scan shift frequency for the scan pattern N + 1 that is a scan section to search for an available shift frequency or an optimal shift frequency. N + 1 timing information. That is, in FIG. 18, T1, T2, and T3 are timing information of a scan pattern located before a scan section for which an optimum shift frequency is to be searched, and Target_T is timing information of a scan section that is a shift frequency optimization target. It is.

  In FIG. 18, at least two of Target_T, T1, T2, and T3 may be the same or different from each other, or different shift frequencies or periods of shift frequencies may be used.

  In FIG. 18, the shift frequency or the shift frequency period information of T1, T2, or T3 is the shift frequency or shift frequency that allows the scan pattern or scan section corresponding to T1, T2, or T3 to be normally input to the scan path. Is used. At this time, the shift frequency corresponding to Target_T or the cycle of the shift frequency may be increased or decreased in order to search for an optimum value. Furthermore, without being limited to the example shown in FIG. 18, one or more shift frequencies, shift frequency periods, or timing information may be assigned to or used for one scan pattern.

  In at least one embodiment of the present invention, the search data (1810, 1820, 1830) used to search for a usable shift frequency or an optimal shift frequency of a scan section is at least as shown in FIG. More than one scan pattern can be included.

  The search data (1810) for searching for the usable shift frequency or the optimum shift frequency of the scan pattern N + 1 includes at least the scan pattern N that precedes the scan pattern N + 1. For example, the scan section or scan pattern included in the search data (1810, 1820, 1830) is repeatedly input to the scan path to search for a shift frequency that can be used in the specific scan section or an optimum shift frequency. Also good.

  At this time, the test normality or test failure for each scan pattern is determined based on the scan test output pattern of the chip using at least two or more scan patterns included in the search data (1810, 1820, 1830). For example, the output pattern and the predicted pattern can be compared. The prediction pattern is included and managed in the search data (1810, 1820, 1830). In other words, the search data (1810, 1820, 1830) can include both the respective prediction patterns corresponding to the respective output patterns for the scan pattern N + 1 and the scan pattern N positioned in front thereof. Then, the usable shift frequency or the optimum shift frequency of the scan section can be searched based on the test normality or test failure information. For example, the usable shift frequency or the optimum shift frequency of the scan pattern N + 1 corresponding to Target_T can be searched.

  In order to search for a usable shift frequency or an optimum shift frequency of the scan pattern N + 1, a scan test is performed using the scan pattern N + 1 and the scan pattern N positioned in front of it. At this time, the test normality or test failure can be determined based on the chip scan test output patterns for the two scan patterns N + 1 and N, respectively. Then, the usable shift frequency or the optimum shift frequency for the scan pattern N + 1 can be searched. The shift frequency at which the scan test result using the scan pattern N + 1 and the scan pattern N positioned before the scan pattern N + 1 is normal is a shift frequency that can be used for the scan pattern N + 1.

  As shown in FIG. 19, the scan section to be searched for the usable shift frequency or the optimum shift frequency is a scan pattern. In order to search for the optimum shift frequency for the scan section, at least three or more scan patterns including scan patterns located before and after the target scan section are used.

  For example, the search data (1910, 1920, 1930) used for searching the usable shift frequency or the optimum shift frequency of the scan section includes at least three or more scan patterns as shown in FIG. A scan pattern or a scan section of search data (1910, 1920, 1930) used to search for an available shift frequency or an optimal shift frequency may be repeatedly input to the scan path. At this time, whether the IC chip test is normal or unsuccessful is determined based on the comparison between the output pattern of the scan pattern included in the search data (1910, 1920, 1930) and the predicted pattern. Then, it is possible to search for a usable shift frequency of a scan section to search for an optimal shift frequency based on whether the test is normal.

  In order to search the search data (1910) for the usable shift frequency or the optimum shift frequency of the scan pattern N + 1, a chip test is performed using the scan pattern N + 1 and the scan pattern N positioned in front of it. At this time, the shift frequency when the test result is normal is a usable shift frequency of the scan pattern N + 1. At this time, the scan pattern N + 2 positioned after the scan pattern N + 1 uses the shift frequency that is normally shifted to the scan path, so that the chip test using the scan pattern N + 2 can be omitted. The shift frequency when the chip test result by the scan pattern N + 2 is also normal can be determined as the usable shift frequency of the scan pattern N + 2.

  As shown in FIG. 19, at least two or more of the timing information Target_T, T1, T2, T3, T4, T5, and T6 may be the same or different shift frequencies or periods of shift frequencies. The period of the shift frequency is the time interval of the shift operation when the scan pattern shifts at the shift frequency, and is the reciprocal of the shift frequency. In at least one embodiment of the present invention, the shift information of the timing information T1, T2, T3, T4, T5, or T6 or the period information of the shift frequency corresponds to T1, T2, T3, T4, T5, or T6. A shift frequency or a period of the shift frequency is used so that the scan pattern or the scan section is normally input to the scan path. At this time, the shift frequency corresponding to Target_T or the cycle of the shift frequency may be increased or decreased in order to search for an optimum value.

  Furthermore, the present invention is not limited to the example shown in FIG. 19, and one or more shift frequencies, shift frequency periods, or timing information may be used in various ways in one scan pattern.

  As shown in FIG. 20, this is a case where the scan section to be searched for the usable shift frequency or the optimum shift frequency is a part of the scan pattern. That is, the scan sections A, A + 1, and A + 2 of the scan pattern N + 1 are scan sections that are to be searched for the optimum shift frequency.

  The timing information T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 may be a scan pattern located before or after a scan section to search for an available shift frequency or an optimal shift frequency or This is the timing information of the scan section. Target_T is timing information of a scan section that is a shift frequency optimization target.

  At least two or more of Target_T, T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 can use the same or different shift frequencies or shift frequency periods.

  In at least one embodiment of the present invention, the shift frequency of T1, T2, T3, T4, T5, T6, T7, T8, T9, or T10 or the period information of the shift frequency includes T1, T2, T3, T4, A shift frequency or a period of the shift frequency is used so that a scan pattern or a scan section corresponding to T5, T6, T7, T8, T9, or T10 is normally input to the scan path. At this time, the shift frequency or the shift frequency period corresponding to Target_T is increased or decreased in order to search for a test normal value or an optimum value. Furthermore, the present invention is not limited to the example shown in FIG. 20, and one or more shift frequencies, shift frequency periods, or timing information are used in various ways in one scan pattern.

  FIG. 20 shows an example of search data (2010, 2020, 2030) for searching for an optimum shift frequency for a certain scan section shorter than the scan pattern or the scan path length. The scan patterns included in the search data (2010, 2020, 2030) may be composed of at least two or more scan patterns as shown in FIG. 18 or at least three or more scan patterns as shown in FIG. When the search data (2010, 2020, 2030) is composed of three scan patterns, the output pattern of the scan path for at least three or more scan patterns is compared with the predicted pattern.

  As shown in the example with reference to FIGS. 18 to 20, the scan pattern or the scan section included in the search data for searching the usable shift frequency or the optimum shift frequency of the scan section is repeated in the scan path. It may be entered.

  Furthermore, the timing information for at least two or more scan patterns or scan sections included in the search data is the same or different from each other, without being limited to the examples shown in FIGS.

  The search data used to search for the optimum shift frequency of the scan section can be configured to include at least two or more scan patterns, as shown in FIG. In at least one embodiment of the present invention, the search data may include information related to the timing information shown in FIG. The timing information can be used to control the timing at which the test device inputs the scan pattern or scan section into the scan path. The timing is a shift frequency or a period of the shift frequency. In another example, as shown in FIGS. 18 to 20, each search data used for searching for the optimum shift frequency for the adjacent scan sections may include scan patterns that overlap each other.

  In at least one embodiment of the present invention, the process of creating search data used to search for the optimum shift frequency of each of a large number of scan sections may be processed collectively using a computer program or software. May be efficient.

  For example, as shown in FIGS. 18-20, the task of constructing or dividing the scan pattern, scan section, and timing information or data associated with the shift frequency used to find the optimal shift frequency for each scan section is Can be processed in a batch using a computer program or software. Furthermore, information such as the number of scan sections to be optimized in such an operation, the bit length of the scan section, and the position of the scan section can be used.

  Further, the search data used to search for a usable shift frequency or an optimum shift frequency of a specific scan section may include a prediction pattern. Further, the search data used to search for the usable shift frequency or the optimum shift frequency of a specific scan section includes the IC chip main input (Primary Input) test data or the main data used together during the scan test. Output (Primary Output) prediction data may also be included.

  21 to 28 are schematic diagrams illustrating an example of a method for generating search data according to at least one embodiment of the present invention. Of these, FIGS. 21 to 23 relate to a method of generating search data when the scan section is a scan pattern, and FIGS. 24 to 26 illustrate a method of generating search data when the scan section is a part of the scan pattern. About.

  FIG. 21 is a schematic diagram illustrating an example of test data including a plurality of scan patterns.

  As shown in FIG. 21, a single shift frequency (for example, T1 = 50 ns (20 MHz)) is given to all the scan patterns in the test data (2100). Accordingly, all scan patterns are shifted in and out at the same shift frequency in the scan path of the IC chip.

  The test data (2100) can be composed of a plurality of subtest data including an input scan pattern and a prediction pattern in pairs. For example, the 51st input scan pattern is paired with the predicted pattern of the 50th input scan pattern. The test data can be created in a format such as STIL (Standard Test Interface Language) or WGL (Waveform Generation Language).

  The doncare prediction pattern of the first subtest data means that when the first input scan pattern is shifted into the scan path, the output pattern shifted out is not compared with a specific prediction pattern. The output pattern shifted out when the first input scan pattern is input after the flip-flop is set or reset to a specific value may not be a doncare prediction pattern.

  FIG. 22 is a schematic diagram illustrating an example of a method for generating search data for searching for an optimum shift frequency for each scan section when the scan section is a scan pattern.

  As shown in FIG. 22, timing information Target_T is given to the target scan section (2210) to search for the optimum shift frequency in the original test data (2100) of FIG. The timing information Target_T is used to identify the target scan section (2210) or to control the shift frequency of the target scan section. For example, Target_T is 50 ns in the initial state, and may be increased or decreased by the test apparatus.

  When the target scan section (2210) is the input scan pattern 51, the search data (2200) given Target_T is repeatedly input to the chip in order to search for the usable shift frequency or the optimum shift frequency of the input scan pattern 51. To do. Every time the input is repeated, the period of the shift frequency of the target scan section (2210) corresponding to Target_T is changed. At this time, the period of the shift frequency of the input scan pattern excluding the target scan section (2210) is the period of the shift frequency (for example, T1 = 50 ns) at which the scan pattern can be normally input to the scan path.

  For example, the search data (2200) is repeatedly input to the chip while the period of the shift frequency corresponding to Target_T is reduced until the maximum usable shift frequency of the target scan section (2210) is searched. At this time, the output pattern for the input scan pattern 50 is compared with the predicted pattern for the input scan pattern 50 included in the subtest data 51. Further, the output pattern for the input scan pattern 51 is compared with the predicted pattern for the input scan pattern 51 included in the subtest data 52. If both the test results of the input scan pattern 50 and the input scan pattern 51 are normal, the shift frequency is a usable shift frequency of the target scan section (2210).

  As the size of the search data (2200) used for searching for the usable shift frequency or the optimum shift frequency of the target scan section (2210) is smaller, the time required for searching for the optimum shift frequency can be shortened. .

  FIG. 23 is a schematic diagram illustrating an example of a search data generation method for shortening the time taken to search for the optimum shift frequency.

  As shown in FIG. 23, the search data (2300) for searching for the usable shift frequency or the optimum shift frequency of the input scan pattern 51 which is the target scan section (2310) is the target scan section (2310). It includes input scan patterns 50 and 52 located before and after that. The prediction pattern included in the subtest data 50 located before the target scan section (2310) is a doncare prediction pattern. That is, when the input scan pattern 50 is shifted into the scan path, the output pattern that is shifted out is not compared with a specific prediction pattern.

  The search data (2300) is repeatedly input to the scan path of the chip while changing the cycle of the shift frequency corresponding to Target_T until the maximum usable shift frequency of the target scan section (2310) is searched. A test result using the input scan pattern 50 is compared with a predicted pattern for the input scan pattern 50 included in the subtest data 51. Further, a test result using the input scan pattern 51 is compared with a predicted pattern for the input scan pattern 51 included in the sub test data 52. If both the test results of the input scan pattern 50 and the input scan pattern 51 are normal, the shift frequency is a usable shift frequency of the target scan section (2310).

  The search data (2300) is not limited to the example shown in FIG. 23, and may include two or more input scan patterns positioned before or after the target scan section.

  FIG. 24 is a schematic diagram illustrating an example of test data including a plurality of scan patterns. 25 to 28 are schematic diagrams illustrating an example of a method for generating search data for searching for an optimum shift frequency when the scan section is a part of a scan pattern.

  As shown in FIG. 24, a single shift frequency (for example, T1 = 50 ns (20 MHz)) is given to all the scan patterns in the test data (2400). Accordingly, all scan patterns are shifted in or out at the same shift frequency in the scan path of the IC chip.

  The test data (2400) can be composed of a plurality of subtest data including an input scan pattern and a prediction pattern in pairs. For example, the 51st input scan pattern is paired with the predicted pattern of the 50th input scan pattern.

  The test data (2400) can be divided into a plurality of scan sections. In this embodiment, for convenience of explanation, when the input scan pattern 51 is divided into three scan sections (2410, 2420, 2430), a method for generating search data for searching for the optimum shift frequency of each scan section. Will be described with reference to FIGS.

  As shown in FIGS. 25 to 27, the search data (2500, 2600, 2700) includes an input scan pattern 51 including a target scan section (2510, 2610, 2710) and input scan patterns 50, 52 positioned before and after the input scan pattern. Including. The prediction pattern included in the subtest data 50 is a doncare prediction pattern. That is, the output pattern that is shifted out when the input scan pattern 50 is shifted into the scan path is not compared with a specific prediction pattern. Timing information Target_T is used to identify the target scan section (2510, 2610, 2710) or to control the shift frequency of the target scan section. For example, Target_T is an initial 50 ns, and may be increased or decreased by a test apparatus.

  As shown in FIG. 25, the search data (2500) gives Target_T timing information to the first target scan section (2510) which is a part of the input scan pattern 51, and the rest of the input scan pattern 51 has T1. Keep timing information as is. The search data (2500) is repeatedly input to the scan path of the chip while changing the cycle of the shift frequency corresponding to Target_T until the maximum usable shift frequency of the first target scan section (2510) is searched. A test result using the input scan pattern 50 is compared with a predicted pattern for the input scan pattern 50 included in the subtest data 51. Further, a test result using the input scan pattern 51 is compared with a predicted pattern for the input scan pattern 51 included in the sub test data 52. If both the test results using the input scan pattern 50 and the input scan pattern 51 are normal, the shift frequency is a usable shift frequency of the first target scan section.

  When searching for the optimum shift frequency of the second target scan section (2610) and the third target scan section (2710), the search data (2600, 2700) of FIGS. Repeat the scan to scan test.

  When one scan pattern is divided into a plurality of scan sections, search data for each scan section (2500, 2600, 2700) is used as shown in FIGS. 25 to 27 in order to search for the optimum shift frequency of each scan section. Without creation, one search data (2800) can be created as shown in FIG.

  As shown in FIG. 28, the search data (2800) includes timing information Target_T1, Target_T2, and Target_T3 in the first to third target scan sections (2810, 2820, 2830). That is, as many timing identifiers as the number of target scan sections to be searched for available shift frequencies or optimum shift frequencies at the same time are created and assigned to each target scan section (2810, 2820, 2830). For example, when a usable shift frequency or an optimal shift frequency of the first target scan section (2810) is searched, the shift frequency corresponding to Target_T1 can be increased or decreased.

  As shown in FIG. 28, when one search data (2800) for a plurality of target scan sections is generated, the storage capacity of the recording medium can be saved as compared to generating search data for each target scan section. Can do. However, there may be restrictions on the number of timing identifiers or shift frequencies that can be used by the test apparatus.

  For example, if the number of timing identifiers that can be used in the test apparatus is limited to three and the scan pattern is divided into four target scan sections, search for each target scan section as shown in FIGS. Data (2500, 2600, 2700) may be created to search for the optimum shift frequency.

  The search data (2500, 2600, 2700, 2800) is not limited to FIGS. 25 to 28, and includes two or more input scan patterns positioned before or after the input scan pattern including the target scan section. Can do.

  The time required to search for the shift frequency can be shortened as the size of the search data used for searching for the usable shift frequency or the optimum shift frequency of the scan pattern or the scan section is as small as possible. For example, as the number of scan patterns or scan sections is reduced, the time required to search for a usable shift frequency or an optimal shift frequency can be shortened.

In order to calculate the total number of shift clock cycles required to search for the optimum shift frequency for all scan patterns of test data, SN, BL, and FN are defined as follows.
SN: the number of scan patterns constituting the test data.
BL: One scan clock cycle is used to shift one bit with the bit length of one scan pattern.
FN: The number of times the shift frequency is increased to search for the optimum shift frequency per scan pattern. It sequentially increases at a predetermined interval from a preset low shift frequency to a preset high shift frequency.

  In at least one embodiment of the present invention, SN = 5,000, BL = 1,000, and FN = 20. For the following method 1 and method 2, the total number of shift clock cycles required to search for the optimum shift frequency for all scan patterns of test data is as follows.

Method 1
As shown in FIG. 22, the total number of shift clock cycles required when searching for the optimum shift frequency of each scan pattern using search data including all input scan patterns is as follows.
Total time required = SNxSNxBLxFN = 500,000,000,000 Shift Clock Cycles
Total time required = SNxSNxBLxFN = 500,000,000 Shift Clock Cycles

Method 2
As shown in FIG. 23, the total number of shift clock cycles required when searching for the optimum shift frequency of each scan pattern using search data including three input scan patterns is as follows (at this time, one The search data including the first and second input scan patterns is used when searching for the optimum shift frequency of the first scan pattern, and when searching for the optimum shift frequency of the last scan pattern. Search data including two input scan patterns of the last input scan pattern and the previous input scan pattern is used).
Total time required = (3 × (SN−2) × BLxFN) + (2 × 2 × BLxFN) = 299, 960,000 Shift Clock Cycles

  In the above equation, (3x (SN-2) xBLxFN) is the optimum scan pattern excluding two scan patterns in the scan pattern set (ie, the first scan pattern input to the chip and the last scan pattern input). This is the total number of shift clock cycles used to retrieve the correct shift frequency.

  In the above equation, (2 × 2 × BL × FN) is the total number of shift clock cycles used to search for the optimum shift frequency of the scan pattern first input to the chip and the scan pattern input last.

  Using Method 2, it can be seen that 99.94% of the total number of shift clock cycles used in Method 1 has been reduced.

  Therefore, the search data used to search for the usable shift frequency or the optimum shift frequency of the scan pattern or scan section should include as few scan patterns or scan sections as possible.

  In at least one embodiment of the present invention, as exemplified with reference to FIG. 18, the search data includes a scan section to be searched for a shift frequency or an optimal shift frequency and a scan pattern located before or after the scan section. Can be composed of at least two or more scan patterns.

  Further, as shown in FIGS. 19 to 28, the search data is composed of at least three scan patterns including a scan section to be searched for the shift frequency or the optimum shift frequency and scan patterns positioned before and after the scan section. Can do.

  In at least one embodiment of the present invention, the search data used to search for the usable shift frequency or the optimal shift frequency of the scan section is stored in a computer-readable recording medium in the form of a data code or a file. It may be stored.

  Furthermore, the process of creating the search data used to search for the usable shift frequency or the optimum shift frequency of the scan section can be performed by the same apparatus or different apparatuses depending on the embodiment, such as a test apparatus or a computer. You can go there.

  FIG. 29 is a flowchart illustrating an example of a method for minimizing chip test time according to at least one embodiment of the present invention.

  As shown in FIG. 29, an apparatus for minimizing scan test time divides a bit pattern or one or more scan patterns into at least two scan sections (step S2900). Examples of dividing the test data bit pattern or scan pattern set into scan sections are shown in FIGS.

  In the process of dividing, the process of creating search data or a file containing these data for scan sections or section groups obtained by dividing thousands or tens of thousands of scan patterns for testing an IC chip is a computer program or software It may be efficient to process collectively using

  For example, the computer program or software scans the test data using information related to the division of the scan section, such as the number of scan sections trying to optimize the shift frequency, the bit length of the scan section, the position of the scan section, etc. It is possible to divide the data into scan section groups and search data for the divided scan sections or scan section groups, or a file including the search data.

  Information related to scan section division is obtained via user interface devices such as keyboards, mice, and voice recognition devices, information data codes and files containing information related to scan section division, or data communication networks. Used by computer programs or software.

  As an example of dividing the scan pattern, the method shown in FIGS. 5 to 10 can be used. The apparatus that minimizes the scan test time assigns a plurality of shift frequencies to each scan section (step S2910). Here, the shift frequency assigned to each scan section is equal to or lower than the shift frequency before the output pattern of the scan path is different from the predicted pattern. The division of the scan pattern into scan sections (step S2900) and the assignment of the shift frequency to the scan section (step S2910) may be performed by the same apparatus or different apparatuses depending on the embodiment, or may be performed by an apparatus such as a test apparatus or a computer. You can go.

  That is, the apparatus for minimizing the scan test time can search the shift frequency immediately before the output pattern and the prediction pattern different from the increase in the shift frequency as the maximum shift frequency that can be assigned to the scan section. In another example, an apparatus for minimizing scan test time searches for a shift frequency when an output pattern and a prediction pattern become the same from different states due to a decrease in shift frequency as a maximum shift frequency that can be assigned to the scan section. be able to. For example, while increasing or decreasing the shift frequency of the scan section, it is possible to detect the shift frequency where the test result is normal, close to the boundary between normal and failure of the scan test, and assign the shift frequency where the test result is normal to the scan section The maximum shift frequency is determined.

  FIG. 30 is a flowchart illustrating an example of a method for determining an optimal shift frequency for each scan section in order to minimize the time for chip test according to at least one embodiment of the present invention.

  As shown in FIG. 30, the apparatus for minimizing scan test time divides one or more scan patterns into at least two scan sections (step S3000).

  The device that minimizes the scan test time, the shift frequency until the output pattern changes from the same state to the predicted pattern, or from the different state to the same while increasing or decreasing the frequency at which the scan section is shifted into the scan path Is searched (step S3010). For example, as a chip used for searching for an optimum shift frequency, a chip that has been inspected as a good product in advance can be used. For example, the optimum shift frequency is searched according to the present embodiment using a non-defective chip whose test result is normal when the scan test is performed using the nominal shift frequency. This is the same in the other embodiments described below.

  Then, the apparatus that minimizes the scan test time determines the shift frequency that is normal for the test before the time when the output pattern and the predicted pattern change from the same state to a different state as the shift frequency of the scan section (step S3020). The previous shift frequency includes a shift frequency that is lower than the shift frequency at the time of entering a different state.

  For example, when the output pattern and the prediction pattern are the same at the first shift frequency, but the output pattern and the prediction pattern of the scan path are different at the second shift frequency obtained by raising the first shift frequency by a predetermined frequency, the scan test time The apparatus that minimizes the second shift frequency is lower than the second shift frequency and provides information for determining whether the test normal shift frequency is determined as the shift frequency of the scan section.

  The frequency unit to be increased or decreased to search for the optimum shift frequency is set in advance in the test apparatus, or the unit may be changed or set by the user.

  In this embodiment, for convenience of explanation, a method for searching for an optimal shift frequency for each scan section through increase / decrease in the shift frequency to be shifted in is described. It is also possible to search for a shift frequency. This also applies to the following embodiments.

  The steps described with reference to FIG. 30 are not all executed by the apparatus that minimizes the scan test time in some embodiments, and at least a part of the steps may be executed by another apparatus such as a computer.

  FIG. 31 is a flowchart showing an example of a more specific process of the method for minimizing the chip test time according to at least one embodiment of the present invention.

  As shown in FIG. 31, the apparatus for minimizing the scan test time divides one or more scan patterns into a plurality of scan sections (step S3100).

  The apparatus for minimizing the scan test time selects one scan section for which the shift frequency is not determined by the present embodiment from among the divided scan sections (step S3110). For example, if a predetermined order is determined between scan patterns for a scan test, an apparatus that minimizes the scan test time can be sequentially selected from the first scan section. Alternatively, an apparatus for selecting a scan section for which the user wants to optimize the shift frequency and minimizing the scan test time can optimize the shift frequency for the selected scan section. In addition, various methods can be used to select the scan section for which the shift frequency is to be optimized.

  The apparatus that minimizes the scan test time increases the shift frequency (step S3120). For example, the nominal shift frequency can be set as the initial shift frequency in a device that minimizes the scan test time.

  The apparatus that minimizes the scan test time starts from an initial shift frequency at which the scan test result is normal, and determines whether or not the scan section can be normally shifted into the scan path with the increased shift frequency (step S3130). An example of a specific method for determining whether or not the selected shift frequency search target scan section can be normally shifted in at the current shift frequency will be described with reference to FIG.

  If normal shift-in of the scan section is possible (step S3140), the apparatus for minimizing the scan test time raises the shift frequency again (step S3120) and determines whether normal shift-in is possible. Repeat (step S3130).

  If the normal shift-in of the scan section is impossible due to the increase of the shift frequency (step S3140), the apparatus for minimizing the scan test time has the scan section below the maximum shift frequency at which the normal shift-in was possible. Or the information for determination is stored in a computer-readable recording medium (step S3150). Then, the above steps are repeated until the shift frequency for all the scan sections is determined or information for determining the shift frequency is stored in a computer-readable recording medium (step S3160). Here, the information stored in the recording medium includes information on the shift with respect to each shift frequency or test normality or failure with respect to the test target IC chip.

  The apparatus that minimizes the scan test time groups the scan sections into section groups as necessary (step S3170). For example, if the test device that actually performs the scan test has restrictions such as the maximum number of shift frequency changes that can be supported during the scan test, the maximum number of shift frequencies, and the delay time required to change the shift frequency, scan A device that minimizes test time groups the scan sections so that the number of scan sections satisfies this restriction. At this time, it may be considered that the total time required for the scan test is minimized. In this case, the lower than the lowest shift frequency among the optimum shift frequencies of at least two or more scan sections included in one scan section group can be determined as the shift frequency of the section group. The step of grouping sections (step S3170) may be omitted depending on the embodiment.

  For example, if the number of changes in the maximum shift frequency that can be supported by the test device is 5, the device that minimizes the scan test time divides the scan section into 5 or less section groups when the number of current scan sections exceeds 5. Then, the lower than the lowest optimum shift frequency among the optimum shift frequencies of the sections in each section group is determined as the shift frequency of the section group. Methods for grouping into section groups include various methods that minimize the total time taken for scan tests that do not group scan sections having the same or similar optimal shift frequency.

  In the embodiment described above, the optimum shift frequency is searched mainly considering the increase of the shift frequency. In another example, the optimum shift frequency of the scan section can be searched while decreasing the shift frequency.

  For example, an apparatus that minimizes the scan test time starts with an initial shift frequency that is a test failure, and determines whether or not the scan section can be normally shifted into the scan path at a shift frequency that is decreased by a predetermined unit. When the normal shift-in of the scan section is obtained by reducing the shift frequency, the apparatus that minimizes the scan test time determines the shift frequency of the scan section to be equal to or lower than the maximum shift frequency at which the normal shift-in is obtained, or Information for determination is stored in a computer-readable recording medium.

  In yet another example, the chip is also affected by the supply voltage, the ambient temperature, and the like, so that the optimum shift frequency can be searched by reflecting such environmental conditions. That is, the apparatus that minimizes the scan test time can perform the process of searching for the optimum shift frequency while changing the conditions such as the supply voltage and the external temperature.

  For example, the apparatus for minimizing the scan test time can increase or decrease the voltage supplied to the chip in consideration of the specifications of the chip or quality-related policies such as QA (Quality Assurance) and QC (Quality Control). S3120). The apparatus for minimizing the scan test time searches for the optimum shift frequency for each scan section according to at least one embodiment of the present invention at each increased or decreased supply voltage. If there are a plurality of optimum shift frequencies searched for by supply voltages of the scan section, the apparatus for minimizing the scan test time determines a shift frequency of the selected scan section that is equal to or lower than the lowest optimum shift frequency (step). S3150). In addition, the process of searching for the optimum shift frequency according to temperature increase / decrease and various conditions can be repeated, and the lowest optimum shift frequency or less can be determined as the shift frequency of the scan section.

  Here, grasping the characteristics such as the operating frequency range of the IC chip while changing the supply voltage or the ambient temperature of the IC chip is generally referred to as electrical characteristic testing or shimming. Creating a table for characteristic information through electrical characteristic testing or shimming is called “Shmoo Plotting”. The created table is referred to as a shim plot.

  Each process of FIG. 31 may be performed not only by the apparatus that minimizes the scan test time but also by other apparatuses such as a computer.

  FIG. 32 is a flowchart showing an example of specific steps for grasping normal shift-in by the method for minimizing the chip test time according to at least one embodiment of the present invention. That is, FIG. 32 corresponds to step S3130 in FIG. 31, but is not limited to the specific step in FIG. 31, and includes a step of determining or determining whether shift-in is normally performed in the scan path. It can be applied to various embodiments including.

  As shown in FIGS. 12 and 32, the apparatus for minimizing the scan test time has an input pattern K-1 (1202) located before the target scan section K (1204) to determine the currently selected shift frequency. Are shifted into the scan path (1210) (step S3200). For example, the input pattern K-1 (1202) is located in front of the scan pattern M including the target scan section K (1204), and examples of (1) or (2) can be given as follows.

(1) When the input pattern K-1 (1202) is a scan pattern that is actually used for the scan test The apparatus for minimizing the scan test time shifts the scan pattern M-1 to the scan path and scan captures it I do. In this case, there is an advantage that an actual scan test operation can be reflected. Here, the scan pattern M-1 is a pattern positioned before the scan pattern M including the target scan section K.

(2) In the case where the scan pattern M-1 is an output pattern predicted as a scan test result using the scan pattern M-1 that is actually used for the scan test, the apparatus that minimizes the scan test time is the scan pattern M-1. There is no need to perform a separate scan capture process after shifting to the scan path. Therefore, in this case, the time required for the clock for scan capture can be reduced, and as a result, the time required for searching for the optimum shift frequency can be shortened.

  The apparatus for minimizing the scan test time performs the scan capture operation after shifting the input pattern K-1 (1202) to the scan path (step S3200). In other embodiments, the scan capture operation is not performed. Next, the apparatus for minimizing the scan test time shifts the target scan section K (1204) into the scan path with the increased / decreased shift frequency (step S3210). When the target scan section K (1204) is a part of the scan pattern M as shown in FIG. 14, the scan pattern M including the target scan section K (1204) is shifted into the scan path.

  At this time, the scan pattern M including the target scan section K (1204) or the target scan section K (1204) is shifted into the scan path, and the bit patterns stored on the scan path are simultaneously shifted out (step S3210). ). Here, the bit pattern to be shifted out is not limited to this example, and can take various forms depending on the type of scan circuit in which the shift-in and shift-out operations are simultaneously performed on the scan path.

  For example, when the target scan section K (1204) is a part of the scan pattern M and shorter than the length of the scan path as shown in FIG. 14, the scan pattern M including the target scan section K (1204) is shifted into the scan path. . At this time, the shift frequency of the portion of the scan pattern M excluding the target scan section K (1204) does not impose restrictions on searching for the optimum shift frequency of the target scan section K (1204). Therefore, the shift frequency of the portion excluding the target scan section K (1204) in the scan pattern M is not increased or decreased together with the shift frequency of the target scan section K (1204), or is different from the target scan section K (1204). Use frequency. Alternatively, the shift frequency of the part excluding the target scan section K (1204) in the scan pattern M is a shift frequency that allows the part excluding the target scan section K (1204) to be input to the scan path.

  In at least one embodiment of the present invention, the shift frequency of the portion excluding the target scan section K (1204) is not more than the nominal shift frequency or the optimum shift frequency is already determined by the method according to at least one embodiment of the present invention. In such a case, a preset shift frequency can be used so as to be equal to or lower than the optimum shift frequency. The preset shift frequency can be changed according to the embodiment, such as a value obtained by adjusting the nominal shift frequency, a value set in the apparatus by a program, or a value set by the user, and is not limited to the above example. .

  The apparatus that minimizes the scan test time compares the output pattern K-1 of the input pattern K-1 of the test target chip with the predicted pattern K-1 (step S3220). If the output pattern K-1 and the predicted pattern K-1 are not the same (step S3220), the apparatus that minimizes the scan test time normally shifts the target scan section K (1204) into the scan path at the current shift frequency. Judgment or determination is made that it is impossible (step S3270). For example, an apparatus that minimizes scan test time stores test failure information on a computer-readable recording medium.

  If the output pattern K-1 and the predicted pattern K-1 of the input pattern K-1 are the same (step S3220), the apparatus that minimizes the scan test time scans the target scan section K (1204) (step S3230). After performing the operation, the shift-out (step S3240) operation is performed. In another embodiment, the shift-out (step S3240) operation is performed without performing the scan capture (step S3230) operation. Furthermore, the bit pattern to be shifted out (step S3240) differs depending on the type of scan circuit that can simultaneously perform shift-in and shift-out operations on the scan path.

  When the output pattern for the target scan section K (1204) is shifted out (step S3240), the input pattern K + 1 (1206) that is simultaneously shifted in is shifted to the target scan section K (1204) that is shifted out (step S3240). A shift frequency that does not change the bit pattern unnecessarily is used. That is, a shift frequency at which the shift-out (step S3240) operation can be normally performed is used. Further, the input pattern K + 1 (1206) that is simultaneously shifted in when the shift-out (step S3240) operation of the target scan section K (1204) is performed uses a shift frequency that can be normally shifted into the scan path.

  The apparatus that minimizes the scan test time compares the output pattern K of the target scan section K (1204) of the test target chip with the predicted pattern K (step S3250). If the output pattern K of the target scan section K (1204) is not the same as the predicted pattern K (step S3250), the apparatus that minimizes the scan test time scans the target scan section K (1204) with the currently used shift frequency. Is determined or determined to be unable to shift in normally (step S3270). For example, an apparatus that minimizes scan test time stores test failure information on a computer-readable recording medium.

  If the output pattern K of the target scan pattern K (1204) and the predicted pattern K are the same (step S3250), the apparatus for minimizing the scan test time scans the target scan section K (1204) with the currently used shift frequency. Is determined or determined to be able to shift in normally (step S3260). For example, an apparatus that minimizes the scan test time stores test normal information on a computer-readable recording medium.

  In at least one embodiment of the present invention, not only the scan pattern including the target scan section K (1204) but also the output pattern of the chip corresponding to the scan pattern positioned before the target scan section K is compared with the corresponding predicted pattern. (1204) usable or optimal shift frequencies can be searched.

  In at least one embodiment of the present invention, the test apparatus determines or determines whether both the scan test results for the target scan section K (1204) and the input pattern K-1 (1202) positioned in front thereof are normal. . If both the tests are normal, the shift frequency used for the target scan section K (1204) is a shift frequency at which the target scan section K (1204) can be normally shifted in the scan path.

  FIG. 33 is a flowchart illustrating an example method for minimizing chip test time according to at least one embodiment of the invention.

  Depending on the type and state of the chip manufacturing process (Process), there may be a process variation between IC chips on different wafers or between IC chips on the same wafer. The power consumption will be greatly affected. In particular, the influence becomes larger in the fine process and the low power process.

  As shown in FIG. 33, the apparatus for minimizing the scan test time performs a process of determining an optimum frequency for each scan section as described above for a plurality of chips (step S3300). Here, the plurality of chips are IC chips on the same wafer or IC chips on different wafers, and chips that have been inspected as good products in advance.

  The device that minimizes the scan test time determines the optimum shift frequency of the scan section that is lower than or equal to the lowest shift frequency among a plurality of optimum shift frequencies searched with a plurality of IC chips for one scan section. Alternatively, information for determining the shift frequency is stored in a computer-readable recording medium (step S3310), and this is performed for each scan section. Here, the information stored in the recording medium includes information on a shift or test success (PASS) or failure (FAIL) for each shift frequency.

  For example, if the shift frequency of the target scan section K of the first chip is A and the shift frequency of the target scan section K of the second chip is B, when the shift frequency A is lower than the shift frequency B, the test apparatus A or lower is selected as the shift frequency, or information for selection is stored in a computer-readable recording medium.

  Each step in FIG. 33 can be performed not only by a device that minimizes a scan test time using a set of scan patterns and shift frequency information searched for a plurality of chips by scan section, but also by other devices such as a computer. it can.

  FIG. 34 is a block diagram showing the configuration of an apparatus for minimizing the test time of an IC chip according to at least one embodiment of the present invention.

  The apparatus for minimizing the scan test time shown in FIG. 34 can perform the method according to at least one embodiment of the present invention described above for optimizing the shift frequency of each scan section. In one embodiment, some or all of the methods shown in FIGS. 12-33 can be applied.

  As shown in FIG. 34, the apparatus for minimizing the scan test time includes a condition setting unit (3400), a pattern dividing unit (3405), a pattern input unit (3410), a pattern comparison unit (3420), and a frequency grasping unit ( Shift frequency search unit) (3430). The condition setting unit (3400) includes a frequency increasing / decreasing unit (3402), a supply voltage increasing / decreasing unit (3404), a temperature increasing / decreasing unit (3406), and the like.

  First, the condition setting unit (3400) sets various conditions for searching for an optimum shift frequency for each scan section. Specifically, the frequency increasing / decreasing unit (3402) increases / decreases the shift frequency, the supply voltage increasing / decreasing unit (3404) increases / decreases the voltage supplied to the chip, and the temperature increasing / decreasing unit (3406) increases / decreases the ambient temperature of the test environment. . The condition setting unit (3400) can set conditions such as supply voltage and ambient temperature, and can set the shift frequency. For example, the condition setting unit (3400) is provided in the host computer (200, 300), the tester body (210, 310), the test head (220, 320), the prober (350), or the like.

  The pattern dividing unit (3405) can divide one or more scan patterns into a plurality of scan sections. For example, the pattern dividing unit (3405) is provided in the host computer (200, 300), the tester body (210, 310), the test head (220, 320), the prober (350), or the like. The pattern dividing unit (3405) can divide the test data into at least one scan section using the method shown in FIGS.

  The pattern input unit (3410) shifts the scan section into the scan path of the test target chip under the conditions set by the condition setting unit (3400). Specifically, the pattern input unit (3410) sequentially shifts the scan pattern or the scan section located before and after the scan section to search for the optimum scan shift frequency into the scan path together with the shift frequency determination target scan section. Can be done. For example, the pattern input unit (3410) is provided in the host computer (200, 300), the tester body (210, 310), the test head (220, 320), the prober (350), or the like.

  The pattern comparison unit (3420) compares the test result of the scan section shifted into the test target chip by the pattern input unit (3410) and the output pattern shifted out with the predicted pattern. For example, the pattern comparison unit (3420) is provided in the host computer (200, 300), the tester body (210, 310), the test head (220, 320), the prober (350), or the like. There may be a time point or frequency at which the output pattern and the prediction pattern change from the same state to a different state or change from the different state to the same state by increasing or decreasing the shift frequency by the condition setting unit (3400).

  The frequency grasping unit (3430) calculates shift frequency information for searching for the previous shift frequency or the same shift frequency whose output pattern is different from the predicted pattern based on the comparison result information or comparison result by the pattern comparison unit (3420). Can be stored in a readable recording medium. For example, shift frequency information that can be normally used for the scan section is stored in a computer-readable recording medium. Furthermore, it is possible to determine the optimum shift frequency of the scan section using such information.

  In at least one embodiment of the present invention, the frequency grasping unit (3430) may determine that the output pattern for both the scan section and the target scan section at least before the target scan section for which the current shift frequency is to be determined is a predicted pattern. The shift frequency in the unified case is stored in a computer-readable recording medium as usable shift frequency information of the target scan section. Furthermore, in FIG. 34, each of two or more parts can be integrated into one module or subdivided. For example, the frequency grasping unit (2030) is provided in the host computer (200, 300), the tester body (210, 310), the test head (220, 320), the prober (350), or the like.

  The above-described apparatus for minimizing the scan test time can be realized in various forms using hardware or software. Further, all or part of the apparatus that minimizes the scan test time can be included in the test apparatus shown in FIGS. 2 and 3, or can be realized using a separate apparatus such as a computer.

  FIG. 35 is a schematic diagram illustrating an example of a method for searching or determining optimal shift frequencies of a plurality of scan sections in parallel according to at least one embodiment of the present invention.

  As shown in FIG. 35, the apparatus for minimizing the scan test time is optimized by searching or determining the optimum shift frequency of different scan sections for each of a plurality of IC chips in parallel. It is possible to reduce the time required for searching or determining a correct shift frequency.

  For example, the optimum shift frequency of different scan sections can be simultaneously searched or determined for each of the plurality of IC chips (3510, 3512, 3514, 3516) located on the test interface board (3500) of the test apparatus. . In at least one embodiment of the present invention, the optimum shift frequency of different scan sections can be searched or determined in parallel by a plurality of test devices or a plurality of test interface boards.

  When searching or determining the optimum shift frequency sequentially for the entire scan section, if h time is taken, if the shift frequency is searched or determined in parallel for n scan sections, the time required is about h / n time. Can be shortened. Accordingly, it is possible to obtain an effect of optimizing by dividing several thousand to several tens of thousands of scan patterns for testing an IC chip within the same time into shorter scan sections.

  FIG. 36 is a schematic diagram illustrating an example of a method for rearranging scan patterns in order to minimize the time for testing an IC chip according to at least one embodiment of the present invention.

  As shown in FIG. 36, the scan patterns on the set of scan patterns for the scan test have a predetermined order. However, the order of such scan patterns is not fixed, and a high shift frequency can be assigned to each scan section and rearranged to reduce the time required for the entire scan test. For example, as shown in FIG. 36, the order of the second scan pattern and the third scan pattern on the set of original scan patterns may be changed. This also changes the order of the predicted output scan pattern.

  When rearranging the order of the scan pattern shifted to the scan path, the scan shift may change the part of the circuit that is switched on the IC chip and the number of switching operations, which may also change the power consumption. Therefore, the shift frequency assigned to the scan pattern (or scan section) may increase. Therefore, after the rearrangement of the scan pattern using the above, the optimum shift frequency is searched or determined for each scan section using the above-described embodiment of the present invention, and the overall scan test time is further shortened. be able to.

  As a method of rearranging the scan pattern, the scan pattern on the original scan pattern set is arbitrarily rearranged one or more times, and the optimum shift frequency is grasped by the above-described embodiment for the rearranged scan pattern set. Thus, the scan pattern time can be determined as the scan pattern arrangement. In another embodiment, there are various methods such as arranging scan patterns having the smallest bit pattern difference between the scan patterns so as to be adjacent to each other.

  As another example of the rearrangement of the scan pattern, a method of searching for the optimum shift frequency described above while sequentially positioning the scan pattern whose order is not determined next to the Kth (K is an integer of 1 or more) scan pattern; It is possible to use the scan pattern having the highest shift frequency as the next pattern of the Kth scan pattern.

  Part or all of the operation of rearranging the scan pattern order can be performed by hardware and firmware or software such as a processor provided in the test apparatus, or can be performed by a separate apparatus such as a computer. .

  Furthermore, when it takes a lot of time to search for the optimal scan pattern arrangement, restrictions such as the maximum number of scan pattern rearrangements or the required time may be provided in order to search for the optimal scan pattern arrangement.

  In at least one embodiment of the present invention, the time required for stress test or burn-in test of an IC chip is shortened by using the optimum frequency of at least two or more test data, and the test quality is improved. Can do. In at least one embodiment of the present invention, the stress test or burn-in test time of the IC chip can be shortened and the quality of the test can be improved by using the optimum shift frequency for at least two scan patterns or scan sections. The optimal shift frequency for each scan pattern or scan section can be retrieved using a scan test time minimization method according to at least one embodiment of the present invention.

  Here, the stress test or the burn-in test is generally performed by operating the IC chip for a long time and applying stress to the IC chip or applying a high voltage and high temperature to the IC chip to accelerate aging. It is to test the quality of the IC chip or to find an early failure (Early-Life Failure) IC chip in advance. Usually, a burn-in test is performed for several tens of hours or more in a high temperature environment exceeding 100 ° C. Hereinafter, the stress test or the burn-in test is collectively referred to as a burn-in test. Further, a test apparatus capable of performing such a burn-in test is referred to as a burn-in test apparatus.

  IC chip aging is greatly affected by heat generation, and heat generation is greatly affected by power consumption of the IC chip.

  For example, Equation 2 represents an element that influences dynamic power consumption, which is power consumption when the circuit of the IC chip operates.

(Equation 2)
P = α × C × f × V _DD ²
α: Activity factor
C: Average Switched Capacitance (ateach cycle)
f: Circuit Frequency
V _DD : Supply Voltage

  In the scan mode of the IC chip, the circuit portion of the IC chip that is activated may differ depending on the bit pattern of the scan pattern. In general, in the scan mode of the IC chip, a switching operation occurs in a larger part of the circuit than in the function mode. Therefore, the capacitance value C that is average-switched as shown in Equation 2 in the scan mode increases, and the power consumption P can increase.

  Further, when the shift frequency is increased, the power consumption P of the IC chip can be increased in proportion to the operating frequency f of the IC chip circuit as shown in Equation 2.

  The increased switching operation of the IC chip further increases the power consumption of the IC chip and increases the heat generation temperature of the IC chip. Therefore, the aging of the IC chip is further accelerated.

  In at least one embodiment of the present invention, the burn-in test apparatus sets a maximum shift frequency that can be assigned to test data or each of the scan sections described above so that aging can be further accelerated during burn-in test and burn-in test time can be shortened. Can be used.

  For example, the burn-in test apparatus can use a scan pattern or a scan section to accelerate the burn-in test during the burn-in test of the IC chip. At this time, a scan test can be performed together.

  Furthermore, when a nominal shift frequency is used during the scan shift operation, high stress is applied to some of the circuit parts activated by the scan pattern, and relatively low stress is applied to the other part. There is. As an example, by dividing the scan pattern of the test data into scan sections and performing burn-in test using the maximum shift frequency that can be assigned to each divided scan section, can aging progress only at a specific part on the circuit? Or a relatively slow phenomenon can be reduced.

  For example, FIG. 41 shows the same scan shift operation when the shift frequency is not optimized for the scan pattern of the test data (4100) and when the scan pattern is divided into scan sections and the shift frequency is optimized (4110). The difference in heat generation of the IC chip is shown. That is, it can be seen that heat generation is generated in a more balanced manner when the scan section with the optimized shift frequency (4110) is used than when the test data without the optimized shift frequency (4100) is used. .

  That is, there is an effect that stress is applied in a balanced manner to the different parts of the IC chip activated by the bit pattern of the scan pattern, and the quality is improved in addition to the speed of the burn-in test. The maximum usable frequency of each scan section of the test data for testing the chip can be used to reduce burn-in test time and improve quality.

  37 and 38 are block diagrams showing the configuration of a burn-in test system according to at least one embodiment of the present invention.

  As shown in FIGS. 37 and 38, the burn-in test apparatus includes a host computer (3700, 3800), a tester body (3710, 3810), a test head (3720, 3820), an interface board (3730, 3830), a temperature control unit ( 3760, 3870), chamber (3750, 3860), and prober (3850).

  A device under test (DUT) located on an interface board for testing is an IC on a wafer or a packaged IC chip. If the DUT is an IC chip on the wafer, it further comprises a prober (3850).

  The tester body (3710, 3810) controls the scan test and the burn-in test as a whole. For example, the tester body (3710, 3810) has a setup for a DUT test, generation of an electrical signal for the DUT test, observation and measurement of a DUT test result signal, temperature control of the chamber via the temperature controller, etc. Control the overall process. The tester body (3710, 3810) can be realized by a computer including a central processing unit (CPU), a memory, a hard disk, a user interface, and the like, and is a device power supply device that supplies power to the DUT according to an embodiment. (Device Power Supply) may further be included. Further, the tester main body (3710, 3810) controls a signal processor (DSP: Digital Signal Processor) (not shown) and a test head for processing various digital signals, and applies signals to the DUT (3740, 3840). Dedicated hardware such as a controller and a signal generator, software, firmware, or the like can be included. The tester body (3710, 3810) is also called a mainframe or a server.

  The host computers (3700, 3800) are computers such as personal computers and workstations, and are devices that allow a user to execute a test program, control a test process, and analyze a test result. In general, the host computer (3700, 3800) includes a CPU, a storage device such as a memory or a hard disk, and a user interface, and is connected to the tester main body (3710, 3810) by wired or wireless communication. The host computer (3700, 3800) includes dedicated hardware, software, firmware, and the like for controlling the test. In this embodiment, the host computer (3700, 3800) and the tester main body (3710, 3810) are shown separately. However, the host computer (3700, 3800) and the tester main body (3710, 3810) are realized by one apparatus. You can also.

  DRAM, SRAM, flash memory, etc. can be used for the memory of the tester main body (3710, 3810) or the host computer (3700, 3800). The memory can store a program and data for performing a DUT test.

  The software or firmware of the tester main body (3710, 3810) or host computer (3700, 3800) is a device driver program for scan test, OS (Operating System) program, DUT test program, and setup for DUT test. , Stored in the memory in the form of an instruction code (Instruction Code) for generating a signal for the DUT test, observing and analyzing the DUT test result signal, and executed by the CPU.

  Therefore, the scan pattern is applied to the DUT by such a program. Furthermore, DUT test and test result reporting and analysis data can be obtained automatically through a program. Various languages such as C, C ++, Java and the like can be used as a language used in the program. The program can be stored in a recording device such as a hard disk, a magnetic tape, or a flash memory.

  The CPU of the tester main body (3710, 3810) or the host computer (3700, 3800) is a processor, and executes software or program code stored in the memory. For example, when a user command is received via a user interface such as a keyboard or a mouse, the CPU analyzes the user command, performs the corresponding work via software or a program, and then outputs the result to a speaker, printer, monitor, etc. Provide to users through the user interface.

  The user interface of the tester body (3710, 3810) or the host computer (3700, 3800) allows information to be exchanged between the user and the device and commands to be transmitted. For example, there are interface devices for user input such as a keyboard, a touch screen, and a mouse, and output interface devices such as a speaker, a printer, and a monitor.

  The test head (3720, 3820) includes a channel for transferring electrical signals between the tester body (3710, 3810) and the DUT. An interface board is provided on the test head (3720, 3820). An interface board used for a packaged IC chip is called a normal load board, and an interface board used for testing an IC chip on a wafer is called a normal probe card.

  The chambers (3750, 3860) are spaces where aging can be applied to the DUT. The chambers (3750, 3860) control the temperature of the DUT located in the chamber by the control of the temperature controller. The temperature control unit may be included in the tester main body (3710, 3810) or the host computer (3700, 3800). Further, the tester body (3710, 3810) or the host computer (3700, 3800) can control the burn-in test time or supply voltage for the DUT.

  The burn-in test apparatus shown in FIGS. 37 and 38 is only one example for deepening the understanding of the present invention. Therefore, the respective configurations are integrated to realize an integrated type, or one configuration is made into a plurality of configurations. Various design changes are possible depending on the embodiment, such as implementation by separation.

  Furthermore, the burn-in test apparatus shown in FIGS. 37 and 38 can be implemented so that the burn-in test and the scan test are performed simultaneously, or only one of them is performed.

  In at least one embodiment of the present invention, the burn-in test apparatus can perform a burn-in test using an optimum shift frequency for each scan section, as described above. In at least one embodiment of the present invention, a test for determining whether the chip is normal or failed can be performed at the same time.

  In at least one embodiment of the present invention, the burn-in test apparatus can perform the burn-in test together with the scan test using the optimum shift frequency for each scan pattern or scan section, as described above. Since the switching operation occurs in more IC chip circuit portions in the scan mode than in the function mode, the aging can be further accelerated through the scan test, and the burn-in test time can be shortened. Furthermore, performing burn-in test using the maximum shift frequency that can be assigned to each divided scan section not only shortens the burn-in test time, but also accelerates aging of specific parts of the circuit due to specific scan patterns. Can be reduced. That is, there is an effect that the stress is applied to the IC chip as a whole in a balanced manner and the quality of the burn-in test is improved. The shorter the length of the scan section that uses the optimized shift frequency, the greater the effect.

  The present invention is not limited to the case where the scan test is performed simultaneously with the burn-in test. The scan test itself does not need to be performed, including only the process of shifting the scan pattern during the burn-in test.

  FIG. 39 is a schematic diagram showing an example of the influence of temperature on the IC chip when performing a burn-in test using a single scan shift frequency according to at least one embodiment of the present invention.

  As shown in FIG. 39, the plurality of scan patterns are all shifted to the scan path of the IC chip (3900) using the same scan shift frequency (for example, 25 MHz). The activated part of the IC chip may differ depending on each scan pattern. For example, the IC chip portion (3910) activated by the scan pattern 1 (3930) and the IC chip portion (3920) activated by the scan pattern 2 (3932) are different from each other.

  Further, the heat generated on the IC chip by each scan pattern may vary depending on the scan shift frequency, the number of times the circuit is switched by the scan pattern, and the like. For example, the temperature of the IC chip portion (3910) activated by the scan pattern 1 is a ° C., and the temperature of the IC chip portion (3920) activated by the scan pattern 2 is b ° C.

  The shift frequency can be increased in order to accelerate burn-in test aging by generating more stress and heat in the IC chip. However, if the shift frequency is increased too much, the problem of overkill for determining a normal IC chip as a defective product may occur. On the other hand, when the shift frequency is lowered, there is a problem that the aging of the burn-in test cannot be accelerated efficiently due to insufficient stress and heat generated in the IC chip.

  FIG. 40 is a schematic diagram showing an example of the influence of temperature on the IC chip when performing a burn-in test using an optimum shift frequency for each scan pattern according to at least one embodiment of the present invention. 39 and 40 are examples using the same IC chip and the same scan pattern.

  As shown in FIG. 40, aging of the IC chip can be accelerated by shifting to the scan path using an optimum shift frequency for each scan pattern.

  Since the burn-in test is usually performed for several tens of hours or more in a high temperature environment exceeding 100 ° C., the time and power consumption during the burn-in test increase the test cost. That is, since IC chip test service providers generally charge costs in proportion to the test time, the time required for the chip test has a great influence on the cost of the chip. In addition, the high temperatures in excess of 100 ° C formed in the chambers used for burn-in testing often use electricity, so the costs for this are substantial and have a significant impact on test service provider costs and chip costs. It will be.

  Therefore, reducing the burn-in test time and the power consumed by the burn-in test is very important in reducing the test cost. Furthermore, reducing the burn-in test time is also very important in the time-to-market of products.

  For example, when the maximum scan shift frequency of scan pattern 1 (3930) shown in FIG. 39 is 25 MHz and the shift frequency of scan pattern 2 (3932) can be set higher, as shown in FIG. 40, scan pattern 2 (4032) The aging of the IC chip can be further accelerated by a temperature (c ° C.) higher than the temperature (b ° C.) shown in FIG. 39.

  For convenience of explanation, FIGS. 39 and 40 illustrate a case where a shift frequency is assigned to a scan pattern and shifts to a scan path. However, as shown in FIGS. It can be divided into scan sections and shifted into the scan path with different shift frequencies.

  For example, it is necessary to maintain the junction temperature of the test target chip within a predetermined range so that the burn-in test time or the burn-in test quality can be predicted. For example, the junction temperature of the device under test or the IC chip can be determined as shown in Equation 3.

(Equation 3)
T _j = T _a + P + θ _ja
Here, _{T j} is the device under test or IC chip junction temperature, _{T a} is the temperature of the surrounding environment (Ambient Temperature), P is the power consumption of the device under test or the IC chip, theta _niv is tested devices or IC chips Represents thermal resistance.

Referring to Equation 3, the control of the _{T j} (Controllability) depends on the control of the _{T a} and P. For example, _{T a} can be controlled to a proper temperature using an apparatus such as a chamber or the thermal chuck (Thermal Chuck) controlling the temperature of the external environment of the test device or IC chip. Therefore, there is a need for a method for controlling power consumption P during chip burn-in testing. For example, a variation in power consumption during a chip burn-in test may significantly affect the junction temperature T _j of the chip, which is bad for the reliability screening process of the chip. May have an effect.

The time required for the burn-in test can be estimated based on the median value of the junction temperature T _j of Equation (3). For example, the junction temperature can be determined by the value of power consumption Pburn-in in FIG. Pburn-in is a median or average value of power consumption based on test data or a power consumption value predicted at the time of a good quality burn-in test.

  FIG. 42 is a graph showing an example of power consumption that occurs during the burn-in test before adjusting the power consumption of test data. FIG. 43 is a graph showing an example of power consumption that occurs during the burn-in test after adjusting the power consumption of the test data.

As shown in FIG. 42, when the power consumption becomes higher than Pburn-in or Pmargin- _high reflecting a _margin , an overburn-in state may occur. When this occurs, the chip yield is adversely affected.

When the power consumption becomes lower than Pburn-in or Pmargin- _high reflecting a _margin , an under burn-in state may occur. When this occurs, a situation where a chip having a potential defect passes a test process is created.

Therefore, the power consumption by the test data needs to be close to P _burn-in as shown in FIG. 43 so that the prediction for burn-in time and burn-in quality is accurate. That is, it is necessary to minimize fluctuations in the heat generation of the IC chip so as not to increase fluctuations in power consumption due to test data.

  An embodiment of a method for improving burn-in quality by optimizing power consumption during burn-in test to shorten or predict burn-in time will be described below.

Step 1
The test data is divided into at least two or more sub data. For example, as shown in FIG. 43, the test data can be divided into three sub-data based on the test time axis.

Step 2
A shift frequency used to input each sub data to the chip is searched or determined so that a difference in power consumption of at least two sub data divided in step 1 is minimized. The frequency used to input each sub data to the chip is searched or determined so that the power consumption by each sub data is close to or the same as the predicted power consumption (or predicted current consumption) for burn-in test. For example, as shown in FIG. 43, the frequency of each sub-data is adjusted so that the power consumption by the test data approaches P _burn-in .

Step 3
A burn-in test is performed using the frequency searched or determined in step 2 for each sub-data. For example, as shown in FIG. 43, the _burn-in test is performed so that the power consumption of each sub-data section approaches P _burn-in .

  The sub-data in steps 1 to 3 is a scan section or functional test data (data used for testing regarding the function of the chip).

  Steps 1 to 3 can be executed by the same apparatus or different apparatuses depending on the embodiment. For example, it can be executed on a device such as a test device or a computer.

  As another example, another method for improving burn-in quality by optimizing the power consumption during the burn-in test to shorten or predict the burn-in time is as follows.

Step 1
The test data is divided into at least two or more sub data.

Step 2
The maximum shift frequency at which a normal chip test result appears normal for each sub-data is searched or determined. For example, the maximum shift frequency is a frequency that is optimized to minimize the test time or a frequency that reflects a margin on the maximum shift frequency.

Step 3
Using the maximum shift frequency searched or determined for each sub-data in step 2, power consumption and current consumption are measured or estimated.

Step 4
Look for sub-data where the power consumption or current consumption measured or estimated in step 3 may be greater than the power consumption criteria for the optimal burn-in test. For example, the power consumption criterion for the optimal burn-in test is P _burn-in or P _margin-high in FIG.

Step 5
The frequency of the sub data retrieved in step 4 is lowered and adjusted so that the power consumption of the sub data is the same as or close to the power consumption or current consumption for the optimal burn-in test. For example, the power consumption criterion for the optimal burn-in test may be P _burn-in , P _margin-high or P _margin-low in FIG. Furthermore, the power consumption or current consumption of each sub-data measured or estimated in step 3 may be smaller than the power consumption or current consumption for the optimal burn-in test. However, it should be noted that a test failure may occur if the frequency of the corresponding sub-data is increased to be equal to or adjacent to the power consumption or current consumption for the optimum burn-in test.

Step 6
A burn-in test is performed using the shift frequency of each sub-data adjusted in step 5.

  In at least one embodiment of the invention, the sub-data of steps 1-6 is a scan section or functional test data.

  Steps 1 to 6 can be executed by the same apparatus or different apparatuses depending on the embodiment. For example, it can be executed on a device such as a test device or a computer.

As another embodiment, a method for searching or determining a frequency corresponding to a target power consumption is as follows. A power consumption value consumed by sub-data is measured or estimated using a certain frequency. Then, a constant value for αxCxV _dd ² is calculated using a relational expression between power consumption and frequency as shown in Equation ² . Then, the target frequency value can be calculated by substituting the constant value and the target power consumption value into Equation 2.

  In at least one embodiment of the present invention, the power consumption consumed by the sub-data can be measured or estimated while increasing or decreasing the frequency, and the target frequency can be searched or determined.

  In at least one embodiment of the present invention, the power consumption consumed by the sub-data can be measured or estimated using an apparatus or software that measures or estimates power or current consumption.

  FIG. 44 is a flowchart illustrating an example of a method for searching for an optimum shift frequency for each scan section in order to minimize the burn-in test time according to at least one embodiment of the present invention.

  As shown in FIG. 44, the burn-in test time minimizing apparatus divides one or more scan patterns into at least two scan sections (step S4400). As an example of the division of the scan pattern, the method shown in FIGS. 5 to 10 can be used. The burn-in test time minimizing apparatus assigns a plurality of shift frequencies to the scan sections, respectively (step S4410). Here, the value of the shift frequency assigned to each scan section is lower than the shift frequency at which the output pattern of the scan path is different from the predicted pattern. Then, the burn-in test time minimizing apparatus performs the burn-in test while shifting the scan section using the shift frequency assigned to each scan section (step S4420).

  The division of the scan pattern into scan sections (step S4400), the assignment of the shift frequency to the scan section (step S4410), the execution of the burn-in test (step S4420), etc. are performed by the same apparatus or different apparatuses depending on the embodiment. Can do.

  The burn-in test time minimizing device searches for the shift frequency immediately before the output pattern and the prediction pattern differ depending on the increase or decrease of the shift frequency, and determines it as the maximum shift frequency that can be assigned to the scan section. Depending on the embodiment, each scan section may be assigned a shift frequency that is lower than the maximum shift frequency retrieved through increasing or decreasing the shift frequency.

  The various embodiments described above can be used as a method of searching for the optimum shift frequency for each scan section for the burn-in test according to at least one embodiment of the present invention. For example, the burn-in test time minimizing apparatus can search the optimum shift frequency for each scan section by executing the method shown in FIGS. Furthermore, the method of changing the scan pattern arrangement order shown in FIG. 36 can also be applied to shorten the burn-in test time and improve the burn-in test quality.

  FIG. 45 is a block diagram illustrating an example of an apparatus for minimizing burn-in test time according to at least one embodiment of the present invention.

  As shown in FIG. 45, the apparatus for minimizing the burn-in test time according to at least one embodiment of the present invention includes a chamber control unit (4500), a shifting unit (4510), and a shift frequency determination unit (shift frequency search unit). Part) (4520).

  The chamber controller (4500) controls the voltage, temperature, burn-in test time, etc. supplied to the IC chip to be inspected.

  The shift frequency grasping unit (4520) searches the scan section for the optimum shift frequency for shifting to the scan path of the IC chip during the burn-in test. For example, the shift frequency grasping unit 4520 can determine an optimum shift frequency for each scan section based on at least one of the various embodiments described above. Furthermore, the optimum shift frequency can be determined by searching or determining not only by the burn-in test time minimizing apparatus but also by a separate apparatus. The shift frequency that is searched or determined is determined by the shift frequency determining unit (4520). It may be used.

  The shifting unit (4510) shifts the scan section to the scan path using the optimum shift frequency obtained by the shift frequency grasping unit (4520) while the burn-in test is performed by the chamber control unit (4500). To minimize burn-in test time.

  In at least one embodiment of the present invention, only the burn-in test can be performed using the frequency optimized for each scan section, or the chip can be tested together with the burn-in test. The burn-in test time minimizing apparatus can perform the above-described scan test together with the burn-in test.

  The burn-in test time minimizing apparatus can be realized as a part of the burn-in test apparatus shown in FIGS. In at least one embodiment of the present invention, only the burn-in test can be performed using the frequency optimized for each scan section, or the chip can be tested together with the burn-in test. For example, only a burn-in test can be performed using a set of scan patterns to which shift frequencies optimized for each scan section are assigned, or both a burn-in test and a scan test can be performed.

  The burn-in test time minimizing apparatus can rearrange the order of scan patterns shifted to the scan path using the scan pattern rearrangement method shown in FIG. In this case, the portion of the circuit that is switched on the IC chip and the number of switching operations are different from those before the rearrangement due to the shift of the scan pattern of the pattern position rearranged on the set of scan patterns. Operating characteristics may change. Therefore, the shift frequency assigned to the scan pattern (or scan section) may be increased. Therefore, using this property, after the rearrangement of the scan pattern, the optimum shift frequency is searched or determined for each scan section using the above-described embodiment, the overall burn-in test time is further shortened, and the test quality is improved. Can be increased. Further, the rearrangement of the scan pattern may be performed not only by the burn-in test time minimizing apparatus but also by a separate apparatus such as a computer and used by the burn-in test time minimizing apparatus.

  FIG. 46 is a table showing an experimental result using an MCU (Micro Control Unit) processor IC chip and a test pattern of the IC chip, in which the shift frequency determination target scan section corresponds to one scan pattern on a one-to-one basis. FIG. 46 shows a critical power-based method (Power-Limit-Based Method) for searching for the maximum possible shift frequency while maintaining the power consumption due to the scan pattern below the allowable power consumption of the IC chip, and the present invention described above. The maximum shift frequency searched for each scan pattern using the shift frequency increase / decrease-based method (Shift-Frequency-Scaling-Based Method) according to at least one embodiment of the present invention.

  As shown in FIG. 46, optimization using the shift frequency increase / decrease base method used the method of FIG. Furthermore, as shown in FIG. 46, there is a difference in the result of the maximum shift frequency between the critical power base method and the shift frequency increase / decrease base method in addition to the power consumption of the IC chip in the test environment of the IC chip and the IC chip. This is because there are circuit structures and features that can affect the frequency, various physical conditions and environments, and the like.

  The power consumption limit in FIG. 46 is an average power consumption when the IC chip is operated in the functional mode at 80 MHz, which is the limit of the functional frequency of the IC chip, and is about 285 mW.

  Usually, the functional frequency limit is different from the frequency limit or scan shift frequency limit at which the IC chip is damaged. For example, the frequency limit is different in circuit operation characteristics, power consumption, influence of signal line interference (Signal Crosspath), critical timing path (Critical Timing Path), etc. depending on the scan test or functional operation mode. Further, there are cases where various restrictions such as a difference in voltage or power supplied to different positions on the circuit may be imposed.

  The first column in FIG. 46 is the scan pattern number, and the second column is the power consumption due to the leakage current of the IC chip. The third column is the dynamic power consumption consumed by a scan shift using a nominal shift frequency of 25 MHz. The fourth column is the sum of the second column and the third column, and is the total power consumption per scan pattern when a nominal shift frequency of 25 MHz is used. The fifth column shows the maximum possible shift frequency of each scan pattern without exceeding the power consumption limit value of 285 mW.

  The sixth column is a test result of the MCU chip when the test is performed at the shift frequency of the fifth column for each scan pattern, and indicates whether the test is normal or unsuccessful.

  The seventh column is the maximum shift frequency searched using the shift frequency increase / decrease base method according to the method according to at least one embodiment of the present invention described above, and all indicate normal test results.

  The eighth column represents the increase / decrease ratio (%) with respect to the seventh column, which is the result of the fifth column contrast shift frequency increase / decrease method, which is the result of the critical power-based method.

  As shown in FIG. 46, it can be seen that the shift frequency in the shift frequency increase / decrease base method is higher than the average by about 30% or more except in the case of the sixth scan pattern in which the scan test is not normally performed in the critical power base method. . For example, there are various reasons such as a case of a false critical path depending on a bit pattern to be shifted, or a bit on a scan pattern corresponding to a doncare bit that does not affect a test result.

  When the IC chip cannot be tested normally even when using a shift frequency that prevents the power consumption consumed by the scan pattern from exceeding the allowable power consumption of the IC chip, as in the case of the sixth scan pattern in FIG. It can be seen that This is because the shift frequency limit is not only the power consumption, but also the signal delay time of the critical timing path due to the circuit structure of the IC chip, the signal interference, the difference in voltage or power supplied to different positions on the circuit, the signal or power This is because there are various effects such as noise, chip manufacturing process variations, and physical characteristics of the circuit. Further, it may be influenced by the test environment and conditions such as the ambient temperature of the test target chip and the Seto state of the chip and the chip test apparatus.

  In addition, even if the value of the scan section or scan pattern bit changes during the shift-in and is loaded into the scan path for an unexpected reason in the process of grasping the optimum shift frequency through the shift frequency increase / decrease, the IC Depending on the structure of the chip circuit, the result pattern after the scan capture operation may appear as a normal bit pattern on the scan path.

  Therefore, before the scan section is loaded into the scan path through the increase / decrease of the shift frequency and the scan capture is performed, the output result of the main output port of the IC chip is compared with the predicted result, and the main output result is normal (PASS). By checking whether or not, the optimum shift frequency can be searched more accurately.

  FIG. 47 is a graph showing an example of a test fail hole that may occur when testing an IC chip.

  There is a step of setting up a test device, test data, or a test program in order to test the IC chip. An abnormal test failure may occur within the range of a normal shift frequency that should be fault-free (Fault-Free) in the IC chip. Such an abnormal test failure (4700) is referred to as a test fail hole (Fail Hole), and is also referred to as a test frequency fail hole or a test frequency period fail hole.

  The example shown in FIG. 47 is a case where an abnormal test failure (4700) occurs at 30 MHz when testing an IC chip. Since the test fail hole may make the mass production test of the IC chip unstable and adversely affect the yield, it is desirable to remove the test fail hole.

  FIG. 48 is a graph illustrating an example of a method for solving the test fail hole problem according to at least one embodiment of the present invention.

  FIG. 48 shows an example for solving the problem of the test fail hole. In order to solve the problem of the test fail hole, there is a method in which a test fail hole is generated but a test for specific sub-data that affects the occurrence of the fail hole is not performed.

  For example, there is a method for preventing the test output data of the IC chip for the sub data in which the fail hole has occurred from being compared with the predicted data. Such a method is called test data masking or predicted result masking of test data (Expected Result Masking). In the following examples, sub-data means scan pattern, scan section or functional test data. A case where the test data masking method is applied to the scan pattern can be referred to as scan pattern masking or masking of a prediction result of the scan test. Another example is a method of removing or not using sub-data that affects the occurrence of test failure holes.

  In the example shown in FIG. 48, the second sub data in which a fail hole is generated at 30 MHz can be searched and masked or removed. However, the method of masking or removing the sub data may lower the failure coverage (Fault Coverage) of the test target IC. Furthermore, if a faulty (Faulty) IC chip has no fault (Fault-Free) by the method of masking or removing sub-data, there is a possibility that a test determination is made. This may cause a field escape problem in which a faulty IC chip goes out to the field.

  Therefore, as another embodiment of the method for solving the problem of the test fail hole, the failure hole is searched for a frequency corresponding to the fail data or the sub data and the fail hole that is generated or has an influence on the occurrence of the fail hole. A frequency that does not generate a fail hole is used in specific sub-data that is generated or affects the generation of the fail hole.

  FIG. 49 is a flowchart illustrating an example of a method for solving the test fail hole problem according to at least one embodiment of the present invention.

  As shown in FIG. 49, the test apparatus selects sub data constituting the test data (step S4900). Here, the sub data is a scan pattern or a scan section. The test apparatus tests the IC chip while increasing / decreasing the frequency of the sub data (step S4910), and searches for usable frequencies or fail holes for the selected sub data based on the PASS or FAIL test result of the IC chip. (Step S4920). Then, the IC chip is tested using a frequency at which no fail hole is generated for the selected sub-data (step S4930).

  For example, when searching for a fail hole with respect to a scan pattern or a scan section, the above-described various methods of searching for an available shift frequency of the scan pattern or scan section using an increase or decrease of the shift frequency can be used. .

  FIG. 50 is a graph illustrating an example of a method for solving the test fail hole problem according to at least one embodiment of the present invention.

  As shown in FIG. 50, a frequency of 25 MHz or less can be used for the second sub data in which the test fail hole (5000) is generated. Here, the sub-data is a scan pattern, a scan section, or functional test data.

  If the first sub data, the second sub data, and the third sub data are the first scan pattern, the second scan pattern, and the third scan pattern, respectively, the first scan pattern, the second scan pattern, and the third scan pattern are sequentially Shift to the scan path of the IC chip to be tested. The method of searching for a test fail hole (5000) for a second scan pattern or a scan section included in the second scan pattern uses a shift frequency increase / decrease to search for an available shift frequency of the scan pattern or scan section. Various methods can be applied.

  For example, the first scan pattern or the third scan pattern positioned before or after the second scan pattern is shifted in using a frequency that can be normally input to the scan path while increasing or decreasing the shift frequency of the second scan pattern. Then, it is possible to search for a fail hole and a usable shift frequency range for the second scan pattern using the scan test result. The shift frequency of the first scan pattern or the third scan pattern used when searching for a fail hole or usable frequency range for the second scan pattern may be the same or different.

  In the scan test process for searching for a fail hole or usable frequency range for the second scan pattern, not only the output pattern of the second scan pattern but also the output pattern of the first scan pattern located before the second scan pattern Can also be compared with the corresponding prediction pattern. At this time, when the test results of the first scan pattern and the second scan pattern are both normal, the current shift frequency is a usable shift frequency of the second scan pattern. As another example, an output pattern of a third scan pattern, which is a scan pattern located after the second scan pattern, can be compared with the predicted pattern. If the test results of the second scan pattern and the third scan pattern are both normal, the current shift frequency is a usable shift frequency of the second scan pattern.

  The scan pattern in which the test fail hole occurs or affects the occurrence of the fail hole may be the first scan pattern or the third scan pattern input before or after the second scan pattern. This is because the shift frequency of the second scan pattern may affect the bit value on the scan path when the output pattern of the first scan pattern is shifted out. Furthermore, when the test result by the second scan pattern is shifted out, the bit value on the scan path may be affected by the shift frequency for shifting in the third scan pattern to the scan path. Therefore, when there is a test fail hole in the test result of a specific scan section or scan pattern, it is determined whether the scan section or scan pattern positioned before or after the scan section or scan pattern affects the occurrence of the fail hole.

  For example, a frequency that can be normally shifted in the scan path is used for the second scan pattern, and the test result is confirmed while increasing the shift frequency of the third scan pattern. At this time, if the test result by the second scan pattern is unsuccessful and the test result by the third scan pattern is normal, the shift frequency of the third scan pattern is set to a frequency at which the test failure of the second scan pattern does not occur. Use. By doing in this way, the influence of the 3rd scan pattern with respect to the fail hole which appears in the test result of the 2nd scan pattern can be removed.

  In at least one embodiment of the invention, a scan test is performed while increasing or decreasing the shift frequency. When a fail hole occurs at a specific shift frequency, a specific scan pattern in which the scan test using the shift frequency corresponding to the fail hole has failed is searched. A chip test is performed using a shift frequency lower than the shift frequency at which the fail hole is generated for the specific scan pattern and the scan pattern before or after the specific scan pattern. That is, a shift frequency lower than the shift frequency at which the fail hole is generated is used for the adjacent scan pattern that affects the generation of the fail hole.

  In at least one embodiment of the present invention, an increase or decrease in shift frequency is used to find a scan section or scan pattern in which a fail hole occurs and a corresponding shift frequency. Then, a shift frequency at which no fail hole is generated within the range of the shift frequency margin considering the manufacturing process and tests is used for the scan section or scan pattern. For example, it is possible to use a shift frequency that is higher than the shift frequency at which a fail hole is generated and does not generate a fail hole within a margin range. In another example, a scan section or scan pattern adjacent to a scan section or scan pattern in which a fail hole has occurred may use a shift frequency that is higher than the shift frequency in which the fail hole has occurred and does not generate a fail hole within the margin range. it can.

  As described above, when a frequency or frequency period at which no fail hole is generated for a specific sub-data is used for the mass production test of the chip, the failure detection rate of the IC chip is lowered by the method of masking or removing the sub-data. Can be solved. Further, it is possible to solve the problem of field escape in which a faulty IC chip goes out to the field. It is possible to search for a specific frequency or a range of frequency periods in which no fail hole is generated, and use it for chip testing.

  FIG. 51 is a graph illustrating an example of a method for searching for a shift frequency for reducing test time and improving yield according to at least one embodiment of the present invention.

  As shown in FIG. 51, it is assumed that at least two or more scan sections are shifted to the scan path of the chip using different shift frequencies and the chip is tested. At this time, a shift frequency with an increased margin is used for the first scan section having a small test normal margin on the basis of a specific shift frequency (5100) in which the test results are all normal in two or more scan sections. A shift frequency with a reduced margin is used for the second scan section with a large test normal margin of the shift frequency.

  The scan section shift frequency margin can be retrieved or determined using scan section test normal or failed information. For example, a margin representing the interval between the frequency or period of frequency that is the boundary between normal and unsuccessful tests in the scan section and a specific shift frequency (5100) can be retrieved or determined. Both the test result by the scan section using the shift frequency reflecting the margin and the scan section positioned before the scan section must be normal.

  Increasing the margin for a scan section with a small shift frequency margin will have a smaller effect on the test when the chip manufacturing process or test environment changes. Therefore, the yield may be improved.

  Furthermore, reducing the margin for a scan section with a large shift frequency or shift frequency cycle margin has the effect of reducing the test time.

  Therefore, the opposite effects of yield improvement and test time reduction can be obtained by considering the frequency margin for each scan section.

  As shown in FIG. 51, the first scan section and the second scan section are both test paths at a nominal shift frequency (5100) 20 MHz. When the shift frequency margin of the first scan section with respect to 20 MHz is smaller than a preset reference value, the test apparatus increases the shift frequency margin of the first scan section to improve the yield during the mass production test of the chip. be able to. That is, the use shift frequency of the first scan section is changed to a value smaller than 20 MHz so as to satisfy the reference value. In addition, if the margin of the shift frequency of the second scan section or the period of the shift frequency is larger than the reference value based on 20 MHz, the margin of the frequency of the second scan section or the period of the frequency is reduced, and the total test is performed during the mass production test of the chip. Time can be shortened. That is, the use shift frequency of the second scan section is changed to a value larger than 20 MHz so as to satisfy the reference value.

  As described above, when a chip test is performed by searching for an optimum shift frequency for at least two or more scan sections, the shift timing of the boundary bits between adjacent scan sections may be a problem.

  If the period of the shift frequency between the first bit of the scan section S2 sequentially shifted in the scan path after the last bit of the scan section S1 is CP_boundary (Clock Period of Boundary Bits), the scan section S2 When the optimum maximum shift frequency period is searched, the first CP_boundary of S1 and S2 may be different from the second CP_boundary of S1 and S2 that determines the optimum shift frequency period. For example, when the second CP_boundary is smaller than the first CP_boundary, the scan test using the scan sections S1 and S2 may determine that there is a failure with respect to a normal chip.

  In such a case, the following method can be used to solve the shift timing problem of the boundary bits of adjacent scan sections.

  (1) When the optimum maximum shift frequency of the scan section S1 is determined, when searching for the optimum maximum shift frequency of the scan section S2 shifted in after the scan section S1, the scan section S1 includes S1 The optimum shift frequency determined for is used.

  (2) A clock edge where a scan bit shift operation is performed is positioned at a boundary of CDP (Clock Definition Period) or a position close to the boundary. CDP is a time interval in which the shape of the clock is defined, and the rising or falling timing of the clock signal is defined in this interval. CDP can be set by device or test data.

  (3) The period of the shift frequency or the shift time interval between the last bit of the scan section S1 and the first bit of the scan section S2 that is sequentially shifted into the scan path thereafter is adjusted. For example, when a scan test is performed using a scan pattern including S1 and S2, a normal chip is adjusted to a cycle of a shift frequency that can be determined to be normal. The period of the shift frequency or the shift time interval is defined by the test data or set by the test apparatus. For example, when creating new test data in which the optimum shift frequency period is assigned to each of the scan sections S1 and S2, timing information for the last bit of the scan section S1 or the first bit of S2 is newly created. The timing information is assigned a period of a shift frequency that can determine that a normal chip is normal when a scan test is performed using a scan pattern including S1 and S2. For example, a period of a nominal shift frequency is assigned.

  (4) When it is determined that there is a failure during a scan test for a normal chip due to a shift timing problem of boundary bits between adjacent scan sections, the shift frequency cycle of the scan section or scan pattern including the boundary bit is increased. To do.

  A function for executing at least one embodiment of the present invention and scan shift frequency information obtained by executing at least one embodiment of the present invention or scan section information reflecting this information can be read by a computer. It can be stored as a computer-readable code or data on a simple recording medium. An example of the code is an executable computer program or software. The code or data is executed or used in an apparatus such as a scan test apparatus, a burn-in test apparatus, or a computer. Computer-readable recording media include all types of recording devices that store data that can be read by a computer system. Examples of computer-readable recording media include various forms of ROM, RAM, FLASH memory, CD-ROM, magnetic tape, floppy disk, hard disk, optical data recording device, and the like.

  Further, the computer-readable recording medium includes a form that is distributed in a computer system connected via a network and stored and executed as computer-readable code or data in a distributed manner. In at least one embodiment of the present invention, computer program code or data is stored on a server computer, and the client computer connects to the server computer to use the code or data, or is downloaded to the client computer for storage or execution. You can For example, the program code can be executed on a server computer or a client computer.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention. It will be apparent to those skilled in the art that the present specification may be embodied in other specific forms without departing from the spirit and essential characteristics of the above configuration. The foregoing detailed description should not be construed as limiting in any respect, but should be considered exemplary. The scope of the specification should be determined by the reasonable company of the appended claims, and all changes within the equivalent scope of the specification are intended to be included within the scope of the invention.

Claims (21)

A scan pattern is input to the scan path via the scan input port of the IC chip including the circuit to be tested, and the output value output via the scan output port is compared with a preset predicted value, and based on the comparison result In an IC chip test apparatus for performing a scan test for inspecting the IC chip for defects,
A shift frequency at which a target scan section to be searched for a usable shift frequency among at least two scan sections included in the scan pattern set is shifted to the scan path and the result of the scan test is normal or A shift frequency search unit for searching for a shift frequency that is a failure is provided.
The shift frequency search unit is configured to search for the shift frequency for the target scan section so that the shift frequency of the target scan section is different from at least one scan section among other scan sections that shift the scan path. Search for a shift frequency where the scan test result is normal or a failure that is increased or decreased or set to a different shift frequency,
IC chip test equipment. The shift frequency search unit may search from a region or failure in which the scan test result changes from normal to failure while increasing or decreasing the shift frequency of the target scan section when searching for a shift frequency that can be used for the target scan section. Search the shift frequency of the region that changes normally,
The IC chip test apparatus according to claim 1. The shift frequency search unit includes a result of a first scan test obtained using a first shift frequency for the target scan section when searching for a shift frequency usable for the target scan section, and the target The first shift when the result of the second scan test obtained by using a second shift frequency different from the first shift frequency for any one scan section before the scan section is normal. Determining a frequency as an available shift frequency for the target scan section;
The IC chip test apparatus according to claim 1 or 2. The IC chip includes a chip on a wafer or a packaged chip,
The IC chip test apparatus according to any one of claims 1 to 3. A scan pattern is input to the scan path via the scan input port of the IC chip including the circuit to be tested, and the output value output via the scan output port is compared with a preset predicted value, and based on the comparison result In an IC chip test apparatus for performing a scan test for inspecting the IC chip for defects,
The first scan pattern including the first scan section is shifted to the scan path of the IC chip to perform a test, and the second scan pattern including the second scan section after the first scan section is shifted to the scan path. A shift frequency search unit that performs a second test step of performing a test and searches for a usable shift frequency for the second scan section,
The shift frequency search unit
The first scan section is shifted to the scan path at a first shift frequency in the first test step, and the second scan section is shifted at a second shift frequency different from the first shift frequency in the second test step. Shift to the scan path,
When searching for an available shift frequency for the second scan section, if both the test result in the first test step and the test result in the second test step are normal, the second shift frequency is Determining the available shift frequency for the second scan section;
IC chip test equipment. The first scan section is the first scan pattern or a part of the first scan pattern;
The second scan section is the second scan pattern or part of the second scan pattern;
The IC chip test apparatus according to claim 5. The shift frequency search unit may be different from at least one scan section among other scan sections that shift the second shift frequency to the scan path when searching for a usable shift frequency for the second scan section. Searching for available shift frequencies for the second scan section, increasing or decreasing to
The IC chip test apparatus according to claim 5 or 6. The IC chip includes a chip on a wafer or a packaged chip,
The IC chip test apparatus according to any one of claims 5 to 7. A scan pattern is input to the scan path via the scan input port of the IC chip including the circuit to be tested, and the output value output via the scan output port is compared with a preset predicted value, and based on the comparison result In an IC chip test method used in an IC chip test apparatus for performing a scan test for inspecting whether there is a defect in the IC chip,
A shift frequency at which a target scan section to be searched for a usable shift frequency among at least two scan sections included in the scan pattern set is shifted to the scan path and the result of the scan test is normal or A shift frequency search step for searching for a shift frequency that is a failure;
In the shift frequency search step, when the shift frequency is searched for the target scan section, the shift frequency of the target scan section is different from at least one of the other scan sections that shift the scan path to the scan path. Searching for a shift frequency at which the scan test result is normal or a failure, increasing or decreasing, or set to a different shift frequency,
IC chip test method. In the shift frequency search step, when searching for a shift frequency that can be used for the target scan section, the shift test results from a region or failure where the result of the scan test changes from normal to failure while increasing or decreasing the shift frequency of the target scan section. Including a step of searching for a shift frequency of a region that changes normally,
The IC chip test method according to claim 9. The shift frequency search step includes a result of a first scan test obtained using a first shift frequency for the target scan section when searching for a shift frequency usable for the target scan section, and the target The first shift when the result of the second scan test obtained by using a second shift frequency different from the first shift frequency for any one scan section before the scan section is normal. Determining a frequency as an available shift frequency for the target scan section;
The IC chip test method according to claim 9 or 10. The IC chip includes a chip on a wafer or a packaged chip,
The IC chip test method according to claim 9. A scan pattern is input to the scan path via the scan input port of the IC chip including the circuit to be tested, and the output value output via the scan output port is compared with a preset predicted value, and based on the comparison result In an IC chip test method used in an IC chip test apparatus for performing a scan test for inspecting whether there is a defect in the IC chip,
The first scan pattern including the first scan section is shifted to the scan path of the IC chip to perform a test, and the second scan pattern including the second scan section after the first scan section is shifted to the scan path. A shift frequency search step of performing a second test step of performing a test and searching for a usable shift frequency for the second scan section,
The shift frequency search step includes
The first scan section is shifted to the scan path at a first shift frequency in the first test step, and the second scan section is shifted at a second shift frequency different from the first shift frequency in the second test step. Shifting to the scan path;
When searching for an available shift frequency for the second scan section, if both the test result in the first test step and the test result in the second test step are normal, the second shift frequency is Determining as a usable shift frequency for the second scan section;
including,
IC chip test method. The first scan section is the first scan pattern or a part of the first scan pattern;
The second scan section is the second scan pattern or part of the second scan pattern;
The IC chip test method according to claim 13. The shift frequency search step may be different from at least one of the other scan sections that shift the second shift frequency to the scan path when searching for an available shift frequency for the second scan section. Searching for available shift frequencies for the second scan section, increasing or decreasing to
The IC chip test method according to claim 13 or 14. The IC chip includes a chip on a wafer or a packaged chip,
The IC chip test method according to any one of claims 13 to 15. A tester body for controlling the scan test of the IC circuit;
A host computer including a processor built in the tester body or provided outside the tester body;
A test head electrically connected to the tester body and for inputting a test data signal to the IC circuit;
An IC chip test apparatus according to any one of claims 1 to 8,
IC chip test system. The host computer includes the IC chip test device;
The IC chip test system according to claim 17. A program for executing the IC chip test method according to any one of claims 9 to 16 is stored.
A computer-readable recording medium. The IC chip test method according to any one of claims 9 to 16 is executed to store information on a shift frequency determined as a usable shift frequency for each target scan section.
A computer-readable recording medium. 17. The test data including the target scan section used to search the usable shift frequency for each target scan section by executing the IC chip test method according to any one of claims 9 to 16. Store,
A computer-readable recording medium.