JP2018006646A - Silicon carbide semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a silicon carbide (SiC) semiconductor device which is low in on-voltage, high in breakdown voltage, and low in loss; and a method for manufacturing the semiconductor device.SOLUTION: In a SiC semiconductor device 10 according to the present invention, a first region 20 where a PiN diode is formed on a principal face of a first conductivity type SiC substrate 11, and a second region 21 where a Schottky barrier diode is formed are formed in parallel; and a breakdown voltage-retaining layer 12 made of a first conductivity type SiC is formed on the principal face of the SiC substrate. In the first region, an epitaxial layer 13 made of a second conductivity type SiC is selectively formed on the breakdown voltage-retaining layer 12; and a first electrode 14a subjected to ohmic junction is formed on the epitaxial layer. In the second region 21, a second electrode 14b subjected to Schottky junction is formed on the breakdown voltage-retaining layer 12. The first electrode 14a and the second electrode 14b electrically adjoin each other.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a high breakdown voltage and low loss silicon carbide (SiC) semiconductor element and a method for manufacturing the same.

  SiC has excellent characteristics such as about 10 times higher dielectric breakdown field strength than silicon (Si), and has attracted attention as a material suitable for a high voltage power semiconductor element.

  In general, a unipolar device such as a field effect transistor (FET) is used as a power semiconductor element having a relatively low breakdown voltage. On the other hand, a high breakdown voltage power semiconductor element is a bipolar device utilizing an effect of improving the electrical conductivity of the breakdown voltage maintenance layer (conductivity modulation effect) by minority carrier injection. Etc. are generally used. In particular, the realization of power devices with a withstand voltage exceeding 10 kV is expected in order to improve the performance and size of power converters used in power infrastructure, high-speed railways, medical acceleration power supplies, industrial high-voltage power supplies, etc. Yes.

  Non-Patent Document 1 discloses a SiC PiN diode having a high breakdown voltage exceeding 20 kV by utilizing a high-purity SiC growth layer having a thickness of 200 μm or more and introducing a spatially modulated electric field concentration relaxation structure. ing.

N. Kaji et al., IEEE Trans. Electron Devices, vol.62 (2015), p.374

  In many power conversion systems, power elements are overwhelmingly used with a current of 50% or less of the rated value (maximum value of the specification). The PiN diode using SiC, which is a promising rectifier diode for ultra-high voltage application, is not limited thereto.

  However, since SiC has a wide forbidden band width of about 3.3 eV, the diffusion potential of the pn junction is as high as about 2.8V. Therefore, the SiC PiN diode has an inherent forward characteristic in which almost no current flows until the voltage reaches about 2.8V. Therefore, even when used in a low current range, an on-voltage of about 3 V is required, and when used in a low current range of 50% or less of the rated value (maximum value of the specification), the power loss becomes relatively large. Therefore, the SiC characteristic of low loss cannot be fully exhibited.

  The present invention has been made in view of the above problems, and a main object thereof is to provide a SiC semiconductor device having a low on-voltage, a high withstand voltage and a low loss, and a manufacturing method thereof.

  In the SiC semiconductor device according to the present invention, the first region where the PiN diode is formed and the second region where the Schottky barrier diode is formed are arranged in parallel on one main surface of the SiC substrate of the first conductivity type. A breakdown voltage maintaining layer made of SiC of the first conductivity type is formed on one main surface of the SiC substrate, and in the first region, the breakdown voltage maintaining layer is formed on the breakdown voltage maintaining layer. An epitaxial layer made of SiC of two conductivity types is selectively formed, and a first electrode that is ohmic-bonded is formed on the epitaxial layer, and a Schottky junction is formed on the breakdown voltage maintaining layer in the second region. The second electrode is formed, the third electrode is formed on the other main surface of the SiC substrate, and the first electrode and the second electrode are electrically conductive. And

  A method for manufacturing a SiC semiconductor device according to the present invention is a method for manufacturing the SiC semiconductor device, wherein a breakdown voltage maintaining layer made of SiC of the first conductivity type is formed on one main surface of the SiC substrate of the first conductivity type. A step (a) of forming by epitaxial growth, a step (b) of forming an epitaxial layer made of SiC of the second conductivity type on the breakdown voltage maintaining layer by epitaxial growth, and a part of the epitaxial layer is selectively removed by etching. A step (c) of exposing the breakdown voltage maintaining layer; and a step (d) of forming a first electrode that forms an ohmic junction on the epitaxial layer and a second electrode that forms a Schottky junction on the exposed breakdown voltage maintaining layer. It is characterized by having.

  According to the present invention, it is possible to provide a SiC semiconductor element having a low on-voltage, a high withstand voltage and a low loss, and a manufacturing method thereof.

It is the figure which showed the general forward direction characteristic of the SiC PiN diode and a Schottky barrier diode. It is the figure which showed typically the structure of the SiC semiconductor element in one Embodiment of this invention, (a) is sectional drawing, (b) shows a top view. It is the figure explaining the snapback phenomenon in the current-voltage characteristic of a SiC semiconductor element. It is a figure explaining the cause which a snapback phenomenon generate | occur | produces. It is a figure for analyzing a snapback voltage. It is the figure which calculated | required the forward characteristic when changing the width | variety of the area | region of a PiN diode by simulation. It is the graph which computed the P / d dependence of the snapback voltage by the current distribution model. It is sectional drawing which showed typically the structure of the trial manufacture SiC semiconductor element. It is the figure which showed the basic characteristic of the SiC semiconductor device made as an experiment, (a) shows a forward direction characteristic, (b) shows a reverse direction characteristic. It is the graph which compared the forward direction characteristic of the prototype SiC semiconductor element with the forward direction characteristic of the PiN diode and SBD which were produced independently. It is the graph which compared the forward direction characteristic of the trial manufactured SiC semiconductor element with the forward direction characteristic of the SiC semiconductor element of the hybrid structure in which the p ⁺ layer was formed by ion implantation. (A)-(e) is sectional drawing which showed the manufacturing method of the SiC semiconductor element. It is the top view which showed the modification of the SiC semiconductor element. It is the top view which showed the other modification of the SiC semiconductor element.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment. Moreover, it can change suitably in the range which does not deviate from the range which has the effect of this invention.

  FIG. 1 is a diagram showing a general forward characteristic of a SiC power diode. A graph indicated by an arrow A indicates a characteristic of a PiN diode. "SBD") characteristic.

  As shown in FIG. 1, the PiN diode has a high on-voltage (about 3 V), but has a small on-resistance due to the conductivity modulation effect. On the other hand, the SBD has a low on-state voltage (about 1 V) but a large on-resistance.

  The present invention focuses on SiC diodes as SiC power elements, and adopts a hybrid structure that operates as an SBD with a low on-voltage in a low current region and operates as a PiN diode with a low on-resistance in a high current region. To do.

  2A and 2B are diagrams schematically showing a configuration of a SiC semiconductor element according to an embodiment of the present invention, in which FIG. 2A is a cross-sectional view and FIG.

The SiC semiconductor element 10 according to the present embodiment includes a first region 20 in which a PiN diode is formed on one main surface of an n ⁺ -type (first conductivity type) SiC substrate 11 and a second region in which an SBD is formed. The region 21 is formed in parallel. In the present embodiment, as shown in FIG. 2B, the second region 21 is formed surrounding the first region 20 in plan view.

As shown in FIG. 2A, a breakdown voltage maintaining layer 12 made of n ⁻ -type (first conductivity type) SiC is formed on the upper surface (one main surface) of the SiC substrate 11. In the first region 20, an epitaxial layer 13 made of p ⁺ -type (second conductivity type) SiC is selectively formed on the n ⁻ breakdown voltage maintaining layer 12. Furthermore, an ohmic contact anode electrode (first electrode) 14 a is formed on the p ⁺ epitaxial layer 13. A cathode electrode (third electrode) 15 is formed on the back surface (the other main surface) of SiC substrate 11. As a result, a PiN diode is formed in the first region 20.

On the other hand, in the second region 21, an anode electrode (second electrode) 14 b having a Schottky junction is formed on the n ⁻ breakdown voltage maintaining layer 12. As a result, the SBD is formed in the second region 21.

Here, the first electrode 14 a and the second electrode 14 b are electrically conductive and function as an anode electrode of the SiC semiconductor element 10. Usually, the first electrode 14a and the second electrode 14b are integrally formed of the same metal material or the like. For example, when the first electrode 14a and second electrode 14b is formed of titanium (Ti), in order to achieve ohmic contact between the ^{p +} epitaxial layer 13, on the ^{p +} epitaxial layer 13, for example, titanium and aluminum (Al ) And a laminated structure (Ti / Al) (not shown) of titanium and aluminum are preferably formed. As a result, the first electrode 14a made of titanium is in ohmic contact with the p ⁺ epitaxial layer 13 through the bonding layer. The second electrode 14b made of titanium is joined to the n ⁻ breakdown voltage maintaining layer 12 by a Schottky junction.

On the other hand, the third electrode 15 is in ohmic contact with the n ⁺ -type SiC substrate 11 and functions as a cathode electrode of the SiC semiconductor element 10. For example, by forming the third electrode 15 from nickel (Ni), ohmic contact with the n ⁺ type SiC substrate 11 can be achieved.

  As described above, the SiC semiconductor element 10 in the present embodiment has a hybrid structure in which the PiN diode and the SBD are formed in parallel on the SiC substrate 11. Thereby, SiC semiconductor element 10 operates as an SBD having a low on-voltage in a low current region, and operates as a PiN diode having a low on-resistance in a high current region. As a result, it is possible to realize a low-loss SiC semiconductor element having a low on-voltage in a low current region while maintaining the high breakdown voltage inherent to the PiN diode.

In addition, as shown in FIG. 2A, the SiC semiconductor element 10 in the present embodiment has a mesa structure in which the p ⁺ epitaxial layer 13 is selectively formed on the n ⁻ breakdown voltage maintaining layer 12 by epitaxial growth. Yes. Therefore, in the vicinity of the junction interface between the p ⁺ epitaxial layer 13 and the n ⁻ breakdown voltage maintaining layer 12, there is no induced defect due to ion implantation as compared with the planar structure selectively formed by ion implantation. As a result, the lifetime of the minority carriers due to induced defects is not shortened, so that a high conductivity modulation effect can be maintained. As a result, it is possible to realize a low-loss SiC semiconductor element having a low on-voltage in a low current region while maintaining the low on-resistance inherent to the PiN diode.

  By the way, the SiC semiconductor element 10 in the present embodiment has a configuration in which a PiN diode and an SBD are connected in parallel in terms of an equivalent circuit. The current-voltage characteristics of the SiC semiconductor device 10 having such a configuration will be described with reference to FIG. 1. Ideally, when the voltage is increased from zero, the current is a certain threshold voltage (SiC). The period until the diffusion potential of the pn junction increases substantially linearly in the SBD operation mode, and when it exceeds a certain threshold voltage, it switches to the PiN diode operation mode and increases rapidly.

However, as shown in FIG. 3, in the current-voltage characteristics of the SiC semiconductor element 10, when switching from the SBD operation mode (SBD mode) to the PiN diode operation mode (PiN mode), as shown by the arrow C, A phenomenon in which the voltage drops discontinuously (snapback phenomenon) may occur. If such a snapback phenomenon occurs, the characteristics of the SiC semiconductor element 10 are not stable, which is a serious problem in practical use. In addition, when the SiC semiconductor element 10 has a plurality of first regions (PiN diode formation regions) 20, if the snapback voltage V _S shown in FIG. 3 varies, a current flows through the PiN diode in the first region 20 having a low V _S. As a result of the concentration, the problem that the area is destroyed arises.

The cause of the occurrence of such a snapback phenomenon is that, as shown in FIG. 4, the current distribution in the SBD mode is laterally spread, and as a result, applied to the p ⁺ / n ⁻ junction constituting the PiN diode. This is because the operation of the PiN diode does not start even when a certain threshold voltage is reached because no voltage is applied.

Next, referring to FIG. 5, the snapback voltage V _S in the SiC semiconductor element 10 is analyzed using a current distribution model.

As shown in FIG. 5, the horizontal spread of the current distribution in the SBD mode is approximated by an inclined line G. Then, the n ⁻ breakdown voltage maintaining layer 12 is divided by a boundary line H into a region 12a having a lateral extension and a region 12b having no lateral extension. Here, the resistance component in the region 12a and _{R 1SP,} when the resistance component in the region 12b and _{R 2sp,} ^p + / n in the center of the ^{p +} epitaxial layer 13 ^- voltage _{V J} applied to the joint has the following formula It is represented by (1).

Here, J _FS is a forward current density that flows through the entire element (cell) via the SBD portion during unipolar operation.

When V _J is equal to the diffusion potential _{V d} of the pn junction of SiC, the operation of the PiN diode begins. The snapback voltage V _{S at} this time is expressed by the following equation (2).

Here, when the width of the first region 20 in which the PiN diode is formed is P, the width of the second region 21 in which the SBD is formed is S, and the thickness of the n ⁻ breakdown voltage maintaining layer 12 is d, r _p = P / D, r _s = S / d. _Here, r p, _{r s} is the width P of the PiN diode region, and the width S of the SBD region, n ^- is a value normalized by thickness d of the breakdown voltage maintained layer 12. Further, the width P of the first region 20 is ½ (P = S) of the entire width of the first region 20, as shown in FIG. As shown in FIG. 2B, when the first region 20 is rectangular, the width P of the first region 20 is ½ of the entire width of the narrower one. In addition, the width S of the second region 21 is a minimum value between the side that defines the outer periphery of the first region 20 and the side that defines the outer periphery of the second region 21.

The angle between the inclined line G and the boundary line H is θ. Φ ′ _B is a voltage drop in the SBD Schottky junction and is expressed by the following equation (3).

Here, A ^* is an effective Richardson constant and is represented by the following equation (4).

Here, m ^* is an effective mass of electrons, q is an elementary charge of electrons, k is a Boltzmann constant, and h is a Planck constant.

As shown in Expression (2), the snapback voltage V _S is determined by (r _p , r _s ) regardless of the structure of the breakdown voltage maintaining layer 12. In addition, when r _p > (1 / tan θ), snapback does not occur. That is, whether snapback occurs or not depends only on r _p (= P / d).

FIG. 6 is a diagram obtained by simulation of the forward characteristics (current-voltage characteristics) when the width P of the PiN diode region is changed in the SiC semiconductor device 10 according to the present embodiment. Here, the thickness d of the n ⁻ breakdown voltage maintaining layer 12 is 100 μm, and the impurity concentration is 7 × 10 ¹⁴ cm ⁻³ . Further, the width P of the PiN diode region and the width S of the SBD region are set to the same value. The graphs indicated by arrows K ₁ , K ₂ , K ₃ , and K ₄ in the figure show forward characteristics when the width P of the PiN diode region is changed to 50 μm, 75 μm, 100 μm, and 150 μm, respectively. For comparison, the dotted line graph indicated by arrow A shows the forward characteristics when the SiC semiconductor element is composed of only a PiN diode.

  Here, the simulation was performed by commercially available software (“DESSIS”; manufactured by Synopsys) that simultaneously solves a two-dimensional Poisson equation and a two-dimensional current continuity equation (diffusion, drift).

As shown in FIG. 6, it can be seen that the width P of the PiN diode region is increased and the snapback phenomenon is suppressed. This is applied to the p ⁺ / n ⁻ junction constituting the PiN diode because the horizontal line H in FIG. 5 shifts downward and the voltage drop across the resistor R _2SP decreases as the width P of the PiN diode region increases. This is because the voltage rises.

FIG. 7 is a graph showing the results of calculating the P / d dependency of the snapback voltage V _S using the above equation (3) obtained from the current distribution model in the SiC semiconductor element 10 according to the present embodiment. . Note that the thickness d of the n ⁻ breakdown voltage maintaining layer 12 is two types, 100 μm and 150 μm, and the width P of the PiN diode region and the width S of the SBD region are the same. In addition, the lateral spreading angle of the current distribution during the operation of the SBD (in FIG. 5, the angle θ between the inclined line G and the boundary line H) was set to 42 °. It has been confirmed that this result is in good agreement with the above two-dimensional simulation result.

As shown in FIG. 7, it is understood that the snapback voltage V _S depends only on P / d regardless of the structure of the n ⁻ breakdown voltage maintaining layer 12. This thickness of the semiconductor region constituting the resistor _{R 2SP} in FIG. 5, given by d-Ptanθ, the negligible effect of this resistor _{R 2SP} is, d-Ptanθ = d, i.e. P / d = 1 This is because / tan θ.

Further, as shown in FIG. 7, when P / d ≧ 1, the snapback voltage V _S gradually approaches the diffusion potential (about 2.8 V) of the SiC pn junction. Therefore, the occurrence of the snapback phenomenon can be suppressed by setting P / d ≧ 1 (more preferably P / d ≧ 1.2).

As described above, the SiC semiconductor device according to the present embodiment includes the first region 20 in which the PiN diode is formed and the second region 21 in which the SBD is formed in parallel. By forming the p ⁺ region constituting the p ⁺ / n ⁻ junction with the p ⁺ epitaxial layer 13 having a mesa structure, a SiC semiconductor device having a low on-voltage, a high breakdown voltage, and a low loss can be realized. Can do.

Moreover, when the width of the first region 20 is P and the thickness of the n ⁻ breakdown voltage maintaining layer 12 is d, P / d ≧ 1 is achieved, thereby realizing an SiC semiconductor element that suppresses the occurrence of the snapback phenomenon. Can do.

  FIG. 8 is a cross-sectional view schematically showing a configuration of a prototype SiC semiconductor device. Note that the prototyped SiC semiconductor element has the basic configuration shown in FIG. 2 and further includes a configuration that satisfies characteristics required for use as an actual device.

As shown in FIG. 8, the prototype SiC semiconductor device includes a first region 20 in which a PiN diode is formed and a second region 21 in which an SBD is formed on an upper surface of an n ⁺ -type SiC substrate 11. Is formed.

Specifically, an n ⁻ breakdown voltage maintaining layer 12 made of SiC is formed on the upper surface of the n ⁺ SiC substrate 11. In the first region 20 where the PiN diode is formed, a p ⁺ epitaxial layer 13 made of SiC is selectively formed on the n ⁻ breakdown voltage maintaining layer 12. Furthermore, an anode electrode 14 a that is in ohmic contact with the bonding layer 30 is formed on the p ⁺ epitaxial layer 13. On the other hand, in the second region 21 in which the SBD is formed, an anode electrode 14 b having a Schottky junction is formed on the n ⁻ breakdown voltage maintaining layer 12. A cathode electrode 15 is formed on the back surface of the n ⁺ SiC substrate 11.

The p ⁺ epitaxial layer 13 has a mesa structure, and a low-concentration p ⁻ electric field relaxation region 31 is formed on the surface of the n ⁻ breakdown voltage maintaining layer 12 along the boundary between the first region 20 and the second region 21. Has been. Thereby, the p ⁻ electric field relaxation region 31 is depleted at the time of reverse bias, and the electric field concentration at the pn junction interface formed near the bottom of the mesa structure can be relaxed.

The SBD formed in the second region 21 has a junction barrier control Schottky structure in which a plurality of spaced apart p barrier regions 32 are formed on the surface of the n ⁻ breakdown voltage maintaining layer 12. Thereby, at the time of reverse bias, the p barrier region 32 can reduce the electric field strength at the Schottky interface, thereby reducing the leakage current at the time of reverse bias.

Furthermore, the outer peripheral portion 22 of the second region 21 where the SBD is formed is provided with a termination structure in which a plurality of p ion implantation regions 36 are formed on the surface of the n ⁻ breakdown voltage maintaining layer 12. Here, each p ion implantation region 36 is formed in the low-concentration p ⁻ ion implantation region 35 and gradually becomes narrower toward the outermost edge. By providing such a termination structure, the termination structure portion is gradually depleted from the inner side toward the outer peripheral portion during reverse bias, and the electric field concentration at the element end can be relaxed, and the breakdown voltage in the off state can be secured. .

FIG. 9 is a diagram showing basic characteristics (current-voltage characteristics) of a prototype SiC semiconductor device, where (a) shows forward characteristics and (b) shows reverse characteristics. Here, in FIG. 9A, the left vertical axis indicates the current value (logarithmic scale), and the right vertical axis indicates the current density. In the prototype SiC semiconductor device, the thickness d of the n ⁻ breakdown voltage maintaining layer 12 was 95 μm, and the impurity concentration was 6 × 10 ¹⁴ cm ⁻³ . Further, the width P of the PiN diode region and the width S of the SBD region were both 150 μm.

As shown in FIG. 9 (a), in the forward characteristics, the current rises as an SBD diode at about 0.8V, and then shifts to the operation mode of the PiN diode at about 3.5V. It was. No snapback phenomenon occurred when switching from the SBD operation mode (SBD mode) to the PiN diode operation mode (PiN mode) (P / d at this time is 1.05). As can be seen from the semilogarithmic plot of the current, the SBD characteristic is also almost ideal (ideal factor n = 1.01). Further, as shown in FIG. 9B, a high breakdown voltage of 11.3 kV was obtained in the reverse characteristics. This corresponds to a breakdown voltage of 85% of the ideal breakdown voltage (13.3 kV) calculated from the n ⁻ breakdown voltage maintaining layer 12.

FIG. 10 is a graph comparing the forward characteristics of the fabricated SiC semiconductor element with the forward characteristics of a PiN diode and an SBD fabricated independently on the same n ⁻ breakdown voltage maintaining layer 12. Here, the graph indicated by the solid line arrows M ₁ is, in the forward characteristics of the SiC semiconductor device of this embodiment, the graph shown by the dashed arrows A and B, a forward characteristic of the PiN diode and SBD. The structure of the PiN diode and SBD fabricated independently is the same as the structure of the PiN diode and SBD fabricated in the first region 20 and the second region 21 of the SiC semiconductor element in this embodiment. In addition, the area of the PiN diode and the SBD manufactured independently in a plan view is an area obtained by adding the areas of the first region 20 and the second region 21 of the SiC semiconductor element in the present embodiment.

  As shown in FIG. 10, the on-resistance in the SBD operation mode of the SiC semiconductor element according to the present embodiment is almost the same as the on-resistance of the SBD manufactured independently. This is because the area of the second region 21 in which the SBD is formed is half of the area of the SBD produced independently, but the current in the second region 21 spreads to the first region 20 in which the PiN diode is formed. Therefore, it is considered that the on-resistance was reduced.

On the other hand, the on-resistance in the operation mode of the PiN diode of the SiC semiconductor element according to the present embodiment was slightly larger than the on-resistance of the PiN diode fabricated independently. This is presumably because the on-resistance is increased because the region where the conductivity modulation effect is exhibited is reduced by the amount of the second region 21 where the SBD is formed. Therefore, the width P of the first region 20 PiN diode is formed by the SBD is greater than the width S of the second region is formed (P> S), shown by a dashed line arrow M ₂ As shown in the graph, the on-resistance in the operation mode of the PiN diode can be made closer to the on-resistance of the PiN diode manufactured independently.

11, the forward characteristics of the SiC semiconductor device fabricated, the same on the surface of the n ^- breakdown voltage sustaining layer 12, the SiC semiconductor device of a hybrid structure to produce a planar PiN diode to form a p ⁺ layer by ion implantation ( It is a graph compared with the forward characteristics of the same SBD structure. Here, a graph indicated by an arrow M is a forward characteristic of the SiC semiconductor device according to the present embodiment, and a graph indicated by an arrow N is an SiC semiconductor device including a planar PiN diode in which a pn junction is formed by ion implantation. Is the forward characteristic.

As shown in FIG. 11, the on-resistance in the operation mode of the PiN diode of the SiC semiconductor element in the present embodiment was significantly smaller than the on-resistance of the SiC semiconductor element provided with the planar PiN diode. This is because a large number of induced defects are generated by ion implantation in the p ⁺ ion implantation layer of the planar type PiN diode, thereby reducing the lifetime of the minority carriers and increasing the on-resistance in the operation mode of the PiN diode. it is conceivable that. On the other hand, since the p ⁺ epitaxial layer of the PiN diode in this embodiment has no induced defects due to ion implantation, a high conductivity modulation effect can be maintained, and as a result, a low on-resistance can be realized. did it.

  12A to 12E are cross-sectional views showing a method for manufacturing an SiC semiconductor device according to the present embodiment.

As shown in FIG. 12A, an n ⁻ type (first conductivity type) SiC breakdown voltage maintaining layer 12 made of SiC is epitaxially grown on one main surface of an n ⁺ type (first conductivity type) SiC substrate 11. Form with. Here, for example, a 4H—SiC single crystal substrate can be used as the SiC substrate 11. In addition, the n ⁻ breakdown voltage maintaining layer 12 preferably has, for example, an impurity concentration in the range of 1 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ⁻³ . Moreover, the thickness of the n ⁻ withstand voltage maintaining layer 12 is preferably in the range of 30 to 300 μm.

Next, as shown in FIG. 12B, an epitaxial layer 13 made of p ⁺ (second conductivity type) SiC is formed on the n ⁻ breakdown voltage maintaining layer 12 by epitaxial growth. Here, the p ⁺ epitaxial layer 13 preferably has an impurity concentration in the range of 1 × 10 ^{18 to} 3 × 10 ²⁰ cm ⁻³ , for example. The thickness of the p ⁺ epitaxial layer 13 is preferably in the range of 0.3 to 6 μm.

Next, as shown in FIG. 12C, a part of the p ⁺ epitaxial layer 13 (second region 21) is selectively removed by etching to expose the n ⁻ breakdown voltage maintaining layer 12a. Etching is performed by, for example, reactive ion etching using a mixed gas of CF ₄ and O ₂ by forming an oxide film on a part of the p ⁺ epitaxial layer 13 (first region 20) and using this oxide film as a mask. be able to. By this etching, the p ⁺ epitaxial layer 13a remaining in the first region 20 has a mesa structure. Further, the etching is preferably an etching that is not strongly anisotropic, and as a result, the p ⁺ epitaxial layer 13a has a mesa structure with a slightly inclined side wall.

Next, as shown in FIG. 12D, along the boundary between the remaining p ⁺ epitaxial layer 13a and the exposed n ⁻ breakdown voltage maintaining layer 12a (the boundary between the first region 20 and the second region 21). The p ⁻ type (second conductivity type) electric field relaxation region 31 having a lower concentration than the p ⁺ epitaxial layer is formed on the surface of the n ⁻ breakdown voltage maintaining layer 12 by ion implantation. The p ⁻ electric field relaxation region 31 can be formed by ion implantation of aluminum (Al), for example.

When a termination structure is provided on the outer peripheral portion 22 of the second region (SBD region) 21 shown in FIG. 8, the p ⁻ ion implantation region 35 is formed by ion implantation simultaneously with the p ⁻ electric field relaxation region 31. Also good.

In the case where the p ⁺ epitaxial layer 13a is formed in a mesa structure with substantially vertical sidewalls, along the boundary between the first region 20 and the second region 21 by oblique ion implantation on the surface of the n ⁻ breakdown voltage maintaining layer 12. Thus, the p ⁻ electric field relaxation region 31 can be formed.

Next, as shown in FIG. 12E, a first electrode 14a that forms an ohmic junction is formed on the p ⁺ epitaxial layer 13a, and a second electrode 14b that forms a Schottky junction is formed on the exposed n ⁻ breakdown voltage maintaining layer 12a. Form. In addition, third electrode 15 is formed on the other main surface of SiC substrate 11. Here, the first electrode 14a and the second electrode 14b can be integrally formed of, for example, titanium (Ti). In this case, in order to achieve ohmic contact between the ^{p +} epitaxial layer 13a, ^{p +} on the epitaxial layer 13a, for example, bonding layer and made of an alloy of titanium and aluminum (Al), a stacked structure of titanium and aluminum (Ti / Al) (not shown) is preferably formed in advance. As a result, the first electrode 14 a is ohmic-contacted with the p ⁺ epitaxial layer 13 via the bonding layer, and the second electrode 14 b is Schottky-bonded with the n ⁻ breakdown voltage maintaining layer 12. The third electrode 15 can be formed of nickel (Ni), for example. Thereby, the third electrode 15 is in ohmic contact with the n ⁺ SiC substrate 11.

  As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course various modifications are possible.

  For example, in the above embodiment, as shown in FIG. 2B, the second region 21 in which the SBD is formed is formed so as to surround the first region 20 in which the PiN diode is formed. Instead, the first region 20 and the second region 21 may have any shape as long as the first region 20 and the second region 21 are formed in parallel in a plan view.

  FIG. 13 is a plan view showing a modification of the SiC semiconductor element in the present embodiment.

  As shown in FIG. 13, the first region 20 in which the PiN diode is formed has an elongated shape, and a plurality of the first regions 20 are arranged apart from each other in parallel. The second region 21 in which the SBD is formed is formed surrounding the plurality of first regions 20. By configuring the first region 20 and the second region 21 in this way, a forward voltage can be reliably applied to the first region 20 constituting the PiN diode, and the snapback phenomenon can be suppressed, and a large number of elements can be connected in parallel. A large current can be obtained by the operation.

  As shown in FIG. 13, the width P of the first region 20 in the present modification is ½ of the width of the short side in the first region 20. Further, the width S of the second region 21 is ½ of the distance between the adjacent first regions 20.

  FIG. 14 is a plan view showing another modification of the SiC semiconductor device according to the present embodiment.

  As shown in FIG. 14, the 1st area | region 20 in which a PiN diode is formed consists of a rectangle, and this is arranged in multiple numbers in zigzag form. The second region 21 in which the SBD is formed is formed surrounding the plurality of first regions 20. By configuring the first region 20 and the second region 21 in this way, a forward voltage can be reliably applied to the first region 20 constituting the PiN diode, and the snapback phenomenon can be suppressed, and a large number of elements can be connected in parallel. A large current can be obtained by the operation.

  As shown in FIG. 14, the width P of the first region 20 in the present modification is ½ of the width of the short side in the first region 20. Further, the width S of the second region 21 is ½ of the minimum distance between the adjacent first regions 20.

  In addition, the shape of the 1st area | region 20 in this embodiment is not limited to a rectangle, A polygon, circle, and an ellipse may be sufficient. In this case, the width P of the first region 20 is ½ of the minimum distance between two opposing sides (or points) at the outer periphery of the first region 20.

  In the above embodiment, as shown in FIG. 8, the SBD of the prototype SiC semiconductor element has a junction barrier control Schottky structure. However, the structure of the SBD is not limited to this and is of another structure. It may be. Further, although the termination structure is provided on the outer peripheral portion 22 of the second region (SBD region) 21, the configuration is not particularly limited, and the termination structure is not necessarily provided.

10 SiC semiconductor device
11 SiC substrate
12 Withstand voltage maintenance layer
13 Epitaxial layer
14a First electrode (anode electrode)
14b Second electrode (anode electrode)
15 Third electrode (cathode electrode)
20 First region
21 Second area
22 outer periphery
30 bonding layers
31 Electric field relaxation region
32 Barrier area
33 Oxide film 34 Surface protective film 35, 36 Ion implantation region

Claims (10)

A SiC semiconductor in which a first region in which a PiN diode is formed and a second region in which a Schottky barrier diode (SBD) is formed are formed in parallel on one main surface of a first conductivity type SiC substrate. An element,
A breakdown voltage maintaining layer made of SiC of the first conductivity type is formed on one main surface of the SiC substrate,
In the first region, an epitaxial layer made of SiC of the second conductivity type is selectively formed on the breakdown voltage maintaining layer, and an ohmic junction first electrode is formed on the epitaxial layer. ,
In the second region, a second electrode having a Schottky junction is formed on the breakdown voltage maintaining layer,
A third electrode is formed on the other main surface of the SiC substrate,
The SiC semiconductor element, wherein the first electrode and the second electrode are electrically conductive.   2. The SiC semiconductor device according to claim 1, wherein P / d ≧ 1 is satisfied, where P is a width of the first region and d is a thickness of the breakdown voltage maintaining layer.   The SiC semiconductor device according to claim 2, wherein P ≧ S is satisfied, where S is a width of the second region in parallel with the first region.   The SiC semiconductor element according to claim 1, wherein the second region is formed so as to surround the first region in plan view.   The electric field relaxation region of the second conductivity type having a concentration lower than that of the epitaxial layer is formed on the surface of the breakdown voltage maintaining layer along a boundary between the first region and the second region. The SiC semiconductor element of description.   The SiC semiconductor device according to claim 1, wherein the PiN diode has a mesa structure.   2. The SiC according to claim 1, wherein in the second region, a plurality of second conductivity type barrier regions are formed on a surface of the breakdown voltage maintaining layer, and the SBD has a junction barrier control Schottky structure. Semiconductor element. A method for producing a SiC semiconductor device according to any one of claims 1 to 7,
A step (a) of forming a breakdown voltage maintaining layer made of SiC of the first conductivity type on one main surface of the SiC substrate of the first conductivity type by epitaxial growth;
Forming an epitaxial layer made of SiC of the second conductivity type on the breakdown voltage maintaining layer by epitaxial growth; and
A step (c) of selectively removing a part of the epitaxial layer by etching to expose the breakdown voltage maintaining layer;
Forming a first electrode that forms an ohmic junction on the epitaxial layer and forming a second electrode that forms a Schottky junction on the exposed breakdown voltage maintaining layer.   The method for manufacturing an SiC semiconductor device according to claim 8, wherein the epitaxial layer remaining after etching in the step (c) has a mesa structure. After the step (c) and before the step (d), the surface of the breakdown voltage maintaining layer is ion-implanted along the boundary between the remaining epitaxial layer and the exposed breakdown voltage maintaining layer by ion implantation. 10. The method of manufacturing an SiC semiconductor device according to claim 8, wherein the electric field relaxation region of the second conductivity type having a lower concentration than the epitaxial layer is formed.

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