JP2018005751A - Tester of information processor and test method of information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tester of information processor capable of reliably and swiftly carrying out system verification, and a test method of information processor.SOLUTION: The tester of information processor including plural CPUs each of which has a DIMM 40 as a main storage unit and a transmission buffer part 202, which includes: a dummy data writing part 22; and a dummy packet transmission control unit 24. The dummy data writing part 22 writes a piece of dummy data on the transmission buffer part 202. The dummy packet transmission control unit 24 gives an instruction to a specific CPU 10 to continuously transmit the dummy data written in the transmission buffer part 202 to another CPU.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an information processing apparatus testing apparatus and an information processing apparatus testing method.

  In recent years, the amount of circuits that can be mounted in a unit area of LSI (Large Scale Integration) has been increasing rapidly due to advances in semiconductor processes. Furthermore, along with the increase in circuit amount, the trend of miniaturization of semiconductor processes in various circuits is remarkable. As the semiconductor process is miniaturized and the circuit amount is increased, the complexity and complexity of logic circuit design and verification or actual machine verification are increased. Therefore, the development man-hours related to verification can be a major factor that increases the system development man-hours.

  Further, in the information processing apparatus, the storage capacity of the main memory has increased as the processing speed increases and the processing data increases. For this reason, memory modules such as DIMM (Dual Inline Memory Module) and HMC (Hardware Management Control) have been increasingly used.

  For example, in a DMA (Direct Memory Access) test, a test around an interconnect circuit that connects CPUs (Central Processing Units) may be performed. Conventionally, when performing this test, a TAS (Transmit Assemble) that generates a packet to be sent to the interconnect circuit receives the packet transmission request, accesses the memory that is the main storage device, acquires the data, and stores the data in the buffer To do. Thereafter, the TAS reads the data from the buffer to generate a packet, and performs the test by transmitting the packet to another CPU via the interconnect circuit. Thus, in the test around the interconnect circuit, access to the main storage device may occur.

  Here, in the manufacturing process of the memory module, an inspection is performed at the stage where the wafer has been manufactured, a defective memory cell is identified, and the defective memory is replaced by a redundant memory cell formed in advance on the same wafer. Remedy is taken. In spite of such relief measures being taken, the yield in the manufacture of memory modules tends to become worse with the recent subdivision of memory cells.

  As a test technique in the information processing apparatus, there is a conventional technique in which a link layer device periodically generates a test signal, and generates and transmits a cycle start packet based on the test signal.

JP 2001-289913 A

  However, due to the deterioration of the yield of the memory module, there is a high possibility that an unrecoverable error (UE: Uncorrectable Error) will occur when accessing the main storage device. If an error that can be repaired occurs when accessing the main storage device, the system verification may be delayed, for example, the test program is terminated.

  In addition, even when using the conventional technology that performs the test using the link layer device, access to the memory module occurs, so the verification may be delayed due to the failure of the memory module. Have difficulty.

  The disclosed technology has been made in view of the above, and an object of the present invention is to provide an information processing apparatus test apparatus and an information processing apparatus test method that reliably perform quick system verification.

  In one aspect of the information processing apparatus testing apparatus and the information processing apparatus testing method disclosed in the present application, the information processing apparatus includes a plurality of arithmetic units including a main storage device and a transmission buffer. An information processing apparatus testing apparatus that tests an information processing apparatus includes a dummy data writing unit that writes dummy data to the transmission buffer. In addition, the test apparatus of the information processing apparatus includes a transmission control unit that instructs the arithmetic device to continuously transmit the dummy data written in the transmission buffer.

  According to one aspect of the information processing apparatus testing apparatus and the information processing apparatus testing method disclosed in the present application, there is an effect that rapid system verification can be surely performed.

FIG. 1 is a hardware configuration diagram of a system board. FIG. 2 is a block diagram of the service processor and TAS. FIG. 3 is a diagram illustrating an exemplary format of a dummy packet. FIG. 4 is a diagram illustrating an example of the format of the status register. FIG. 5 is a diagram illustrating an example of a format of the dummy packet information register. FIG. 6 is a diagram illustrating an example of a dummy packet transmission start register. FIG. 7 is a flowchart of packet transmission test processing.

  Embodiments of an information processing apparatus testing apparatus and an information processing apparatus testing method disclosed in the present application will be described below in detail with reference to the drawings. The information processing apparatus test apparatus and the information processing apparatus test method disclosed in the present application are not limited to the following embodiments.

  FIG. 1 is a hardware configuration diagram of a system board. A system board (SB) 1 shown in FIG. 1 is mounted on an information processing apparatus such as a server. The system board 1 includes, for example, a CPU 10, a service processor (SP) 20, a memory controller 30, and a DIMM 40.

  In this embodiment, a plurality of CPUs 10 which are arithmetic devices are mounted on one system board 1. Here, although two CPUs 10 are described in FIG. 1, the number of CPUs 10 may be more than two. The CPUs 10 are connected by an interconnect 15. The CPU 10 is connected to the memory controller 30.

  The CPU 10 includes a core 11 and an interconnect controller (ICC) 100. Here, in FIG. 1, a state in which one core 11 is mounted on one CPU 10 is described. However, the present invention is not limited to this, and a plurality of cores 11 may be mounted on one CPU 10.

  The core 11 is connected to the interconnect controller 100. The core 11 transmits a data read / write command to the DIMM 40 to the memory controller 30. As a result, the core 11 reads / writes data from / to the DIMM 40 via the memory controller 30.

  The interconnect controller 100 includes a transmission / reception circuit 101, a crossbar switch (XB: Crossbar) 102, a data link control circuit 103, and a SerDes (Serializer Deserializer) 104.

  In this embodiment, a plurality of transmission / reception circuits 101 are arranged on one interconnect controller 100. The transmission / reception circuit 101 communicates with another interconnect controller 100 via the interconnect 15. Thus, the transmission / reception circuit 101 realizes communication between the CPU 10 on which the transmission / reception circuit 101 is mounted and another CPU 10.

  The transmission / reception circuit 101 includes a TAS 111 and an RBF (Receive Buffer) 112. The TAS 111 controls packet transmission. The RBF 112 controls packet reception. The TAS 111 will be described in detail later.

  The crossbar switch 102 is a switch that connects the transmission / reception circuit 101 and the data link control circuit 103. The crossbar switch 102 switches a path for connecting the transmission / reception circuit 101 and the data link control circuit 103 according to the destination of the packet transmitted from the transmission / reception circuit 101.

  In the present embodiment, a plurality of data link control circuits 103 are arranged on one interconnect controller 100. The data link control circuit 103 performs processing in the data link layer on the packet input from the crossbar switch 102 and outputs the packet to the SirDes 104. Conversely, the data link control circuit 103 performs processing in the data link layer on the packet input from the SerDes 104 and outputs the packet to the crossbar switch 102.

  One SerDes 104 is arranged so as to correspond to each data link control circuit 103. Further, the SerDes 104 is connected to the SerDes 104 of another interconnect controller 100 via the interconnect 15.

  The SerDes 104 converts the packet received from the data link control circuit 103 into a serial signal. Then, the SerDes 104 transmits the packet converted into the serial signal to the SerDes 104 of another CPU 10 via the interconnect 15. In addition, the SerDes 104 receives a packet transmitted from the SerDes 104 of another CPU 10 via the interconnect 15. Then, the SerDes 104 converts the received packet into a parallel signal and transmits it to the data link control circuit 103.

  The interconnect 15 connects the SerDes 104 to each other. Here, although one interconnect 15 is described as an example in FIG. 1, the interconnect 15 is actually arranged so as to extend from each SerDes 104 to a plurality of SerDes 104.

  The memory controller 30 is connected to each CPU 10 mounted on the system board 1. The memory controller 30 receives data read and write commands from the core 11 for the DIMM 40. Then, the memory controller 30 reads and writes data from and to the DIMM 40 according to instructions from the core 11.

  When executing DMA, the memory controller 30 receives a data read command from the TAS 111 of the transmission / reception circuit 101. Then, the memory controller 30 reads the designated data from the DIMM 40 and transmits it to the TAS 111.

  The DIMM 40 is a main storage device. The DIMM 40 outputs data stored under the control of the memory controller 30. The DIMM 40 stores data under the control of the memory controller 30. For example, when data transmission is performed, the data is read from the DIMM 40 and the read data is transmitted to the other CPU 10.

  The service processor 20 is connected to each CPU 10 mounted on the system board 1. Then, the service processor 20 monitors and controls each CPU 10 such as disabling the interconnect controller 100.

  Next, referring to FIG. 2, a test around the interconnect 15 related to DMA will be described. FIG. 2 is a block diagram of the service processor and TAS.

  The service processor 20 receives a packet transmission test start command from an external device connected to the information processing device on which the system board 1 is mounted. Then, the service processor 20 executes a packet transmission test. Here, in the packet transmission test, a packet is transmitted from one CPU 10 and received by another CPU 10. As a result, it is possible to verify the transmission quality of the route connecting from the TAS 111 of the interconnect controller 100 on the transmission side to the RBF 112 of the interconnect controller 100 on the reception side. Specifically, the TAS 111, the data link control circuit 103, and the SerDes 104 of the interconnect controller 100 on the transmission side can be verified. In addition, the interconnect 15 can be verified. Further, the SerDes 104, the data link control circuit 103, and the RBF 112 of the interconnect controller 100 on the receiving side can be verified. Thereafter, the service processor 20 monitors the TAS controller 125, and when the transmission of all dummy data is completed, the packet transmission test is completed.

  Here, the service processor 20 has an interface for directly reading from and writing to an SRAM (Static Random Access Memory) mounted in a transmission buffer unit 202 described later. The service processor 20 investigates a failure in the SRAM of the transmission buffer unit 202 and writes a dummy packet during a packet transmission test through this interface.

  The service processor 20 includes a state management unit 21, a dummy data writing unit 22, a packet information setting unit 23, and a dummy packet transmission control unit 24. The service processor 20 is an example of an “information processing apparatus test apparatus”.

  When the packet transmission test is started, the state management unit 21 sets the state register 121 so that packet transmission / reception in the TAS 111 becomes invalid. Thereby, transmission / reception of the packet by TAS111 is stopped.

  Further, the state management unit 21 sets the dummy packet transmission operation register 122 so that the dummy packet transmission operation becomes valid when the dummy data writing unit 22 described later completes the writing of the dummy packet.

  After that, when the packet transmission test is completed, the state management unit 21 sets the dummy packet transmission operation register 122 so that the dummy packet transmission operation is invalidated, and sets the state register 121 so that packet transmission / reception in the TAS 111 is valid. Set. The state management unit 21 is an example of an “operation stop unit”.

  The dummy data writing unit 22 has dummy data including a packet header and a payload of a dummy packet in advance. When the status register 121 is set by the status management unit 21 so that packet transmission / reception in the TAS 111 is invalidated, the dummy data writing unit 22 writes the dummy data in the header area 221 of the transmission buffer unit 202.

  FIG. 3 is a diagram illustrating an exemplary format of a dummy packet. As shown in the format 300, the dummy packet has a packet header 301, a payload 302, and an ECRC (End-to-end Cyclic Redundancy Check) 303. In this embodiment, the dummy data writing unit 22 writes dummy data including the packet header 301 and the payload 302 in the header area 221 of the transmission buffer unit 202.

  When the dummy packet transmission operation register 122 is set so that the dummy packet transmission operation is enabled by the state management unit 21, the packet information setting unit 23 sets information on a packet to be transmitted in the dummy packet information register 123. Specifically, the packet information setting unit 23 sets the packet length of the packet to be transmitted, the destination, the validity / invalidity of error generation, and the like in the dummy packet information register 123.

  The dummy packet transmission control unit 24 sets the dummy packet transmission start register 124 so that dummy packet transmission is enabled when the packet information to be transmitted by the packet information setting unit 23 is set in the dummy packet information register 123.

  Thereafter, when the packet transmission test is completed, the dummy packet transmission control unit 24 sets the dummy packet transmission start register 124 so that the dummy packet transmission becomes invalid. The dummy packet transmission control unit 24 is an example of a “transmission control unit”.

  The TAS 111 includes a status register 121, a dummy packet transmission operation register 122, a dummy packet information register 123, and a dummy packet transmission start register 124. The TAS 111 includes a TAS controller (TC: TAS Controller) 125, a packet transmission circuit (PS: Packet Send) 126, and a payload acquisition (PA: Payload Acquire) unit 127.

  The status register 121 is a register that determines validity / invalidity of transmission / reception of a packet of the TAS 111. FIG. 4 is a diagram illustrating an example of the format of the status register. A value 211 represents a bit number in the status register 121. A value 212 is a value representing validity / invalidity of transmission / reception of a packet of the TAS 111. In this embodiment, when the value 212 is “1”, the transmission / reception of the packet of the TAS 111 becomes invalid. When the value 212 is “0”, transmission / reception of the packet of the TAS 111 is valid. A value 213 is a bit number in an area where transmission / reception of a packet of the TAS 111 is set. Information 214 represents information determined by the status register 121. “E” represents “Enable” and indicates that this register is a register representing the validity / invalidity of transmission / reception of a packet of the TAS 111. For example, when the packet transmission test is started, the value 212 of the status register 121 is set to “1” by the status management unit 21.

  The dummy packet transmission operation register 122 is a register representing the validity / invalidity of the dummy packet transmission operation. FIG. 5 is a diagram illustrating an example of a format of the dummy packet information register. An area 231 represents a virtual channel (VC). The virtual channel used for transmission of the dummy packet is designated by each bit of the value 232 set by the packet information setting unit 23. An area 233 represents a port (PORT). Each bit of the value 234 set by the packet information setting unit 23 specifies a port used for transmission of the dummy packet. An area 235 represents a packet length (LEN: length). The packet length of the dummy packet is designated by each bit of the value 236 set by the packet information setting unit 23. An area 237 sets whether or not to execute error generation (EG). By setting the value 238 by the packet information setting unit 23, it is determined whether or not an error is included in the dummy packet. When the value 238 is “0”, the ECRC added to the dummy packet is left as it is. When the value 238 is “1”, the ECEC added to the dummy packet is destroyed, for example, by being inverted.

  The dummy packet transmission start register 124 is a register for starting transmission of a dummy packet. FIG. 6 is a diagram illustrating an example of a dummy packet transmission start register. A value 241 represents whether or not to start transmission of a dummy packet. When the value 241 is “0”, transmission of the dummy packet is stopped. If the value 241 is “1”, transmission of a dummy packet is started. For example, when the packet transmission test is executed, the value 241 of the dummy packet transmission start register 124 is set to “1” by the dummy packet transmission control unit 24. Further, “S” in FIG. 6 represents Start and indicates that this register is a register indicating whether or not to start transmission of a dummy packet.

  A plurality of TAS controllers 125 are mounted on the TAS 111. The TAS controller 125 includes a command receiving unit (CR: Command Receive) 201, a transmission buffer unit (TB: Transmit Buffer) 202, and a transmission request unit (TR: Transmit Request) 203.

  The transmission buffer unit 202 is realized by an SRAM, for example. The transmission buffer unit 202 is a temporary storage area for temporarily storing the packet header and payload of a packet to be transmitted when the packet cannot be transmitted immediately due to arbitration waiting or the like during packet transmission. The transmission buffer unit 202 has a header area 221 for storing a packet header and a payload area 222 for storing a payload in the case of normal packet transmission. The header area 221 corresponds to an example of “additional information writing area”. The payload area 222 corresponds to an example of “data writing area”.

  The instruction receiving unit 201 includes an FSM (Finite State Machine) 210. The FSM 210 executes processing by the transition of the state transition, and realizes the operation of the TAS controller 125. In other words, the TAS controller 125 executes various processes as the state of the FSM 210 transitions. That is, if the state transition of the FSM 210 is stopped, the TAS controller 125 stops the process.

  Here, the processing executed by each unit of the TAS controller 125 will be described as the operation of each unit, but in actuality, the processing is executed by the state transition of the FSM 210. However, as will be described later, when the FSM 230 arranged in the transmission request unit 203 changes state and executes the process of the transmission request unit 203, the process is performed without changing the state of the FSM 210.

  When the dummy packet transmission operation register 122 sets the dummy packet transmission operation to invalid, the command reception unit 201 performs a normal operation. For example, when performing DMA transmission of a packet, the command receiving unit 201 receives a packet transmission command and a packet header from the transmission control unit 131. This packet transmission command corresponds to an example of “transmission request”. Then, the command receiving unit 201 determines whether to use a payload for generating a packet to be transmitted in accordance with the received packet transmission command. When using the payload, the command receiving unit 201 requests the payload acquisition unit 127 to issue a payload request. The command receiving unit 201 stores the received packet header in the header area 221 of the transmission buffer unit 202. This packet header corresponds to an example of “additional information”.

  Thereafter, the command receiving unit 201 receives a packet transmission completion notification from the transmission request unit 203. When receiving the packet transmission completion notification, the instruction receiving unit 201 changes the state of the FSM 210 and shifts the TAS controller 125 to the next stage of the next packet transmission process.

  Further, when the dummy packet transmission operation is set to be valid in the dummy packet transmission operation register 122, the update of the FSM 210 of the instruction receiving unit 201 is suppressed. That is, the state transition of the FSM 210 is stopped. Thereby, the processing of each part of the TAS controller 125 including the instruction receiving unit 201 is stopped. In this case, as described later, after transmitting the dummy packet, the command receiving unit 201 receives a packet transmission completion notification from the transmission requesting unit 203. However, when the packet transmission test is executed, the update of the FSM 210 of the instruction receiving unit 201 accompanying the packet transmission completion notification is suppressed, so the TAS controller 125 does not move to the next stage of the packet transmission process.

  The transmission request unit 203 has an FSM 230. The FSM 230 executes processing by the transition of the state transition, and realizes the operation of the transmission request unit 203. In other words, when the state of the FSM 230 changes, the FSM 230 executes packet transmission processing. The transmission request unit 203 stops its operation when the update of the FSM 210 of the command receiving unit 201 is suppressed. However, even in this state, if the update of the FSM 230 is started, the transmission request unit 203 resumes the operation. That is, when the dummy packet transmission operation is set to be invalid in the dummy packet transmission operation register 122, the transmission request unit 203 executes the process by the state transition of the FSM 210. Further, when the dummy packet transmission operation is set to be valid in the dummy packet transmission operation register 122, the transmission request unit 203 executes processing by the state transition of the FSM 230.

  When the dummy packet transmission operation is set to be invalid in the dummy packet transmission operation register 122, the transmission request unit 203 performs a normal operation. Specifically, when the transmission request unit 203 confirms that the header and the payload are stored in the header region 221 and the payload region 222 of the transmission buffer unit 202, the transmission request unit 203 reads the header from the header region 221, and then loads the payload region 222. Read payload from. Then, the transmission request unit 203 generates a packet using the read header and payload. Next, the transmission request unit 203 transmits the generated packet to the packet transmission circuit 126.

  Thereafter, the transmission request unit 203 receives a packet transmission completion notification from the packet transmission circuit 126. Then, the transmission request unit 203 transmits a packet transmission completion notification to the command receiving unit 201.

  When the dummy packet transmission operation is set valid in the dummy packet transmission operation register 122, the transmission request unit 203 performs a packet transmission test operation. Specifically, the transmission request unit 203 checks the dummy packet transmission start register 124. If the transmission start of the dummy packet is valid in the dummy packet transmission start register 124, the transmission request unit 203 acquires the dummy packet information from the dummy packet information register 123.

  Next, the transmission request unit 203 transmits a packet data read request to the transmission buffer unit 202. Then, the transmission request unit 203 reads out dummy data including the header and payload of the dummy packet from the header area 221 according to the information of the dummy packet. Next, the transmission request unit 203 generates a dummy packet using the read dummy data. In this embodiment, since the payload area 222 is not used, the transmission request unit 203 can generate a dummy packet with the dummy data read from the header area 221. That is, the transmission request unit 203 can generate a dummy packet more easily than when the header of the dummy packet is written in the header area 221 and the payload of the dummy packet is written in the payload area 222. At this time, when ECRC destruction is specified in the acquired dummy packet information, the transmission request unit 203 generates a pseudo-destroyed packet by inverting the generated ECRC. In addition, the transmission request unit 203 does not transmit a packet having a packet length different from the packet length set by the dummy packet information.

  Thereafter, the transmission request unit 203 transmits the dummy packet generated for the port and virtual channel specified by the acquired dummy packet information to the packet transmission circuit 126. The transmission request unit 203 checks the dummy packet transmission start register 124 when the packet transmission circuit 126 starts transmission of the dummy packet. Since the dummy packet transmission start register 124 is fixed in a state where the dummy packet transmission operation is set to be valid, the transmission request unit 203 immediately reads the next dummy data from the header area 221. Then, the transmission request unit 203 generates a dummy packet and transmits it to the packet transmission circuit 126. As a result, the transmission request unit 203 can perform continuous transmission of dummy packets. Thereafter, the transmission request unit 203 receives a packet transmission completion notification from the packet transmission circuit 126 by transmitting a dummy packet. Then, the transmission request unit 203 transmits a packet transmission completion notification to the command receiving unit 201. The transmission request unit 203 is an example of a “transmission unit”.

  The packet transmission circuit 126 receives a packet transmitted from the transmission request unit 203 of each TAS controller 125. Then, the packet transmission circuit 126 performs arbitration on each received packet and selects a packet that has won the arbitration. Thereafter, the packet transmission circuit 126 transmits a transmission request for the selected packet to the crossbar switch 102. Thereafter, when a packet transmission permission notification is received from the crossbar switch 102, the packet transmission circuit 126 transmits the selected packet to the crossbar switch 102. When transmitting a packet, the packet transmission circuit 126 issues a packet transmission completion notification to the transmission request unit 203 that is the output source of the packet.

  The payload acquisition unit 127 receives a request for issuing a payload request from the command reception unit 201. Then, the payload acquisition unit 127 issues a payload request specified by the issue request to the DMA control unit 132. Thereafter, the payload acquisition unit 127 acquires the payload read from the DIMM 40 as a response to the issued payload request from the DMA control unit 132. Then, the payload acquisition unit 127 stores the acquired payload in the payload area 222 of the transmission buffer unit 202. The command receiving unit 201 and the payload acquisition unit 127 are an example of a “data acquisition unit”.

  The transmission control unit 131 is realized by the core 11. The transmission control unit 131 transmits the packet transmission command and the packet header to the command receiving unit 201.

  The DMA control unit 132 is realized by the memory controller 30. The DMA control unit 132 receives the payload request issued by the command receiving unit 201. Then, the DMA control unit 132 reads the payload specified by the received payload request from the DIMM 40. Thereafter, the DMA control unit 132 transmits the read payload to the payload acquisition unit 127 as a response to the payload request.

  The crossbar switch 102 receives a packet transmission request from the packet transmission circuit 126. If the packet that has received the transmission request can be transmitted, the crossbar switch 102 transmits a transmission permission to the packet transmission circuit 126. Thereafter, the crossbar switch 102 receives from the packet transmission circuit 126 the packet for which the transmission permission has been notified. Then, the crossbar switch 102 transmits the received packet to the data link control circuit 103.

  Here, the CPU 10 on the receiving side will be briefly described. In the case of the packet transmission test, the status register 121 is set in the TAS 111 of the CPU 10 on the receiving side in an invalid state of packet transmission / reception. Therefore, the RBF 112 on the receiving side discards the dummy packet received after the verification by the core 11 is completed.

  In the case of the packet transmission test, the core 11 of the CPU 10 on the receiving side performs verification using the received dummy packet. The core 11 is an example of a “verification unit”.

  Next, the flow of the packet transmission test process will be described with reference to FIG. FIG. 7 is a flowchart of packet transmission test processing.

  When the service processor 20 receives an instruction to start a packet transmission test, the state management unit 21 sets the state register 121 so that transmission / reception of the packet of the TAS 111 is invalidated (step S1).

  Next, the dummy data writing unit 22 writes dummy data including the packet header and payload of the dummy packet in the header area 221 of the transmission buffer unit 202 (step S2).

  Next, the state management unit 21 sets the dummy packet transmission operation register 122 to “1” (step S3). That is, the state management unit 21 sets the dummy packet transmission operation register 122 so that the dummy packet transmission operation becomes valid.

  The packet information setting unit 23 sets dummy packet information including information on packet length, destination, and necessity of error generation in the dummy packet information register 123 (step S4).

  Next, the dummy packet transmission control unit 24 sets the dummy packet transmission start register 124 to “1” (step S5). That is, the dummy packet transmission control unit 24 sets the dummy packet transmission start register 124 so that transmission of the dummy packet is started.

  When the dummy packet transmission start register 124 is set to “1”, the transmission request unit 203 acquires dummy packet information from the dummy packet information register 123. The transmission request unit 203 transmits a dummy data read request to the transmission buffer unit 202 (step S6).

  Next, the transmission request unit 203 reads the dummy data from the header area 221 of the transmission buffer unit 202 according to the information of the dummy packet (step S7).

  Next, the transmission request unit 203 calculates ECRC or the like and assigns the packet to the packet to generate a dummy packet (step S8). Then, the transmission request unit 203 transmits the generated dummy packet to the packet transmission circuit 126.

  The packet transmission circuit 126 receives a dummy packet from the transmission request unit 203. Then, the packet transmission circuit 126 arbitrates each received packet. Thereafter, the packet transmission circuit 126 transmits a transmission request for the packet that has won the arbitration to the crossbar switch 102 (step S9).

  Thereafter, the packet transmission circuit 126 receives a notification of packet transmission permission (step S10). When receiving the transmission permission notification, the packet transmission circuit 126 transmits the packet to the crossbar switch 102 (step S11).

  When packet transmission from the packet transmission circuit 126 to the crossbar switch 102 is started, the transmission request unit 203 determines whether transmission of all dummy packets is completed (step S12). If transmission of all dummy packets has not been completed (No at Step S12), the transmission request unit 203 determines whether or not the dummy packet transmission start register 124 is set to “0” (Step S13). When the dummy packet transmission start register 124 is “1” (No at Step S13), the transmission request unit 203 returns to Step S6.

  On the other hand, when the dummy packet transmission start register 124 is “0” (step S13: Yes), the transmission request unit 203 ends the dummy packet transmission process, and the packet transmission test process ends. However, since the dummy packet transmission start register 124 is set to “1” and fixed at this stage of the packet transmission test, it is unlikely that the process follows this route. The confirmation process of the dummy packet transmission start register 124 in step S13 is a process for confirmation only in the packet transmission test.

  When the transmission of the dummy packet to the crossbar switch 102 is started, the packet transmission circuit 126 transmits a packet transmission completion notification to the transmission request unit 203. The transmission request unit 203 transmits the received packet transmission completion notification to the command receiving unit 201 (step S14). Here, since the update of the FSM 210 is suppressed, the state of the FSM 210 does not change, and the transition to the next stage of packet transmission by the TAS controller 125 does not occur. In FIG. 7, for the sake of explanation, step S14 is described after step S12. However, step S14 is actually performed in parallel with steps S6 to S13.

  After transmission of all dummy packets is completed (step S12: affirmative), the dummy packet transmission control unit 24 sets the dummy packet transmission start register 124 to “0” (step S15). That is, the dummy packet transmission control unit 24 sets the dummy packet transmission start register 124 so that transmission of the dummy packet is stopped.

  Next, the state management unit 21 sets the dummy packet transmission operation register 122 to “0”. That is, the state management unit 21 sets the dummy packet transmission operation register 122 so that the dummy packet transmission operation becomes invalid. Further, the state management unit 21 sets the state register 121 so that transmission / reception of the packet of the TAS 111 is enabled (step S16).

  As described above, the test apparatus of the information processing apparatus according to the present embodiment directly writes dummy data to the SRAM included in the TAS transmission buffer, generates a dummy packet from the dummy data, and transmits other data through the interconnect. Processing to be transmitted to the CPU is continuously executed. Thereby, it is possible to easily verify the route including the interconnect between the CPUs. As described above, since the packet transmission test can be performed with the dummy packet without referring to the memory which is the main storage device, it is possible to avoid the stop of the test due to the memory failure, shorten the test time, and the development man-hours. Can be greatly reduced. That is, rapid system verification can be performed reliably.

  Further, since the packet header and payload of the dummy packet are stored in the header area of the transmission buffer, the dummy packet can be generated with the data read from the header area. Therefore, a dummy packet can be easily generated as compared with the case where the packet header and the payload are stored in the header area and the payload area, respectively.

  In the above description, the verification by the packet transmission test in one TAS controller 125 has been described. However, if a plurality of TAS controllers 125 are installed, transmission tests using destinations or packets corresponding to the number of TAS controllers 125 can be performed in parallel. Furthermore, in the above description, verification between CPUs in one system board has been mainly described. However, the present invention is not limited to this, and verification can also be performed between CPUs mounted on different system boards.

1 System board 10 CPU
11 Core 15 Interconnect 20 Service Processor 21 State Management Unit 22 Dummy Data Writing Unit 23 Packet Information Setting Unit 24 Dummy Packet Transmission Control Unit 30 Memory Controller 40 DIMM
100 Interconnect Controller 101 Transmission / Reception Circuit 102 Crossbar Switch 103 Data Link Control Circuit 104 SerDes
111 TAS
112 RBF
121 status register 122 dummy packet transmission operation register 123 dummy packet information register 124 dummy packet transmission start register 125 TAS controller 126 packet transmission circuit 127 payload acquisition unit 131 transmission control unit 132 DMA control unit 201 command reception unit 202 transmission buffer unit 203 transmission request Part 210 FSM
221 Header area 222 Payload area 230 FSM

Claims (5)

An information processing apparatus testing apparatus for testing an information processing apparatus including a plurality of arithmetic units having a main storage device and a transmission buffer,
A dummy data writer for writing dummy data to the transmission buffer;
A test apparatus for an information processing apparatus, comprising: a transmission control unit that instructs a specific arithmetic device to continuously transmit the dummy data written in the transmission buffer to another arithmetic device. The arithmetic unit is
A data acquisition unit that receives a transmission request, acquires data from the main storage unit, and stores transmission data including data and additional information in the transmission buffer;
Generating a packet based on the transmission data stored in the transmission buffer, and transmitting the generated packet to the other arithmetic device;
A verification unit that performs verification based on the transmission data transmitted from the other arithmetic device;
An operation stop unit that stops operations other than the transmission unit;
The dummy data writing unit writes the dummy data as the transmission data in the transmission buffer,
2. The information processing apparatus according to claim 1, wherein the transmission control unit instructs the transmission unit to continuously transmit the dummy data written in the transmission buffer by the dummy data writing unit. 3. Test equipment. The arithmetic device further includes an interconnect serving as a path connecting to the other arithmetic device,
The transmission unit transmits the generated packet to the other arithmetic device via the interconnect,
The information processing apparatus testing device according to claim 2, wherein the transmission control unit instructs the transmission unit to transmit the dummy data via the interconnect. The transmission buffer has an additional information writing area and a data writing area,
The information processing apparatus testing apparatus according to claim 1, wherein the dummy data writing unit writes the dummy data in the additional information writing area of the transmission buffer. An information processing apparatus test method for testing an information processing apparatus including a plurality of arithmetic devices having a main storage device and a transmission buffer,
Write dummy data to the transmission buffer,
A method for testing an information processing apparatus, comprising: instructing a specific arithmetic device to continuously transmit the dummy data written in the transmission buffer to another arithmetic device.

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