JP2018098308A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which has good electrical characteristics and high reliability.SOLUTION: A semiconductor device manufacturing method comprises the steps of: forming in a first insulator covering a transistor, a contact hole to expose part of the transistor; forming a first conductor in the contact hole; forming a second conductor which covers at least the first conductor; forming a second insulator on the first insulator and the second conductor; subsequently, processing the second insulator to form a recess to expose the first insulator and the second conductor; and forming in the recess, a third conductor connected with the second conductor.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.

  Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  In recent years, semiconductor devices have been developed, and LSIs, CPUs, and memories are mainly used. The CPU is a collection of semiconductor elements each having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes serving as connection terminals.

  A semiconductor circuit (IC chip) such as an LSI, a CPU, or a memory is mounted on a circuit board, for example, a printed wiring board, and used as one of various electronic device components.

  In addition, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

  A transistor using an oxide semiconductor is known to have extremely small leakage current in a non-conduction state. For example, a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).

  In addition, for the purpose of improving the carrier mobility of a transistor, a technique of stacking oxide semiconductor layers having different electron affinities (or conduction band bottom levels) is disclosed (see Patent Document 2 and Patent Document 3).

  In recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for integrated circuits in which transistors and the like are integrated at high density. There is also a need for improved productivity of semiconductor devices including integrated circuits.

JP 2012-257187 A JP 2011-124360 A JP 2011-138934 A

  An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics and a manufacturing method thereof. An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof. An object of one embodiment of the present invention is to provide a highly productive semiconductor device and a manufacturing method thereof.

  An object of one embodiment of the present invention is to provide a semiconductor device in which favorable electric resistance is obtained between elements provided in the semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to suppress deterioration in electrical resistance between elements provided in a semiconductor device.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

In one embodiment of the present invention, a conductor that prevents oxidation of the conductor is provided over the conductor provided in the semiconductor device.

According to one embodiment of the present invention, an opening that exposes part of a transistor is formed in a first insulator that covers the transistor, the first conductor is formed in the opening, and at least the first conductor is covered. After the second conductor is formed and the second insulator is formed on the first insulator and the second conductor, the second insulator is processed to obtain the first insulator and the second insulator. This is a method for manufacturing a semiconductor device in which a recess exposing the conductor is formed, and a third conductor connected to the second conductor is formed in the recess.

Further, in the above manufacturing method, after the fourth conductor is formed over the opening and the first insulator, the first conductor may be formed by polishing the fourth conductor.

In the above manufacturing method, after the opening is formed, a third insulator is formed so as to be in contact with the side surface of the opening, the bottom of the opening, and the first insulator, and the bottom of the opening and the first The third insulator provided on the first insulator is removed by anisotropic etching to form a fourth insulator in contact with the side surface of the opening, and then the first conductor is placed in the opening. It may be formed.

In the above manufacturing method, the side surface and the lower surface of the first conductor may be surrounded by the first conductive film.

In the above manufacturing method, the side surface and the lower surface of the third conductor may be surrounded by the second conductive film.

In the above manufacturing method, a third conductive film may be formed between the third conductor and the second conductive film.

In the above manufacturing method, the first conductive film preferably contains at least one of titanium, tantalum, ruthenium, and cobalt.

In the above manufacturing method, the second conductive film includes at least one of titanium, tantalum, ruthenium, and cobalt, and the third conductive film includes at least one of titanium, tantalum, ruthenium, and cobalt. Preferably it is.

In the above manufacturing method, it is preferable that the first conductor includes tungsten and the third conductor includes copper.

In the above manufacturing method, the second conductor preferably contains tantalum.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly productive semiconductor device and a manufacturing method thereof can be provided.

According to one embodiment of the present invention, a semiconductor device in which favorable electric resistance can be obtained between elements provided in the semiconductor device and a manufacturing method thereof can be provided. Further, according to one embodiment of the present invention, deterioration in electrical resistance between elements provided in a semiconductor device can be suppressed.

In a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, a semiconductor device with improved operating frequency can be provided.

Alternatively, a novel semiconductor device can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention. 4A and 4B are a block diagram and a circuit diagram illustrating a structure example of a memory device according to one embodiment of the present invention. FIG. 7 is a block diagram illustrating a structural example of a semiconductor device according to one embodiment of the present invention. 10A and 10B are a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a timing chart illustrating an operation example of the semiconductor device. FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention and a timing chart illustrating an operation example of the semiconductor device. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. 10A and 10B are a flowchart and a perspective schematic diagram illustrating an example of a manufacturing process of an electronic component. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

  Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

  In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may not be described in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.

  In this specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

  In addition, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

  For example, in this specification and the like, when X and Y are explicitly described as being connected, X and Y are electrically connected, and X and Y are functional. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

  Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

  In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done. Note that in this specification and the like, a channel region refers to a region through which a current mainly flows.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.

  Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor). Sometimes referred to as “channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

  In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

  Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

  Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. By including impurities, for example, DOS (Density of States) of a semiconductor may increase or crystallinity may decrease. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed, for example, by mixing impurities. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

  Note that in this specification and the like, a silicon oxynitride film has a higher oxygen content than nitrogen in its composition. For example, preferably oxygen is 55 atomic% to 65 atomic%, nitrogen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range. The silicon nitride oxide film has a nitrogen content higher than that of oxygen. For example, preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.

  In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, the term “insulator” can be restated as an insulating film or an insulating layer. In addition, the term “conductor” can be restated as a conductive film or a conductive layer. In addition, the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.

  The transistors described in this specification and the like are field-effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.

  Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

  Note that in this specification, a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing as an OS FET, it can be said to be a transistor including an oxide or an oxide semiconductor.

(Embodiment 1)
<Method for Manufacturing Semiconductor Device>
Hereinafter, an example of a method for manufacturing wirings connected to the transistor 200 and the transistor 400 included in the semiconductor device of one embodiment of the present invention will be described.

  FIG. 1 is a cross-sectional view of a semiconductor device including the transistor 200 and the transistor 400. Note that the structures of the transistor 200 and the transistor 400 illustrated in FIG. 1 are merely examples, and transistors having different structures can be used in addition to these structures.

[Transistor 200]
The transistor 200 includes an insulator 210a, an insulator 210b, an insulator 212, and a conductor 203, an insulator 214, an insulator 216, and an insulator 214 which are disposed so as to be embedded in the insulator 212. And the conductor 205 disposed so as to be embedded in the insulator 216, the insulator 220 disposed on the insulator 216 and the conductor 205, the insulator 222 disposed on the insulator 220, and the insulator 222 An insulator 224 disposed above, the oxide 230a disposed on the insulator 224, the oxide 230b, the oxide 230c, the insulator 250 disposed on the oxide 230c, and the insulator 250 Disposed conductors 260 (conductor 260a, conductor 260b, and conductor 260c), insulator 270 disposed on conductor 260, and few Both insulator 250, and has an insulator 272 which is arranged in contact with a side surface of the conductor 260, the oxide 230 insulator 274 and disposed in contact with the insulator 272, and.

Note that in this specification, the oxide 230a, the oxide 230b, and the oxide 230c may be collectively referred to as an oxide 230. In addition, only the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230.

Note that the transistor 200 has a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, but is not limited to this structure. Alternatively, a single layer including only the oxide 230b or a stacked structure including only the oxide 230b and the oxide 230c may be employed. In the transistor 200, the structure in which the conductors 260a and 260b are stacked is described; however, the present invention is not limited to this. For example, only the conductor 260b may be provided.

Here, an enlarged view of the region 239 in the vicinity of the channel in FIG. 1 is shown in FIG. As shown in FIG. 33, the oxide 230 includes the region 231 (the region 231a and the region 231b), the region 232 (the region 232a and the region 232b), the region 233 (the region 233a and the region 233b), and the region 234, the region 231b.

The region 231, the region 232, and the region 233 are regions with high carrier density and low resistance. In particular, the region 231 may function as a source region or a drain region by increasing the carrier density compared to other regions. Further, since the region 234 has a lower carrier density than other regions, at least part of the region 234 may function as a region where a channel is formed.

Further, the region 232 and the region 233 are regions arranged between a source region or a drain region and a region where a channel is formed. The region 233 is a region having a higher carrier density than the region 234 and a lower carrier density than the region 232 and the region 231. In addition, the region 232 has higher carrier density than the regions 234 and 233 and lower carrier density than the region 231.

By providing the region 232 and the region 233, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed, so that the on-state current of the transistor is increased. Can do.

The region 233 may function as a so-called overlap region (also referred to as a Lov region) overlapping with the conductor 260 functioning as a gate electrode.

The region 231 is in contact with the insulator 274 and preferably has at least one concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen higher than that of the region 232, the region 233, and the region 234.

The region 232 has a region overlapping with the insulator 272. The region 232 is disposed between the region 231 and the region 233, and has at least one concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen higher than that of the region 233 and the region 234. It is preferable. On the other hand, it is preferable that at least one concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen be smaller than that of the region 231.

The region 233 has a region overlapping with the conductor 260. The region 233 is disposed between the region 232 and the region 234, and it is preferable that at least one concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen be higher than that in the region 234. On the other hand, it is preferable that at least one concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen be smaller than that in the region 231 and the region 234.

The region 234 overlaps with the conductor 260. The region 234 is disposed between the region 233a and the region 233b, and at least one concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen has a concentration of the region 231, the region 232, and the region 233. It is preferable to be smaller than the above.

Note that in the oxide 230, at least part of the region 231 or the region 231 may function as a source region or a drain region. In the oxide 230, at least part of the region 234 may function as a region where a channel is formed.

In addition, in the oxide 230, the boundaries of the region 231, the region 232, the region 233, and the region 234 may not be clearly detected. Concentrations of metal elements such as indium and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes in each region, but also continuously change in each region (also referred to as gradation). You may do it. In other words, the closer to the region 234 from the region 231 to the region 232 and from the region 232 to the region 233, the lower the concentration of the metal element such as indium and the impurity element such as hydrogen and nitrogen. .

In the figure, the region 234, the region 231, the region 232, and the region 233 are formed in the oxide 230a, the oxide 230b, and the oxide 230c. What is necessary is just to be formed in the oxide 230b at least. Further, in FIGS. 1 and 33, the boundaries of the respective regions are displayed substantially perpendicular to the upper surface of the oxide 230, but this embodiment is not limited to this. For example, the region 233 may protrude toward the conductor 260 near the surface of the oxide 230b, and may recede toward the conductor 252a or the conductor 252b near the lower surface of the oxide 230a.

Note that in the transistor 200, the oxide 230 is preferably a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). Since a transistor including an oxide semiconductor has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

On the other hand, in a transistor including an oxide semiconductor, its electrical characteristics are likely to vary due to impurities and oxygen vacancies in the oxide semiconductor, and reliability may deteriorate. In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Therefore, a transistor including an oxide semiconductor containing oxygen vacancies is likely to be normally on. Therefore, oxygen vacancies in the oxide semiconductor are preferably reduced as much as possible.

In particular, when oxygen vacancies exist at the interface between the region 234 where the channel is formed in the oxide 230 and the insulator 250 functioning as a gate insulating film, electrical characteristics are likely to fluctuate and reliability is deteriorated. There is.

Thus, the insulator 250 in contact with the region 234 of the oxide 230 preferably contains more oxygen than oxygen (also referred to as excess oxygen) that satisfies the stoichiometric composition. That is, excess oxygen in the insulator 250 diffuses into the region 234, so that oxygen vacancies in the region 234 can be reduced.

Further, the insulator 272 is preferably provided in contact with the insulator 250. For example, the insulator 272 preferably has a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits). Since the insulator 272 has a function of suppressing diffusion of oxygen, oxygen in the excess oxygen region is efficiently supplied to the region 234 without diffusing to the insulator 274 side. Accordingly, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved.

Further, the transistor 200 is preferably covered with an insulator having a barrier property to prevent entry of impurities such as water or hydrogen. An insulator having a barrier property is a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _2, etc.), copper atoms, and the like. Insulators using an insulating material that has (which is difficult to transmit the above impurities). In addition, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen hardly transmits).

For example, the transistor 200 is provided over the insulator 222. An insulator 274 is provided so as to cover the transistor 200. With the structure in which the insulator 222 and the insulator 274 are in contact with each other at the outer edge of the transistor 200, the transistor 200 can be surrounded by an insulator having a barrier property. With this structure, impurities such as hydrogen and water can be prevented from entering the transistor 200. Alternatively, oxygen contained in the insulator 224 and the insulator 250 can be prevented from diffusing from the transistor 200 to the interlayer film.

Hereinafter, a detailed structure of the semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

The conductor 205 functioning as the second gate electrode is provided so as to overlap with the oxide 230 and the conductor 260. The conductor 205 is preferably provided in contact with the conductor 203.

Here, the conductor 205 is preferably provided larger than the region 234 in the oxide 230. In particular, the conductor 205 preferably extends in a region outside the end where the region 234 of the oxide 230 intersects the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through the insulator on the side surface of the oxide 230 in the channel width direction.

Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a back gate) electrode. In that case, the threshold voltage of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being linked. In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200 can be made higher than 0 V and the off-state current can be reduced. Therefore, the drain current (Icut) when the voltage applied to the conductor 260 is 0 V can be reduced. Note that in this specification and the like, Icut refers to a drain current when the voltage of the gate electrode that controls the switching operation of the transistor 200 is 0V.

Although details will be described later with reference to FIG. 9, the conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably arranged so as to overlap with the conductor 260 also in a region outside the end portion intersecting with the channel width direction (W length direction) of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with an insulator outside the side surface of the oxide 230.

With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a closed circuit, and oxidation A channel formation region formed in the object 230 can be covered.

That is, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. . In this specification, a transistor structure in which a channel formation region is electrically surrounded by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

In the conductor 205, a conductor 205a is formed in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and a conductor 205b is formed further inside. Here, the heights of the upper surfaces of the conductors 205a and 205b and the height of the upper surface of the insulator 216 can be approximately the same. Note that although the transistor 200 has a structure in which the conductors 205a and 205b are stacked, the present invention is not limited to this. For example, only the conductor 205b may be provided.

Note that the conductor 203 is extended in the channel width direction similarly to the conductor 260, and functions as a wiring for applying a potential to the conductor 205, that is, the second gate electrode. Here, a conductor 205 embedded in the insulator 214 and the insulator 216 is provided over the conductor 203 functioning as a wiring of the second gate electrode. By providing the conductor 205 over the conductor 203, the distance between the conductor 203 having the function of the first gate electrode and the wiring and the conductor 203 can be appropriately designed. That is, the insulator 214, the insulator 216, and the like are provided between the conductor 203 and the conductor 260, so that the parasitic capacitance between the conductor 203 and the conductor 260 can be reduced and the withstand voltage can be increased.

Further, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the switching speed of the transistor can be improved and a transistor having high frequency characteristics can be obtained. Further, by increasing the withstand voltage between the conductor 203 and the conductor 260, the reliability of the transistor 200 can be improved. Therefore, it is preferable to increase the thickness of the insulator 214 and the insulator 216. Note that the extending direction of the conductor 203 is not limited thereto, and the conductor 203 may be extended in the channel length direction of the transistor 200, for example.

Here, the conductor 205a and the conductor 203a diffuse impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO ₂ ), a copper atom, and the like. It is preferable to use a conductive material having a function of suppressing (the above-described impurities are hardly transmitted). Alternatively, it is preferable to use a conductive material that has a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.

Since the conductor 205a and the conductor 203a have a function of suppressing oxygen diffusion, the conductivity can be prevented from being reduced due to oxidation of the conductor 205b and the conductor 203b. As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, the conductor 205a and the conductor 203a may be a single layer or a stack of the above conductive materials. Accordingly, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 200 side through the conductor 203 and the conductor 205 from the insulator 210 can be suppressed.

The conductor 205b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that although the conductor 205b is illustrated as a single layer, it may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above-described conductive material.

In addition, since the conductor 203b functions as a wiring, a conductor having higher conductivity than the conductor 205b is preferably used. For example, a conductive material mainly containing copper or aluminum can be used. The conductor 203b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

In particular, copper is preferably used for the conductor 203. Since copper has low resistance, it is preferably used for wiring and the like. On the other hand, since copper easily diffuses, the characteristics of the transistor 200 may be deteriorated by diffusing into the oxide 230. Thus, the insulator 214 can be formed using a material such as aluminum oxide or hafnium oxide with low copper permeability, whereby copper diffusion can be suppressed.

The insulator 210a, the insulator 210b, and the insulator 214 preferably function as barrier insulating films that prevent impurities such as water or hydrogen from entering the transistor from the substrate side. Therefore, the insulator 210a, the insulator 210b, and the insulator 214 are formed of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO _2, etc.), a copper atom, or the like. It is preferable to use an insulating material having a function of suppressing diffusion of impurities (it is difficult for the impurities to pass through). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits).

For example, aluminum oxide or the like is preferably used for the insulator 210a and the insulator 210b, and silicon nitride or the like is preferably used for the insulator 214. Accordingly, impurities such as hydrogen and water can be prevented from diffusing from the insulator 210 and the insulator 214 to the transistor side. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing from the insulator 210 and the insulator 214 to the substrate side. Further, the insulator 210a and the insulator 210b may have different film formation methods. For example, the insulator 210a may be formed by an atomic layer deposition (ALD) method, and the insulator 210b may be formed by a sputtering method.

In addition, by providing a structure in which the conductor 205 is stacked over the conductor 203, the insulator 214 can be provided between the conductor 203 and the conductor 205. Here, even when a metal that easily diffuses, such as copper, is used for the conductor 203b, by providing silicon nitride or the like as the insulator 214, the metal can be prevented from diffusing into a layer above the insulator 214.

The insulator 212, the insulator 216, and the insulator 280 that function as interlayer films preferably have a lower dielectric constant than the insulator 210 or the insulator 214. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

For example, as the insulator 212, the insulator 216, and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), titanate An insulator such as strontium (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used as a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

The insulator 220, the insulator 222, and the insulator 224 function as gate insulators.

Here, as the insulator 224 in contact with the oxide 230, an oxide insulator containing more oxygen than oxygen that satisfies the stoichiometric composition is preferably used. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and reliability can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3 in TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has a thickness of 0.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

In the case where the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing at least one diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). Is preferred.

Since the insulator 222 has a function of suppressing oxygen diffusion, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. In addition, the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.

The insulator 222 is, for example, so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator including a -k material in a single layer or a stacked layer. By using a high-k material for the insulator that functions as a gate insulator, transistors can be miniaturized and highly integrated. In particular, it is preferable to use an insulating material such as aluminum oxide and hafnium oxide that has a function of suppressing diffusion of impurities and oxygen (the oxygen hardly transmits). In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

The insulator 220 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high dielectric constant can be obtained by combining with an insulator of a high-k material.

Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, the present invention is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.

The oxide 230 includes an oxide 230b and an oxide 230c over the oxide 230b. The oxide 230 includes a region 231, a region 232, a region 233, and a region 234. Note that at least part of the region 231 is in contact with the insulator 274 and preferably has at least one concentration of a metal element such as indium, hydrogen, and nitrogen higher than that of the region 234.

When the transistor 200 is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least part of the region 234 functions as a region where a channel is formed.

Here, as illustrated in FIG. 33, the oxide 230 preferably includes a region 233 and a region 234. With such a structure, in the transistor 200, the on-state current can be increased and the leakage current (off-state current) at the time of non-conduction can be reduced.

Further, by including the oxide 230b over the oxide 230a, diffusion of impurities into the oxide 230b can be suppressed from a structure formed below the oxide 230a. In addition, as illustrated in FIG. 3, by including the oxide 230b under the oxide 230c, diffusion of impurities into the oxide 230b can be suppressed from a structure formed above the oxide 230c. .

In addition, a curved surface is provided between the side surface of the oxide 230 and the upper surface of the oxide 230. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm at the end of the oxide 230b.

As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, as the metal oxide to be the region 234, an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

Since a transistor including an oxide semiconductor has extremely low leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

For example, the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, or cerium. It is preferable to use a metal oxide such as neodymium, hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

Here, the region 234 of the oxide 230 is described.

The region 234 preferably has a stacked structure with oxides having different atomic ratios of metal atoms. Specifically, in the case where the oxide 230a, the oxide 230b, and the oxide 230c have a stacked structure, in the metal oxide used for the oxide 230a or the oxide 230c, the atomic ratio of the element M in the constituent elements is In the metal oxide used for the oxide 230b, the atomic ratio of the element M in the constituent elements is preferably larger. In the metal oxide used for the oxide 230a or the oxide 230c, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. . In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a or the oxide 230c. . Note that in the case where the oxide 230c is included, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used for the oxide 230c.

Next, the region 231, the region 232, and the region 233 of the oxide 230 are described.

The region 231, the region 232, and the region 233 are regions in which a metal atom such as indium or an impurity is added to a metal oxide provided as the oxide 230 to reduce resistance. Note that each region has higher conductivity than at least the oxide 230b in the region 234. Note that in order to add impurities to the region 231, the region 232, and the region 233, for example, plasma treatment, an ion implantation method in which an ionized source gas is added by mass separation, or mass separation of the ionized source gas is performed. A dopant which is at least one of a metal element such as indium and an impurity may be added by using an ion doping method, a plasma immersion ion implantation method, or the like that is added without adding.

That is, in the region 231, the region 232, and the region 233, by increasing the content of metal atoms such as indium in the oxide 230, electron mobility can be increased and resistance can be reduced.

Alternatively, the insulator 274 containing an element serving as an impurity can be formed in contact with the oxide 230, whereby the impurity can be added to the region 231, the region 232, and the region 233.

That is, the resistance of the region 231, the region 232, and the region 233 is reduced by adding an element that forms oxygen vacancies or an element that is captured by oxygen vacancies. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 231, the region 232, and the region 233 may include one or more of the above elements.

Note that in FIGS. 1 and 33, the region 234, the region 231, the region 232, and the region 233 are formed in the oxide 230a, the oxide 230b, and the oxide 230c, but the present invention is not limited thereto. For example, these regions may be formed at least in the oxide 230b. Further, in FIGS. 1 and 33, the boundaries of the respective regions are displayed substantially perpendicular to the upper surface of the oxide 230, but this embodiment is not limited to this. For example, the region 233 may protrude toward the conductor 260 near the surface of the oxide 230b, and may recede toward the conductor 252a or the conductor 252b near the lower surface of the oxide 230a.

Further, in the transistor 200, since the region 233 and the region 232 are provided, a high-resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; On-state current and mobility can be increased. In addition, since the region 233 includes the source region and the drain region, and the gate does not overlap in the channel length direction, formation of unnecessary capacitance can be suppressed. In addition, by including the region 233, leakage current at the time of non-conduction can be reduced.

Therefore, by appropriately selecting the range of the region 231a and the region 231b, a transistor having electrical characteristics that meet requirements can be easily provided in accordance with circuit design.

The insulator 250 functions as a gate insulating film. The insulator 250 is preferably provided in contact with the upper surface of the oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in the TDS (Thermal Desorption Spectroscopy) analysis, the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. This is an oxide film. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

By providing the insulator from which oxygen is released by heating as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b. Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

The conductor 260 functioning as the first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a. As the conductor 260a, a conductive oxide is preferably used. For example, a metal oxide that can be used as the oxide 230a or the oxide 230b can be used. In particular, among In—Ga—Zn-based oxides, the metal atomic ratio is high from [In]: [Ga]: [Zn] = 4: 2: 3 to 4.1, and the vicinity thereof. It is preferable to use those. By providing such a conductor 260a, permeation of oxygen to the conductor 260b and the conductor 260c can be suppressed, and an increase in electrical resistance value of the conductor 260b and the conductor 260c due to oxidation can be prevented.

Further, by forming such a conductive oxide by a sputtering method, oxygen can be added to the insulator 250 and oxygen can be supplied to the oxide 230b. Accordingly, oxygen vacancies in the region 426a of the oxide 230 can be reduced.

For the conductor 260c, for example, a metal such as tungsten can be used. Alternatively, a conductor that can improve the conductivity of the conductor 260a by adding an impurity such as nitrogen to the conductor 260a may be used as the conductor 260b. For example, titanium nitride or the like is preferably used for the conductor 260b.

In the case where the conductor 205 extends in a region outside the end portion intersecting with the channel width direction of the oxide 230, the conductor 260 overlaps with the insulator 250 in the region. Preferably it is. That is, it is preferable that the conductor 205, the insulator 250, and the conductor 260 form a stacked structure outside the side surface of the oxide 230.

With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a closed circuit, and oxidation A channel formation region formed in the object 230 can be covered.

That is, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. .

Further, the insulator 270 functioning as a hard mask may be provided over the conductor 260b. By providing the insulator 270, when processing the conductor 260, the side surface of the conductor 260 is substantially vertical, specifically, the angle formed between the side surface of the conductor 260 and the substrate surface is 75 degrees or more and 100 degrees or less. Preferably, it can be set to 80 degrees or more and 95 degrees or less. By processing the conductor into such a shape, the insulator 272 to be formed next can be formed into a desired shape.

An insulator 272 functioning as a barrier film is provided in contact with the side surfaces of the insulator 250, the conductor 260, and the insulator 270.

Here, the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, oxygen in the insulator 250 can be prevented from diffusing outside. Further, entry of impurities such as hydrogen and water into the oxide 230 from an end portion of the insulator 250 or the like can be suppressed.

By providing the insulator 272, an upper surface and a side surface of the conductor 260 and a side surface of the insulator 250 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. Thus, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250. Therefore, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulating film.

In the case where the transistor is miniaturized and the channel length is formed to be greater than or equal to 10 nm and less than or equal to 30 nm, the impurity element contained in the structure provided around the transistor 200 is diffused, so that the region 231a and the region 231b There is a risk of electrical conduction.

Thus, as shown in this embodiment, by forming the insulator 272, impurities such as hydrogen and water can be prevented from entering the insulator 250 and the conductor 260, and oxygen in the insulator 250 can be reduced. Can be prevented from spreading outside. Therefore, when the first gate voltage is 0 V, the source region and the drain region can be prevented from being electrically connected.

The insulator 274 is provided to cover the insulator 270, the insulator 272, the oxide 230, and the insulator 224. Here, the insulator 274 is provided in contact with the top surfaces of the insulator 270 and the insulator 272 and in contact with a side surface of the insulator 272.

The insulator 274 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, the insulator 274 is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like. By forming such an insulator 274, oxygen can be prevented from being transmitted through the insulator 274 and supplying oxygen to oxygen vacancies in the regions 231 a and 231 b, thereby reducing the carrier density. . Further, it is possible to prevent the region 231a and the region 231b from being excessively expanded to the region 234 side by being mixed with impurities such as water or hydrogen through the insulator 274.

Note that in the case where the region 231, the region 232, and the region 233 are provided by forming the insulator 274, the insulator 274 preferably includes at least one of hydrogen and nitrogen. By using an insulator having an impurity such as hydrogen or nitrogen for the insulator 274, an impurity such as hydrogen or nitrogen is added to the oxide 230 so that the region 231, the region 232, and the region 233 are formed in the oxide 230. Can be formed.

An insulator 280 that functions as an interlayer film is provided over the insulator 274. As in the case of the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that an insulator similar to the insulator 210 may be provided over the insulator 280.

[Transistor 400]
Next, the transistor 400 having different electrical characteristics from the transistor 200 is described. The transistor 400 is a transistor that can be manufactured in parallel with the transistor 200 described above, and is preferably formed in the same layer as the transistor 200. By manufacturing in parallel with the transistor 200, the transistor 400 can be manufactured without increasing unnecessary steps.

As illustrated in FIG. 1, the transistor 400 includes an insulator 214 and an insulator 216 disposed over a substrate 208, a conductor 405 disposed to be embedded in the insulator 214 and the insulator 216, and an insulator 216, an insulator 220 disposed on the conductor 410, an insulator 222 disposed on the insulator 220, an insulator 424a disposed on each other on the insulator 222, and insulation Body 424b, oxide 430a1 disposed over insulator 424a, oxide 430a2 disposed over insulator 424b, oxide 430b1 disposed in contact with the top surface of oxide 430a1, and oxide 430a2 The oxide 430b2 disposed in contact with the upper surface of the oxide, the upper surface of the insulator 222, the side surfaces of the oxide 430a1 and the oxide 430a2, and the oxide 430 1 and the oxide 430c disposed in contact with the side surface and the upper surface of the oxide 430b2, the insulator 450 disposed on the oxide 430c, the conductor 460a disposed on the insulator 450, and the conductor The conductor 460b disposed over the conductor 460a, the insulator 470 disposed over the conductor 460b, the insulator 450, the conductor 460a, the conductor 460b, and the insulator 470 are disposed in contact with each other. And an insulator 274 disposed in contact with the upper surface of the oxide 430c and in contact with the side surface of the insulator 472. Here, the top surface of the insulator 472 is preferably substantially coincident with the top surface of the insulator 470. The insulator 274 is preferably provided to cover the insulator 470, the conductor 460, the insulator 472, and the oxide 430.

Note that in FIG. 1, the insulator 424a and the insulator 424b are formed as separate structures; however, the insulator 424a and the insulator 424b may be provided as one continuous insulator 424. In that case, the insulator 424 is preferably provided so as to overlap with the oxide 430. That is, the oxide 430 is provided so as to overlap with the insulator 424. Note that the insulator 424 includes a first region in contact with the oxide 430c and a second region in contact with the oxide 430b1 and the oxide 430b2. In the insulator 424, the thickness of the first region is smaller than that of the second region.

Hereinafter, the oxide 430a1, the oxide 430a2, the oxide 430b1, the oxide 430b2, and the oxide 430c may be collectively referred to as an oxide 430. Note that although the transistor 400 has a structure in which the conductors 460a and 460b are stacked, the present invention is not limited to this. For example, only the conductor 460b may be provided.

Here, the conductor, the insulator, and the oxide included in the transistor 400 can be formed in the same step as the conductor, the insulator, and the oxide included in the transistor 200 in the same layer. Therefore, the conductor 403 (the conductor 403a and the conductor 403b) includes the conductor 203 (the conductor 203a and the conductor 203b), the oxide 430 (the oxide 430a1, the oxide 430a2, the oxide 430b1, the oxide 430b2, and The oxide 430c) is the oxide 230 (oxide 230a, oxide 230b, and oxide 230c), the insulator 450 is the insulator 250, and the conductor 460 (conductor 460a and conductor 460b) is the conductor 260 ( The conductor 260a and the conductor 260b), the insulator 470 corresponds to the insulator 270, and the insulator 472 corresponds to the insulator 272. Therefore, the conductor, the insulator, and the oxide included in the transistor 400 can be formed using a material similar to that of the transistor 200, and the structure of the transistor 200 can be referred to.

Further, the structure may include the insulator 212 disposed over the insulator 210 and the conductor 403 disposed so as to be embedded in the insulator 212. Here, in the conductor 403, a conductor 403a is formed in contact with the inner wall of the opening of the insulator 212, and a conductor 403b is formed further inside. The conductor 403 (the conductor 403a and the conductor 403b) corresponds to the conductor 203 (the conductor 203a and the conductor 203b) and can be formed using a similar material. You can visit.

The oxide 430c is preferably formed to cover the oxide 430a1 and the oxide 430b1, and the oxide 430a2 and the oxide 430b2. Further, the side surface of the oxide 430a1 and the side surface of the oxide 430b1 are preferably substantially coincident, and the side surface of the oxide 430a2 and the side surface of the oxide 430b2 are preferably substantially coincident. For example, the oxide 430c is formed on the side surfaces of the insulator 424a and the insulator 424b, the side surfaces of the oxide 430a1 and the oxide 430a2, the top surface and side surfaces of the oxide 430b1 and the oxide 430b2, and a part of the top surface of the insulator 222. Formed in contact. Here, when the oxide 430c is viewed from above, the side surfaces of the oxide 430c are located on the side surfaces of the oxide 430a1 and the oxide 430b1, and outside the side surfaces of the oxide 430a2 and the oxide 430b2.

The oxides 430a1 and 430b1, and the oxides 430a2 and 430b2 are formed to face each other with the conductor 405, the oxide 430c, the insulator 450, and the conductor 460 interposed therebetween.

In addition, a curved surface is provided between the side surface of the oxide 430b1 or the side surface of the oxide 430b2 and the upper surface of the oxide 430b1 or the upper surface of the oxide 430b2. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curvature radius of the curved surface at the end portion of the oxide 430b1 or the oxide 430b2 is 3 nm to 10 nm, preferably 5 nm to 6 nm.

The oxide 430 has a region in contact with the insulator 274, and the resistance of the region and the vicinity thereof is reduced as in the region 231, the region 232, and the region 233 of the transistor 200. Thus, part of the oxide 430a1, the oxide 430b1, and the oxide 430c or part of the oxide 430a2, the oxide 430b2, and the oxide 430c can function as any of the source region and the drain region of the transistor 400.

A region between the oxide 430a1 and the oxide 430a2 and the oxide 430b1 and the oxide 430b2 in the oxide 430c functions as a channel formation region. Here, the distance between the oxide 430a1 and the oxide 430a2 and the oxide 430b1 and the oxide 430b2 is preferably increased. For example, the distance in the channel length direction of the conductor 260 of the transistor 200 is preferably larger. Thus, off-state current of the transistor 400 can be reduced.

The oxide 430c of the transistor 400 can be formed using a material similar to that of the oxide 230c of the transistor 200. That is, the oxide 430c can be a metal oxide that can be used for the oxide 230a or the oxide 230b. For example, in the case where an In—Ga—Zn oxide is used as the oxide 430c, the atomic ratio of In, Ga, and Zn contained in In: Ga: Zn = 1: 3: 2, In: Ga: Zn = 4: 2: 3, In: Ga: Zn = 1: 1: 1, or In: Ga: Zn = 1: 3: 4.

The oxide 430c preferably has different electrical characteristics from the oxide 230b when used in a transistor. Therefore, for example, in the oxide 430c and the oxide 230b, the oxide material, the content ratio of the element included in the oxide, the thickness of the oxide, or the width or length of the channel formation region formed in the oxide It is preferable that any one of them is different.

Hereinafter, the case where a metal oxide that can be used for the oxide 230a is used as the oxide 430c is described. For example, as the oxide 430c, a metal oxide with relatively high insulating properties and a relatively small atomic ratio of In is preferably used. When such a metal oxide is used as the oxide 430c, the atomic ratio of the element M in the constituent element in the oxide 430c is larger than the atomic ratio of the element M in the constituent element in the oxide 230b. can do. In the oxide 430c, the atomic ratio of the element M to In can be larger than the atomic ratio of the element M to In in the oxide 230b. Accordingly, the threshold voltage of the transistor 400 can be made higher than 0 V, the off current can be reduced, and Icut can be made extremely small.

The oxide 430c functioning as a channel formation region of the transistor 400 preferably has reduced oxygen vacancies and impurities such as hydrogen or water as in the oxide 230c of the transistor 200 and the like. Accordingly, the threshold voltage of the transistor 400 can be made higher than 0 V, the off current can be reduced, and Icut can be made extremely small.

The threshold voltage of the transistor 400 including the oxide 430c is preferably higher than that of the transistor 200 in which a negative potential is not applied to the back gate. In order to make the threshold voltage of the transistor 400 higher than the threshold voltage of the transistor 200, for example, the metal oxide used as the oxide 230b of the transistor 200 has an In atomic ratio of oxide 230a and oxide. It is preferable to use a metal oxide that is relatively larger than the metal oxide used for the object 430c.

In addition, the distance between the oxide 430a1 or the oxide 430b1 of the transistor 400 and the oxide 430a2 or the oxide 430b2 is preferably larger than the width of the region 234 of the transistor 200. Accordingly, the channel length of the transistor 400 can be made longer than the channel length of the transistor 200, so that the threshold voltage of the transistor 400 can be made larger than the threshold voltage of the transistor 200 in which no negative potential is applied to the back gate. it can.

In the transistor 400, a channel formation region is formed in the oxide 430c, whereas in the transistor 200, a channel formation region is formed in the oxide 230a, the oxide 230b, and the oxide 230c. Therefore, the thickness of the oxide 430 in the channel formation region of the transistor 400 can be smaller than the thickness of the oxide 230 in the channel formation region of the transistor 200. Thus, the threshold voltage of the transistor 400 can be higher than the threshold voltage of the transistor 200 in which a negative potential is not applied to the back gate.

The conductor 460 functioning as the top gate of the transistor 400 and the conductor 405 functioning as the back gate are diode-connected to the source and electrically connected to the back gate of the transistor 200, whereby the back gate of the transistor 200 The voltage can be controlled. With such a structure, the threshold value of the transistor 200 can be controlled.

[Method for forming openings, wirings, etc.]
As illustrated in FIG. 2A, the transistor 200 and the transistor 400 are covered with an insulator 280. As illustrated in FIG. 2B, openings are provided in the insulator 280 and the insulator 274. The opening is formed so as to reach the oxide 230 and the oxide 430. In this embodiment, the opening is formed so that the oxide 230c and the oxide 430c are exposed, but the present invention is not limited to this. Part of the oxide 230c and the oxide 430c may be removed, and the opening may be formed so that the oxide 230b, the oxide 430b1, and the oxide 430b2 are exposed.

The opening is formed so that the angle formed between the side surface of the opening and the substrate surface is substantially perpendicular. Specifically, the angle formed between the side surface of the opening and the substrate surface is 75 ° to 100 °, preferably 80 ° to 95 °. The insulator 280 may be processed using a lithography method. In addition, dry etching, wet etching, or the like can be used to form the opening, but dry etching that can be anisotropically etched is preferably used to form the opening having the above shape.

In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that a mask is not necessary when an electron beam or an ion beam is used. Note that the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.

Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed over the insulator 280, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do. The etching of the insulator 280 and the insulator 274 may be performed after the resist mask is removed, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the oxide film is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed. Or the structure which applies the high frequency power supply of the same frequency to each parallel plate type | mold electrode may be sufficient. Or the structure which applies the high frequency power source from which a frequency differs to each parallel plate type | mold electrode may be sufficient. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

An insulator 251A is formed so as to cover the inside of the opening and the insulator 280 (see FIG. 3A). The insulator 251A is preferably formed on the side wall of the opening formed substantially vertically, and is preferably formed using an atomic layer deposition (ALD) method having excellent coverage. The insulator 251A is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, for example, aluminum oxide or hafnium oxide. By providing such an insulator 251A on the side surface of the opening, intrusion of impurities such as water or hydrogen into the insulator 280 can be suppressed after a post-process or device creation.

Next, anisotropic etching is performed on the insulator 251A to remove the insulator 251A formed on the top surface of the insulator 280 and the bottom of the opening, and the insulator 251a, the insulator 251b, and the insulating are formed on the side surface of the opening. A body 451a and an insulator 451b are formed (see FIG. 3B). Note that the insulator 251a, the insulator 251b, the insulator 451a, the insulator 451b, and the insulator formed at the same time in the process may be collectively referred to as an insulator 251.

Subsequently, a conductor is formed inside the opening. The conductor is formed by forming a conductive film so as to cover the inside of the opening and the insulator 280, and removing the conductive film above the insulator 280 by polishing using a chemical mechanical polishing (CMP) method or the like. Can do. For the formation of the conductive film, an ALD method, a CVD method, a sputtering method, a plating method, or the like can be used. In this embodiment, after a conductive film made of titanium nitride is formed and a conductive film made of tungsten is formed thereon, polishing is performed by a CMP method, so that the conductor 252a, the conductor 252b, the conductor 454a, and the conductor A body 454b is formed (see FIG. 4A). Note that in this specification, the conductor 252a, the conductor 252b, the conductor 454a, and the conductor 454b may be collectively referred to as a conductor 252.

In the case where the material used for the conductor 252 is easily oxidized and the resistance value is increased due to the oxidation, that is, the conductivity may be deteriorated, it is necessary to prevent oxidation in a subsequent process. Therefore, in this embodiment, the conductor 254 is formed so as to cover the conductor 252. The conductor 254 forms a conductive film so as to cover the conductor 252a, the conductor 252b, the conductor 454a, the conductor 454b, and the insulator 280, and the conductor 252a, the conductor 252b, the conductor 454a, and the conductor The conductive film can be formed so that 454b is not exposed (see FIG. 4B). In this embodiment, tantalum nitride is used as the conductor 252a, the conductor 252b, the conductor 454a, and the conductor 454b in order to prevent oxidation of tungsten and titanium nitride used for the conductor 252.

Note that the conductor 254 may be provided for each conductor provided inside the opening, that is, for each opening, or may include a pattern of a conductor such as a wiring formed in a later process. May be formed. The former case is advantageous in that the exposed area of the insulator 280 after the formation of the conductor 254 is increased, and the contact area between the insulator 282 and the insulator 280 described later is increased. On the other hand, in the latter case, one conductor 254 covers the plurality of openings and is electrically connected to the conductor formed therein. In addition, when the insulator is etched in a later step to form a recess corresponding to the pattern of the conductor, the conductor 254 is preferable as an etching stopper. The latter method is also preferable when the distance between the openings is short and it is difficult to separate the respective conductors 254. Depending on the size of the conductor 254 and the distance (space) between the conductors 254, a formation method may be properly used, and the above formation methods may be combined as appropriate in one device.

Next, the insulator 282 is formed so as to cover the insulator 280 and the conductor 254 (see FIG. 5). Oxygen is preferably supplied to the insulator 280 by formation of the insulator 282. In this embodiment, aluminum oxide is formed as the insulator 282 by a sputtering method. Here, since the conductor 252a, the conductor 252b, the conductor 454a, and the conductor 454b are covered with the conductor 254, oxidation due to formation of the insulator 282 is suppressed.

It is preferable that oxygen be supplied to the insulator 280 by forming the insulator 282 over the insulator 280. In particular, in the case where an oxide semiconductor is used for the transistor 200, by providing an insulator to which oxygen is supplied in an interlayer film or the like in the vicinity of the transistor 200, oxygen vacancies in the oxide 230 included in the transistor 200 are reduced and reliability is improved. Can be improved. Further, the insulator 280 that covers the transistor 200 may function as a planarization film that covers the uneven shape below the transistor 200.

As the insulator 280, an oxide material from which part of oxygen is released by heating is preferably used. The oxide which desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ in TDS analysis. An oxide film having atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

An insulator 284 is formed over the insulator 282. The insulator 284 can be formed using silicon oxynitride, silicon oxide, silicon nitride oxide, silicon nitride, or the like by a CVD method, a sputtering method, or the like.

A recess is formed in the insulator 282 and the insulator 284 (see FIG. 6). For the formation of the recess, dry etching or wet etching can be used. However, dry etching is preferably used for fine processing and anisotropic etching. Note that in forming the recess, the insulator 282 and the insulator 284 are processed so that the conductor 254 and / or the insulator 280 are exposed.

Note that as described above, the recess may be formed only above the conductor 254, or may be formed above the conductor 254 and the insulator 280 so that the recess extends over the conductor 254. Good.

Next, a conductor 256 is formed inside the recess. The conductor can be formed by forming a conductive film so as to cover the inside of the opening and the insulator 284 and removing the conductive film above the insulator 284 by polishing using a CMP method or the like. For the formation of the conductive film, an ALD method, a CVD method, a sputtering method, a plating method, or the like can be used. In this embodiment, a conductive film made of tantalum nitride is formed by a sputtering method, a conductive film made of ruthenium is formed thereon by a CVD method, and a conductive film made of copper is further formed thereon by a plating method. The semiconductor device shown in FIG. 1 can be obtained by performing polishing by the CMP method and forming the conductor 256. The formation of each conductive film is not limited to the above. A conductive film made of ruthenium may be formed before forming a conductive film made of tantalum nitride, and then a conductive film made of tantalum nitride may be formed. In forming a conductive film made of copper, copper may be formed by a plating method using a conductive film made of ruthenium as a seed layer, or after forming copper as a seed layer using a sputtering method. Copper may be further formed by the method.

The conductor 256 formed in this manner can function as a wiring. The conductor 256 is electrically connected to the transistor 200 or the transistor 400 through the conductor 254, the conductor 252a, the conductor 252b, the conductor 454a, and the conductor 454b, and forms various circuits.

An insulator 251a, an insulator 251b, an insulator 451a, and an insulator 451b are provided on the side surface of the opening formed in the insulator 280 so that impurities such as water or hydrogen enter the insulator 280. Therefore, deterioration of characteristics of the semiconductor device, particularly long-term characteristics, can be suppressed, and reliability can be improved. In addition, when the insulator 282 is formed in order to supply oxygen to the insulator 280, a conductor 254 for suppressing oxidation of the conductor formed to be embedded in the insulator 280 is provided. In addition, it is possible to prevent an increase in resistance value in the conductor and a connection portion between the conductor and the wiring, and a semiconductor device with improved characteristics such as an operating frequency and an on-current can be manufactured.

<Constituent materials for semiconductor devices>
Hereinafter, constituent materials that can be used for the semiconductor device will be described.

<< Board >>
As a substrate over which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

A flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The substrate has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. When the substrate is thinned, a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. Further, as the substrate, a sheet woven with fibers, a film, a foil, or the like may be used. A substrate that is a flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed. As the substrate which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.

<< Insulator >>
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

Here, for the insulator that functions as a gate insulator, a high-k material having a high relative dielectric constant is used for the insulator that functions as a gate insulator, so that transistors can be miniaturized and highly integrated. Become. On the other hand, for an insulator functioning as an interlayer film, a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant as an interlayer film. Therefore, the material may be selected according to the function of the insulator.

Insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium. There are oxynitrides having silicon and nitrides having silicon and hafnium.

Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Examples include silicon oxide or resin having holes.

In particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Further, for example, silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.

In addition, a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.

Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

For example, as the insulator 222, the insulator 214, and the insulator 210, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. Note that the insulator 222, the insulator 214, and the insulator 210 preferably include aluminum oxide, hafnium oxide, or the like.

For example, as the insulator 212, the insulator 216, the insulator 220, the insulator 224, and the insulator 250, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon An insulator containing gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. Specifically, silicon oxide, silicon oxynitride, or silicon nitride is preferably included.

For example, in the insulator 224 and the insulator 250 that function as gate insulators, aluminum oxide, gallium oxide, or hafnium oxide is in contact with the oxide 230, whereby silicon contained in silicon oxide or silicon oxynitride is oxidized. It can suppress mixing with the thing 230. FIG. On the other hand, in the insulator 224 and the insulator 250, silicon oxide or silicon oxynitride is in contact with the oxide 230, so that an interface between aluminum oxide, gallium oxide or hafnium, and silicon oxide or silicon oxynitride is formed. A trap center may be formed. In some cases, the trap center can change the threshold voltage of the transistor in the positive direction by capturing electrons.

The insulator 212, the insulator 216, and the insulator 280 preferably include an insulator with a low relative dielectric constant. For example, the insulator 212, the insulator 216, and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, and oxide to which carbon and nitrogen are added It is preferable to have silicon, silicon oxide having holes, resin, or the like. Alternatively, the insulator 212, the insulator 216, and the insulator 280 are added with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and nitrogen. It is preferable to have a stacked structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

As the insulator 270 and the insulator 272, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. Examples of the insulator 270 and the insulator 272 include aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, and silicon oxide Alternatively, silicon nitride or the like may be used.

<< Conductor >>
As the conductor, a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more elements can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

A plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

Note that in the case where an oxide is used for a channel formation region of the transistor, the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

In particular, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as the conductor functioning as a gate electrode. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed can be captured in some cases. Alternatively, hydrogen mixed from an external insulator or the like may be captured.

As the conductor 260a, the conductor 260b, the conductor 203a, the conductor 203b, the conductor 205a, the conductor 205b, the conductor 252a, and the conductor 252b, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel A material containing one or more metal elements selected from titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

<< Metal oxide >>
As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. Below, the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one kind or plural kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

Here, a case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Composition of metal oxide]
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

Note that in this specification and the like, they may be described as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where a CAC-OS or a CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is an electron serving as carriers. It is a function that does not flow. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

Oxide semiconductors have various structures and different properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor having oxide semiconductor]
Next, the case where the above oxide semiconductor is used for a transistor is described.

Note that by using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

For the transistor, an oxide semiconductor with low carrier density is preferably used. In the case where the carrier density of the oxide semiconductor film is decreased, the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / What is necessary is just to be cm ³ or more.

In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.

In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in an adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

[impurities]
Here, the influence of each impurity in the oxide semiconductor is described.

In the oxide semiconductor, when silicon or carbon which is one of Group 14 elements is included, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density is increased, and the oxide semiconductor is likely to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Accordingly, nitrogen in the oxide semiconductor is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5 × 10 ¹⁹ atoms / cm ^{3 in} SIMS, preferably 5 × 10 ^18. atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced for the channel region of the transistor, stable electrical characteristics can be imparted.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
<Method for Manufacturing Semiconductor Device>
Hereinafter, an example of a detailed method for manufacturing the transistor 200 included in the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 7 to 15, (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A1-A2 shown to (A). Moreover, (C) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of A3-A4 in (A).

First, the substrate 208 is prepared, and the insulator 210a and the insulator 210b are sequentially formed over the substrate (see FIG. 7). The insulator 210a and the insulator 210b are formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, or a pulsed laser deposition (PLD). Or ALD method can be used.

The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Further, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Further, the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.

In this embodiment, an aluminum oxide film is formed as the insulator 210a by an ALD method, and an aluminum oxide film is formed as the insulator 210b by a sputtering method. Conversely, an aluminum oxide film may be formed as the insulator 210a by a sputtering method, and an aluminum oxide film may be formed as the insulator 210b by an ALD method. Alternatively, a single-layer structure in which only one of the insulator 210a and the insulator 210b is formed may be used.

Next, the insulator 212 is formed over the insulator 210b. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 212 by a CVD method.

Next, an opening reaching the insulator 210b is formed in the insulator 212. The opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. Wet etching may be used to form the opening, but dry etching is preferable for fine processing. The insulator 210b is preferably selected from an insulator that functions as an etching stopper film when the insulator 212 is etched to form a groove. For example, in the case where a silicon oxynitride film is used for the insulator 212 that forms the groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the insulator 210b.

After the opening is formed, a conductive film to be the conductor 203a is formed. The conductive film preferably includes a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductor to be the conductor 203a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as the conductive film to be the conductor 203a, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using such a metal nitride as the conductor 203a, it is possible to prevent the metal from diffusing out of the conductor 203a even when a metal that easily diffuses such as copper is used in the conductor 203b described later.

Next, a conductive film to be the conductor 203b is formed over the conductive film to be the conductor 203a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film to be the conductor 203b.

Next, by performing CMP treatment, the conductive film to be the conductor 203a and part of the conductive film to be the conductor 203b are removed, and the insulator 212 is exposed. As a result, the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening. Accordingly, the conductor 203 including the conductor 203a and the conductor 203b having a flat upper surface can be formed (see FIG. 7). Note that part of the insulator 212 may be removed by the CMP treatment.

Next, the insulator 214 is formed over the conductor 203. The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon nitride is formed as the insulator 214 by a CVD method. In this manner, by using an insulator that does not easily transmit copper, such as silicon nitride, as the insulator 214, even if a metal that easily diffuses such as copper is used for the conductor 203b, the metal is a layer above the insulator 214. Can be prevented from diffusing.

Next, an insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 216 by a CVD method.

Next, an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216. Wet etching may be used to form the opening, but dry etching is preferable for fine processing.

After the opening is formed, a conductive film to be the conductor 205a is formed. The conductive film to be the conductor 205a desirably includes a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, tantalum nitride is formed by a sputtering method as the conductive film to be the conductor 205a.

Next, a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as the conductive film to be the conductor 205b, titanium nitride is formed by an ALD method, and tungsten is formed by a CVD method on the titanium nitride.

Next, by performing CMP treatment, the conductive film to be the conductor 205a and part of the conductive film to be the conductor 205b are removed, and the insulator 216 is exposed. As a result, the conductive films to be the conductors 205a and 205b remain only in the openings. Accordingly, the conductor 205 including the conductor 205a and the conductor 205b having a flat upper surface can be formed (see FIG. 7). Note that part of the insulator 212 may be removed by the CMP treatment.

Next, the insulator 220 is formed over the insulator 216 and the conductor 205. The insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the insulator 222 is formed over the insulator 220. The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In particular, as the insulator 222, hafnium oxide is preferably formed by an ALD method. Hafnium oxide formed by the ALD method has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 200 do not diffuse inside the transistor 200 and are contained in the oxide 230. Generation of oxygen vacancies can be suppressed.

Next, an insulating film to be the insulator 224 is formed over the insulator 222. The insulating film to be the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. The first heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed in a reduced pressure state. Alternatively, in the first heat treatment, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. May be.

By the heat treatment, impurities such as hydrogen and water contained in the insulating film to be the insulator 224 can be removed.

Alternatively, plasma treatment containing oxygen in a reduced pressure state may be performed as the heat treatment. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example. Alternatively, a power supply for applying RF (Radio Frequency) may be provided on the substrate side. High-density oxygen radicals can be generated by using high-density plasma, and by applying RF to the substrate side, oxygen radicals generated by the high-density plasma are efficiently guided into the insulating film to be the insulator 224. be able to. Alternatively, plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that the first heat treatment may not be performed.

The heat treatment can also be performed after the insulator 220 is formed and after the insulator 222 is formed. Although the above heat treatment conditions can be used for the heat treatment, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.

In this embodiment, as the heat treatment, treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere after the insulating film to be the insulator 224 is formed.

Next, an oxide film to be the oxide 230a and an oxide film to be the oxide 230b are sequentially formed over the insulating film to be the insulator 224. Note that the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film to be the oxide 230a and the oxide film to be the oxide 230b. The vicinity of the interface between the oxide film to be formed and the oxide film to be the oxide 230b can be kept clean.

The oxide film to be the oxide 230a and the oxide film to be the oxide 230b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, in the case where an oxide film to be the oxide 230a and an oxide film to be the oxide 230b are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. In the case where the oxide film is formed by a sputtering method, the In-M-Zn oxide target can be used.

In particular, part of oxygen contained in the sputtering gas may be supplied to the insulating film to be the insulator 224 when the oxide film to be the oxide 230a is formed. Note that the ratio of oxygen contained in the sputtering gas for the oxide film to be the oxide 230a is 70% or more, preferably 80% or more, and more preferably 100%.

In the case where the oxide film to be the oxide 230b is formed by a sputtering method, an oxygen-deficient type is formed by forming the film so that the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. An oxide semiconductor is formed. A transistor including an oxygen-deficient oxide semiconductor can have a relatively high field-effect mobility.

In this embodiment, the oxide film to be the oxide 230a is formed by a sputtering method with a target of In: Ga: Zn = 1: 3: 4 [atomic ratio]. The oxide film to be the oxide 230b is formed by a sputtering method with a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Note that each oxide film is preferably formed in accordance with characteristics required for the oxide 230 by appropriately selecting a deposition condition and an atomic ratio.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, impurities such as hydrogen and water in the oxide film to be the oxide 230a and the oxide film to be the oxide 230b can be removed. In this embodiment mode, after processing for one hour at a temperature of 400 ° C. in a nitrogen atmosphere, the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.

Next, the insulator 224, the oxide 230a, and the oxide 230b are formed by processing the insulating film to be the insulator 224, the oxide film to be the oxide 230a, and the oxide film to be the oxide 230b into island shapes. (See FIG. 7). In this step, for example, the insulator 222 can be used as an etching stopper film.

Here, the insulator 224 is not necessarily processed into an island shape. Half-etching may be performed on the insulating film to be the insulator 224. By performing half-etching on the insulating film, the insulating film 224 is formed under the oxide 230c formed in a later step. Note that the insulating film to be the insulator 224 can be processed into an island shape when the insulating film 272A which is a later step is processed.

Here, the oxide 230 a and the oxide 230 b are formed so as to overlap with the conductor 205 at least partially. In addition, the side surface of the oxide 230 is preferably substantially perpendicular to the insulator 222. Since the side surface of the oxide 230 is substantially perpendicular to the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased. Note that in the cross-sectional shape, an angle formed by the side surface of the oxide 230 and the upper surface of the insulator 222 may be an acute angle. In that case, the angle formed between the side surface of the oxide 230 and the upper surface of the insulator 222 is preferably as large as possible.

In addition, a curved surface is provided between the side surface of the oxide 230 and the upper surface of the oxide 230. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm at the end of the oxide 230b.

In addition, the film | membrane coverage in a subsequent film-forming process improves by not having a corner | angular part in an edge part.

Note that the oxide film may be processed by a lithography method. In addition, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing. In the lithography method, a hard mask may be used instead of the resist mask.

In addition, by performing the treatment such as dry etching, impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the oxide 230a, the oxide 230b, or the like. Examples of impurities include fluorine and chlorine.

Cleaning is performed in order to remove the impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate.

As the wet cleaning, a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-described heat treatment conditions can be used.

Next, an oxide film to be the oxide 230c is formed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b. The oxide film to be the oxide 230c can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The oxide film to be the oxide 230c may be formed using the same conditions as those for the oxide film to be the oxide 230a, or the same conditions as the film formation conditions for the oxide film to be the oxide 230b. You may form into a film using. Further, a film may be formed by combining these conditions.

In this embodiment, the oxide film to be the oxide 230c is formed by a sputtering method with a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. At this time, the film may be formed with an oxygen ratio of 70% or more, preferably 80% or more, more preferably 100%.

Note that the oxide film is preferably formed in accordance with characteristics required for the oxide 230 by appropriately selecting a deposition condition and an atomic ratio.

Next, the oxide film to be the oxide 230c is processed into an island shape to form the oxide 230c (see FIG. 8). Here, the oxide 230c is formed to cover the oxide 230a and the oxide 230b. It is preferable. The processing may be performed using a lithography method. In addition, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing. In the lithography method, a hard mask may be used instead of the resist mask.

Next, over the insulator 222 and the oxide 230, an insulating film to be the insulator 250, a conductive film to be the conductor 260a, a conductive film to be the conductor 260b, a conductive film to be the conductor 260c, and the insulator An insulating film to be 270 is sequentially formed.

The insulating film to be the insulator 250 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Note that oxygen is excited by microwaves, high-density oxygen plasma is generated, and the insulating film to be the insulator 250 is exposed to the oxygen plasma, so that oxygen is supplied to the insulating film to be the insulator 250 and the oxide 230. Can be introduced.

Further, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film to be the insulator 250 can be reduced.

The conductive film to be the conductor 260a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, for example, an oxide semiconductor that can be used as the oxide 230 becomes a conductive oxide by performing resistance reduction treatment. Therefore, an oxide that can be used as the oxide 230 may be formed as the conductive film to be the conductor 260a, and the resistance of the oxide may be reduced in a later step. Note that oxygen can be added to the insulator 250 by forming an oxide that can be used as the oxide 230 over the conductive film to be the conductor 260a by a sputtering method in an atmosphere containing oxygen. it can. By adding oxygen to the insulator 250, the added oxygen can supply oxygen to the oxide 230 through the insulator 250.

The conductive film to be the conductor 260b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the case where an oxide semiconductor that can be used as the oxide 230 is used for the conductive film to be the conductor 260a, the conductive film to be the conductor 260a is formed by sputtering the conductive film to be the conductor 260b. The electrical resistance value can be reduced to provide a conductor. This can be called an OC (Oxide Conductor) electrode. A conductor may be further formed on the conductor on the OC electrode by sputtering or the like.

The conductive film to be the conductor 260c can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed. In this embodiment, treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere.

The insulating film to be the insulator 270 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the thickness of the insulating film to be the insulator 270 is preferably larger than the thickness of the insulating film 272A which is formed in a later step. Accordingly, when the insulator 272 is formed in a later process, the insulator 270 can easily remain on the conductor 260.

Next, the insulating film to be the insulator 270 is etched to form the insulator 270. Subsequently, using the insulator 270 as a mask, the insulating film to be the insulator 250, the conductive film to be the conductor 260a, the conductive film to be the conductor 260b, and the conductive film to be the conductor 260c are etched to form the insulator 250. And the conductor 260 (the conductor 260a, the conductor 260b, and the conductor 260c) are formed (see FIG. 9). The insulator 250, the conductor 260a, the conductor 260b, the conductor 260c, and the insulator 270 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.

The side surface of the insulator 250, the side surface of the conductor 260a, the side surface of the conductor 260b, the side surface of the conductor 260c, and the side surface of the insulator 270 are preferably in the same plane.

In addition, the same surface shared by the side surface of the insulator 250, the side surface of the conductor 260a, the side surface of the conductor 260b, the side surface of the conductor 260c, and the side surface of the insulator 270 is preferably substantially perpendicular to the substrate. . Note that in the cross-sectional shape, the insulator 250, the conductor 260a, the conductor 260b, the conductor 260c, or the side surface of the insulator 270 and the top surface of the oxide 230 may have an acute angle. In that case, the angle between the side surface of the insulator 250, the conductor 260a, the conductor 260b, the conductor 260c, or the insulator 270 and the top surface of the oxide 230 is preferably as large as possible.

Further, in some cases, the upper portion of the region where the oxide 230 does not overlap with the insulator 250 is etched. In this case, the thickness of the region of the oxide 230 that overlaps with the insulator 250 may be larger than the thickness of the region that does not overlap with the insulator 250.

Next, an insulating film 272A is formed so as to cover the insulator 222, the insulator 224, the oxide 230, the insulator 250, the conductor 260, and the insulator 270 (see FIG. 10). The insulating film 272A is preferably formed with a sputtering apparatus. By using a sputtering method, an excess oxygen region can be easily formed in the insulator 250 in contact with the insulator 272.

Here, during film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, whereby particles sputtered from the target are ejected. The sputtered particles adhere to and deposit on the film formation surface to form a film. In addition, some ions recoil by the target, pass through the formed film through the film formed as recoil ions, and may be taken into the insulator 250 in contact with the deposition surface. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulator 250. When the ions are taken into the insulator 250, a region into which the ions are taken is formed in the insulator 250. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 250.

By introducing excess oxygen into the insulator 250, an excess oxygen region can be formed. Excess oxygen in the insulator 250 is supplied to the oxide 230, so that oxygen vacancies in the oxide 230 can be filled. Further, similarly to the insulator 250, oxygen is preferably introduced into the insulator 224 through the oxide 230 c.

Therefore, as a means for forming the insulating film 272A, a film is formed in an oxygen gas atmosphere using a sputtering apparatus, so that oxygen is supplied to the insulator 250 and the insulator 224 while the insulating film 272A is formed. Can be introduced. For example, by using aluminum oxide having a barrier property for the insulating film 272A, excess oxygen introduced into the insulator 250 can be effectively contained.

Subsequently, in the oxide 230, a region 231, a region 232, a region 233, and a region 234 shown in FIG. 33 are formed. The region 231, the region 232, and the region 233 are regions in which a metal atom such as indium or an impurity is added to a metal oxide provided as the oxide 230 to reduce resistance. Note that each region has higher conductivity than at least the oxide 230b in the region 234.

In order to add impurities to the regions 231, 232, and 233, for example, a metal element such as indium and a dopant that is at least one of impurities may be added through the insulating film 272A (see FIG. 11). .)

The dopant is added by an ion implantation method in which ionized source gas is added by mass separation, an ion doping method in which ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like. Can be used. When mass separation is performed, the ionic species to be added and the concentration thereof can be strictly controlled. On the other hand, when mass separation is not performed, high-concentration ions can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.

The oxide 230 can have high carrier density and low resistance by increasing the indium content. Thus, a metal element such as indium that improves the carrier density of the oxide 230 can be used as the dopant.

That is, in the region 231, the region 232, and the region 233, by increasing the content of metal atoms such as indium in the oxide 230, electron mobility can be increased and resistance can be reduced.

Accordingly, at least the atomic ratio of indium to the element M in the region 231 is larger than the atomic ratio of indium to the element M in the region 234.

As the dopant, the above-described element that forms oxygen vacancies or an element that is trapped by oxygen vacancies may be used. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

Here, the insulating film 272A is provided to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 270. Therefore, in the direction perpendicular to the top surface of the oxide 230, the thickness of the insulating film 272A is different in the vicinity of the insulator 250, the conductor 260, and the insulator 270 side and in other regions. That is, the thickness of the insulating film 272A is larger in the periphery of the insulator 250, the conductor 260, and the insulator 270 than in the other regions. In other words, by adding a dopant through the insulating film 272A, the region 231, the region 232, and the region 233 can be provided in a self-aligned manner even in a transistor whose channel length is reduced to about 10 to 30 nm. . The region 233 may be formed by diffusion of the dopants in the region 231 and the region 232 in a process such as a heat treatment performed in a later process.

Further, in the transistor 200, since the region 233 and the region 232 are provided, a high-resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; On-state current and mobility can be increased. In addition, since the region 233 includes the source region and the drain region, and the gate does not overlap in the channel length direction, formation of unnecessary capacitance can be suppressed. In addition, by including the region 233, leakage current at the time of non-conduction can be reduced.

Therefore, by appropriately selecting the range of the region 231a and the region 231b, a transistor having electrical characteristics that meet requirements can be easily provided in accordance with circuit design.

Next, anisotropic etching is performed on the insulating film 272A to form the insulator 272 in contact with the side surfaces of the insulator 250, the conductor 260, and the insulator 270 (see FIG. 12). As an anisotropic etching process, it is preferable to perform a dry etching process. Thus, the insulator 272 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.

Here, by forming the insulator 270 thicker than the insulating film 272A, the insulator 270 and the insulator 272 remain even if the insulating film 272A over the insulator 270 is removed. be able to. The insulating film 272A on the side surface of the oxide 230 is removed by making the height of the structure including the insulator 250, the conductor 260, and the insulator 270 higher than the height of the oxide 230. Can do. Further, when the end portion of the oxide 230 is round, the time for removing the insulating film 272A formed in contact with the side surface of the oxide 230 is shortened, and the insulator 272 is more easily formed. be able to.

Although not illustrated, the insulating film 272 </ b> A may remain on the side surface of the oxide 230. In that case, the film property of an interlayer film formed in a later process can be improved. In addition, since the insulator remains on the side surface of the oxide 230, impurities such as water or hydrogen mixed in the oxide 230 can be reduced, and oxygen can be prevented from being outwardly diffused from the oxide 230. is there.

Since the structure body in which the insulating film 272A remains is formed in contact with the side surface of the oxide 230, an insulator 274 containing an element serving as an impurity is formed in a later step, and the region 231a, In the case where the region 231b is formed, the interface region between the insulator 224 and the oxide 230 is not reduced in resistance, and thus leakage current can be suppressed. Alternatively, even when a dopant is added so that the oxide 230a has a concentration peak when indium is added to the oxide 230, generation of a leakage current through the oxide 230a can be suppressed.

Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. By performing the heat treatment, the added dopant diffuses into the region 233 of the oxide 230, so that the on-state current can be increased.

Next, the insulator 274 is formed so as to cover the insulator 224, the oxide 230, the insulator 272, and the insulator 270 (see FIG. 13).

For example, aluminum oxide is preferably formed as the insulator 274 by an ALD method. Aluminum oxide formed by the ALD method has a high film property and is a dense film. The insulator 274 preferably has a barrier property against oxygen, hydrogen, and water. Since the insulator 274 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 200 do not diffuse inside the transistor 200 and are contained in the oxide 230. Generation of oxygen vacancies can be suppressed.

Here, the insulator 274 is preferably in contact with the insulator 222 at the outer edge of the transistor 200. With such a structure, the transistor 200 can be surrounded by an insulator having a barrier property. With this structure, impurities such as hydrogen and water can be prevented from entering the transistor 200. Alternatively, oxygen contained in the insulator 224 and the insulator 250 can be prevented from diffusing from the transistor 200 to the interlayer film.

In addition, by providing such an insulator 274 over the region 231a and the region 231b, oxygen or excessive impurities such as water or hydrogen can be mixed into the region 231a and the region 231b, and the carrier density can be changed. Can be prevented.

Further, by forming the insulator 274 containing an element that becomes an impurity in contact with the oxide 230, the impurity can be added to the region 231, the region 232, and the region 233.

In the case where the insulator 274 containing an impurity element is formed in contact with the oxide 230, the region 231a and the region 231b are added with an impurity element such as hydrogen or nitrogen included in the deposition atmosphere of the insulator 274. Is done. Oxygen vacancies are formed by the added impurity element around the region in contact with the insulator 274 of the oxide 230, and the impurity element enters the oxygen vacancies, whereby the carrier density is increased and the resistance is reduced. At that time, the impurity diffuses also in the region 232 and the region 233 which are not in contact with the insulator 274, so that the resistance is reduced.

Therefore, it is preferable that the concentration of at least one of hydrogen and nitrogen be higher in the region 231a and the region 231b than in the region 234. The concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like. Here, the concentration of hydrogen or nitrogen in the region 234 is approximately equal to the vicinity of the center of the region overlapping with the insulator 250 of the oxide 230b (for example, the distance from both side surfaces in the channel length direction of the insulator 250b of the oxide 230b). The concentration of hydrogen or nitrogen in (part) may be measured.

Note that the resistance of the region 231, the region 232, and the region 233 is reduced by adding an element that forms oxygen vacancies or an element that is captured by oxygen vacancies. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 231, the region 232, and the region 233 may include one or more of the above elements.

In the case of forming the insulator 274 containing an impurity element, the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulator 274 including the element serving as an impurity is preferably formed in an atmosphere containing at least one of nitrogen and hydrogen. By performing deposition in such an atmosphere, oxygen vacancies are formed around the oxide 230b and the oxide 250c that do not overlap with the insulator 250, and the oxygen vacancies are bonded to an impurity element such as nitrogen or hydrogen. Thus, the carrier density can be increased. In this manner, the region 231a and the region 231b with reduced resistance can be formed. As the insulator 274, silicon nitride, silicon nitride oxide, or silicon oxynitride can be used by, for example, a CVD method. In this embodiment, silicon nitride oxide is used as the insulator 274.

Therefore, in the method for manufacturing a semiconductor device described in this embodiment, the source region and the drain region are formed in a self-aligned manner by forming the insulator 274 even in a transistor whose channel length is miniaturized to about 10 nm to 30 nm. be able to. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.

Here, an upper surface and side surfaces of the conductor 260 and the insulator 250 are covered with the insulator 270 and the insulator 272, so that an impurity element such as nitrogen or hydrogen is mixed into the conductor 260 and the insulator 250. Can be prevented. Thus, an impurity element such as nitrogen or hydrogen can be prevented from entering the region 234 functioning as a channel formation region of the transistor 200 through the conductor 260 and the insulator 250. Therefore, the transistor 200 having favorable electrical characteristics can be provided.

Note that in the above, the region 231, the region 232, the region 233, and the region 234 are formed using the dopant addition treatment or the reduction in resistance by the formation of the insulator 274, but this embodiment mode is based on this. It is not limited. For example, each region or the like may be formed through both steps. Further, plasma treatment may be used.

For example, plasma treatment may be performed on the oxide 230 using the insulator 250, the conductor 260, the insulator 272, and the insulator 270 as masks. The plasma treatment may be performed in an atmosphere containing an element that forms oxygen vacancies or an element trapped by oxygen vacancies. For example, plasma treatment may be performed using argon gas and nitrogen gas.

Next, an insulating film to be the insulator 280 is formed over the insulator 274. The insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used. In this embodiment, silicon oxynitride is used as the insulating film.

Next, part of the insulating film to be the insulator 280 is removed to form the insulator 280 (see FIG. 14). The insulator 280 is preferably formed so that the upper surface has flatness. For example, the top surface of the insulator 280 may have flatness immediately after being formed as an insulating film to be the insulator 280. Alternatively, for example, the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process. Examples of the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process. Note that the top surface of the insulator 280 is not necessarily flat.

Next, an opening reaching the region 231a of the oxide 230 and an opening reaching the region 231b of the oxide 230 are formed in the insulator 280 and the insulator 274. The opening may be formed using a lithography method. Note that the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 252a and the conductor 252b are provided in contact with the side surface of the oxide 230.

After the step illustrated in FIG. 14, the insulator 251, the conductor 252, the conductor 254, the conductor 256, the insulator 282, and the insulator 284 are formed by performing the steps illustrated in FIGS. it can. In this manner, the transistor 200 illustrated in FIG. 15 can be manufactured.

Note that as illustrated in FIGS. 15A and 15C, a conductor 252 may be provided in an opening formed in the insulator 280, the insulator 274, and the insulator 270 and reaching the upper surface of the conductor 260c. . An insulator 251 is preferably formed on the side surface of the opening, as in the first embodiment. A conductor 252 is formed inside the insulator 251.

A conductor 254 is provided so as to cover the conductor 252. In addition, a conductor 256 is provided in contact with the upper surface of the conductor 254 inside the recesses of the insulator 282 and the insulator 284. The conductor 256 can function as a wiring connected to the gate of the transistor 200.

Here, FIG. 19A is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in FIG.

The conductor 252 is preferably in contact with at least the upper surface of the oxide 230 and further in contact with the side surface of the oxide 230. In particular, as illustrated in FIG. 19A, the conductor 252 is preferably in contact with both or one of the side surface on the A5 side and the side surface on the A6 side in the channel width direction of the oxide 230. As described above, the conductor 252 is in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, so that the contact area of the conductor 252 and the oxide 230 is not increased. The contact area between the conductor 252 and the oxide 230 can be reduced. Thus, the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.

  Here, in the oxide 230, since the oxide 230a and the oxide 230b are covered with the oxide 230c, the conductor 252 is in contact with the oxide 230c. In addition, the oxide 230 c and the insulator 222 are in contact with each other at the outer edge of the insulator 224.

Note that in FIG. 19A, the conductor 254 is provided separately for each opening, but the present invention is not limited to this. As shown in FIG. 19B, the conductor 256 may be provided so as to include the pattern.
[Modification of transistor]

16 to 18 illustrate structural examples different from those of the transistor illustrated in FIG.

FIG. 16 illustrates an example in which the insulator 224 extends to the outside of the oxide 230a and the oxide 230b, and the end portion thereof coincides with the end portion of the oxide 230c.

When the oxide 230a and the oxide 230b are processed, a part of the insulator 224 which is a base is left, and when the oxide 230c is processed, the remaining insulator 224 is removed so that the insulator 224 having such a shape is formed. can get. In the transistor having such a shape, the insulator 222 and the oxide 230c are not in direct contact with each other. For other structures, the structure of the transistor 200 illustrated in FIG. 15 is referred to.

FIG. 19C shows a cross section along A5-A6 in FIG. The conductor 252 is in contact with the upper surface and the side surface of the oxide 230c. Further, the insulator 224 and the oxide 230c are provided between the insulator 222 and the conductor 252 outside the oxide 230a and the oxide 230b.

In FIG. 17, the oxide 230a, the oxide 230b, and the oxide 230c are successively formed and processed in a lump. End portions of the oxide 230a, the oxide 230b, and the oxide 230c are formed to be consistent with or continuous with each other.

In such a structure, when the insulator 272 is formed, the insulator 224 and the insulator 272 are in direct contact with each other, so that more oxygen can be supplied to the insulator 272, which is preferable. In addition, after the insulator 272 is processed, in the formation of the insulator 274, the insulator 274 covers the side surface of the insulator 224, so that the entry of impurities such as hydrogen and water into the insulator 224 is suppressed. preferable. For other structures, the structure of the transistor 200 illustrated in FIG. 15 is referred to.

FIG. 19D shows a cross section along A5-A6 in FIG. The conductor 252 is in contact with an upper surface and a side surface of the oxide 230c, a side surface of the oxide 230b, a side surface of the oxide 230a, and a side surface of the insulator 224. Further, the conductor 252 is in contact with the insulator 222 outside the oxide 230.

FIG. 18 illustrates an example in which one transistor includes a plurality of oxides 230. Source regions of the plurality of oxides 230 are connected by a first conductor 252, and drain regions of the plurality of oxides 230 are connected by a second conductor 252. In addition, a conductor 260 is provided with an insulator 250 provided over a region where a plurality of oxide 230 channels are formed.

The transistor 200 has a plurality of channel formation regions for one gate electrode, which is different from the structure of the transistor 200 illustrated in FIGS. Since the transistor 200 includes a plurality of channel formation regions, a large on-state current can be obtained. In addition, since each channel formation region has a structure covered with a gate electrode, that is, an s-channel structure, a large on-state current can be obtained in each channel formation region. Although FIG. 18 shows an example having three channel regions, the number of channel formation regions is not limited to this. For other structures, the structure of the transistor 200 illustrated in FIG. 15 is referred to.

FIG. 34 shows a cross section along A5-A6 in FIG. The conductor 252 is in contact with an upper surface and a side surface of the oxide 230c, a side surface of the oxide 230b, a side surface of the oxide 230a, and a side surface of the insulator 224. Further, the conductor 252 is in contact with the insulator 222 outside the oxide 230.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

[Storage device 1]
The semiconductor device illustrated in FIGS. 20 and 21 includes a transistor 300, a transistor 200, and a capacitor 100.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

  20 and 21, the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 3004 is electrically connected to the first gate of the transistor 200, and the wiring 3006 is electrically connected to the second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. .

  The semiconductor device illustrated in FIGS. 20 and 21 has the characteristic that the potential of the gate of the transistor 300 can be held, so that data can be written, held, and read as described below.

  Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).

  When the off-state current of the transistor 200 is small, the charge of the node FG is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when the gate of the transistor 300 is _supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 300 into a “conductive state”. Therefore, by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 300 is turned “on” when the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). On the other hand, when a low-level charge is _{supplied to} the node FG, the transistor 300 remains in a “non-conduction state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.

<Structure of Semiconductor Device 1>
The semiconductor device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

  The transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.

  The transistor 300 may be either a p-channel type or an n-channel type.

  The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

  The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.

  The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

  Note that the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

  Note that the transistor 300 illustrated in FIGS. 20A and 20B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.

  As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

  The insulator 322 may function as a planarization film that planarizes a step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

  The insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.

  As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

  Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 324 is preferably equal to or less than 0.7 times that of the insulator 326, and more preferably equal to or less than 0.6 times. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

  As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 20, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  For example, as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

  A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 20, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 20, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 370. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 20, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  An insulator 390, an insulator 209, an insulator 210a, an insulator 210b, and an insulator 212 are sequentially stacked over the insulator 384. Any of the insulator 390, the insulator 209, the insulator 210a, the insulator 210b, and the insulator 212 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

  For example, the insulator 390, the insulator 210a, and the insulator 210b have a barrier property such that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. It is preferable to use a membrane. Therefore, a material similar to that of the insulator 324 can be used.

  As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

  As the film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 390, the insulator 210a, and the insulator 210b.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

  For example, the insulator 209 and the insulator 212 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 209 and the insulator 212, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  The insulator 390, the insulator 209, the insulator 210a, the insulator 210b, and the insulator 212 are embedded with a conductor 396, a conductor included in the transistor 200 (conductor 203), and the like. Note that the conductor 396 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 396 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  In particular, the conductor 396 in a region in contact with the insulator 390, the insulator 210a, and the insulator 210b is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 are layers having a barrier property against oxygen, hydrogen, and water and can be completely separated from each other, so that diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. .

Over the insulator 212, an insulator 214 and an insulator 216 are sequentially stacked. Any of the insulator 214 and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

  For example, the insulator 214 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. Therefore, a material similar to that of the insulator 324 can be used.

  As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

  As the film having a barrier property against hydrogen, for example, the insulator 214 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

  For example, the insulator 216 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  The insulator 214 and the insulator 216 are embedded with a conductor 218, a conductor included in the transistor 200 (conductor 205), and the like. Note that the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  In particular, the conductor 218 in a region in contact with the insulator 214 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 are layers having a barrier property against oxygen, hydrogen, and water and can be completely separated from each other, so that diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. .

  A transistor 200 is provided above the insulator 216. Note that the transistor 200 illustrated in FIGS. 20A and 20B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  In addition, an insulator 251, a conductor 252, and the like are provided in openings formed in the insulator 220, the insulator 222, and the insulator 280.

  The conductor 252 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 252 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  In addition, a conductor 254 is provided over the conductor 252. The insulator 282 and the insulator 284 are provided over the insulator 280 and the conductor 254, and the conductor 256 is embedded in the insulator 282 and the insulator 284. The conductor 256 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

A capacitor element 100 is provided above the conductor 256. The capacitor 100 includes a conductor 110, a conductor 120, and an insulator 130.

An insulator 155 is provided over the conductor 256, the conductor 110 is provided in a plurality of openings formed in the insulator 155, an insulator 130 is provided over the conductor 110, and the insulator 130 is provided over the insulator 130. The conductor 120 is provided so as to overlap with the conductor 110. The insulator 282, the insulator 284, and the insulator 155 can be formed using a material similar to that of the insulator 320.

The conductor 256A in contact with the conductor 110 is electrically connected to the conductor 252A and the conductor 252B in order to be electrically connected to the transistor 200 and the transistor 300. In FIG. 20, the conductor 256A and the conductor 254 provided between the conductor 252A and the conductor 252B are separated from those provided over the conductor 256A and those provided over the conductor 256B. However, the present embodiment is not limited to this. The conductor 254 may be provided so as to be electrically connected to both the conductor 252A and the conductor 252B.

The conductor 110 includes a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above-described elements (tantalum nitride, nitride). A titanium film, a molybdenum nitride film, a tungsten nitride film, or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

  In FIG. 20, the conductor 110 has a single-layer structure; however, the structure is not limited to the structure, and a stacked structure including two or more layers may be used. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

  In addition, an insulator 130 is provided over the conductor 110 as a dielectric of the capacitor 100. Examples of the insulator 130 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. What is necessary is just to use, and it can provide by lamination | stacking or a single layer.

  For example, the insulator 130 may be formed using a material having high dielectric strength such as silicon oxynitride. With this configuration, the capacitor 100 includes the insulator 130, whereby the dielectric strength is improved and electrostatic breakdown of the capacitor 100 can be suppressed.

  A conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110. Note that the conductor 120 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

In the capacitor 100 illustrated in FIG. 20, the conductor 110, the insulator 130, and the conductor 120 overlap in the opening formed in the insulator 155, so that the conductor 110, the insulator 130, and the conductor 120 are overlapped. Is preferably a film having good coverage. Therefore, the conductor 110, the insulator 130, and the conductor 120 are preferably formed using a film formation method having good step coverage such as a CVD method or an ALD method.

Since the capacitor 100 is formed along the shape of the opening provided in the insulator 155, the capacitance can be increased as the opening is formed deeper. Further, the capacitance can be increased as the number of the openings is increased. By forming such a capacitive element 100, the capacitance can be increased without increasing the upper area of the capacitive element 100.

  An insulator 150 is provided over the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.

  The above is the description of the configuration example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Variation 1 of Storage Device 1>
An example of a modification of the present embodiment is shown in FIG. FIG. 21 is different from FIG. 20 in the configuration of the transistor 300.

  In the transistor 300 illustrated in FIG. 21, a semiconductor region 313 where a channel is formed (a part of the substrate 311) has a convex shape. In addition, a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

The conductor 252A connected to the transistor 200 and the conductor 254 provided over the conductor 252B electrically connected to the conductor 316 of the transistor 300 are provided without being separated. However, the shape of the conductor 254 is not limited to this. As shown in FIG. 20, the conductors 252A and 252B may be provided separately.

  The above is the description of the modified example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, a frame memory including a semiconductor device according to one embodiment of the present invention, which can be used for a display controller IC, a source driver IC, and the like is described.

As the frame memory, for example, a DRAM (Dynamic Random Access Memory) having 1T (transistor) 1C (capacitance) type memory cells can be applied. Further, a memory device in which an OS transistor is used for a memory cell (hereinafter referred to as “OS memory”) can be used. Here, a RAM having 1T1C type memory cells will be described as an example of the OS memory. Here, such a RAM is referred to as “DOSRAM (Dynamic Oxide Semiconductor RAM, Drum)”. FIG. 22 shows a configuration example of the DOSRAM.

<< DOSRAM 1400 >>
The DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).

The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. Global bit lines GBLL and GBLR are stacked on the memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.

The memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> -1425 <N-1>. FIG. 23A illustrates a configuration example of the local memory cell array 1425. The local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR. In the example of FIG. 23A, the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.

FIG. 23B illustrates a circuit configuration example of the memory cell 1445. The memory cell 1445 includes a transistor MW1, a capacitor CS1, and terminals B1 and B2. The transistor MW1 has a function of controlling charging / discharging of the capacitor CS1. The gate of the transistor MW1 is electrically connected to the word line, the first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the first terminal of the capacitor. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant voltage (for example, a low power supply voltage) is input to the terminal B2.

The transistor MW1 includes a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1. For example, the voltage at the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage at the terminal B1 may be changed according to the operation of the DOSRAM 1400.

The back gate of the transistor MW1 may be electrically connected to the gate, source, or drain of the transistor MW1. Alternatively, a back gate is not necessarily provided in the transistor MW1.

The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> -1426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the voltage difference between the bit line pair, and a function of holding this voltage difference. The switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.

Here, the bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier. A global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form one bit line pair. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the bit line pair (BLL, BLR) and the global bit line pair (BLL, BLR) are also represented.

(Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. Have a function of holding an address signal input from the outside and a function of generating an internal address signal

(Row circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.

A column selector 1413 and a sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413. The plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.

(Column circuit 1415)
The column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

The global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference. Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.

An outline of the writing operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by the input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address. The local sense amplifier array 1426 amplifies and holds the written data. In the specified local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.

An outline of the reading operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the voltage difference between the bit line pairs in each column as data. The switch array 1444 writes the data in the column specified by the address among the data held in the local sense amplifier array 1426 to the global bit line pair. The global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.

Since data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of times of rewriting in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.

The transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the power consumption of the display controller IC and the source driver IC can be reduced by using the DOSRAM 1400 as a frame memory.

Since the MC-SA array 1420 has a stacked structure, the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reason, since the load to be driven when accessing the DOSRAM 1400 is reduced, the energy consumption of the display controller IC and the source driver IC can be reduced.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an FPGA (field programmable gate array) is described as an example of a semiconductor device to which a transistor using an oxide according to one embodiment of the present invention (OS transistor) is applied. In the FPGA of this embodiment, an OS memory is applied to the configuration memory and the register. Here, such FPGA is referred to as “OS-FPGA”.

The OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.

FIG. 24A illustrates a configuration example of the OS-FPGA. The OS-FPGA 3110 illustrated in FIG. 24A is capable of context switching by a multi-context structure, fine-grain power gating, and NOFF (normally off) computing. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.

The programmable area 3115 has two input / output blocks (IOB) 3117 and a core 3119. The IOB 3117 has a plurality of programmable input / output circuits. The core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130. The LAB 3120 includes a plurality of PLE 3121s. FIG. 24B illustrates an example in which the LAB 3120 includes five PLE 3121s. As shown in FIG. 24C, the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.

With reference to FIGS. 25A to 25C, the SB 3131 will be described. Data, dataab, signals context [1: 0], and word [1: 0] are input to SB3131 shown in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship. The number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal. The signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.

The SB 3131 includes PRSs (programmable routing switches) 3133 [0] and 3133 [1]. The PRSs 3133 [0] and 3133 [1] have a configuration memory (CM) that can store complementary data. Note that PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.

FIG. 25B illustrates a circuit configuration example of the PRS 3133 [0]. PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration. PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal. The signals context [0] and word [0] are input to the PRS 3133 [0], and the signals context [1] and word [1] are input to the PRS 3133 [1]. For example, in the SB 3131, when the signal context [0] becomes “H”, the PRS 3133 [0] becomes active.

The PRS 3133 [0] includes a CM 3135 and a Si transistor M31. The Si transistor M31 is a pass transistor controlled by the CM 3135. The CM 3135 includes memory circuits 3137 and 3137B. The memory circuits 3137 and 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitor C31 and OS transistors MO31 and MO32. The memory circuit 3137B includes a capacitor CB31 and OS transistors MOB31 and MOB32.

The OS transistors MO31, MO32, MOB31, and MOB32 each have a back gate, and each of these back gates is electrically connected to a power supply line that supplies a fixed voltage.

The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. Nodes N32 and NB32 are charge holding nodes of the CM 3135. The OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0]. The OS transistor MOB32 controls a conduction state between the node N31 and the low potential power supply line VSS.

Data held in the memory circuits 3137 and 3137B has a complementary relationship. Therefore, either one of the OS transistors MO32 or MOB32 becomes conductive.

With reference to FIG. 25C, an operation example of PRS3133 [0] will be described. Configuration data has already been written in the PRS 3133 [0], the node N32 of the PRS 3133 [0] is “H”, and the node NB32 is “L”.

While the signal context [0] is “L”, the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained at “L”.

While the signal context [0] is “H”, the PRS 3133 [0] is active. When the signal context [0] changes to “H”, the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.

When the input terminal changes to “H” during a period in which PRS 3133 [0] is active, the OS transistor MO32 of the memory circuit 3137 is a source follower, and thus the gate voltage of the Si transistor M31 increases due to boosting. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.

In the PRS 3133 having a multi-context function, the CM 3135 also has a function of a multiplexer.

FIG. 26 shows a configuration example of the PLE 3121. The PLE 3121 includes an LUT (Look Up Table) block 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block 3123 is configured to multiplex the output of the internal 16-bit CM pair according to the inputs inA-inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration stored in the CM 3126.

The PLE 3121 is electrically connected to the power line for the voltage VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.

In order to realize NOFF computing, the register block 3124 is configured by a nonvolatile register. The nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.

The register block 3124 includes OS-FFs 3140 [1] 3140 [2]. Signals user_res, load, and store are input to the OS-FFs 3140 [1] and 3140 [2]. The clock signal CLK1 is input to the OS-FF 3140 [1], and the clock signal CLK2 is input to the OS-FF 3140 [2]. FIG. 27A illustrates a configuration example of the OS-FF 3140.

The OS-FF 3140 includes an FF 3141 and a shadow register 3142. The FF 3141 includes nodes CK, R, D, Q, and QB. A clock signal is input to the node CK. A signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node, and node Q is a data output node. Nodes Q and QB have a complementary logic relationship.

The shadow register 3142 functions as a backup circuit for the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.

The shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B. The memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitor C36 and OS transistors MO35 and MO36. The memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. Nodes N36 and NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, respectively, and are charge holding nodes. Nodes N37 and NB37 are gates of the Si transistors M37 and MB37.

The OS transistors MO35, MO36, MOB35, and MOB36 each have a back gate, and these back gates are each electrically connected to a power supply line that supplies a fixed voltage.

An example of an operation method of the OS-FF 3140 will be described with reference to FIG.

(backup)
When the “H” signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data in the FF 3141. The node N36 becomes “L” when the data of the node Q is written, and the node NB36 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed and the power switch 3127 is turned off. Although the data of the nodes Q and QB of the FF 3141 are lost, the shadow register 3142 holds the backed up data even when the power is turned off.

(recovery)
The power switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.

By combining the fine grain power gating and the backup / recovery operation of the OS-FF 3140, the power consumption of the OS-FPGA 3110 can be effectively reduced.

An error that may occur in the memory circuit is a soft error due to the incidence of radiation. A soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair. An OS memory using an OS transistor has high soft error resistance. Therefore, by installing the OS memory, a highly reliable OS-FPGA 3110 can be provided.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, an example of a CPU including a semiconductor device according to one embodiment of the present invention, such as the memory device described above, will be described.

<Configuration of CPU>
A semiconductor device 5400 illustrated in FIG. 28 includes a CPU core 5401, a power management unit 5421, and a peripheral circuit 5422. The power management unit 5421 includes a power controller 5402 and a power switch 5403. The peripheral circuit 5422 includes a cache 5404 having a cache memory, a bus interface (BUS I / F) 405, and a debug interface (Debug I / F) 406. The CPU core 5401 includes a data bus 5423, a control device 5407, a PC (program counter) 408, a pipeline register 5409, a pipeline register 5410, an ALU (Arithmetic logic unit) 411, and a register file 5412. Data exchange between the CPU core 5401 and the peripheral circuit 5422 such as the cache 5404 is performed via the data bus 5423.

The semiconductor device (cell) can be applied to many logic circuits including a power controller 5402 and a control device 5407. In particular, the present invention can be applied to all logic circuits that can be configured using standard cells. As a result, a small semiconductor device 5400 can be provided. In addition, a semiconductor device 5400 that can reduce power consumption can be provided. In addition, a semiconductor device 5400 that can increase the operation speed can be provided. In addition, a semiconductor device 5400 that can reduce fluctuations in power supply voltage can be provided.

In the semiconductor device (cell), a p-channel Si transistor and a transistor including the oxide semiconductor described in the above embodiment (preferably an oxide containing In, Ga, and Zn) in a channel formation region are used. By applying the semiconductor device (cell) to the semiconductor device 5400, a small semiconductor device 5400 can be provided. In addition, a semiconductor device 5400 that can reduce power consumption can be provided. In addition, a semiconductor device 5400 that can increase the operation speed can be provided. In particular, manufacturing costs can be kept low by using only p-channel Si transistors.

The control device 5407 controls the operations of the PC 5408, the pipeline register 5409, the pipeline register 5410, the ALU 5411, the register file 5412, the cache 5404, the bus interface 5405, the debug interface 5406, and the power controller 5402 so that the input is performed. A function of decoding and executing an instruction included in a program such as an executed application.

The ALU 5411 has a function of performing various arithmetic processes such as four arithmetic operations and logical operations.

The cache 5404 has a function of temporarily storing frequently used data. The PC 5408 is a register having a function of storing an address of an instruction to be executed next. Although not shown in FIG. 28, the cache 5404 is provided with a cache controller that controls the operation of the cache memory.

The pipeline register 5409 is a register having a function of temporarily storing instruction data.

The register file 5412 includes a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing of the ALU 5411, and the like.

The pipeline register 5410 is a register having a function of temporarily storing data used for the arithmetic processing of the ALU 5411 or data obtained as a result of the arithmetic processing of the ALU 5411.

The bus interface 5405 functions as a data path between the semiconductor device 5400 and various devices outside the semiconductor device 5400. The debug interface 5406 has a function as a signal path for inputting an instruction for controlling debugging to the semiconductor device 5400.

The power switch 5403 has a function of controlling supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400. The various circuits belong to several power domains, and the various circuits belonging to the same power domain are controlled by the power switch 5403 to supply power. The power controller 5402 has a function of controlling the operation of the power switch 5403.

The semiconductor device 5400 having the above structure can perform power gating. The flow of power gating operation will be described with an example.

First, the CPU core 5401 sets the timing at which the supply of power supply voltage is stopped in the register of the power controller 5402. Next, an instruction to start power gating is sent from the CPU core 5401 to the power controller 5402. Next, various registers and the cache 5404 included in the semiconductor device 5400 start data saving. Next, supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400 is stopped by the power switch 5403. Next, when an interrupt signal is input to the power controller 5402, supply of power supply voltage to various circuits included in the semiconductor device 5400 is started. Note that a counter may be provided in the power controller 5402 so that the timing at which the supply of the power supply voltage is started is determined using the counter without depending on the input of the interrupt signal. Next, the various registers and the cache 5404 start data restoration. Next, the execution of the instruction in the control device 5407 is resumed.

Such power gating can be performed in the entire processor or in one or a plurality of logic circuits constituting the processor. Further, power supply can be stopped even in a short time. For this reason, power consumption can be reduced with fine granularity spatially or temporally.

When power gating is performed, it is preferable that information held by the CPU core 5401 and the peripheral circuit 5422 can be saved in a short time. By doing so, the power can be turned on and off in a short time, and the power saving effect is increased.

In order to save the information held by the CPU core 5401 and the peripheral circuit 5422 in a short time, it is preferable that the flip-flop circuit can save data in the circuit (referred to as a flip-flop circuit that can be backed up). In addition, it is preferable that the SRAM cell can save data in the cell (referred to as a backupable SRAM cell). A flip-flop circuit or SRAM cell that can be backed up preferably includes a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region. As a result, when the transistor has a low off-state current, the flip-flop circuit and the SRAM cell that can be backed up can hold information without supplying power for a long time. In addition, when a transistor has a high switching speed, a backupable flip-flop circuit or an SRAM cell may be able to save and restore data in a short time.

An example of a flip-flop circuit that can be backed up will be described with reference to FIG.

A semiconductor device 5500 illustrated in FIG. 29 is an example of a flip-flop circuit that can be backed up. The semiconductor device 5500 includes a first memory circuit 5501, a second memory circuit 5502, a third memory circuit 5503, and a reading circuit 5504. A potential difference between the potential V1 and the potential V2 is supplied to the semiconductor device 5500 as a power supply voltage. One of the potential V1 and the potential V2 is at a high level, and the other is at a low level. Hereinafter, a configuration example of the semiconductor device 5500 will be described by using as an example the case where the potential V1 is low level and the potential V2 is high level.

The first memory circuit 5501 has a function of holding data when a signal D including data is input in a period in which the power supply voltage is supplied to the semiconductor device 5500. In the period when the power supply voltage is supplied to the semiconductor device 5500, the first memory circuit 5501 outputs a signal Q including retained data. On the other hand, the first memory circuit 5501 cannot hold data in a period in which the power supply voltage is not supplied to the semiconductor device 5500. That is, the first memory circuit 5501 can be called a volatile memory circuit.

The second memory circuit 5502 has a function of reading and storing (or saving) data held in the first memory circuit 5501. The third memory circuit 5503 has a function of reading and storing (or saving) data held in the second memory circuit 5502. The reading circuit 5504 has a function of reading data held in the second memory circuit 5502 or the third memory circuit 5503 and storing (or returning) the data in the first memory circuit 5501.

In particular, the third memory circuit 5503 has a function of reading and storing (or saving) data held in the second memory circuit 5502 even during a period in which the power supply voltage is not supplied to the semiconductor device 5500. .

As illustrated in FIG. 29, the second memory circuit 5502 includes a transistor 5512 and a capacitor 5519. The third memory circuit 5503 includes a transistor 5513, a transistor 5515, and a capacitor 5520. The reading circuit 5504 includes a transistor 5510, a transistor 5518, a transistor 5509, and a transistor 5517.

The transistor 5512 has a function of charging and discharging the capacitor 5519 with charges corresponding to data stored in the first memory circuit 5501. The transistor 5512 can charge and discharge the capacitor 5519 with charge according to data held in the first memory circuit 5501 at high speed. Specifically, the transistor 5512 desirably includes crystalline silicon (preferably polycrystalline silicon, more preferably single crystal silicon) in a channel formation region.

The transistor 5513 is selected to be conductive or non-conductive in accordance with the charge held in the capacitor 5519. The transistor 5515 has a function of charging and discharging the capacitor 5520 with a charge corresponding to the potential of the wiring 5544 when the transistor 5513 is in a conductive state. The transistor 5515 preferably has extremely low off-state current. Specifically, the transistor 5515 preferably includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region.

Specifically, the connection relation of each element is described. One of a source and a drain of the transistor 5512 is connected to the first memory circuit 5501. The other of the source and the drain of the transistor 5512 is connected to one electrode of the capacitor 5519, the gate of the transistor 5513, and the gate of the transistor 5518. The other electrode of the capacitor 5519 is connected to the wiring 5542. One of a source and a drain of the transistor 5513 is connected to the wiring 5544. The other of the source and the drain of the transistor 5513 is connected to one of the source and the drain of the transistor 5515. The other of the source and the drain of the transistor 5515 is connected to one electrode of the capacitor 5520 and the gate of the transistor 5510. The other electrode of the capacitor 5520 is connected to the wiring 5543. One of a source and a drain of the transistor 5510 is connected to the wiring 5541. The other of the source and the drain of the transistor 5510 is connected to one of the source and the drain of the transistor 5518. The other of the source and the drain of the transistor 5518 is connected to one of the source and the drain of the transistor 5509. The other of the source and the drain of the transistor 5509 is connected to one of the source and the drain of the transistor 5517 and the first memory circuit 5501. The other of the source and the drain of the transistor 5517 is connected to the wiring 5540. In FIG. 29, the gate of the transistor 5509 is connected to the gate of the transistor 5517; however, the gate of the transistor 5509 is not necessarily connected to the gate of the transistor 5517.

The transistor described in the above embodiment can be applied to the transistor 5515. Since the off-state current of the transistor 5515 is small, the semiconductor device 5500 can hold information without supplying power for a long time. Since the switching characteristics of the transistor 5515 are favorable, the semiconductor device 5500 can perform high-speed backup and recovery.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, one embodiment of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

<Semiconductor wafer, chip>
FIG. 30A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 712 are provided on the substrate 711. The circuit region 712 can be provided with a semiconductor device according to one embodiment of the present invention.

  Each of the plurality of circuit regions 712 is surrounded by the isolation region 713. A separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. FIG. 30B shows an enlarged view of the chip 715.

  Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD that may occur in the dicing process can be reduced, and a reduction in yield due to the dicing process can be prevented. In general, the dicing step is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, and preventing charging. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, the productivity of the semiconductor device can be increased.

<Electronic parts>
An example of an electronic component using the chip 715 will be described with reference to FIGS. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic parts have a plurality of standards, names, and the like depending on the terminal take-out direction, the terminal shape, and the like.

  Electronic components are completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).

  The post-process will be described with reference to the flowchart shown in FIG. After the semiconductor device or the like according to one embodiment of the present invention is formed over the substrate 711 in the previous step, a “back surface grinding step” of grinding the back surface (the surface where the semiconductor device or the like is not formed) of the substrate 711 is performed (step S721). . By reducing the thickness of the substrate 711 by grinding, the electronic component can be downsized.

  Next, a “dicing process” for separating the substrate 711 into a plurality of chips 715 is performed (step S722). Then, a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723). For the bonding of the chip 715 and the lead frame in the die bonding step, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that the chip 715 may be bonded on the interposer substrate instead of the lead frame.

  Next, a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip 715 are electrically connected with a thin metal wire (step S724). A silver wire, a gold wire, etc. can be used for a metal fine wire. For wire bonding, for example, ball bonding or wedge bonding can be used.

  The chip 715 that has been wire bonded is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and deterioration of characteristics due to moisture, dust, etc. (reliability Reduction) can be reduced.

  Next, a “lead plating process” for plating the leads of the lead frame is performed (step S726). The plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably. Next, a “molding process” for cutting and molding the lead is performed (step S727).

  Next, a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728). An electronic component is completed through an “inspection process” (step S729) for checking whether the external shape is good or not, and whether there is a malfunction.

  A perspective schematic view of the completed electronic component is shown in FIG. FIG. 31B is a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 750 illustrated in FIG. 31B includes a lead 755 and a chip 715. The electronic component 750 may have a plurality of chips 715.

  An electronic component 750 illustrated in FIG. 31B is mounted on a printed board 752, for example. A plurality of such electronic components 750 are combined and each is electrically connected on the printed circuit board 752 to complete a substrate (mounting substrate 754) on which the electronic components are mounted. The completed mounting board 754 is used for an electronic device or the like.

(Embodiment 8)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 28 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.

  FIG. 32A is an external view illustrating an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The automobile 2980 includes an antenna, a battery, and the like.

  An information terminal 2910 illustrated in FIG. 32B includes a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like in a housing 2911. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

  A laptop personal computer 2920 illustrated in FIG. 32C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.

  A video camera 2940 illustrated in FIG. 32D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided on the housing 2941, and the display portion 2944 is provided on the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.

  FIG. 32E illustrates an example of a bangle information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In addition, an antenna, a battery, and the like are provided inside the information terminal 2950 and the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.

  FIG. 32F illustrates an example of a wristwatch type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. Further, an antenna, a battery, and the like are provided inside the information terminal 2960 and the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

  The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and release, and power saving mode execution and release. . For example, the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.

  In addition, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. Further, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

  For example, a memory device including the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the above electronic devices for a long period. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

100 Capacitor 110 Conductor 120 Conductor 130 Insulator 150 Insulator 155 Insulator 200 Transistor 203 Conductor 203a Conductor 203b Conductor 205 Conductor 205a Conductor 205b Conductor 208 Substrate 209 Insulator 210 Insulator 210a Insulator 210b Insulator 212 insulator 214 insulator 216 insulator 218 conductor 220 insulator 222 insulator 224 insulator 230 oxide 230a oxide 230b oxide 230c oxide 231 region 231a region 231b region 232 region 232a region 232b region 233 region 233a Region 233b region 234 region 239 region 250 insulator 251 insulator 251a insulator 251A insulator 251b insulator 252 conductor 252a conductor 252A conductor 252b conductor 252B conductor 25 Conductor 256 Conductor 256A Conductor 256B Conductor 260 Conductor 260a Conductor 260b Conductor 260c Conductor 270 Insulator 272 Insulator 272A Insulator 274 Insulator 280 Insulator 282 Insulator 284 Insulator 300 Transistor 311 Substrate 313 Semiconductor Region 314a low resistance region 314b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 324 insulator 326 insulator 328 conductor 330 conductor 350 insulator 352 insulator 354 insulator 356 conductor 360 insulator 362 insulator Body 364 insulator 366 conductor 370 insulator 372 insulator 374 insulator 376 conductor 380 insulator 382 insulator 384 insulator 386 conductor 390 insulator 396 conductor 400 transistor 403 conductor 403a conductor 403b conductor Body 405 conductor 410 conductor 424 insulator 424a insulator 424b insulator 426a region 430 oxide 430a1 oxide 430a2 oxide 430b1 oxide 430b2 oxide 430c oxide 450 insulator 451a insulator 451b insulator 454a conductor 454b conductor Body 460 Conductor 460a Conductor 460b Conductor 470 Insulator 472 Insulator 711 Board 712 Circuit area 713 Separation area 714 Separation line 715 Chip 750 Electronic component 752 Printed board 754 Mounting board 755 Lead 1400 DOSRAM
1405 controller 1410 row circuit 1411 decoder 1412 word line driver circuit 1413 column selector 1414 sense amplifier driver circuit 1415 column circuit 1416 global sense amplifier array 1417 input / output circuit 1420 MC-SA array 1420 sense amplifier array 1422 memory cell array 1423 sense amplifier array 1425 local Memory cell array 1426 Local sense amplifier array 1444 Switch array 1445 Memory cell 1446 Sense amplifier 1447 Global sense amplifier 2910 Information terminal 2911 Case 2912 Display portion 2913 Camera 2914 Speaker portion 2915 External connection portion 2917 Microphone 2920 Notebook personal computer 2921 Case Body 2922 Display unit 29 3 Keyboard 2924 Pointing device 2940 Video camera 2941 Housing 2942 Housing 2943 Display unit 2944 Operation switch 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Housing 2952 Display unit 2960 Information terminal 2961 Housing 2962 Display unit 2963 Band 2964 Buckle 2965 Operation switch 2966 I / O terminal 2967 Icon 2980 Car 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3006 Wiring 3110 OS-FPGA
3111 Controller 3112 Word driver 3113 Data driver 3115 Programmable area 3117 IOB
3119 Core 3120 LAB
3121 PLE
3123 LUT block 3123 block 3124 register block 3125 selector 3126 CM
3127 Power Switch 3128 CM
3130 SAB
3131 SB
3133 PRS
3135 CM
3137 Memory circuit 3137B Memory circuit 3140 OS-FF
3141 FF
3142 Shadow register 3143 Memory circuit 3143B Memory circuit 3188 Inverter circuit 3189 Inverter circuit 5400 Semiconductor device 5401 CPU core 5402 Power controller 5403 Power switch 5404 Cache 5405 Bus interface 5406 Debug interface 5407 Controller 5408 PC
5409 Pipeline register 5410 Pipeline register 5411 ALU
5412 Register file 5421 Power management unit 5422 Peripheral circuit 5423 Data bus 5500 Semiconductor device 5501 Memory circuit 5502 Memory circuit 5503 Memory circuit 5504 Circuit 5509 Transistor 5510 Transistor 5512 Transistor 5513 Transistor 5515 Transistor 5517 Transistor 5518 Transistor 5519 Capacitance element 5520 Capacitance element 5540 Wiring 5541 Wiring 5542 Wiring 5543 Wiring 5544 Wiring

Claims (10)

Forming an opening exposing a portion of the transistor in the first insulator covering the transistor;
Forming a first conductor in the opening;
Forming a second conductor covering at least the first conductor;
A second insulator is formed on the first insulator and the second conductor, and then the second insulator is processed to form the first insulator and the second conductor. Forming an exposed recess,
A method for manufacturing a semiconductor device, wherein a third conductor connected to the second conductor is formed in the recess. In claim 1,
A fourth conductor is formed over the opening and the first insulator, and then the first conductor is formed by polishing the fourth conductor. Manufacturing method. In claim 1 or claim 2,
After the opening is formed, a third insulator is formed so as to contact the side surface of the opening, the bottom of the opening, and the first insulator;
By removing the bottom of the opening and the third insulator provided on the first insulator by anisotropic etching, a fourth insulator in contact with the side surface of the opening is formed. ,
A method for manufacturing a semiconductor device, wherein the first conductor is formed in the opening. 4. The method for manufacturing a semiconductor device according to claim 1, wherein a side surface and a lower surface of the first conductor are surrounded by the first conductive film. 5. The method for manufacturing a semiconductor device according to claim 1, wherein a side surface and a lower surface of the third conductor are surrounded by a second conductive film. 6. The method for manufacturing a semiconductor device according to claim 5, wherein a third conductive film is formed between the third conductor and the second conductive film. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the first conductive film includes at least one of titanium, tantalum, ruthenium, and cobalt. 7. The method according to claim 6, wherein the second conductive film includes at least one of titanium, tantalum, ruthenium, and cobalt, and the third conductive film includes at least one of titanium, tantalum, ruthenium, and cobalt. A method for manufacturing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductor includes tungsten, and the third conductor includes copper. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the second conductor includes tantalum.

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