JP2018084545A - Simulated target generator and simulated target generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a concrete method for accurately simulating a Doppler effect by compressing/expanding in a time axis direction, and a simulated target generator used for that purpose. SOLUTION: Using a relative velocity parameter between a radar device and a target that changes according to a simulation scenario, sampling compression/expansion of a first sampling period for writing input signal data to a memory device is performed, and input from the memory device is performed. The second sampling period for reading the signal data is used. [Selection diagram] Fig. 3A

Description

  The present invention relates to a simulation target generation device and a simulation target generation method, and can be suitably used for, for example, a simulation target generation method for radar mounted on a flying object and a simulation target generation device used therefor.

  Flying objects with radar are known. Some radars can use the Doppler effect to measure the distance and relative speed between targets. In order to simulate the overall operation of a flying object equipped with such a radar, it is desirable to use a simulated target in order to operate the radar alone.

  In relation to the above, Patent Document 1 (Japanese Patent No. 2666737) discloses an invention relating to a radar / target wave simulator. The radar / target wave simulation apparatus includes a reception antenna unit, an orthogonal demodulation unit, a signal processing unit, and a transmission antenna unit. Here, the receiving antenna unit receives a radar wave transmitted from the test radar. The orthogonal demodulator demodulates the orthogonal video signal from the radar wave reception signal obtained by the receiving antenna unit. The signal processing unit delays the orthogonal video signal demodulated by the orthogonal demodulation unit by a time corresponding to the relative distance between the test radar and the pseudo target, and converts the orthogonal video signal between the test radar and the pseudo target. With a Doppler modulation function that modulates at a Doppler frequency corresponding to the relative velocity of the signal, and a power control function that reduces the orthogonal video signal to a power intensity that corresponds to the relative distance between the test radar and the simulated target. The radar target signal is simulated and generated by executing it selectively. The transmission antenna unit transmits the radar target signal generated by the signal processing unit to the test radar as a radar target wave.

  Further, Patent Document 2 (Japanese Patent No. 3242587) discloses an invention relating to a radar simulation signal generator. The radar simulation signal generator includes receiving means, first waveform memory means, first signal processing means, and first transmitting means. Here, the receiving means receives a radar pulse signal. The first waveform memory means records the radar pulse signal received by the receiving means. The first signal processing means performs signal processing of the radar pulse signal recorded in the first waveform memory means. The first transmission means transmits the radar pulse signal after the signal processing recorded in the waveform memory means. The first signal processing means includes compression means for compressing the radar pulse signal recorded in the first waveform memory means in the time axis direction and increasing the frequency of the radar pulse signal recorded in the first waveform memory means. .

  Patent Document 2 claims that the Doppler effect can be simulated by performing decimation / repetition so that the radar pulse signal is compressed / expanded in the time axis direction. This technique is referred to as DRFM (Digital Radio). When trying to realize it using a Frequency Memory (digital radio frequency memory), it is very difficult to simulate the Doppler effect because the waveform is distorted by thinning and repetition.

  Patent Document 3 (Japanese Patent No. 4413757) discloses an invention relating to a radar echo generating apparatus that receives a radar wave from a radar and returns it with a delay. The radar echo generation apparatus includes a branching unit, a first oscillator, a second oscillator, a first memory unit, a second memory unit, and a reproducing unit. Here, the branching means branches the RF input of the received radar wave into a first signal and a second signal. The first oscillator generates an oscillating wave having a frequency lower than the radar wave band. The second oscillator generates an oscillating wave having a higher frequency than the radar wave band. The first memory means stores a signal obtained by down-converting the first signal with the oscillation wave of the first oscillator, gives a delay, and outputs it. The second memory means stores a signal obtained by down-converting the second signal with the oscillation wave of the second oscillator, gives the same amount of delay as the delay given by the first memory means, and outputs it. The reproducing means up-converts the outputs of the first and second memory means using the oscillation waves used for the respective down-conversion, synthesizes them in the same phase, and outputs them.

  Patent Document 3 discloses a measure for performing a sampling rate in the frequency domain using an FFT (Fast Fourier Transform) circuit and an inverse FFT circuit in order to solve the problem of Patent Document 2. Certainly, by performing conversion from the time domain to the frequency domain, it is possible to realize a simulated Doppler effect without performing compression and expansion in the time axis direction. However, as long as the FFT process and the inverse FFT process are performed, it is necessary to perform the data processing for each block for every predetermined time length, so that a problem of time delay inevitably occurs.

  In order to avoid these problems, there is a method in which the frequency of the radar signal is increased or decreased by a mixer by the amount corresponding to the Doppler shift frequency. However, in this case, it is necessary to have the frequency information of the radar signal supplied from the outside. That is, since it is necessary to calculate the Doppler shift frequency, the Doppler effect cannot be performed without preliminary information on the frequency of the radar signal.

Japanese Patent No. 2666737 Japanese Patent No. 3224287 Patent No. 4413757

  Provided are a specific method for accurately realizing the Doppler effect by compressing and expanding in the time axis direction, and a simulated target generator used for that purpose. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The means for solving the problem will be described below using the numbers used in the (DETAILED DESCRIPTION). These numbers are added to clarify the correspondence between the description of (Claims) and (Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  The simulation target generator (1A, 1B) according to an embodiment includes a memory device (12), a receiving device (11), a writing device (115), a reading device (132), and a transmitting device (13). It has. Here, the receiving device (11) samples input radio signals received from the outside (100, 200) every first sampling period to generate input signal data. The writing device (115) writes the input signal data to the write address (P1) of the memory device (12) at a timing according to the first sampling period. The read device (132) receives input signal data stored in the read address (P2) before the write address (P1) of the memory device (12) from the outside during the first sampling period, or The data is read at every second sampling period sampled and compressed with the relative speed parameter calculated by the control device (10A, 10B) of this device. The transmission device (13) transmits the read input signal data as an output radio signal (W2).

  In the simulation target generation method according to the embodiment, the receiving device (11) receives an input radio signal from the outside (100, 200), and the receiving device (11) receives the input radio signal in a first sampling period (ΔT1). ) To generate input signal data, and the writing device (115) writes the input signal data to the write address (P1) of the memory device (12) at a timing corresponding to the first sampling period. (S103, S203) and the reading device (132) inputs the input signal data stored in the read address (P2) before the write address (P1) from the outside in the first sampling period, or Second sampling period sampled and compressed with the relative speed parameter calculated by the controller (10A, 10B) And that (S106, S206) for reading out the bets, the transmission device (13) comprises and transmitting the read input signal data as an output a radio signal (W2).

  According to the one embodiment, the relative velocity parameter between the Doppler radar device and the target, which changes according to the simulation scenario, the first sampling period for writing the input signal data to the memory device, and the input signal data from the memory device. Sampling compression / expansion can be realized by using the difference from the second sampling period for reading out.

FIG. 1 is a diagram for explaining the principle of radar. FIG. 2A is a block circuit diagram illustrating a configuration example in which radar evaluation is performed using the simulated target generator according to the first embodiment. FIG. 2B is a block circuit diagram showing another configuration example in which radar evaluation is performed using the simulated target generator according to the first embodiment. FIG. 3A is a block circuit diagram illustrating a configuration example of the simulated target generator according to the first embodiment. FIG. 3B is a diagram illustrating a configuration example of the memory device according to the first embodiment. FIG. 3C is a diagram illustrating a configuration example of the control device according to the first embodiment. FIG. 3D is a block circuit diagram illustrating a configuration example of a computer according to the first embodiment. FIG. 4 is a flowchart illustrating an example of a radar evaluation method according to the first embodiment. FIG. 5A is a block circuit diagram showing a configuration example of the simulated target generator according to the second embodiment. FIG. 5B is a diagram illustrating a configuration example of the memory device according to the second embodiment. FIG. 5C is a diagram illustrating a configuration example of a control device according to the second embodiment. FIG. 6 is a flowchart illustrating an example of a radar evaluation method according to the second embodiment.

  Referring to the accompanying drawings, a simulation target generation apparatus according to the present invention and a simulation target generation method using the simulation target generation apparatus are implemented, and a radar is evaluated using the simulation target generation apparatus and the simulation target generation method The form for implementing this will be described below.

  First, the principle of radar will be described. FIG. 1 is a diagram for explaining the principle of radar.

  In the diagram of FIG. 1, a radar device 100 and a target 150 are shown. The configuration of the radar apparatus 100 will be described. The radar device 100 includes a control device 110, a transmission device 120, an antenna 130, and a reception device 140. The control device 110 is electrically connected to the transmission device 120 and the reception device 140. The antenna 130 is electrically connected to the transmission device 120 and the reception device 140.

  In the example of FIG. 1, the radar apparatus 100 includes only one antenna 130, but may further include another antenna. In other words, in the example of FIG. 1, the transmission device 120 and the reception device 140 are connected to the same antenna 130. For example, the antenna 130 is connected only to the transmission device 120 and another antenna is connected to the reception device 140. May be. Here, the description will be continued assuming that the radar apparatus 100 includes only one antenna 130.

  The operation of the radar apparatus 100 will be described. The control device 110 controls the operations of the transmission device 120 and the reception device 140. The transmission device 120 is controlled by the control device 110 to generate a transmission signal, and transmits the radar wave W1 to the outside via the antenna 130. The radar wave W1 reaches the surface of the target 150 and is reflected. The reflected radar wave W1 is called a reflected wave W2. Here, when the target 150 moves so that the distance D to the radar apparatus 100 changes, the Doppler effect occurs. That is, the frequency of the reflected wave W2 is different from the frequency of the radar wave W1. When the reflected wave W2 reaches the antenna 130, the reception device 140 generates a reception signal corresponding to the reflected wave W2 and transmits it to the control device 110. The control device 110 can calculate the distance D from the antenna 130 to the target 150 and the relative velocity V between the antenna 130 and the target 150 based on the received signal.

(First embodiment)
FIG. 2A is a block circuit diagram illustrating a configuration example in which radar evaluation is performed using the simulated target generator 1A according to the first embodiment. FIG. 2A shows a radar device 100 and a simulated target generator 1A according to the present embodiment. In other words, FIG. 2A is a diagram in which the target 150 in FIG. 1 is replaced with the simulated target generator 1A according to the present embodiment.

  The components of the simulated target generator 1A according to this embodiment shown in FIG. 2A will be described. The simulated target generator 1A includes a reception antenna 111, a reception device 11, a memory device 12, a control device 10A, a transmission device 13, and a transmission antenna 131.

  The connection relationship of the components of the simulated target generator 1A according to this embodiment shown in FIG. 2A will be described. The control device 10A is electrically connected to each of the reception device 11, the memory device 12, and the transmission device 13. The receiving antenna 111 is electrically connected to the receiving device 11. The transmission antenna 131 is electrically connected to the transmission device 13. The memory device 12 is electrically connected to the subsequent stage of the receiving device 11. The memory device 12 is electrically connected to the front stage of the transmission device 13.

  The operation of the simulated target generator 1A according to this embodiment shown in FIG. 2A will be described. First, the receiving device 11 receives the radar wave W <b> 1 transmitted from the radar device 100 via the receiving antenna 111. The receiving device 11 generates input signal data representing the received radar wave W1. The memory device 12 stores the generated input signal data. The transmission device 13 reads the input signal data from the memory device 12 to generate a simulated reflected wave W3, and transmits it to the radar device 100 via the transmission antenna 131. When the control device 10A appropriately controls the above-described operations of the reception device 11, the memory device 12, and the transmission device 13, the simulated target generation device 1A is equivalent to the reflected wave W2 reflected from the surface of the target 150 in FIG. A simulated reflected wave W3 having characteristics is transmitted toward the radar apparatus 100. That is, by appropriately adjusting the delay time from when the receiving device 11 receives the radar wave W1 to when the transmitting device 13 transmits the simulated reflected wave W3, the radar device 100 simulates the simulated target generator 1A. 1 can be calculated as the same value as the distance D to the target 150 in FIG. Further, by appropriately adjusting the frequency of the simulated reflected wave W3, the radar apparatus 100 can change the simulated relative speed between the simulated target generator 1A and the relative speed V between the target 150 and the target 150 in FIG. It can be calculated as the same value.

  FIG. 2B is a block circuit diagram illustrating another configuration example in which radar evaluation is performed using the simulated target generator 1A according to the first embodiment. The simulation illustrated in FIG. 2A can also be performed using an external transmitter 220 including another antenna 230 instead of the transmission device 120 of the radar device 100, as illustrated in FIG. 2B. In this case, the radar wave W1 is transmitted from the transmitter 220 via the antenna 230, and the simulated reflected wave W3 is received by the receiver 140 via the antenna 130. However, the simulated target generator 1A according to this embodiment is used. Can be used as in FIG. 2A. Here, the description will be continued on the assumption that the simulation is performed with the configuration of FIG. 2A.

  FIG. 3A is a block circuit diagram showing a configuration example of the simulated target generator 1A according to the first embodiment. The components of the simulated target generator 1A shown in FIG. 3A will be described. The simulated target generator 1A includes a control device 10A, a receiving device 11, a receiving antenna 111, a memory device 12, a transmitting device 13, and a transmitting antenna 131. The receiving device 11 includes a receiving circuit 112, a sampling frequency oscillator 113, an analog / digital (A / D) converter 114, and a writing device 115. The transmission device 13 includes a reading device 132, a Doppler shift frequency oscillator 133, a sampling frequency oscillator 134, a mixer 135, a digital / analog (D / A) converter 136, and a transmission circuit 137.

  The connection relationship of the components of the simulated target generator 1A of FIG. 3A will be described. The receiving antenna 111 is connected to the receiving circuit 112. The receiving circuit 112 is connected to the receiving antenna 111 and the A / D converter 114. The sampling frequency oscillator 113 is connected to the A / D converter 114. The A / D converter 114 is connected to the receiving circuit 112, the sampling frequency oscillator 113, and the writing device 115. The writing device 115 is connected to the control device 10 </ b> A, the A / D converter 114, and the memory device 12. The memory device 12 is connected to the control device 10A, the writing device 115, and the reading device 132. The control device 10A is connected to the writing device 115, the memory device 12, the reading device 132, and the Doppler shift frequency oscillator 133. The reading device 132 is connected to the control device 10 </ b> A, the memory device 12, and the D / A converter 136. The Doppler shift frequency oscillator 133 is connected to the control device 10 </ b> A and the mixer 135. The sampling frequency oscillator 134 is connected to the mixer 135. The mixer 135 is connected to the Doppler shift frequency oscillator 133, the sampling frequency oscillator 134, and the D / A converter 136. The D / A converter 136 is connected to the reading device 132, the mixer 135, and the transmission circuit 137. The transmission circuit 137 is connected to the D / A converter 136 and the transmission antenna 131. The transmission antenna 131 is connected to the transmission circuit 137.

  FIG. 3B is a diagram illustrating a configuration example of the memory device 12 according to the first embodiment. The memory device 12 is divided into a total of M storage areas from the first address to the Mth address and managed.

  FIG. 3C is a diagram illustrating a configuration example of the control device according to the first embodiment. The control device 10 </ b> A includes a write address calculation unit 101 and a read address calculation unit 102.

  Part or all of the simulated target generator 1A according to the present embodiment may be configured as a computer. FIG. 3D is a block circuit diagram illustrating a configuration example of the computer 300 according to the first embodiment. 3D includes a bus 301, an interface 302, an arithmetic device 303, a storage device 304, and an external storage device 305. The interface 302, the arithmetic device 303, the storage device 304, and the external storage device 305 are connected to each other via a bus 301 so that they can communicate with each other. The storage device 304 stores various programs and data. The arithmetic device 303 executes various programs stored in the storage device 304 and reads data from the storage device 304 or writes data to the storage device 304. The interface 302 outputs the result of the calculation by the calculation device 303 to the outside, and inputs data from the outside. The external storage device 305 reads a program or data from an external storage medium 306 or writes a program or data.

  The operation of the components of the simulated target generator 1A shown in FIGS. 3A to 3D will be described. The control device 10A controls operations of the reception device 11, the memory device 12, and the transmission device 13 in accordance with a simulation scenario used for radar evaluation. This simulation scenario defines a change with time of a distance parameter that simulates the distance D between the target 150 played by the simulated target generator 1A and the radar apparatus 100. Similarly, the simulation scenario also defines a change with time of a relative speed parameter that simulates the relative speed V between the target 150 and the radar apparatus 100. The simulation scenario may be programmed in advance before starting the simulation, or may be changed or added during the execution of the simulation.

  The reception circuit 112 receives an input radio signal such as a radar wave W1 via the reception antenna 111, and generates an input signal as an analog signal corresponding to the input radio signal. The sampling frequency oscillator 113 generates a first sampling signal having a predetermined first sampling frequency. The A / D converter 114 A / D-converts the input signal as an analog signal input from the receiving circuit 112 at the first sampling frequency of the first sampling signal input from the sampling frequency oscillator 113, and the input signal as a digital signal Is generated. In other words, the A / D converter 114 performs A / D conversion on an input signal as an analog signal every time a first sampling period that is the reciprocal of the first sampling frequency elapses, and generates an input signal as a digital signal. . The writing device 115 is controlled by the control device 10A, generates input signal data representing an input signal as a digital signal, and writes the input signal data to a predetermined write address of the memory device 12. This write operation is performed at a timing corresponding to the first sampling period. Note that this writing operation may be performed every first sampling period, or two or more writings of the first sampling period may be performed collectively. Here, the write address is calculated by the write address calculation unit 101, and is automatically incremented every time the first sampling period elapses, for example.

  Control device 10A calculates a Doppler shift frequency between radar wave W1 and reflected wave W2 in accordance with the simulation scenario. The Doppler shift frequency calculated here is generated when the target 150 is located at a distance D from the radar device 100 and moves at a relative speed V with respect to the radar device 100. In other words, the Doppler shift frequency can be uniquely calculated from the first sampling frequency and the distance parameter and the relative speed parameter that change along the simulation scenario. The control device 10 </ b> A generates a control signal representing the calculated Doppler shift frequency and transmits it to the Doppler shift frequency oscillator 133.

The Doppler shift frequency oscillator 133 receives the control signal. The Doppler shift frequency oscillator 133 generates a Doppler shift frequency signal having a Doppler shift frequency represented by the received control signal and transmits it to the mixer. The sampling frequency oscillator 134 generates a first sampling signal having the same first sampling frequency as the sampling frequency oscillator 134 and transmits the first sampling signal to the mixer 135. The mixer 135 multiplies the first sampling signal and the Doppler shift signal to generate a second sampling signal having a second sampling frequency. The reciprocal of the second sampling frequency thus obtained is referred to as a second sampling period. The second sampling period is calculated from the following formula.
ΔT2 = (ΔT1-2 × V (C / F1))
Here, ΔT2 is the second sampling period, ΔT1 is the first sampling period, V is the relative speed, C is the speed of light, and F1 is the first sampling frequency.

  The D / A converter 136 receives the second sampling signal, and reads the input signal data stored in the memory device 12 as a digital signal via the reading device 132 each time the second sampling period elapses. Convert to analog signal. In other words, the reading device 132 reads input signal data from the memory device 12 in accordance with a request from the D / A converter 136, generates a digital signal represented by the read input signal data, and transmits the digital signal to the D / A converter 136. Thereafter, the D / A converter 136 converts the received digital signal into an output signal as an analog signal, and transmits it to the transmission circuit 137.

  The control device 10A calculates the address of the memory device 12 in which the input signal data read here is stored. This address is called a read address. The read address is calculated by the read address calculator 102. For example, every time the read device 132 reads input signal data from the memory device 12, that is, every time the second sampling period elapses, the read address calculator 102 reads the read address. Increment the address.

  The transmission circuit 137 generates a radio output signal representing the output signal and transmits the radio output signal to the radar apparatus 100 via the transmission antenna 131.

  The overall operation of the simulated target generator 1A according to the present embodiment, that is, the radar evaluation method according to the present embodiment will be described. FIG. 4 is a flowchart illustrating an example of a radar evaluation method according to the first embodiment. The flowchart of FIG. 4 includes a total of 8 steps from the 0th step S100 to the 7th step S107. The flowchart of FIG. 4 starts from the 0th step S100. After the 0th step S100, the first step S101 is executed.

  In the first step S101, the simulated target generator 1A is initialized. Specifically, a simulation scenario programmed in the control device 10A starts, and the initial conditions are reflected in each component of the simulated target generator 1A.

First, the control device 10A determines the total memory amount of the memory device 12. Here, as shown in FIG. 3B, the unit memory capacity obtained by dividing the memory device 12 into a total of M areas is equal to or larger than the data size of the input signal data stored in one sampling. Is also big. The memory capacity of the memory device 12 is equal to or larger than M times the unit memory capacity. The value of M is equal to or greater than the quotient of the maximum delay time that can be taken in the simulation scenario divided by the first sampling period. This delay time is the time from when the radar device 100 transmits the radar wave W1 until the simulated reflected wave W3 is received, and after the simulated target generator 1A receives the input radio signal, the output radio signal is received. It is also the time to send. The memory device 12 for which the total amount of memory has been determined preferably initializes, that is, erases the data stored in the area.

Next, as shown in FIG. 3B, the control device 10A sets the initial value of the write address P1 and the initial value of the read address P2 in the memory device 12. In the example of FIG. 3B, the read address P2 is set to an address before the write address P1. Here, the interval from the read address P2 to the write address P1 is called an address distance. The address distance is proportional to the delay time. Therefore, the initial value of the address distance is calculated by the following formula according to the initial condition of the delay time.
ΔP = Tout1 / ΔT1
Here, ΔP is the address distance, Tout1 is the initial value of the delay time, and ΔT1 is the first sampling period.

  Following the first step S101, a second step S102 is executed.

  In the second step S102, the control device 10A determines whether or not the first sampling period has elapsed. If the first sampling period has elapsed (YES), the third step S103 is then executed. If the first sampling period has not elapsed (NO), the fifth step S105 is executed next.

  In the third step S <b> 103, the writing device 115 is controlled by the control device 10 </ b> A to write input signal data into the memory device 12. Following the third step S103, a fourth step S104 is executed.

  In the fourth step S104, the write address calculation unit 101 increments the write address. Here, when the incremented write address exceeds the maximum address M of the memory device 12, the maximum address M is subtracted from the write address. In other words, the storage area of the memory device 12 is used cyclically. Following the fourth step S104, a second step S102 is executed.

  In the fifth step S105, the control device 10A determines whether or not the second sampling period has elapsed. If the second sampling period has elapsed (YES), the sixth step S106 is then executed. If the second sampling period has not elapsed (NO), then the second step S102 is executed.

  In the sixth step S <b> 106, the reading device 132 is controlled by the control device 10 </ b> A to read input signal data from the memory device 12. After the sixth step S106, a seventh step S107 is executed.

  In the seventh step S107, the read address calculation unit 102 increments the read address. Here, when the incremented write address exceeds the maximum address M, the maximum address M is subtracted from the read address. Following the seventh step S107, a second step S102 is executed.

  By executing the steps of the flowchart of FIG. 4 as described above, the simulated target generator 1A according to the present embodiment and the radar evaluation method using the same enable sampling compression / decompression. Specifically, when the target 150 approaches the radar apparatus 100 in the simulation scenario, that is, the distance D or the value of the distance parameter decreases, the address distance decreases. On the other hand, moving the target 150 away from the radar device 100 in the simulation scenario, that is, increasing the value of the distance D or the distance parameter corresponds to an increase in the address distance. In addition, a decrease in the relative speed or the relative speed parameter between the target 150 and the radar apparatus 100 in the simulation scenario corresponds to a decrease in the second sampling period, that is, the first sampling period is sampled and compressed with the relative speed parameter. This corresponds to the second sampling period. Conversely, increasing the relative speed or relative speed parameter between the target 150 and the radar device 100 in the simulation scenario corresponds to increasing the second sampling period, that is, sampling the first sampling period with the relative speed parameter. This corresponds to extending to the second sampling period.

(Second Embodiment)
In the first embodiment described above, the write operation and the read operation are individually performed on the same memory device 12. Therefore, the possibility that the writing device 115 and the reading device 132 access the memory device 12 at the same timing cannot be denied. The problem that a malfunction may occur due to a memory access collision is solved by the simulated target generator 1B according to the second embodiment and a radar evaluation method using the same.

  FIG. 5A is a block circuit diagram showing a configuration example of the simulated target generator 1B according to the second embodiment. The simulated target generator 1B according to the second embodiment differs from the simulated target generator 1A according to the first embodiment in the following points. First, as the memory device 12, a main memory device 12A, a first sub memory device 12B, and a second sub memory device 12C are used. FIG. 5B is a diagram illustrating a configuration example of the memory device 12 according to the second embodiment. The main memory device 12A according to the present embodiment is the memory device 12 according to the first embodiment. The capacity of each of the first sub memory device 12B and the second sub memory device 12C may be smaller than the capacity of the main memory device 12A. Further, the first sub-memory capacity and the second sub-memory device 12C may have the same capacity or different capacities.

  Next, the control device 10A according to the first embodiment is replaced with the control device 10B according to the second embodiment. The control device 10B according to the present embodiment further includes a sub memory switching unit 103 in addition to the write address calculation unit 101 and the read address calculation unit 102 of the first embodiment. FIG. 5C is a diagram illustrating a configuration example of the control device 10B according to the second embodiment.

  Other configurations of the simulated target generator 1B according to the present embodiment are the same as those in the first embodiment, and thus further detailed description thereof is omitted.

  In this embodiment, in order to avoid a memory access conflict, the main memory device 12A is used for the input signal data write operation, and the first sub memory device 12B and the second sub memory device are used for the input signal data read operation. 12C is used. Here, the contents of the main memory device 12A in which the input signal data is written are partially copied to each of the first sub memory device 12B and the second sub memory device 12C. In the example shown in FIG. 5B, the contents stored in the main memory device 12A from the A1 address to the A2 address are copied to the first sub memory device 12B. In the main memory device 12A, the contents stored from the A2 address to the A3 address are copied to the second sub memory device 12C.

  Here, in order to avoid a memory access conflict in the main memory device 12A, the first sub memory device 12B, and the second sub memory device 12C, the following conditions are preferably satisfied. That is, the A1 address is an address equal to the read address P2 or an address before the read address P2. The A2 address is an address after the read address P2 and an address before the write address P1. The A3 address is an address after the A2 address and is an address before the write address P1. However, in the context of these addresses, it is necessary to consider that the address of the main memory device 12A is used cyclically. As will be described in detail later, when the read address P2 is incremented and exceeds the A2 address, bank switching occurs. That is, the roles of the first sub memory device 12B and the second sub memory device 12C are interchanged.

  The overall operation of the simulated target generator 1B according to the second embodiment, that is, the radar evaluation method according to the second embodiment will be described. FIG. 6 is a flowchart illustrating an example of a radar evaluation method according to the second embodiment. The flowchart of FIG. 6 includes a total of 10 steps from the 0th step S200 to the 9th step S209. The flowchart of FIG. 6 starts from the 0th step S200. After the 0th step S200, the first step S201 is executed.

  In the first step S201, the simulated target generator 1B is initialized. This initialization is obtained by adding the following operation to the initialization in the first step S101 according to the first embodiment. That is, the initial values of the first address A1, the second address A2, and the third address A3 are determined so as to satisfy the above-described conditions for the write address P1 and the read address P2, and the first sub memory device 12B and the second sub memory device 12C It is preferable to initialize, ie erase, the stored data. Following the first step S201, a second step S202 is executed.

  In the flowchart of FIG. 6, the second step S202 to the seventh step S207 are the same as the second step S102 to the seventh step S107 of the first embodiment, respectively, and further detailed description is omitted. However, the eighth step S208 is executed after the seventh step S207.

  In the eighth step S208, the control device 10B determines whether or not the read address P2 incremented in the seventh step S207 exceeds the maximum address of the first sub memory device 12B or the second sub memory device 12C. In other words, it is determined whether the data stored in the first sub memory device 12B or the second sub memory device 12C has been read to the end. The read address P2 exceeds the maximum address of the first sub memory device 12B or the second sub memory device 12C, that is, the data stored in the first sub memory device 12B or the second sub memory device 12C is read to the end. If yes (YES), the ninth step S209 is then executed. On the other hand, the read address P2 does not exceed the maximum address of the first sub memory device 12B or the second sub memory device 12C, that is, the data stored in the first sub memory device 12B or the second sub memory device 12C. If it has not been read to the end (NO), the second step S202 is then executed.

  In the ninth step S209, the sub memory switching unit 103 switches the sub memory. That is, when the first sub memory device 12B has been read to the end, the next read address P2 to be read is set to the A2 address which is the minimum address of the second sub memory device 12C. Also, the input signal data stored in the storage area of the later address starting from the A3 address which is the maximum address of the second sub memory device 12C in the main memory device 12A is copied to the first sub memory device 12B. To do. On the contrary, when the second sub memory device 12C is read to the end, similarly, the operation in which the first sub memory device 12B and the second sub memory device 12C in the above description are replaced is performed. Following the ninth step S209, a second step S202 is executed.

  By executing the steps of the flowchart of FIG. 6 as described above, the simulated target generator 1B according to the present embodiment and the radar evaluation method using the same are obtained in the case of the first embodiment. In addition, memory access conflicts can be avoided. This leads to suppression of radar evaluation errors that may be caused by jitter caused by memory access collisions, that is, to increase simulation accuracy.

(Third embodiment)
The third embodiment is obtained by adding the following changes to the second embodiment described above. That is, in the second embodiment, the input signal data is written to the main memory 12A, the input signal data written to the main memory device 12A is alternately copied to the first sub memory device 12B and the second sub memory device 12C, and the first The input signal data copied to the sub memory device 12B and the second sub memory device 12C was read. On the contrary, in the third embodiment, input signal data is alternately written in the first sub memory device 12B and the second sub memory device 12C, and the input signal data written in the first sub memory device 12B and the second sub memory device 12C. Is copied to the main memory device 12C, and the input signal data copied to the main memory device 12C is read. Needless to say, in the case of the third embodiment, similarly to the case of the second embodiment, it is possible to solve a problem that may cause a problem due to a memory access conflict.

  Other configurations and operations of the third embodiment are the same as those of the second embodiment, and thus further detailed description is omitted.

  The invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. In addition, the features described in the embodiments can be freely combined within a technically consistent range.

DESCRIPTION OF SYMBOLS 1A Simulation target generator 1B Simulation target generator 10A Control apparatus 10B Control apparatus 101 Write address calculation part 102 Read address calculation part 103 Sub memory switching part 11 Receiving apparatus 111 Reception antenna 112 Reception circuit 114 Analog / digital (A / D) converter 115 Writing Device 12 Memory Device 12A Main Memory Device 12B First Sub Memory Device 12C Second Sub Memory Device 13 Transmitting Device 131 Transmitting Antenna 132 Reading Device 133 Doppler Shift Frequency Oscillator 134 Sampling Frequency Oscillator 135 Mixer 136 Digital / Analog (D / A ) Converter 137 Transmitter circuit 100 Radar device 110 Controller 120 Transmitter 130 Antenna 140 Receiver 150 Target 220 Transmitter 230 Container 300 Computer 301 bus 302 interface 303 computing device 304 memory device 305 external storage device 306 storage medium D distance P1 write address P2 read address V relative speed W1 radar W2 reflected wave W3 simulated reflected wave

Claims (8)

A simulation target generator,
A memory device;
A receiving device that samples input radio signals received from the outside for each first sampling period and generates input signal data;
A writing device that writes the input signal data to a write address of the memory device at a timing according to the first sampling period;
Input signal data stored at a read address before the write address of the memory device is sampled with a relative speed parameter input from the outside during the first sampling period or calculated by the control device of the device A readout device that reads out each compressed and decompressed second sampling period;
A simulation target generation device comprising: a transmission device that transmits the read input signal data as an output radio signal. The simulated target generator according to claim 1,
Further comprising the control device;
The controller is
A write address calculation unit that increments the write address each time the first sampling period elapses and subtracts the maximum address from the write address when the write address is greater than the maximum address of the memory device;
A read address calculation unit that increments the read address every time the second sampling period elapses and subtracts the maximum address from the read address when the read address is larger than the maximum address of the memory device; Simulated target generator. The simulated target generator according to claim 2,
The memory device includes:
A main memory device for writing the input signal data;
A first sub-memory device that copies a portion of the input signal data written to the main memory device and reads the copied portion of the input signal data;
A second sub memory device for copying another part of the input signal data written to the main memory device and reading the copied part of the other input signal data;
The controller is
A simulated target generating apparatus, further comprising: a sub memory switching unit that switches a target for reading the input signal data between the first sub memory device and the second sub memory device. The simulated target generator according to claim 2,
The memory device includes:
A first sub memory device for writing the input signal data;
A second sub memory device for writing another input signal data;
A main memory device for copying the input signal data written in the first sub memory device and the second sub memory device and reading the copied input signal data;
The controller is
A simulated target generating apparatus, further comprising: a sub memory switching unit that switches a target to which the input signal data is written between the first sub memory device and the second sub memory device. A simulation target generation method,
The receiving device receives an input radio signal from the outside;
The receiving device samples the input radio signal every first sampling period to generate input signal data;
A writing device writes the input signal data to a write address of a memory device at a timing according to the first sampling period;
The reading device samples and compresses / decompresses the input signal data stored at the read address before the write address, with the first sampling period input from the outside, or with the relative speed parameter calculated by the control device. Reading every second sampling period;
A simulation target generation method comprising: a transmission device transmitting the read input signal data as an output radio signal. In the simulation target generating method according to claim 5,
The writing is
A write address calculation unit of the control device increments the write address every time the first sampling period elapses;
The write address calculation unit comprises subtracting the maximum address from the write address when the write address is greater than the maximum address of the memory device;
The reading is
The read address calculation unit of the control device increments the read address every time the second sampling period elapses;
The simulation target generation method, wherein the read address calculation unit includes subtracting the maximum address from the read address when the read address is larger than the maximum address of the memory device. In the simulation target generating method according to claim 6,
The writing is
Writing the input signal data to a main memory device of the memory device;
Copying a portion of input signal data written to the main memory device to a first sub-memory device;
Copying another portion of the input signal data written to the main memory device to a second sub-memory device;
The reading is
Reading the partial input signal data copied to the first sub-memory device;
Reading the other part of the input signal data copied to the second sub-memory device,
Incrementing the read address is
A simulation target generation method comprising: switching a target for reading the input signal data between the first sub memory device and the second sub memory device. In the simulation target generating method according to claim 6,
The writing is
Writing the input signal data to a first sub-memory device of the memory device;
Writing the other input signal data to a second sub-memory device of the memory device;
Copying the input signal data written to the first sub-memory device and the second sub-memory device to a main memory device of the memory device;
The reading is
Reading the input signal data copied to the main memory device;
Incrementing the read address is
A simulation target generation method comprising: switching a target for reading the input signal data between the first sub memory device and the second sub memory device.

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