JP2018082609A - DC / DC converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC / DC converter having improved power supply efficiency. A DC / DC converter 1 includes a switching element T11 that performs on / off operation and a drive circuit 3 that controls on / off of the switching element T11. Further, switching is performed between the inductor L1 whose current is controlled by the switching element T11, the smoothing capacitor C1 which is connected to the inductor L1 and performs a rectifying operation together with the inductor L1, and the oscillator 9 which generates the rectangular wave signal CLK that operates the drive circuit 3. The output current detection unit 4 for detecting the output detection current Sense flowing through the element T11 is provided. The oscillator 9 generates a square wave signal CLK at a fixed oscillation frequency when the output detection current Sense is equal to or more than a predetermined value, and is lower than the fixed oscillation frequency when the output detection current Sense is equal to or less than a predetermined value. And, a square wave signal CLK is generated at an oscillation frequency proportional to the output detection current Sense. [Selection diagram] Fig. 1

Description

  The present invention relates to a DC / DC converter that switches between a PWM method and a PFM method according to the weight of a load.

  Conventionally, a battery is mounted as a driving power source in a portable electronic device. Since the output voltage of the battery decreases due to use or discharge of the device, the electronic device is provided with a DC voltage conversion circuit (DC / DC converter) that converts the voltage of the battery into a constant voltage. A portable electronic device uses a synchronous rectification DC / DC converter that is small and has high conversion efficiency. A synchronous rectification DC / DC converter is generally a PWM (Pulse Width Modulation) DC / DC converter, and includes a main switching transistor and a synchronization transistor, and both transistors are alternately turned on and off. That is, the main switching transistor is turned on to supply energy from the input side to the output side, and the main switching transistor is turned off to release the energy accumulated in the choke inductor. At this time, the synchronizing transistor is turned off in synchronization with the timing at which the energy stored in the choke inductor is released to the load side. And the output voltage is kept substantially constant by controlling the pulse width of the pulse signal for driving the main switching transistor according to the output voltage or the output current.

  By the way, in the DC / DC converter, when converting the voltage of the battery, high conversion efficiency is required in a wide load region from a heavy load with a large amount of power supply to a light load with a small amount of power supply. However, when the load is light, the power loss of the DC / DC converter that occurs when driving the main switching transistor is relatively larger than the power consumption at the load, so that the conversion efficiency may be significantly reduced. Generally known.

  Therefore, in order to improve the reduction in conversion efficiency at light load, a DC / DC converter that switches from PWM to PFM (Pulse Frequency Modulation) at light load has been proposed. This DC / DC converter is driven by the PWM method during normal operation including a heavy load, and is driven by the PFM method at a light load. In this PFM method, a true PFM method for controlling the switching frequency of the drive signal supplied to the main switching transistor according to the output voltage of the DC / DC converter, and a constant switching frequency of the drive signal supplied to the main switching transistor are used. There is a pseudo PFM method in which the switching operation is thinned out according to the output voltage of the DC / DC converter. In any PFM method, since the switching frequency at light load is smaller than that at PWM method, the power loss of the DC / DC converter can be reduced, and the decrease in conversion efficiency at light load can be suppressed. .

  Patent Document 1 can be cited as a related art related to the above.

  Conventionally, in order to achieve high efficiency in a DC / DC converter, in addition to PWM control, SLLM [Simple Light Load Mode] control during no load or light load has been introduced. According to the DC / DC converter that employs this SLLM control technology, by applying an offset voltage to the current detection voltage that represents the detection value of the current flowing through the inductor, the difference between the output voltage and the reference voltage can be reduced or light. At the time of load, the comparator confirms that the magnitude of the current detection voltage is greater than the difference between the output voltage and the reference voltage. At this time, since the oscillator signal of the oscillator that turns on the switching element can be invalidated, the switching operation of the switching element can be intermittently controlled until the difference between the output voltage and the reference voltage becomes large. Therefore, since it is not necessary to add a comparator for intermittent control, the efficiency is improved as compared with the DC / DC converter based on PWM control in the current mode at the time of light load or no load. Miniaturization can be achieved.

  Patent Document 2 can be cited as a related art related to the above.

  Conventionally, there has been known one that provides a switching regulator having high efficiency even at a light load. For example, the oscillation frequency of the oscillator is controlled by the output signal of the error amplifier, and the on / off state of the switching element is controlled by using the output signal of the oscillator, so that the oscillation frequency is kept low and switching loss is reduced at light loads. be able to.

  Note that Patent Document 3 can be cited as a related art related to the above.

JP 2012-60883 A International Publication WO2005 / 079910 JP 2012-257408 A

  However, switching between the PWM method and the PFM method in the DC / DC converter of Patent Document 1 causes a problem that the magnitude of the load current varies depending on the input / output setting (difference between the input voltage and the output voltage).

  Further, in the DC / DC converter employing the SLLM control technology of Patent Document 2, it is difficult to maintain the high efficiency of the DC / DC converter at light load or no load, and the smaller the output current value, the more A decrease in efficiency occurs.

  Further, the method disclosed in Patent Document 3 does not directly detect the load current and control the oscillation frequency, but causes a problem that quantitative control cannot be realized because of asynchronous control. As a result, periodic fluctuations may occur, and when entering an audible area, a problem arises in that sound can be heard.

  An object of the present invention is to eliminate the above-mentioned problems, quantitatively detect a load current, determine a light load state by controlling an internal clock, and switch between a PWM method and a PFM method, Provided is a DC / DC converter that can improve the conversion efficiency of a power supply, and a DC / DC converter that is space-saving and does not sound.

  The DC / DC converters (1, 2) according to the present invention are coupled to an input voltage (Vin) and perform on / off operations, switching elements (T11, T21), and on / off control of the switching elements (T11, T21). The drive circuit (3) which performs is provided. Furthermore, the inductors (L1, L2) whose current is controlled by the switching elements (T11, T21) and the smoothing capacitors (C1, C2) connected to the inductors (L1, L2) and performing a rectifying operation together with the inductors (L1, L2). And an output for detecting an output detection current (Isense) flowing through a rectangular wave signal (an oscillator (9) that generates CLK and a switching element (T11, T21) or an inductor (L1, L2)) that operates the drive circuit (3). When the output detection current (Isense) is greater than or equal to a predetermined value, the oscillator (9) generates a rectangular wave signal (CLK) at a fixed oscillation frequency and outputs the output detection current (Isense). ) Is below a predetermined value, the oscillation frequency is lower than the fixed oscillation frequency and proportional to the output detection current (Isense). Fosc) in generating a rectangular wave signal (CLK).

  In the DC / DC converters (1, 2) of the present invention, the oscillator (9) includes a constant current source (CC) that generates a constant constant current (Icc) regardless of the magnitude of the output detection current (Isense). And a linear current source (CL) that generates a linear current (Icl) that responds to the magnitude of the output detection current (Isense).

  In the DC / DC converters (1, 2) of the present invention, the oscillator currents (Iosc1, Iosc2) set by the sum (+) of the constant current (Icc) and the linear current (Icl) or the difference (−) between the two. ) To set the oscillation frequency (Fosc) of the oscillator (9).

  The DC / DC converters (1, 2) of the present invention perform PWM control when the output detection current (Isense) is equal to or greater than a predetermined value, and perform PFM control when the output detection current is equal to or less than the predetermined value. .

  In the DC / DC converter (1, 2) of the present invention, when PFM control is performed, the setting of the oscillation frequency (Fosc) of the oscillator (9) is governed by the linear current (Icl).

  In the DC / DC converters (1, 2) of the present invention, when PFM control is performed, the lower limit value of the oscillation frequency (Fosc) is set to an audible frequency band or higher.

  The DC / DC converter (1, 2) according to the present invention further includes a feedback voltage (Vfb) generated based on a voltage generated in the smoothing capacitors (C1, C2) and a reference set in advance to a predetermined magnitude. An error amplifier (7) is provided that compares the voltage (Vref) with each other and outputs the difference between the two voltages as an error signal (Verr). In addition, a slope circuit (11) that generates a slope signal (Vsl) based on a rectangular wave signal generated by the oscillator (9), and a comparison result signal between the error signal (Verr) and the slope signal (Vsl) are drive circuits. And a PWM comparator (10) for outputting to (3).

  The DC / DC converter (1, 2) of the present invention is a current mode type in which a current component corresponding to the output detection current (Isense) is superimposed on the slope signal (Vsl).

  Further, the DC / DC converter (1, 2) of the present invention supplies the current to the inductor (L1, L2) when the switching element (T11, T21) is turned off, so that the switching element (T11, T21) is supplied. And rectifier elements (T12, D12, T22, D22) coupled to a common node (N1) of the inductors (L1, L2).

  Further, the DC / DC converters (1, 2) of the present invention include a reverse current detection circuit (5) for detecting a reverse current flowing from the ground potential (GND) toward the common node (N1), and reverse current detection. When the circuit (5) detects a predetermined reverse current, the operation of the rectifying element (T12) or the switching element (T21) coupled to the ground potential (GND) is turned off.

  The DC / DC converter of the present invention detects the magnitude of the load current, and when the load current falls below a predetermined magnitude, switches the DC / DC converter switching drive method from PWM control to PFM control, and further loads Since the control is automatically performed so that the oscillation frequency is lowered in proportion to the current, it is possible to suppress a decrease in power efficiency when the load current is small and no load is applied.

1 is a circuit diagram of a current mode synchronous rectification step-down DC / DC converter according to a DC / DC converter of the present invention. The signal waveform figure of the output part of the DC / DC converter of FIG. 1 is shown. The circuit diagram of the DC / DC converter of a current mode synchronous rectification boost type DC / DC converter according to the present invention is shown. It is a figure which shows the relationship between the oscillation frequency Fosc of an oscillator, and load current IL in FIG. 1, FIG. FIGS. 1 and 2 are diagrams illustrating a case where an oscillator current Iosc1 generated in response to a change in the output detection current Isense is determined by the sum of a constant current Icc and a linear current Icl. FIGS. 1 and 2 are diagrams illustrating a case where an oscillator current Iosc2 generated in response to a change in an output detection current Isense is determined by a difference between a linear current Icl and a constant current Icc. 1 and 2 are diagrams showing the relationship between the oscillator currents Iosc1 and Iosc2 and the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9. FIG. It is a figure which shows the example of 1 structure of oscillator part OSCr. It is a timing chart for explaining operation of oscillator part OSCr. It is a figure which shows the 1st structural example of current source CS11. It is a figure which shows the 2nd structural example of current source CS11. It is a figure which shows the 3rd structural example of current source CS11. It is a figure which shows the 4th structural example of current source CS11.

<First embodiment of the present invention>
FIG. 1 is a circuit diagram showing a current mode synchronous rectification step-down DC / DC converter according to the present invention. The DC / DC converter 1 of this configuration example steps down the input voltage Vin supplied to the input terminal VIN and generates a desired output voltage Vout at the output terminal VOUT.

  The DC / DC converter 1 of this configuration example includes a switching element T11, a rectifying element T12, a drive circuit 3, an output current detection unit 4, a reverse current detection circuit 5, a feedback voltage generation circuit 6, an error amplifier 7, a phase compensation circuit 8, An oscillator 9, a PWM comparator 10, a slope voltage generation circuit 11, an inductor L1, and a smoothing capacitor C1 are provided.

  The switching element T11 is a P-channel type MOS [Metal Oxide Semiconductor] field effect transistor connected to the drive circuit 3, the output current detection unit 4, and the rectifier element T12. It functions as a switching transistor that controls the current to flow. A source S of the switching element T <b> 11 is connected to the output current detection unit 4. The drain D of the switching element T11 is connected to the drain D of the rectifying element T12. A gate signal GH is applied from the drive circuit 3 to the gate G of the switching element T11. The switching element T11 is turned off when the gate signal GH is at a high level, and turned on when the gate signal GH is at a low level. The rectifying element T12 supplies a current toward the inductor L1 when the switching element T11 is off.

  The rectifying element T12 is an N-channel MOS field effect transistor connected to the switching element T11 and the driving circuit 3, and operates as a synchronous rectifying transistor in a complementary manner in synchronization with the switching element T11. The drain D of the rectifying element T12 is connected to the drain D of the switching element T11. A common connection point between the rectifying element T12 and the switching element T11 is indicated as a node N1. The rectifying element T12 is turned on when the switching element T11 is turned off, and is turned off when the switching element T11 is turned on. The source S of the rectifying element T12 is connected to the ground potential GND. A gate signal GL is applied from the drive circuit 3 to the gate G of the rectifying element T12. The rectifying element T12 is turned on when the gate signal GL is at a high level, and turned off when the gate signal GL is at a low level.

  By switching on / off the switching element T11 and the rectifying element T12 in a complementary manner, a rectangular-wave switching voltage Vsw appears at the node N1. By smoothing the switching voltage Vsw by the inductor L1 and the smoothing capacitor C1, the output voltage Vout is extracted to the output terminal VOUT. The inductor L1 and the smoothing capacitor C1 are connected in series between the node N1 and the ground potential GND, and a common connection point thereof is indicated by a node N2. A voltage generated in the smoothing capacitor C1, that is, an output voltage Vout is generated at the node N2.

  In the DC / DC converter 1 of this configuration example, the switching element T11, the rectifying element T12, the inductor L1, and the smoothing capacitor C1 are used to step down the input voltage Vin supplied to the input terminal VIN and to obtain a desired output voltage. A step-down switch output stage for generating Vout at the output terminal VOUT is formed.

  In addition, when integrating the components (symbols 3 to 11 and the like) of the DC / DC converter 1 in an IC, the switching element T11 and the rectifying element T12 may be built in the IC or may be externally attached to the IC. Is possible. When externally attached to the IC, external terminals for externally outputting the gate signal GH and the gate signal GL are necessary. Further, an N-channel MOS field effect transistor can be used as the switching element T11. Further, as the switching element T11 and the rectifying element T12, an IGBT (Insulated Gate Bipolar Transistor) or the like can be used. Further, the switching element T11 and the rectifying element T12 may be constituted by bipolar transistors.

  Further, as a rectification method of the switch output stage, an asynchronous rectification method can be adopted instead of the synchronous rectification method using the rectifying element T12. In that case, a rectifier diode D12 is used as an alternative to the rectifier element T12. In this case, the cathode K of the rectifier diode D12 may be connected to the node N1, and the anode A of the rectifier diode D12 may be connected to the ground potential GND.

  In the drive circuit 3, in order to prevent an excessive through current flowing from the switching element T11 to the rectifying element T12, the gate signal GH is at a low level and the gate signal GL is not at a high level. A section (so-called dead time) in which the gate signal GH is at a high level and the gate signal GL is at a low level is provided.

  Further, the drive circuit 3 has a function of forcibly stopping the switching operation of the switch output stage according to an abnormality protection signal (not shown) (the gate signal GH output to the switching element T11 is set to the high level and is output to the rectifying element T12). A gate signal GL having a low level).

  The output current detection unit 4 detects an output detection current Isense that flows from the input terminal VIN toward the switching element T11. The output detection current Isense is a current proportional to the load current IL flowing through the load RL, and is a current reflecting the state of the load RL. Therefore, by detecting the magnitude of the output detection current Isense, it is possible to determine whether the load RL is in a no-load, light-load, medium-load, or heavy-load state.

  The reverse current detection circuit 5 detects a reverse current to the rectifying element T12, that is, a current flowing from the inductor L1 to the ground potential GND through the rectifying element T12. The presence or absence of the reverse current is performed by detecting a so-called zero cross point at which the switching voltage Vsw switches from negative to positive while the rectifying element T12 is on. When a reverse current exceeding a predetermined value is detected, a zero cross detection signal Szc is output from the reverse current detection circuit 5, and a gate signal GL is generated based on the zero cross detection signal Szc so as to turn off the rectifying element T12.

  The feedback voltage generation circuit 6 includes resistors R1 and R2 connected in series between the output terminal VOUT and the ground potential GND, and outputs the feedback voltage Vfb from the node N3 that is a common connection point. The feedback voltage Vfb is a voltage proportional to the voltage generated in the smoothing capacitor C1, and is also a DC voltage proportional to the output voltage Vout generated at the output terminal VOUT.

  The error amplifier 7 generates an error voltage Verr according to the difference between the reference voltage Vref input to the non-inverting input terminal (+) and the feedback voltage Vfb input to the inverting input terminal (−). The error voltage Verr increases when the feedback voltage Vfb is lower than the reference voltage Vref, and decreases when the feedback voltage Vfb is higher than the reference voltage Vref. The error voltage Verr is output from the output side of the error amplifier 7. Note that it is possible to convert the output from the output side of the error amplifier 7 into a current instead of a voltage. Such an error amplifier is known as a transconductance error amplifier.

  The phase compensation circuit 8 includes a series circuit of a resistor R3 and a capacitor C3 connected in series between the output terminal of the error amplifier 70 and the ground potential GND. It is well known to use such a phase compensation circuit for a DC / DC converter. The phase compensation circuit 8 is used to increase the difference with respect to the phase delay of 180 degrees in the DC / DC converter 1, that is, the phase margin. For example, assuming that the phase when the loop gain of the DC / DC converter 1 is 0 db (gain of 1) is 120 degrees, the phase margin is 180 degrees−120 degrees = 60 degrees. It is said that the phase margin is, for example, 45 degrees or more.

  The oscillator 9 includes a constant current source CC, a linear current source CL, and an oscillator unit OSCr coupled to the power supply voltage Vcc. The oscillator unit OSCr is constituted by, for example, a well-known CR oscillator, or a circuit in which inverters or differential amplifiers are connected in a ring shape. Regardless of the circuit configuration, in the present invention, the sum (+) of the constant current Icc generated by the constant current source CC and the linear current Icl generated by the linear current source CL, or the difference (−) thereof. The oscillation frequency Fosc of the clock signal CLK generated by the oscillator section OSCr is controlled based on the oscillator current (Iosc1, Iosc2) set by the above.

  The magnitude of the constant current Icc generated by the constant current source CC is always a constant current value regardless of whether the DC / DC converter 1 is under PWM control or PFM control. This is why it is called a constant current source. On the other hand, the linear current Icl generated by the linear current source CL has a constant current value when the DC / DC converter 1 is driven by the PWM method, but is detected by the switching element T11 when driven by the PFM. The variable current value has a magnitude proportional to the output detection current Isense. This is why it is called a linear current. The linear current Icl generated by the linear current source CL is set to a magnitude obtained by multiplying the output detection current Isense by a predetermined coefficient m, that is, Icl = m * Isense.

  In the generation of each of the linear current Icl that responds to the output detection current Isense and the constant current Icc that does not respond to the output detection current Isense, addition or subtraction thereof, and setting of these current ratios, for example, a current mirror circuit is used. Use it.

  The PWM comparator 10 compares the error voltage Verr applied to the inverting input terminal (−) and the slope voltage Vsl applied to the non-inverting input terminal (+) to generate the pulse width modulation signal pwm. Based on the pulse width modulation signal pwm, the DC / DC converter 1 performs PWM control.

  The pulse width modulation signal pwm output from the PWM comparator 10 is applied to the driving circuit 3 at the subsequent stage, and the switching element T11 and the rectifying element T12 are complementarily turned on and off. A sequential circuit (for example, an RS flip-flop) (not shown) is prepared inside the drive circuit 3. A clock signal CLK that is a rectangular wave signal generated by the oscillator 9 is applied to the set terminal of the RS flip-flop, and a pulse width modulation signal pwm is applied to the reset terminal. In this case, the clock signal CLK corresponds to the set signal of the RS flip-flop, and the pulse width modulation signal pwm corresponds to the reset signal of the RS flip-flop.

  The slope voltage generation circuit 11 generates a slope signal Vsl for operating the PWM comparator 10 by pulse width modulation. The slope signal Vsl is a triangular wave signal generated based on the clock signal CLK generated by the oscillator 9. Note that a voltage reflecting the magnitude of the switching voltage Vsw extracted from the node N1 is superimposed on the slope voltage generation circuit 11. More precisely, the slope voltage generation circuit 11 receives the input of the input voltage Vin and the switching voltage Vsw, and the voltage across the switching element T11 (= Vin−Vsw = Isense × Ron (T11), where Ron (T11) generates a slope signal Vsl reflecting the on-resistance value of the switching element T11. Thus, a voltage reflecting the output detection current Isense or the load current IL is superimposed on the voltage waveform of the slope signal Vsl, and a well-known current mode type DC / DC converter is configured. In the present invention, the current mode type DC / DC converter is not an indispensable component, and is also applied to the voltage mode type.

  FIG. 2 shows signal waveforms extracted from the output stage of the DC / DC converter 1 shown in FIG. 1, that is, the node N1 and the output terminal VOUT. Hereinafter, FIG. 2 will be described with reference to FIG.

  (A1) and (a2) in FIG. 2 are cases in which the DC / DC converter 1 is controlled by the frequency modulation (PFM) method when the load is light, and (a1) in FIG. A switching voltage Vsw (referred to herein as switching voltage SW1) extracted from N1 is shown. The frequency of the switching voltage SW1 is indicated by fosc1. The discontinuous signal components shown between the rectangular signals are caused by a zero-crossing phenomenon that occurs during no load or light load. The zero crossing means a state in which the minimum value of the triangular wave current flowing through the node N1 is lower than the ground potential GND after the switching element T11 shown in FIG. 1 is switched from the ON period to the ON period of the rectifying element T12.

  With the conventional control method, fluctuations appear periodically in the output voltage Vout, and the ripple component increases. In addition to this, when current is exchanged between the input capacitor and the output capacitor, a so-called switching noise signal is generated. If the frequency of the switching noise signal is placed in an audible frequency band, it will be heard by human ears and cause discomfort. According to the present invention, it is possible to prevent the sound due to switching noise at a light load and the sound due to the fluctuation of the output voltage Vout and the fluctuation of the input voltage Vin immediately before switching between the light load and the heavy load by the synchronous control. In order to suppress such switching noise, the oscillator 9 is controlled so that the frequency used in the PFM method is higher than the audible frequency band (for example, the oscillation frequency is higher than 20 KHz).

  (A2) in FIG. 2 shows an output voltage Vout (referred to herein as an output voltage Vout1) output to the output terminal VOUT under the condition (a1). The output voltage Vout1 generated at the output terminal VOUT has a ripple component superimposed thereon. This ripple component is shown with an enlarged vertical width for the convenience of drawing, but is actually several tens to 100 mV.

  (B1) and (b2) in FIG. 2 are similar to (a1) and (a2) in FIG. 2 when the DC / DC converter 1 is controlled by a frequency modulation (PFM) method when the DC / DC converter 1 is in a light load state. Switching voltage Vsw (referred to herein as switching voltage SW2). The frequency of the switching voltage SW2 shown in (b1) of FIG. 2 is indicated by fosc2, and this frequency fosc2 is higher than the frequency fosc1 of the switching voltage SW1 shown in (a1) of FIG. However, under the condition (b1), the output voltage Vout (herein referred to as output voltage Vout2) output to the output terminal VOUT includes a ripple component having a frequency fosc21 lower than the frequency fosc1. Show. For example, the frequency fosc2 is 100 KHz, and even if it is sufficiently higher than the audible frequency band, the frequency fosc21 is lower than the audible frequency band. When such an event occurs, a so-called “swelling sound” generated in the smoothing capacitor C1 is heard by the human ear or affects other electronic devices and becomes noise, which causes discomfort to the human. In order to solve such a problem, in the present invention, the output detection current Isense is detected, and the oscillation frequency Fosc of the oscillator 9 is controlled. Thereby, it becomes stable switching and a frequency component like the frequency fosc21 does not generate | occur | produce.

  (B1) in FIG. 2 is a case where the DC / DC converter 1 is controlled by the frequency modulation (PFM) system, similar to (a1) in FIG. 2, and the load state is more than in (a1) in FIG. A switching voltage Vsw (referred to herein as switching voltage SW3) in a heavy medium load state is shown. The frequency of the switching voltage SW3 is indicated by fosc3. The frequency fosc3 is higher than the frequency fosc1 shown in (a1) of FIG. 2, and is in a relationship of fosc3> fosc1. Therefore, even with the same PFM method, the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9 increases as the load increases, and the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9 decreases as the load decreases. Indicates that it is controlled to be low. It should be noted that the period and amplitude in which discontinuous signal components are generated between the rectangular wave signals of the switching voltages SW2 and SW3 correspond to zero crossing.

  (C2) in FIG. 2 shows the output voltage Vout (referred to herein as output voltage Vout3) output to the output terminal VOUT under the condition (c1). Note that the output voltage Vout3 generated at the output terminal VOUT has a ripple component superimposed, as in (a2) of FIG.

  (D1) and (d2) in FIG. 2 are different from (a1), (a2), (b1), (b2), (c1), and (c2) in FIG. A switching voltage Vsw (referred to herein as switching voltage SW4) in the case of being controlled by the modulation (PWM) method, that is, when the load state is a heavy load is shown. The frequency of the switching voltage SW4 is indicated by fosc4. Note that there is no period in which a discontinuous signal component is generated between the rectangular signals of the switching voltage SW4. This is because in the heavy load state, the minimum value of the triangular wave current (coil current) is sufficiently higher than the ground potential GND, and no zero crossing occurs.

  (D2) in FIG. 2 shows the output voltage Vout (referred to herein as output voltage Vout4) output to the output terminal VOUT under the condition (d1). The output voltage Vout4 generated at the output terminal VOUT has a ripple component superimposed as in (a2), (b2), and (c2) of FIG.

<Second embodiment of the present invention>
FIG. 3 is a circuit diagram showing a current mode synchronous rectification boost DC / DC converter according to the present invention. The DC / DC converter 2 boosts the input voltage Vin supplied to the input terminal VIN and takes out a desired output voltage Vout to the output terminal VOUT.

  The DC / DC converter 2 of this configuration example includes a switching element T21, a rectifying element T22, a drive circuit 3, an output current detection unit 4, a reverse current detection circuit 5, a feedback voltage generation circuit 6, an error amplifier 7, a phase compensation circuit 8, An oscillator 9, a PWM comparator 10, a slope voltage generation circuit 11, an inductor L2, and a smoothing capacitor C2 are provided.

  The DC / DC converter 2 is different from the step-down type shown in FIG. The other circuit parts are the same. Here, a description will be given of a circuit unit in which both are different.

  The switching element T21 is an N-channel MOS field effect transistor connected to the rectifying element T22, the drive circuit 3, and the inductor L2, and functions as a switching transistor that repeatedly turns on and off to control a current flowing through the inductor L2. To do. The switching element T21 operates complementarily in synchronization with the rectifying element T22. The source S of the switching element T21 is connected to the ground potential GND. The drain D of the switching element T21 is commonly connected to the drain D of the rectifying element T22 and one end of the inductor L2. This common connection point is indicated by node N1. A gate signal GL is applied from the drive circuit 3 to the gate G of the switching element T21. The switching element T21 is turned on when the gate signal GL is at a high level, and turned off when the gate signal GL is at a low level.

  The other end of the inductor L2 is connected to the input terminal VIN to which the input voltage Vin is supplied via the output current detection unit 4. That is, the switching element T21 is coupled to the input voltage Vin through the inductor L2. The current flowing through the inductor L2 is controlled by the switching element T21.

  The drain D of the rectifying element T22 is connected to the drain D of the switching element T21 and one end of the inductor L2. The source S of the rectifying element T22 is connected to the node N2, that is, the output terminal VOUT. A gate signal GH is applied from the drive circuit 3 to the gate G of the rectifying element T22. The rectifying element T22 is turned off when the gate signal GH is at a high level, and turned on when the gate signal GH is at a low level.

  A smoothing capacitor C2 is connected between the node N2, that is, the output terminal VOUT, and the ground potential GND. The smoothing capacitor C2 performs rectification and smoothing operation together with the inductor L2 and the rectifying element T22.

  Instead of the synchronous rectification method using the rectifying element T22, an asynchronous rectification method can be adopted. In that case, a rectifier diode D22 is used as an alternative to the rectifier element T22. In this case, the anode A of the rectifier diode D22 may be connected to the node N1, and the cathode K of the rectifier diode D22 may be connected to the node N2 (output terminal VOUT).

  The above description is different from the synchronous rectification step-up DC / DC converter 1 shown in FIG. 1 in the second embodiment of the present invention, that is, the synchronous rectification step-up DC / DC converter 2. The other circuit portions are the same as those in FIG. Also in the DC / DC converter 2, the oscillator 9 including the constant current source CC and the linear current source CL is applied. Although the step-down type is exemplified in the first embodiment of the present invention and the step-up type is exemplified in the second embodiment, a so-called step-up / step-down type DC / DC that switches between the step-down type and the step-up type is illustrated. Needless to say, the present invention can be applied to a DC converter.

  4 shows the oscillation of the clock signal CLK of the oscillator 9 in response to the magnitude of the load current IL flowing through the load RL in each of the DC / DC converter 1 of FIG. 1 and the DC / DC converter 2 of FIG. It is a figure which shows a mode that the frequency Fosc changes. Frequency modulation (PFM) control in which the oscillation frequency Fosc changes according to the magnitude of the load current IL is performed from IL1 to IL2 where the load current IL is relatively small. On the other hand, when the load current IL exceeds IL2, the mode is switched to pulse width modulation (PWM) control in which the oscillation frequency Fosc is fixed. When the load current IL falls below IL1, the oscillation frequency Fosc is maintained at fosc (a), and the constant current Icc and the linear current Icl of the oscillator 9 shown in FIGS. Is controlled. The oscillation frequency fosc (a) is set to the upper limit (for example, around 20 KHz) of the audible frequency band.

  Thus, when the load current IL (or output detection current Isense) is larger than the predetermined value IL2, the oscillator 9 sets the oscillation frequency Fosc of the rectangular wave signal CLK to a fixed value, and the load current IL (or output detection current Isense). Is smaller than the predetermined value IL2, the oscillation frequency of the rectangular wave signal CLK is lowered from the fixed value as the load current IL (or output detection current Isense) decreases.

  FIG. 5 shows a constant current Icc, a linear current Icl, an oscillator current Iosc1 set by the oscillator 9, and output detection in each of the DC / DC converter 1 of FIG. 1 and the DC / DC converter 2 of FIG. It is a figure which shows the relationship with the electric current Isense. Note that the output detection current Isense has a magnitude proportional to the load current IL. FIG. 5 shows a case where the oscillator current Iosc1 is determined by the sum (+) of the constant current Icc and the linear current Icl.

  In FIG. 5, the constant current Icc is always maintained at a constant magnitude without responding to the output detection current Isense. On the other hand, the linear current Icl is increased or decreased in proportion to the output detection current Isense in the section where the output detection current Isense is Is10 to Is20, but is maintained constant when the output detection current Isense exceeds Is20. The As a result, the oscillator current Iosc1 set as the sum of both responds to the linear current Icl. The control of the oscillator current Iosc1 is a source for controlling the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9, that is, switching between PFM control and PWM control. When the output detection current Isense is lower than Is10, the oscillator current Iosc1 is fixed to a predetermined magnitude. As a result, a decrease in the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9 is suppressed. In any case, when the PFM control is entered, the linear current Icl becomes dominant in the control of the oscillation frequency Fosc.

  6 shows a constant current Icc, a linear current Icl, an oscillator current Iosc2 set by the oscillator 9, and output detection in each of the DC / DC converter 1 of FIG. 1 and the DC / DC converter 2 of FIG. It is a figure which shows the relationship with the electric current Isense. Note that the output detection current Isense has a magnitude proportional to the load current IL. FIG. 6 shows a case where the oscillator current Iosc2 is determined by the difference (−) between the constant current Icc and the linear current Icl.

  In FIG. 6, the constant current Icc is always maintained at a constant magnitude without responding to the output detection current Isense. This shows the same characteristics as in FIG. On the other hand, the linear current Icl is increased or decreased in proportion to the output detection current Isense when the output detection current Isense is between Is1 and Is2, but is maintained constant when the output detection current Isense exceeds Is2. . These characteristics are the same as in FIG. As a result, the oscillator current Iosc2 set by the difference between the two responds to the linear current Icl. In FIG. 6, the constant current Icc is subtracted from the linear current Icl. However, the linear current Icl may be subtracted from the constant current Icc. In such a case, the circuit configuration of the oscillator 9 is configured so that the linear current Icl decreases as the output detection current Isense increases from Is1 to Is2.

  FIG. 7 is a diagram showing the relationship between the oscillator currents Iosc1 and Iosc2 shown in FIGS. 5 and 6 and the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9, respectively. 7 is substantially the same as that shown in FIG. That is, FIG. 4 shows how the change of the oscillation frequency Fosc depends on the load current IL, but FIG. 7 shows how the oscillation frequency Fosc is controlled depending on the oscillator currents Iosc1 and Iosc2. . Note that PFM control is performed when the oscillator currents Iosc1 and Iosc2 are in the range from Iosc12a to Iosc12b. On the other hand, when the oscillator currents Iosc1 and Iosc2 exceed Iosc12b, PWM control is performed.

<Oscillator section>
FIG. 8 is a diagram illustrating a configuration example of the oscillator unit OSCr. The oscillator section OSCr in this figure includes P-channel MOS field effect transistors P11 to P16, N-channel MOS field effect transistors N11 to N15, capacitors C11 and C12, and resistors R11 and R12, and includes a current source CS11. Is a type of CR oscillator that generates a rectangular wave signal CLK having an oscillation frequency Fosc by periodically repeating charging and discharging of the capacitors C11 and C12 using the oscillator current Iosc generated by the above.

  The current source CS11 corresponds to the previous constant current source CC and the linear current source CL, and the oscillator current Iosc corresponds to the previous oscillator current Iosc1 or Iosc2. The configuration and operation of the current source CS11 will be described in detail later.

  The sources of the transistors P11 to P16 are all connected to the application terminal of the power supply voltage Vcc. Each of the gates of the transistors P11 to P16 is connected to the drain of the transistor P11. The drain of the transistor P11 is connected to the first end of the current source CS11 (= the output end of the oscillator current Iosc).

  As described above, the transistors P11 to P16 have the oscillator current Iosc flowing through the drain of the transistor P11 at a predetermined mirror ratio A to E (for example, A = 4, B = 4, C = 2, D = 4, E = 1). By copying each of them, a current mirror circuit that generates mirror currents IP12 to IP16 of a plurality of systems (five systems in this figure) is formed.

  The drain of the transistor P12 is connected to the first end of the capacitor C11, the drain of the transistor N11, and the gate of the transistor N12. The drain of the transistor P13 is connected to the drain of the transistor N12 and the gate of the transistor N13. The drain of the transistor P14 is connected to the first end of the capacitor C12, the drain of the transistor N13, and the gate of the transistor N14. The drain of the transistor P15 is connected to the drain of the transistor N14 and the gate of the transistor N15. The drain of the transistor P16 is connected to the drain of the transistor N15 and the gate of the transistor N11.

  The source of the transistor N12 is connected to the first end of the resistor R11. The source of the transistor N14 is connected to the first end of the resistor R12. The second end of the current source CS11, the source of the transistor N11, the second end of the capacitor C11, the second end of the resistor R11, the source of the transistor N13, the second end of the capacitor C12, the second end of the resistor R12, and the transistor N15 Both of the second ends are connected to the ground end.

  FIG. 9 is a timing chart for explaining the operation of the oscillator unit OSCr, in which the node voltage V11, the node voltage V13, the node voltage V12, the node voltage V14, and the node voltage V15 are depicted in order from the top.

  The node voltage V11 is the gate voltage of the transistor N12. Node voltage V12 is the gate voltage of transistor N13. Node voltage V13 is the gate voltage of transistor N14. The node voltage V14 is the gate voltage of the transistor N15. The node voltage V15 is a gate voltage of the transistor N11. For example, the node voltage V15 is output as the rectangular wave signal CLK. Before the power supply voltage Vcc is input to the oscillator unit OSCr, the node voltages V11 to V15 are all at a low level.

  When the power supply voltage Vcc is input to the oscillator part OSCr, the charging of the capacitor C11 by the mirror current IP12 is started, so that the node voltage V11 starts to rise. However, when the node voltage V11 is lower than the threshold voltage Vtri1 (= VGS (N12) + R11 × IP13, VGS (N12) is an on-threshold voltage of the transistor N12), the transistor N12 is not turned on. As a result, the node voltage V12 becomes high level and the transistor N13 is turned on. When the transistor N13 is on, both ends of the capacitor C12 are short-circuited, so that the node voltage V13 becomes low level and the transistor N14 is turned off. Therefore, the node voltage V14 becomes high level and the transistor N15 is turned on, so that the node voltage V15 becomes low level and the transistor N11 is turned off. When the transistor N11 is off, both ends of the capacitor C11 are open, so that charging of the capacitor C11 is continued.

  Thereafter, when the node voltage V11 rises and exceeds the threshold voltage Vtri1, the transistor N12 is turned on, so that the node voltage V12 becomes low level and the transistor N13 is turned off. When the transistor N13 is off, both ends of the capacitor C12 are opened, and charging of the capacitor C12 by the mirror current IP14 is started, so that the node voltage V13 starts to rise. However, when the node voltage V13 is lower than the threshold voltage Vtri2 (= VGS (N14) + R12 × IP15, VGS (N14) is an on-threshold voltage of the transistor N14), the transistor N14 is not turned on. As a result, the node voltage V14 is maintained at a high level, so that the transistor N15 remains on. Therefore, since the node voltage V15 is maintained at a low level, the transistor N11 remains off. As described above, when the transistor N11 is off, both ends of the capacitor C11 are open, so that the charging of the capacitor C11 is continued.

  Note that the time t1 required from when the node voltage V11 starts to rise until it exceeds the threshold voltage Vtri1 can be expressed as t1 = C11 × Vtri1 / IP12. That is, the larger the mirror current IP12 (and hence the oscillator current Iosc), the shorter the time t1.

  Thereafter, when the node voltage V13 rises and exceeds the threshold voltage Vtri2, the transistor N14 is turned on, the node voltage V14 becomes low level, and the transistor N15 turns off, so that the node voltage V15 becomes high level. As a result, when the transistor N11 is turned on and both ends of the capacitor C11 are short-circuited, the node voltage V11 becomes low level and the transistor N12 is turned off, so that the node voltage V12 becomes high level and the transistor N13 is turned on. At this time, since both ends of the capacitor C12 are short-circuited, the node voltage V13 becomes low level and the transistor N14 is turned off again. Accordingly, the node voltage V14 rises to a high level and the transistor N15 is turned on, so that the node voltage V15 falls to a low level and the transistor N11 is turned off.

  The time t2 required from when the node voltage V12 starts to rise until it exceeds the threshold voltage Vtri2 can be expressed as t2 = C12 × Vtri2 / IP14. That is, the larger the mirror current IP14 (and hence the oscillator current Iosc), the shorter the time t2.

  By repeating the above series of operations, the rectangular wave signal CLK (= node voltage V15) having the oscillation frequency Fosc (= 1 / (t1 + t2)) can be generated. As the oscillator current Iosc is increased, the times t1 and t2 are shortened, so that the oscillation frequency Fosc is increased. Conversely, the smaller the oscillator current Iosc, the longer the times t1 and t2, and thus the lower the oscillation frequency Fosc.

<Current source>
FIG. 10 is a diagram illustrating a first configuration example of the current source CS11. The current source CS11 of the first configuration example includes a constant current source CC that generates a constant current Icc, and a linear current source CL that generates a linear current Icl.

  Constant current source CC includes a constant voltage source 111, an npn bipolar transistor 112, and a resistor 113.

  The constant voltage source 111 is a circuit unit that generates the constant voltage V111, and a band gap reference voltage source or the like can be preferably used.

  The transistor 112 and the resistor 113 function as a voltage / current conversion unit that converts the constant voltage V111 into a constant current Icc. More specifically, the base of the transistor 112 is connected to the output terminal of the constant voltage source 111 (= application terminal of the constant voltage V111). The emitter of the transistor 112 is connected to the first end of the resistor 113. The second end of the resistor 113 is connected to the ground end. The collector of the transistor 112 corresponds to the output terminal of the constant current Icc.

  The linear current source CL includes a voltage output type differential amplifier 121, an npn bipolar transistor 122, and a resistor 123.

  The differential amplifier 121 is the difference between the input voltage Vin input to the non-inverting input terminal (+) and the switch voltage Vsw input to the inverting input terminal (−) (= the voltage between both ends in the ON period of the switching element T11). ) To generate a linear voltage V121. Note that, as the output detection current Isense flowing during the ON period of the switching element T11 increases, the switch voltage Vsw decreases, and thus the linear voltage V121 increases. Thus, if the switch voltage Vsw is used not only for the current mode control but also for the variable control of the oscillation frequency Fosc, the output current detection unit 4 is omitted (= the slope voltage generation circuit 11 and the linear current source). Therefore, the circuit scale of the DC / DC converter 1 can be reduced.

  The transistor 122 and the resistor 123 function as a voltage / current converter that converts the linear voltage V121 into a linear current Icl. More specifically, the base of the transistor 122 is connected to the output terminal of the differential amplifier 121 (= application terminal of the linear voltage V121). The emitter of the transistor 122 is connected to the first end of the resistor 123. A second end of the resistor 123 is connected to the ground end. The collector of the transistor 122 corresponds to the output terminal of the linear current Icl. The linear current Icl varies in proportion to the linear voltage V121 (and thus the output detection current Isense).

  In the current source CS11 of this configuration example, the collectors of both the transistors 112 and 122 are commonly connected to the output terminal of the oscillator current Iosc. Therefore, the oscillator current Iosc (= Icc + Icl) obtained by adding the constant current Icc and the linear current Icl can be generated. This oscillator current Iosc corresponds to the oscillator current Iosc1 in FIG.

  FIG. 11 is a diagram illustrating a second configuration example of the current source CS11. The current source CS11 of the second configuration example is based on the first configuration example (FIG. 10), but the configuration of the linear current source CL is changed. Therefore, the same constituent elements as those in the first configuration example are denoted by the same reference numerals as those in FIG. 10, and redundant descriptions are omitted. In the following, feature portions of the second configuration example will be mainly described.

  Unlike the first configuration example (FIG. 10), the linear current source CL includes a current output type differential amplifier 124 and a current mirror circuit 125.

  The differential amplifier 124 has a difference between the input voltage Vin input to the non-inverting input terminal (+) and the switch voltage Vsw input to the inverting input terminal (−) (= voltage between both ends in the ON period of the switching element T11). ) To directly generate a linear current Icl. As the output detection current Isense flowing during the ON period of the switching element T11 increases, the linear current Icl1 increases in proportion to this. In this way, if the switch voltage Vsw is used not only for the current mode control but also for the variable control of the oscillation frequency Fosc, the output current detection unit 4 can be omitted, so that the DC / DC converter 1 The circuit scale can be reduced. This is the same as the first configuration example (FIG. 10).

  The current mirror circuit 125 is connected between the output terminal of the differential amplifier 124 and the ground terminal, and turns back the direction in which the linear current Icl flows. More specifically, the current mirror circuit 125 draws the linear current Icl from the output terminal of the oscillator current Iosc by mirroring the linear current Icl flowing into the current mirror circuit 125.

  In the current source CS11 of this configuration example, the collector of the transistor 112 and the output terminal of the current mirror circuit 125 are commonly connected to the output terminal of the oscillator current Iosc. Therefore, the oscillator current Iosc (= Icc + Icl) obtained by adding the constant current Icc and the linear current Icl can be generated. This oscillator current Iosc corresponds to the oscillator current Iosc1 in FIG. This is the same as the first configuration example (FIG. 10).

  FIG. 12 is a diagram illustrating a third configuration example of the current source CS11. The current source CS11 of the third configuration example is based on the first configuration example (FIG. 10), and a current mirror circuit 130 is added. Therefore, the same components as those in the first configuration example are denoted by the same reference numerals as those in FIG. 10, and redundant descriptions are omitted. In the following, the characteristic portions of the third configuration example will be mainly described.

  The current mirror circuit 130 is connected between the output terminal of the constant current source CC and the power supply terminal, and turns back the direction in which the constant current Icc flows. More specifically, the current mirror circuit 130 flows the linear current Icl into the output terminal of the oscillator current Iosc by mirroring the constant current Icc drawn into the constant current source CC.

  In the current source CS11 of this configuration example, the collector of the transistor 122 and the output terminal of the current mirror circuit 130 are commonly connected to the output terminal of the oscillator current Iosc. Therefore, the oscillator current Iosc (= Icl−Icc) obtained by subtracting the constant current Icc from the linear current Icl can be generated. This oscillator current Iosc corresponds to the oscillator current Iosc2 of FIG.

  FIG. 13 is a diagram illustrating a fourth configuration example of the current source CS11. The current source CS11 of the fourth configuration example uses the same linear current source CL as that of the second configuration example (FIG. 11) while being based on the third configuration example (FIG. 12). Even with this modification, it is possible to generate the oscillator current Iosc (= Icl−Icc) obtained by subtracting the constant current Icc from the linear current Icl. This is the same as the third configuration example (FIG. 12).

  In the oscillator 9, as a means for generating the constant current Icc and the linear current Icl, adding or subtracting them, and setting the current ratio thereof, as described above, a current mirror circuit is used. It is desirable to use it.

  As described above, the DC / DC converter of the present invention adjusts the oscillation frequency of the oscillator based on the output detection current proportional to the load current, so that switching between PWM control and PFM control can be performed smoothly. As a result, the present invention can be applied to a wide range of DC / DC converters regardless of the difference between the voltage mode type and the current mode type and the difference between the step-down type, the step-up type, and the step-up / step-down type.

DESCRIPTION OF SYMBOLS 1, 2 DC / DC converter 3 Drive circuit 4 Output current detection part 5 Reverse current detection circuit 6 Feedback voltage generation circuit 7 Error amplifier 8 Phase compensation circuit 9 Oscillator 10 PWM comparator 11 Slope voltage generation circuit C1, C2 Smoothing capacitor C3 Capacitor CC Constant current source CL Linear current source D12, D22 Rectifier diode GH, GL Gate signal OSCr Oscillator section CLK Clock signal Fosc Oscillation frequency Szc Zero cross detection signal Icc Constant current Icl Linear current pwm Pulse width modulation signal Iosc1, Iosc2 Oscillator current IL Load current Isense Output detection current L1, L2 Inductor N1-N3 Node R1-R3 Resistance RL Load T11, T21 Switching element T12, T22 Rectifier element Vcc Power supply voltage VIN Input terminal Vin Input Voltage Vsw Switching voltage VOUT Output terminal Vout Output voltage Vfb Feedback voltage Vref Reference voltage Verr Error signal Vsl Slope signal P11 to P16 P channel type MOS field effect transistor N11 to N15 N channel type MOS field effect transistor C11, C12 Capacitor R11, R12 Resistance CS11 current source 111 constant voltage source 112 npn type bipolar transistor 113 resistor 121 differential amplifier (voltage output type)
122 npn-type bipolar transistor 123 resistor 124 differential amplifier (current output type)
125 Current mirror circuit 130 Current mirror circuit

Claims (20)

A switching element connected to the input voltage and performing an on / off operation;
A drive circuit for performing on / off control of the switching element;
An inductor whose current is controlled by the switching element;
A smoothing capacitor connected to the inductor and rectifying with the inductor;
An oscillator for generating a rectangular wave signal for operating the driving circuit;
An output current detection unit for detecting an output detection current flowing in the switching element or the inductor;
The oscillator generates the rectangular wave signal at a fixed oscillation frequency when the output detection current is greater than or equal to a predetermined value, and more than the fixed oscillation frequency when the output detection current is less than or equal to a predetermined value. A DC / DC converter that generates the rectangular wave signal at an oscillation frequency that is low and proportional to the output detection current.   The oscillator includes a constant current source that generates a constant current regardless of the magnitude of the output detection current, and a linear current source that generates a linear current that responds to the magnitude of the output detection current. The DC / DC converter described in 1.   The DC / DC converter according to claim 2, wherein an oscillation frequency of the oscillator is set based on an oscillator current set by a sum of the constant current and the linear current or a difference between the two.   The linear current is fixed at a first current value when the output detection current is smaller than a first threshold, and the magnitude of the output detection current when the output detection current is larger than the first threshold and smaller than a second threshold. 3. The DC / DC according to claim 2, wherein the first current value is variably controlled from the first current value to the second current value in response to the first current value, and is fixed to the second current value when the output detection current is larger than the second threshold value. DC converter.   The DC / DC converter according to claim 2, wherein PWM control is performed when the output detection current is equal to or greater than a predetermined value, and PFM control is performed when the output detection current is equal to or less than a predetermined value.   The DC / DC converter according to claim 5, wherein when performing the PFM control, the setting of the oscillation frequency of the oscillator is governed by the linear current.   The DC / DC converter according to claim 5, wherein, when performing the PFM control, a lower limit value of the oscillation frequency is equal to or higher than an audible frequency band.   The DC / DC converter further compares a feedback voltage generated based on the voltage generated in the smoothing capacitor with a reference voltage preset to a predetermined magnitude, and outputs a difference between the two voltages as an error signal. An error amplifier that generates a slope signal based on a rectangular wave signal generated by the oscillator; and a PWM comparator that outputs a comparison result signal between the error signal and the slope signal to the drive circuit. The DC / DC converter as described in any one of Claims 1-7.   The DC / DC converter according to claim 8, wherein a voltage component corresponding to the output detection current is superimposed on the slope signal.   The DC / DC converter further comprises a rectifying element coupled to a common node of the switching element and the inductor to supply current to the inductor when the switching element is off. Item 10. The DC / DC converter according to any one of Items 9.   The DC / DC converter further includes a reverse current detection circuit that detects a reverse current flowing from a ground potential toward the common node, and when the reverse current detection circuit detects the predetermined reverse current, The DC / DC converter according to claim 10, wherein an operation of the rectifying element or the switching element coupled to a potential is turned off.   9. The DC / DC converter according to claim 8, wherein the error amplifier is a transconductance type.   The DC / DC converter according to any one of claims 1 to 12, wherein the DC / DC converter is a current mode type or a voltage mode type.   The DC / DC converter according to any one of claims 1 to 13, wherein the DC / DC converter is one of a step-down type, a step-up type, and a step-up / down type.   The DC / DC converter according to claim 3, wherein the oscillator further includes an oscillator unit that generates the rectangular wave signal by repeatedly charging and discharging a capacitor using the oscillator current.   The DC / DC converter according to claim 3, wherein the constant current source includes a constant voltage source that generates a constant voltage, and a voltage / current conversion unit that converts the constant voltage into the constant current.   4. The linear current source includes a voltage output type differential amplifier that generates a linear voltage corresponding to a voltage across the switching element, and a voltage / current converter that converts the linear voltage into the linear current. The DC / DC converter described in 1.   The DC / DC converter according to claim 3, wherein the linear current source includes a current output type differential amplifier that generates the linear current according to a voltage across the switching element.   4. The DC / DC converter according to claim 3, wherein the oscillator includes a current mirror circuit used for generating the constant current and the linear current, adding or subtracting them, and setting a current ratio thereof. An oscillator that generates a rectangular wave signal; and a drive circuit that drives a switch output stage of a DC / DC converter in synchronization with the rectangular wave signal;
The oscillator sets the oscillation frequency of the rectangular wave signal to a fixed value when the output detection current flowing through the switch output stage is larger than a predetermined value, and the output detection current when the output detection current is smaller than the predetermined value. The power supply control device characterized by lowering the oscillation frequency of the rectangular wave signal from the fixed value as the value becomes smaller.

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