JP2018078153A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent non-uniformity of on-voltage characteristics in a semiconductor substrate. A semiconductor device 1 includes a semiconductor substrate 10 partitioned into a plurality of IGBT regions SI1-3 and a plurality of diode regions SD1-3. At least the first drift region 24, the body region 25, the emitter region 26, and the trench insulating gate portion 30 are arranged in the IGBT region SI1-3. At least the second drift region 24 and the anode region 27 are arranged in the diode region SD1-3. The diode region SD1 is arranged in a range including the central portion. The area of each of the diode regions SD1-3 decreases from the central portion toward the periphery. [Selection diagram] Fig. 1

Description

  The technology disclosed in this specification relates to a semiconductor device including a semiconductor substrate provided with an IGBT structure and a diode structure.

  For example, development of a semiconductor device used as an in-vehicle power device is underway. As an example of this type of semiconductor device, a reverse conducting IGBT is known. The reverse conducting IGBT includes a semiconductor substrate on which an IGBT structure and a diode structure are provided. The diode structure is connected in antiparallel to the IGBT structure and operates as a freewheeling diode. Patent Document 1 discloses an example of a semiconductor device called a reverse conducting IGBT.

JP 2011-082220 A

  This type of semiconductor device is packaged as a module and then mounted on a power conversion device such as an inverter. Such packaging and mounting processes apply stress to the semiconductor substrate of the semiconductor device. The stress applied to the semiconductor substrate increases the distortion of the crystal structure of the semiconductor substrate and fluctuates the local on-voltage characteristics (Von characteristics) of the semiconductor device. The stress applied to the semiconductor substrate has an in-plane distribution having a maximum value at the center. For this reason, in this type of semiconductor device, the variation in the on-voltage characteristics at the center of the semiconductor substrate is large, and as a result, the on-voltage characteristics are not uniform in the semiconductor substrate.

  Further, the on-voltage characteristics of the semiconductor device strongly depend on the temperature. For this reason, in this type of semiconductor device, if the temperature difference in the semiconductor substrate is large, the on-voltage characteristics are not uniform in the semiconductor substrate.

  Such non-uniform on-voltage characteristics can cause local current concentration. The present specification provides a technique for improving non-uniform on-voltage characteristics due to stress applied to a semiconductor substrate and temperature in the semiconductor substrate.

  One embodiment of a semiconductor device disclosed in this specification includes a semiconductor substrate, a first main surface electrode, and a second main surface electrode. The semiconductor substrate is partitioned into a plurality of IGBT regions and a plurality of diode regions. The first main surface electrode coats the first main surface of the semiconductor substrate. The second main surface electrode coats the second main surface of the semiconductor substrate. An IGBT structure provided on a semiconductor substrate has a first conductivity type collector region, a second conductivity type first drift region, a first conductivity type body region, a second conductivity type emitter region, and an insulated gate portion. . The collector region is in contact with the first main surface electrode. The first drift region is provided on the collector region. The body region is provided on the first drift region and is in contact with the second main surface electrode. The emitter region is separated from the drift region by the body region, and is in contact with the second main surface electrode. The insulated gate portion faces the body region at a portion separating the drift region and the emitter region. The insulated gate portion may be a trench type or a planar type. The diode structure provided on the semiconductor substrate has a second conductivity type cathode region, a first conductivity type anode region, and a second conductivity type second drift region. The cathode region is in contact with the first main surface electrode. The anode region is in contact with the second main surface electrode. The second drift region is provided between the cathode region and the anode region, and includes an impurity concentration lower than the impurity concentration of the cathode region. The second drift region has the same impurity concentration as the first drift region, and may be a region continuous from the first drift region. In the IGBT region, at least a first drift region, a body region, an emitter region, and an insulated gate portion are disposed. At least a second drift region and an anode region are disposed in the diode region. When the semiconductor substrate is viewed in plan, IGBT regions and diode regions are alternately arranged from the central portion toward the periphery. A diode region is arranged in a range including the central portion. The area of each diode region decreases from the center toward the periphery.

  Since the IGBT region is a region where a channel is formed, a local variation in on-voltage characteristics of the IGBT region is sensitive to stress and temperature variation applied to the semiconductor substrate. On the other hand, since the diode region is not a region where a channel is formed, local variations in on-voltage characteristics of the diode region are insensitive to stresses and temperature variations applied to the semiconductor substrate. In the semiconductor device of the above-described embodiment, since many diode regions are arranged on the center side where the stress applied to the semiconductor substrate is maximum, a large variation in on-voltage characteristics is suppressed, and the on-voltage characteristics in the semiconductor substrate are reduced. Variation is equalized. In the semiconductor device of the above embodiment, when the semiconductor substrate is viewed in plan, the IGBT regions and the diode regions are alternately arranged from the central portion toward the periphery. Since the diode region is interposed between the IGBT regions, the temperature increase of the IGBT region is suppressed by heat extraction from the diode region, and thereby the variation of the on-voltage characteristics in the semiconductor substrate is made uniform. As described above, the semiconductor device of the above embodiment can improve the non-uniform on-voltage characteristics due to the stress applied to the semiconductor substrate and the temperature in the semiconductor substrate.

FIG. 3 is a schematic cross-sectional view of a main part of a semiconductor device, corresponding to a line II in FIG. 2. It is a top view which shows the layout of the IGBT area | region and diode area | region currently formed in the semiconductor substrate of a semiconductor device. It is a top view which shows the layout of the IGBT area | region and diode area | region currently formed in the semiconductor substrate of the semiconductor device of a modification. FIG. 10 is a schematic cross-sectional view of a main part of a semiconductor device according to a modification, corresponding to the line II in FIG. 2. FIG. 10 is a schematic cross-sectional view of a main part of a semiconductor device according to a modification, corresponding to the line II in FIG. 2.

  As shown in FIGS. 1 and 2, the semiconductor device 1 includes a semiconductor substrate 10 partitioned into a plurality of IGBT regions SI1-3 and a plurality of diode regions SD1-3. When the semiconductor substrate 10 is viewed in plan, the IGBT regions SI1-3 and the diode regions SD1-3 are alternately arranged from the central portion toward the periphery, and the diode region SD1 is disposed in a range including the central portion. Yes. In the example shown in FIG. 2, each of the plurality of IGBT regions SI1-3 and the plurality of diode regions SD2-3 is arranged around the diode region SD1. Instead of this example, as shown in FIG. 3, a part of each of the plurality of IGBT regions SI1-3 and the plurality of diode regions SD1-3 may be divided by a region for gate wiring.

  As shown in FIG. 1, the semiconductor device 1 includes a collector electrode 36 that covers the back surface of the semiconductor substrate 10 and an emitter electrode 38 that covers the surface of the semiconductor substrate 10. The semiconductor device 1 further includes a trench insulating gate portion 30 provided in each of the IGBT regions SI1-3 and a dummy trench 40 provided in each of the diode regions SD1-2.

The semiconductor substrate 10 includes a p-type collector region 21, an n-type cathode region 22, an n-type buffer region 23, an n ⁻ -type drift region 24, a p-type body region 25, an n ⁺ -type emitter region 26 and p. A type anode region 27 is provided.

  Collector region 21 is arranged in each of IGBT regions SI1-3. The collector region 21 is provided in a part of the back layer portion of the semiconductor substrate 10 and is exposed on the back surface of the semiconductor substrate 10. The collector region 21 has a high impurity concentration and is in ohmic contact with the collector electrode 36. The collector region 21 is formed, for example, by introducing boron from the back surface of the semiconductor substrate 10 using an ion implantation technique.

  The cathode region 22 is disposed in each of the diode regions SD1-3. The cathode region 22 is provided in a part of the back layer portion of the semiconductor substrate 10 and is exposed on the back surface of the semiconductor substrate 10. The cathode region 22 has a high impurity concentration and is in ohmic contact with the collector electrode 36. The cathode region 22 is formed, for example, by introducing phosphorus from the back surface of the semiconductor substrate 10 using an ion implantation technique.

  The buffer region 23 is disposed in each of the IGBT region SI1-3 and the diode region SD1-3. The buffer region 23 is provided between the collector region 21 and the drift region 24 in the IGBT region SI1-3. The buffer region 23 is provided between the collector region 21 and the drift region 24 in the diode region SD1-3. The buffer region 23 is formed, for example, by introducing phosphorus from the back surface of the semiconductor substrate 10 using an ion implantation technique.

  The drift region 24 is disposed in each of the IGBT region SI1-3 and the diode region SD1-3. The drift region 24 is provided between the buffer region 23 and the body region 25 in the IGBT region SI1-3. The drift region 24 is provided between the buffer region 23 and the anode region 27 in the diode region SD1-3. The drift region 24 is a remaining portion in which another region is formed in the semiconductor substrate 10, and the impurity concentration is constant in the thickness direction.

  Body region 25 is arranged in each of IGBT regions SI1-3. The body region 25 is provided in the surface layer portion of the semiconductor substrate 10 and is exposed on the surface of the semiconductor substrate 10. Body region 25 has a main body region 25a and a contact body region 25b. Contact body region 25b has an impurity concentration higher than that of main body region 25a and is in ohmic contact with emitter electrode 38. The body region 25 disposed in each of the IGBT regions SI1-3 is provided between the adjacent trench insulating gate portions 30, and is in contact with both side surfaces of the adjacent trench insulating gate portions 30. The body region 25 is formed, for example, by introducing boron from the surface of the semiconductor substrate 10 using an ion implantation technique.

  The emitter region 26 is arranged in each of the IGBT regions SI1-3. The emitter region 26 is provided in the surface layer portion of the semiconductor substrate 10 and is exposed on the surface of the semiconductor substrate 10. The emitter region 26 has a high impurity concentration and is in ohmic contact with the emitter electrode 38. A plurality of emitter regions 26 arranged in each of the IGBT regions SI1-3 are provided between adjacent trench insulating gate portions 30, and at least one emitter region 26 is adjacent to the adjacent trench insulating gate portion 30. It is in contact with one side and at least one other emitter region 26 is in contact with the other side. The emitter region 26 is formed, for example, by introducing arsenic or phosphorus from the surface of the semiconductor substrate 10 using an ion implantation technique.

  The anode region 27 is disposed in each of the diode regions SD1-3. The anode region 27 is provided in the surface layer portion of the semiconductor substrate 10 and is exposed on the surface of the semiconductor substrate 10. The anode region 27 has a main anode region 27a and a contact anode region 27b. The contact anode region 27b has an impurity concentration higher than that of the main anode region 27a and is in ohmic contact with the emitter electrode 38. The anode region 27 disposed in each of the diode regions SD1-3 is provided between the adjacent dummy trenches 40 and is in contact with both side surfaces of the adjacent dummy trenches 40. The anode region 27 is formed, for example, by introducing boron from the surface of the semiconductor substrate 10 using an ion implantation technique.

  The trench insulating gate portion 30 extends in the depth direction so as to penetrate the emitter region 26 and the body region 25 and reach the drift region 24 in each of the IGBT regions SI1-3. The emitter region 26 and the body region 25 are in contact with the side surface of the trench insulating gate portion 30. The drift region 24 is in contact with the side surface and the bottom surface of the trench insulating gate portion 30. The trench insulating gate portion 30 has a gate insulating film 32 and a gate electrode 34. The gate electrode 34 is insulated from the semiconductor substrate 10 by the gate insulating film 32. The gate electrode 34 is electrically connected to the gate wiring, and is configured to be able to apply a gate voltage.

  The dummy trench 40 extends in the depth direction so as to penetrate the anode region 27 and reach the drift region 24. The anode region 27 is in contact with the side surface of the dummy trench 40. The drift region 24 is in contact with the side surface and the bottom surface of the dummy trench 40. The dummy trench 40 includes a dummy trench insulating film 42 and a dummy trench electrode 44. The dummy trench electrode 44 is insulated from the semiconductor substrate 10 by the dummy trench insulating film 42. The dummy trench electrode 44 is electrically connected to the emitter electrode 38. Instead of this example, the potential of the dummy trench electrode 44 may be floating.

  As described above, in the semiconductor device 1, the collector electrode 36, the collector region 21, the buffer region 23, the drift region 24, the body region 25, the emitter region 26, the emitter electrode 38, and the trench insulating gate portion 30 constitute an IGBT structure. The IGBT structure is selectively disposed in the IGBT region SI1-3. In the semiconductor device 1, the collector electrode 36, the cathode region 22, the buffer region 23, the drift region 24, the anode region 27, the emitter electrode 38, and the dummy trench 40 constitute a diode structure, and the diode structure is the diode region SD1-3. Are selectively arranged. The collector electrode 36 functions as a cathode electrode in the diode structure, and the emitter electrode 38 functions as an anode electrode in the diode structure.

  In the example shown in FIG. 1, all IGBT structures are selectively disposed in the IGBT region SI1-3, and all diode structures are selectively disposed in the diode region SD1-3. However, the back surface structure is not limited to such a layout. For example, as shown in FIG. 4, in the back surface structure of the diode region SD1-3, each of the collector region 21 and the cathode region 22 may be distributed in the plane. In this example, since the area of the cathode region 22 in the diode region SD1-3 is reduced, the amount of carrier injection during diode operation can be suppressed. Further, as shown in FIG. 5, each of the collector region 21 and the cathode region 22 may be uniformly distributed over the entire back surface of the semiconductor substrate 10.

  Thus, the IGBT region SI1-3 and the diode region SD1-3 are distinguished by the surface structure. The IGBT region SI1-3 is a region in which at least the drift region 24, the body region 25, the emitter region 26, and the trench insulated gate portion 30 are disposed in the IGBT structure, and is a region where a channel is formed. The diode region SD1-3 is a region in which at least the drift region 24 and the anode region 27 are arranged in the diode structure, and a channel is not formed.

  Next, the operation of the semiconductor device 1 will be described. First, the operation of the IGBT structure in the IGBT region SI1-3 will be described. When a higher potential than the emitter electrode 38 is applied to the collector electrode 36 and a potential higher than the threshold is applied to the gate electrode 34, a channel is formed in the body region 25 on the side surface of the gate insulating film 32, and the IGBT structure is turned on. . At this time, electrons flow from the emitter electrode 38 toward the collector electrode 36 via the emitter region 26, the channel of the body region 25, the drift region 24, the buffer region 23, and the collector region 21. On the other hand, holes flow from the collector region 21 toward the emitter electrode 38 via the buffer region 23, the drift region 24, and the body region 25. As described above, when the IGBT structure is turned on, a current flows from the collector electrode 36 toward the emitter electrode 38. Thereafter, when the potential of the gate electrode 34 falls below the threshold value, the channel disappears and the IGBT structure is turned off.

  Next, the operation of the diode structure of the diode region SD1-3 will be described. When a potential higher than that of the collector electrode 36 is applied to the emitter electrode 38, a forward voltage is applied to the pn junction formed by the body region 25 and the drift region 24, and holes are injected from the body region 25 into the drift region 24. The On the other hand, electrons are injected from the cathode region 22 into the drift region 24. In this way, the pn diode having the diode structure becomes conductive, and a reflux current flows.

  Next, features of the semiconductor device 1 will be described. As shown in FIG. 2, when the semiconductor device 1 is viewed in plan, the semiconductor device 1 includes an IGBT region SI1 from the center to the periphery of the element region where the IGBT region SI1-3 and the diode region SD1-3 are present. -3 and diode regions SD1-3 are alternately arranged. Further, the diode region SD-1 is arranged in a range including the central portion. Further, each area of the diode region SD-1 decreases from the central portion toward the periphery. In other words, each area of the IGBT region SI1-3 increases from the center toward the periphery.

  Since the IGBT region SI1-3 is a region where a channel is formed, the local variation of the on-voltage characteristics of the IGBT region SI1-3 is sensitive to the stress applied to the semiconductor substrate 10 and the temperature variation. On the other hand, since the diode region SD1-3 is not a region where a channel is formed, the local variation of the on-voltage characteristics of the diode region SD1-3 is insensitive to the stress applied to the semiconductor substrate 10 and the temperature variation. .

  As described in the background art, the semiconductor device 1 is packaged as a module and then mounted on a power conversion device such as an inverter. Such packaging and mounting processes apply stress to the semiconductor substrate 10 of the semiconductor device 1. The stress applied to the semiconductor substrate 10 has an in-plane distribution having a maximum value at the center. In the semiconductor device 1, many diode regions SD <b> 1-3 are arranged on the center side where the stress applied to the semiconductor substrate 10 is maximum. For this reason, in the semiconductor device 1, large fluctuations in the on-voltage characteristics are suppressed, and fluctuations in the on-voltage characteristics in the semiconductor substrate 10 are made uniform.

  In the semiconductor device 1, when the semiconductor substrate 10 is viewed in plan, the IGBT regions SI1-3 and the diode regions SD1-3 are alternately arranged from the central portion toward the periphery. By interposing the diode region SD1-3 between the IGBT regions SI1-3, the local temperature rise of the IGBT region SI1-3 is suppressed by the heat extraction from the diode region SD1-3. The fluctuation of the on-voltage characteristic in the inside is made uniform.

  As described above, the semiconductor device 1 can improve non-uniform electrical characteristics due to the stress applied to the semiconductor substrate 10 and the temperature in the semiconductor substrate 10. As a result, local current concentration caused by non-uniform electrical characteristics can be suppressed, and the semiconductor device 1 can have high reliability.

  The semiconductor device 1 is useful when mounted on, for example, a power converter having a large capacity. The power converter is increased in capacity by switching elements connected in parallel. In this case, it is important to use switching elements connected in parallel so that the electric characteristics are uniform so that current concentration does not occur in one switching element. However, if the electrical characteristics fluctuate due to the packaging and mounting process and nonuniform electrical characteristics occur between the switching elements, the current may concentrate on one switching element. Since the technology applied to the semiconductor device 1 can suppress fluctuations in electrical characteristics due to packaging and mounting processes, fluctuations in electrical characteristics between the semiconductor devices 1 can also be suppressed. For this reason, the technique applied to the semiconductor device 1 can improve the reliability of the power converter having a large capacity.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1: Semiconductor device 10: Semiconductor substrate 21: Collector region 22: Cathode region 23: Buffer region 24: Drift region 25: Body region 25a: Main body region 25b: Contact body region 26: Emitter region 27: Anode region 27a: Main anode Region 27b: Contact anode region 30: Trench insulating gate portion 32: Gate insulating film 34: Gate electrode 36: Collector electrode 38: Emitter electrode 40: Dummy trench 42: Dummy trench insulating film 44: Dummy trench electrode SD1-3: Diode region SI1-3: IGBT area

Claims (1)

A semiconductor substrate partitioned into a plurality of IGBT regions and a plurality of diode regions;
A first main surface electrode that coats the first main surface of the semiconductor substrate;
A second main surface electrode that coats the second main surface of the semiconductor substrate,
The IGBT structure provided on the semiconductor substrate is
A first conductivity type collector region in contact with the first principal surface electrode;
A first conductivity type first drift region provided on the collector region;
A body region of a first conductivity type provided on the first drift region and in contact with the second main surface electrode;
An emitter region of a second conductivity type separated from the drift region by the body region and in contact with the second main surface electrode;
An insulating gate portion facing the body region at a portion separating the drift region and the emitter region;
The diode structure provided on the semiconductor substrate is:
A second conductivity type cathode region in contact with the first principal surface electrode;
An anode region of a first conductivity type in contact with the second principal surface electrode;
A second drift region of a second conductivity type provided between the cathode region and the anode region and having an impurity concentration lower than the impurity concentration of the cathode region;
In the IGBT region, at least the first drift region, the body region, the emitter region, and the insulated gate portion are disposed,
In the diode region, at least the second drift region and the anode region are disposed,
When the semiconductor substrate is viewed in plan, the IGBT regions and the diode regions are alternately arranged from the center toward the periphery,
The diode region is arranged in a range including the central portion,
The semiconductor device, wherein the area of each of the diode regions decreases from the central portion toward the periphery.

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