JP2018073017A - Semiconductor device, image recording apparatus and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, an image recording apparatus and an electronic apparatus, which are of novel configurations.SOLUTION: A semiconductor device has a plurality of modules and a plurality of programmable switches. The module has a neuron circuit, a synapse circuit, and an error circuit. The neuron circuit has a function capable of switching between the function of an input neuron circuit and that of a hidden neuron circuit. The synapse circuit includes a first multiplier circuit for changing data corresponding to a bonding strength, an analog memory for storing the data, and a second multiplier circuit for outputting a first signal as a second signal weighted in accordance with the data. The error circuit has a function capable of switching between the function of an output neuron circuit and the function of a hidden error circuit. The analog memory has a transistor provided with an oxide semiconductor in a channel formation region. The programmable switch has a function of switching electrical connections between the modules.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device, a recording device, and an electronic device.

  As television (TV) becomes larger, it is desired that a high-definition video can be viewed. For example, an image receiving apparatus for supporting 8K broadcasting has been developed (Non-Patent Document 1).

  On the other hand, broadcasting satellites used in digital television broadcasting have a limit on the transmission band that can be transmitted. For full high-definition (FullHD, 2K), it is necessary to transmit 4 times the image data at 4K and 16 times at 8K. The technology (codec) for decompressing (decoding) on the receiving side is important.

  In the encoder, as a compression algorithm, intra-frame prediction (acquisition of difference data between adjacent pixels), inter-frame prediction (acquisition of difference data of each pixel between frames), motion compensation prediction (prediction of the motion of the moving object, the movement Image data compression is realized by obtaining difference data of each pixel from an image of a moving body, orthogonal transform (discrete cosine transform), encoding, and the like.

S. Kawashima, et al. "13.3-In. 8K X 4K 664-ppi OLED Display Using CAAC-OS FETs", SID 2014 DIGEST, pp. 627-630.

  In order to send the image data compressed on the transmission side in real time, it is necessary to compress the image data within a limited time and at a high compression rate. That is, a highly efficient encoder is required. In particular, in motion compensation prediction, it is necessary to efficiently extract a moving body pattern from image data. On the other hand, when emphasizing real-time characteristics, there is no time margin when sending a broadcast signal, so it can be said that further compression is unnecessary as long as it can be compressed within the transmission band.

  Now, 8K digital TV broadcasts are planned to be mixed with 4K digital TV broadcasts, and content distribution with 8K digital TV alone, including the continuation or coexistence of conventional full high-definition broadcasts, is within normal viewing time. Expected to decrease. Therefore, for content distribution to specific users who want to enjoy 8K high-quality content, distribution to contracted users (cable TV, etc.), distribution at specific times (such as nighttime), and purchase of specific media Distribution (DVD (Digital Versatile Disc), Blu-ray Disc, etc. for home theater use)) and the like. Therefore, a device for recording (recording) the content or a device for reproducing the recorded content is required. However, as described above, there is a possibility that the broadcast signal to be transmitted may not necessarily be sufficiently compressed, and there is a risk that convenience may be impaired, such as requiring a huge amount of recording storage devices.

  In view of the above, an object of one embodiment of the present invention is to provide a novel semiconductor device, a recording device, and an electronic device which have different structures from existing semiconductor devices, recording devices, and electronic devices.

  One embodiment of the present invention provides a semiconductor device, a recording device, and an electronic device that record a broadcast signal again in a state where the compression rate is increased, that is, in a state where the data amount is reduced. The pattern extraction used for the compression processing includes a plurality of modules having a plurality of neuron circuits, a plurality of synapse circuits, and a plurality of error circuits, and the modules are connected by a programmable switch.

  The neuron circuit functions as an input neuron circuit or a hidden neuron circuit. When functioning as an input neuron circuit, an output signal is generated from an input signal from the outside of the semiconductor device to a synapse circuit in the module. When functioning as a hidden neuron circuit, an output signal to the synapse circuit in the module is generated from a signal obtained by adding the input signals from the synapse circuit of the module in the previous stage.

  The synapse circuit has an analog memory that stores data corresponding to the coupling strength between the neuron circuit of the module and the neuron circuit of the module in the subsequent stage, and the synapse circuit receives data from the neuron circuit of the module according to the data of the analog memory. The output signal weighted to the input signal is output to the neuron circuit of the module in the subsequent layer and the error circuit of the module, and the data of the analog memory is updated according to the error signal from the error circuit of the module, and the data is converted to the data of the analog memory. Therefore, an error signal weighted to the error signal from the error circuit of the same module is output to the error circuit of the module in the previous stage.

  The error circuit functions as an output neuron circuit or a hidden error circuit. When functioning as an output neuron circuit, an output signal to the outside of the semiconductor device is generated from a signal obtained by adding the input signals from the synapse circuits in the same layer, and the difference between the teacher signal given from the outside of the semiconductor device and the output signal is generated. The generated error signal is output to the synapse circuit of the module. When it functions as a hidden error circuit, it generates an output signal to the neuron circuit of the module in the subsequent layer from the signal obtained by adding the input signals from the synapse circuit in the same layer, and the error signal from the synapse circuit of the module in the subsequent layer An error signal generated from the difference from the output signal is output to the synapse circuit of the module.

  By configuring the analog memory with a transistor using an oxide semiconductor, an ideal analog memory can be configured. Therefore, there is no need to mount a large-scale capacitor element for storage, and Since there is no need to restore analog data by a regular refresh operation, the chip area can be reduced and the power consumption can be reduced.

  In addition, the connection between the modules can be programmable, and one layer can be composed of a plurality of modules, and a multilayer structure can be formed.

  By appropriately connecting the input signal of the neuron circuit, the output signal and error signal (output) of the synapse circuit, the input signal of the error circuit, the output signal and the error signal (input) in the layer, the number of neurons in the same layer can be reduced. Can be increased.

  In the case of a multi-layer structure, the neuron circuit in the module in the layer to which the input signal from the outside of the semiconductor device is input is set to function as the input neuron circuit, and the output signal to the outside of the semiconductor device is output and the outside of the semiconductor device Set the error circuit in the module of the layer to which the teacher signal from is input to function as an output neuron circuit, so that the neuron circuit in the other layer module functions as a hidden neuron circuit, and the error circuit functions as a hidden error circuit Set. These settings are also programmable and can be set as appropriate. With such a configuration, the hierarchical structure such as the number of neurons and the number of neurons in the same layer can be freely changed. Connection between modules is a programmable switch composed of a transistor (OS transistor) using an oxide semiconductor, and the hierarchical structure is set by turning on / off the switch according to data stored in a memory composed of the transistor. The power consumption for maintaining the hierarchical concept can be made extremely low.

  In a semiconductor device, learning data is given as an input signal of an input neuron circuit, a teacher signal corresponding to the learning data is given as an input signal of an output neuron circuit, and a pattern is obtained by updating data in an analog memory according to an error signal. learn. After learning, when target data is given as an input signal of the input neuron circuit, it is possible to determine that the target data and the learning data are identical or similar. Here, by setting the data of the programmable switch so that the data of the target object (moving body) is used as learning data and a preferable hierarchical structure is set, the object in the image data can be detected. That is, it is possible to efficiently extract a moving body pattern from image data, to efficiently perform motion compensation prediction, and to record a recording device using the semiconductor device with a reduced amount of broadcast signal data. Can be provided.

  Hereinafter, one embodiment of the present invention will be described.

  One embodiment of the present invention is a semiconductor device having a function of encoding video data, and the semiconductor device includes a plurality of modules and a plurality of programmable switches. The modules include a neuron circuit, a synapse circuit, and the like. And the error circuit, the neuron circuit has a function capable of switching between the function of the input neuron circuit and the function of the hidden neuron circuit, and the synapse circuit changes the data corresponding to the coupling strength. And an analog memory for storing data, and a second multiplier circuit for outputting the first signal as a second signal weighted according to the data, the error circuit being an output neuron circuit The analog memory has an oxide semiconductor in the channel formation region. Has a transistor, the programmable switch is a semiconductor device having a function of switching the electrical connection between modules.

  In one embodiment of the present invention, a neuron circuit includes a first switching circuit, and when the first switching circuit functions as an input neuron circuit, a circuit that amplifies an input signal from the outside and outputs the signal to a synapse circuit In the case of functioning as a hidden neuron, a semiconductor device having a function of switching a current output from a synapse circuit into a voltage and outputting it to a synapse circuit included in another module is preferable.

  In one embodiment of the present invention, the error circuit includes a second switching circuit. When the second switching circuit functions as an output neuron circuit, the current output from the synapse circuit is converted into a voltage to generate another module. The difference signal between the signal output as the input signal of the other module and the signal output as the input signal of another module and the teacher signal, and the multiplication signal of the differential coefficient generated based on the signal output as the input signal of another module and the difference signal A circuit that outputs the error signal obtained from the above to the synapse circuit, and when it functions as a hidden error circuit, the differential signal generated based on the signal obtained by converting the current output from the synapse circuit into a voltage, and the teacher signal and reference A semiconductor device having a function of switching between a signal obtained by a difference from a voltage and a circuit that outputs an error signal obtained by a multiplication signal to a synapse circuit It is preferred.

  One embodiment of the present invention is a recording device having a function of storing video data, which includes a storage device and the semiconductor device described above, and the semiconductor device generates compressed data obtained by compressing a video signal. The storage device is a recording device having a function of storing compressed data.

  One embodiment of the present invention is an electronic device including a display portion and the above-described recording device.

  According to one embodiment of the present invention, efficient image data compression is possible by efficiently executing motion compensation prediction. Further, according to one embodiment of the present invention, a pattern of a moving object can be extracted efficiently in accordance with image data. In addition, according to one embodiment of the present invention, in order to cope with a larger number of patterns of a moving body, a broadcast signal using a semiconductor device that can freely change a hierarchical structure such as the number of neurons and the number of neurons in the same layer is used. It is possible to provide a recording device that records data with a reduced amount of data.

FIG. 6 illustrates an example of a block diagram. FIG. 6 illustrates an example of a circuit diagram. FIG. 6 illustrates an example of a block diagram. FIG. 6 illustrates an example of a block diagram. FIG. 6 illustrates an example of a circuit diagram. FIG. 6 illustrates an example of a circuit diagram. FIG. 6 illustrates an example of a circuit diagram. FIG. 6 illustrates an example of a circuit diagram. FIG. 6 illustrates an example of a circuit diagram. The figure explaining an example of a flowchart. The figure explaining an example of a flowchart. The figure for demonstrating an example of operation | movement. The figure explaining an example of a flowchart. FIG. 6 illustrates an example of a block diagram. FIG. 6 illustrates an example of a block diagram. FIG. 6 illustrates an example of a block diagram. FIG. 6 illustrates an example of a block diagram.

  Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  In the present specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It is also possible. In addition, for example, the constituent elements referred to as “first” in one embodiment of the present specification and the like may be omitted in other embodiments or in the claims.

  Note that in the drawings, the same element, an element having a similar function, an element of the same material, an element formed at the same time, or the like may be denoted by the same reference numeral, and repeated description thereof may be omitted.

(Embodiment 1)
Embodiments of the present invention will be described with reference to FIGS.

<Module configuration>
FIG. 1 shows a circuit block of a module 100 constituting a semiconductor device. The module 100 includes n (n is a natural number) neuron circuits NU, m × n (m is a natural number) synapse circuits SU, and m error circuits EU.

  Hereinafter, each circuit block constituting the module 100 shown in FIG. 1 will be described.

  FIG. 2A shows the configuration of the neuron circuit NU. The neuron circuit NU can function as an input neuron circuit or a hidden neuron circuit. The neuron circuit NU includes an amplifier 101, a selection circuit 102, a differential amplifier 103, a switch 104, and a resistor 105.

  When the neuron circuit NU is caused to function as an input neuron circuit, the switching signal (IN? In the figure) of the selection circuit 102 is switched to the “1” side. The neuron circuit NU that functions as an input neuron circuit is a circuit that generates an output signal x from the input signal i from the outside of the semiconductor device via the selection circuit 102 and the amplifier 101 to the synapse circuit SU in the same module.

  The selection circuit 102 is preferably configured to input and output an analog signal. For example, it can be composed of a pass transistor and an analog switch.

  The amplifier 101 illustrated in FIG. 2A can be configured as a unity gain buffer 106 as illustrated in FIG. 2C, the amplifier circuit 107 may be used to change the reference signal level of the output signal x. Further, as illustrated in FIG. 2D, a buffer 108 that generates a differential signal may be used to generate a differential signal pair (x and xb) as an output signal. Further, when an input signal i having sufficient driving capability is given, it is not always necessary to mount the amplifier 101.

  On the other hand, when the neuron circuit NU is caused to function as a hidden neuron circuit, the switching signal (IN? In the figure) of the selection circuit 102 is switched to the “0” side. The neuron circuit NU that functions as a hidden neuron circuit outputs an input signal i output from the synapse circuit SU of the module in the previous layer to the synapse circuit SU of a different module via the differential amplifier 103, the selection circuit 102, and the amplifier 101. A signal x is generated.

When the input signal i is an output signal of the synapse circuit SU, the input signal i is a signal corresponding to the sum of currents of each synapse circuit SU (= Σw [i, j] x [j]). Converting the sum of the current in resistor 105 to a voltage, it generates a differential voltage between the threshold voltage theta _N in the differential amplifier 103.

  A signal for controlling on / off of the switch 104 (Ri? In the figure) is to turn on the switch 104 by the signal Ri when the neuron circuit NU functions as a hidden neuron circuit, and to turn off the switch 104 in other periods. What is necessary is just to set.

The output signal of the differential amplifier 103 has a characteristic that becomes f _H (X) in Expression (1) when the input signal X is a variable, or a characteristic that can be approximated to the characteristic.

In Expression (1), α _H is an arbitrary constant and corresponds to the rate of change of the output signal when X = θ _N. Is the sum of the current of the synapse circuit Σw [i, j] x when [j] exceeds a threshold voltage theta _N, the output signal _f H (X) = 1, i.e. H level ( "H" or high level, This is expressed as that the neuron circuit NU fires. That is, the threshold voltage theta _N is equivalent to the threshold when the neuron circuit NU fires.

  If it is not necessary to use all n neuron circuits NU in the module, the input signal i of the unnecessary neuron circuit NU may be set to “0”. In this case, the output signal x of the neuron circuit NU is also “0”, and the subsequent synapse circuit SU does not function effectively.

  FIG. 3 shows a configuration of the synapse circuit SU. The synapse circuit SU includes an analog memory AM and multiplication circuits MUL1 to MUL3.

  The analog memory AM has a function of storing data corresponding to the coupling strength (weighting factor) w between the neuron circuit NU of the module and the neuron circuit NU of the module in the subsequent stage, and outputting a corresponding voltage.

  The multiplication circuit MUL1 multiplies the output signal x of the neuron circuit NU of the same module by the weight coefficient w of the analog memory AM, and generates an output signal wx. A current corresponding to the multiplication result is supplied as the output signal wx. That is, the output signal wx weighted to the output signal x from the neuron circuit NU of the same module according to the data of the analog memory AM is output to the neuron circuit NU of the module in the subsequent layer and the error circuit EU of the module.

  The multiplication circuit MUL2 multiplies the output signal x of the neuron circuit NU of the same module with the output signal d of the error circuit EU of the same module, and generates an output signal dw. A current corresponding to the multiplication result is supplied as the output signal dw. The output signal dw is supplied as a current corresponding to a change in the weighting factor w stored in the analog memory AM. That is, the data in the analog memory AM is updated according to the error signal d from the error circuit EU of the same module.

  The multiplication circuit MUL3 multiplies the output signal d of the error circuit EU of the module and the weighting factor w of the analog memory AM to generate an output signal wd. A current corresponding to the multiplication result is supplied as the output signal wd. That is, the error signal wd weighted to the error signal d from the error circuit EU of the same module according to the data of the analog memory AM is output to the error circuit EU of the module in the previous stage.

  FIG. 4 shows the configuration of the error circuit EU. The error circuit EU can function as an output neuron circuit or a hidden error circuit. The error circuit EU includes a differential amplifier 111, a switch 112, a resistor 113, a differentiation circuit DV, a multiplication circuit MUL4, a selection circuit 114, a differential amplifier 115, a switch 116, and a resistor 117.

  When the error circuit EU is caused to function as an output neuron circuit, a signal to be output is switched to the “1” side by a switching signal (ON? In the figure) of the selection circuit 114. The error circuit EU functioning as an output neuron circuit generates a signal o to the outside of the semiconductor device from the signal Σwx corresponding to the sum of currents by the output signal wx from the synapse circuit SU in the same layer by the differential amplifier 111. When the error circuit EU functions as an output neuron circuit, the differential amplifier 115 generates a differential signal (eo) between the teacher signal e and the signal o given from the outside of the semiconductor device. Further, when the error circuit EU functions as an output neuron circuit, a differential coefficient f 'for the signal o is generated by the differential circuit DV. Further, the multiplication circuit MUL4 generates an error signal d by multiplying the differential coefficient f 'by the difference signal (eo). The error signal d is output to the synapse circuit SU of the same module. When the teacher signal e is given as a voltage, a signal for controlling on / off of the switch 116 (Re? In the figure) is set so that the switch 116 is turned off.

Further, in the differential amplifier 111, converted into a voltage by the output signal Σwx the resistor 113 corresponding to the sum of the currents from the synapse circuit SU of the same layer, and generates a differential voltage between the threshold voltage theta _O.

The signal o of the differential amplifier 111 has a characteristic that becomes f _O (X) in Expression (2) when the input signal X is a variable, or a characteristic that can be approximated to the characteristic.

In Expression (2), α _O is an arbitrary constant and corresponds to the rate of change when X = θ _O. When the output signal Σwx exceeds the threshold voltage θ _O , the output signal f _O (X) = 1, that is, the H level, which is expressed as the output neuron circuit EU fires. That is, θ _O corresponds to a threshold value when the output neuron circuit EU fires.

  On the other hand, when the error circuit EU functions as a hidden error circuit, the output signal is switched to the “0” side by the switching signal (ON? In the figure) of the selection circuit 114. The error circuit EU functioning as a hidden error circuit generates a signal o in the same manner as the error circuit EU functioning as an output neuron circuit. Specifically, the differential amplifier 111 generates a signal o from a signal Σwx corresponding to the sum of currents based on the output signal wx from the synapse circuit SU in the same layer. Further, when the error circuit EU functions as a hidden error circuit, it is given as a current sum teacher signal e by the error signal wd from the synapse circuit SU of the module in the subsequent layer, and a differential signal is generated by the differential amplifier 115.

Here, the teacher signal e is a signal Σw [i, j] d [i] corresponding to the sum of the currents w [i, j] d [i]. This signal is converted into a voltage by the resistor 117, and is referred to. generating a difference signal as a differential voltage between the voltage theta _E. Further, the differential coefficient f ′ for the signal o is generated by the differentiating circuit DV. Further, the multiplication circuit MUL4 generates an error signal d by multiplication of the differential coefficient f ′ and the difference signal. The error signal d is output to the synapse circuit SU of the same module.

  When one layer is composed of a plurality of modules, the signal Σwx of the synapse circuit SU in the module in the preceding layer is the input signal of the neuron circuit NU that functions as a plurality of hidden neuron circuits in the plurality of modules, and a plurality of signals in the preceding layer It becomes an input signal of the error circuit EU that functions as a plurality of error circuits in this module. In this case, the input signal i is converted into a voltage by the resistor 105 in any one of the plurality of hidden neuron circuits, or the input signal Σwx is converted into a voltage in the resistor 113 by any one of the plurality of error circuits. That's fine. A signal for controlling on / off of the switch 112 (RΣwx? In the figure) can be set so that the switch 112 is turned on when the error circuit EU functions as a hidden error circuit and is turned off during other periods. Good.

  When one layer is composed of a plurality of modules, the error signal wd of the synapse circuit SU in the module in the subsequent layer becomes the teacher signal e of the error circuit EU functioning as a plurality of hidden error circuits in the plurality of modules. In this case, the teacher signal e may be converted into a voltage by the resistor 117 in any one of the plurality of error circuits EU. That is, a signal (Re? In the figure) for controlling on or off of the switch 116 turns on the switch 116 when the error circuit EU functions as a hidden error circuit, and turns off the switch 116 in other periods. It should be set as follows.

<Configuration of each circuit constituting the module>
FIG. 5 shows a configuration of a multiplication circuit MUL applicable to the multiplication circuits MUL1 to MUL4 in the synapse circuit SU and the error circuit EU. The multiplication circuit MUL includes a first transistor Tr01 to a fourteenth transistor Tr14, a capacitive element C0, and a capacitive element C1. The multiplier circuit has a configuration in which a Chimble multiplier circuit is applied, and a current proportional to the product of the potential of the input signal A and the potential of the input signal B is obtained as the output signal Y. Note that if the capacitive element C0 and the capacitive element C1 are sufficiently larger than the gate capacitances of the eighth transistor Tr08 and the eleventh transistor Tr11, the potential change of the input signal B is multiplied by C1 / (C0 + C1) to be the eighth. To the gates of the transistor Tr08 and the eleventh transistor Tr11. Therefore, the input range of the input signal B can be increased, and the linearity of the multiplication circuit MUL can be maintained over a wide input range. Similarly, by providing a capacitance element for the input signal A, the linearity of the multiplication circuit MUL can be maintained for the input signal A over a wide input range.

FIG. 6 shows the configuration of the differentiating circuit DV in the error circuit EU. The differentiation circuit DV is composed of an OP amplifier 121, an OP amplifier 122, and a multiplication circuit MUL. Here, the OP amplifier 121 has a characteristic that the output signal Y ₁ = f (X) = 1 / (1 + e ^−αX ) with respect to the difference X = A−Vref between the non-inverted input signal A and the inverted input signal Vref. Or it shall have the characteristic which can approximate the said characteristic. Further, the OP amplifier 122 outputs the output signal Y ₂ = f (X ₂ ) = 1 / (1 + e− ^αX ₂ ) with respect to the difference X ₂ = Vref−A = −X between the non-inverted input signal Vref and the inverted input signal A. Or a characteristic that can be approximated to the characteristic. Here, Y ₂ = f (−X) = 1 / (1 + e ^{+ αX} ) = e ^−αX / (e ^−αX +1) = 1−1 / (1 + e ^−αX ) = 1−f (X). Therefore, the output of the multiplication circuit MUL is Y = Y ₁ .Y ₂ = f (X) (1−f (X)) = f ′ (X) (= df (X) / dX). That is, it can be seen that a differentiation circuit of f (X) can be realized.

  FIG. 7 shows a configuration of the analog memory AM in the synapse circuit SU. The analog memory AM includes a transistor Tr15 and a capacitive element C. An ideal analog memory can be formed by using the transistor Tr15 as an oxide semiconductor that has an extremely low off-state current. Accordingly, there is no need to mount a large-scale capacitor element for storing data, and there is no need to restore analog data by a periodic refresh operation, so that the chip area and power consumption can be reduced. . Note that since the current corresponding to the changed amount is supplied when the data is updated, the data change amount can be changed by adjusting the period during which the signal line WL is set to “H”.

<3-layer neural network>
Now, a three-layer neural network using two modules 100 shown in FIG. 1 as a semiconductor device, that is, a neural network having an input layer, a hidden layer, and an output layer will be described. In addition, learning of the neural network will be described. To do. FIG. 17 shows a three-layer neural network using the first module 100_1 and the first module 100_2. The neuron circuit NU of the first module 100_1 is an input neuron circuit, the error circuit EU of the first module 100_1 is a hidden error circuit, the neuron circuit NU of the second module 100_2 is a hidden neuron circuit, and the error circuit of the second module 100_2 Let EU be the output neuron circuit. The output signal of the synapse circuit SU of the first module 100_1 is the input signal of the neuron circuit NU of the second module 100_2, and the error signal of the synapse circuit SU of the second module 100_2 is the input of the error circuit EU of the first module 100_1. Signal.

  In the three-layer neural network, the synapse circuit SU of the first module 100_1 can obtain desired signals O [1] to O [n] with respect to the input signals I [1] to I [n]. Data corresponding to the weighting factor w1 [j, i] (j and i are natural numbers) and the weighting factor w2 [k, j] (k is a natural number) of the synapse circuit SU of the second module 100_2 are stored in each analog memory AM. To do is equivalent to learning. More specifically, an arbitrary value is given as an initial value to the weighting coefficients w1 [j, i] and w2 [k, j], and input data used for learning is input to the input signals I [1] to I [ n], a teacher signal as an output expected value is given to the input signals E [1] to E [n] of the output neuron circuit, and the signals O [1] to O [n] of the output neuron circuit and the input signals E [1] to E [1] to Convergence to weighting coefficients w1 [j, i] and w2 [k, j] that minimize the sum of square errors with E [n] corresponds to learning.

  The sum of square errors of the output neuron circuit signals O [1] to O [n] and the input signals E [1] to E [n] can be expressed by Expression (3).

  When e2 [k] = E [k] −O [k], Expression (3) can be written as Expression (4).

  The minimum value of the square error sum is determined by the gradient method, which is the local minimum value for the weighting factors w1 [j, i] and w2 [k, j], that is, w1 that satisfies the expressions (5) and (6). This corresponds to obtaining [j, i] and w2 [k, j].

  That is, this corresponds to updating the weighting factors w1 [j, i] and w2 [k, j] in accordance with the value on the left side of the equations (5) and (6).

  Here, the weighting coefficient w2 [k, j] has the relationship of Expression (7).

In Equation (7), Y = α ₀ (Σw2 [k, j] x2 [j] −θ ₀ ). Therefore, the weighting coefficient w2 [k, j] only needs to be changed by an amount corresponding to _ηw2 · e2 [k] · f ′ (Y) · x2 [j]. Note that η _w2 is a constant.

  Further, the weighting factor w1 [j, i] has the relationship of Expression (8).

In Equation (8), X = α _H (Σw1 [j, i] x1 [i] −θ _H ), Y = α ₀ (Σw2 [k, j] x2 [j] −θ ₀ ). The weighting coefficient w1 [j, i] has a value corresponding to η _w1 · (Σe2 [k] · f ′ (Y) · w2 [k, j]) · f ′ (X) · x1 [i]. You can change it.

In the error circuit EU (output neuron circuit) of the second module 100_2, the differential signal e2 [k] between the teacher signal E [k] and the signal o [k] is acquired by the differential amplifier 115, and the differential signal with respect to the signal Y f ′ (Y) is acquired by the differentiation circuit DV, and the multiplication result d2 [k] = e2 [k] · f ′ (Y) of the difference signal e2 [k] is acquired by the multiplication circuit MUL4. To do. Here, Y = α ₀ (Σw2 [k, j] x2 [j] −θ ₀ ). The signal d2 [k] is an output signal to the synapse circuit SU [k, j] of the second module 100_2.

In the synapse circuit SU [k, j] of the second module 100_2, for the input signal d2 [k] from the error circuit EU [k] of the second module 100_2, dw2 = d2 [k] · x2 [j ] = E2 [k] · f ′ (Y) · x2 [j] by an amount (η _w2 · dw2 = η _w2 · e2 [k] · f ′ (Y) · x2 [j]) corresponding to the analog memory AM Data (weighting coefficient w2 [k, j]) is changed. The output signal w2 [k, j] d2 [k] = e2 [k] · f of the synapse circuit SU [k, j] of the second module 100_2 to the error circuit EU [j] of the first module 100_1. '(Y) · w2 [k, j]. Hereinafter, the output signal w2 [k, j] d2 [k] may be expressed as the output signal w2d2.

The error circuit EU [j] (hidden error circuit) of the first module 100_1 is an output signal w1 [j, i] x1 [i] (current) of the synapse circuit SU [j, i] of the first module 100_1. The signal Σw1 [j, i] x1 [i] which is the sum and w2 [k, j] d2 [k] = e2 [k] which is the output signal of the synapse circuit SU [k, j] of the second module 100_2 A signal Σw2 [k, j] d2 [k] = Σe2 [k] corresponding to the sum of currents represented by f ′ (Y) · w2 [k, j] · f ′ (Y) · w2 [k, j] = e1 [j] as an input signal, the signal X is obtained from the Σw1 [j, i] x1 [i] by the differential amplifier, and the difference signal EX is obtained from the e1 [j] by the differential amplifier 103. Then, the output signal f ′ (X) is obtained from the signal X by the differentiation circuit DV, and the multiplication result d of f ′ (X) and the signal EX is obtained. [J] = e1 [j] · f '(X) = Σe2 [k] · f' (Y) · w2 [k, j] · f '(X) is acquired by multiplying circuit MUL. Here, X = α _H (Σw1 [j, i] x1 [i] −θ _H ). The signal d1 [j] is an output signal to the synapse circuit SU [j, i] of the first module 100_1.

In the synapse circuit SU [j, i] of the first module 100_1, for the input signal d1 [k] from the error circuit EU [j] of the first module 100_1, dw1 = d1 [j] · x1 [i ] = Σe2 [k] · f '(Y) · w2 [k, j] · f' (X) · x1 [ an amount corresponding to _{i] (η w1 · dw1 =} η w1 · Σe2 [k] · f ' (Y) · w2 [k, j] · f ′ (X) · x1 [i]) changes the data (weight coefficient w1 [j, i]) of the analog memory AM. Note that the output signal w1 [j, i] d1 [j] (= wd1) of the synapse circuit SU [j, i] of the first module 100_1 is not output to other modules.

  As described above, the weighting factors w1 [j, i] and w2 [k, j] can be updated in the semiconductor device, and a desired output signal can be obtained with respect to the input signal in the semiconductor device. In addition, data corresponding to the weighting factors w1 [j, i] and w2 [k, j] can be stored in each analog memory AM. That is, the semiconductor device can be learned.

<4-layer neural network>
FIG. 8 shows an example in which the module 100 is combined to form a four-layer neural network as a semiconductor device. Here, the neuron circuits NU of modules U [1,1], U [1,2], U [1,3] are input neuron circuits, modules U [2,1], U [2,2], U [ 3,1], U [3,2], U [4,1], U [4,2] neuron circuit NU as the first hidden neuron circuit, modules U [2,3], U [3,3 ] Is the second hidden neuron circuit, and the error circuit EU is the output neuron circuit. The output signal wx of the synapse circuit SU of the module U [1,1] is used as the input signal I of the neuron circuit NU of the modules U [2,1] and U [2,2], and the synapse circuit SU of the module U [1,2]. Output signal wx of module U [3,1], input signal I of neuron circuit NU of U [3,2], and output signal wx of synapse circuit SU of module U [1,3] are assigned to module U [4,1. ], The input signal I of the neuron circuit NU of U [4,2] and the error signal WD of the synapse circuit SU of the module U [2,3] are converted into the modules U [2,1], U [3,1], U [ 4, 1], and the error signal WD of the synapse circuit SU of the module U [3, 3] is converted into the modules U [2, 2], U [3, 2], U [4, 2]. The input signal E of the error circuit EU.

  Between the modules, wiring groups H [1,1] to H [4,6] and V [1,1] to V [3,6] each composed of a plurality of signal lines are arranged. A programmable switch PS is arranged at the intersection. Here, the circuit configuration of the programmable switch PS is shown in FIG. In FIG. 8, at the intersection where the programmable switch is arranged, when the wiring groups are electrically connected by the programmable switch, a black circle indicating the electrical connection is given.

  The programmable switch PS shown in FIG. 9 includes a transistor Tr16 and a transistor Tr17. When the transistor Tr16 made of an oxide semiconductor is on (signal line WW = “H”), data is transmitted as a gate potential of the transistor Tr17. The data is stored from BL, and the conduction of the transistor Tr17 is controlled in accordance with the data. That is, the conduction state between the wiring V and the wiring H can be programmed.

  In FIG. 8, the input signal of the semiconductor device is input to the input neuron circuits of the modules U [1,1], U [1,2], U [1,3] via the wiring group H [1,3]. The The output of the output neuron circuit of the module U [3, 3] is output as an output signal of the semiconductor device via the wiring group H [3, 6]. The teaching signal of the semiconductor device is input to the output neuron circuits of the modules U [2, 3] and U [3, 3] via the wiring groups H [4, 4] and V [3, 3].

  The output signal of the synapse circuit SU of the module U [1,1] is transmitted to the neurons of the modules U [2,1] and U [2,2] via the wiring groups V [1,4] and H [2,3]. Input to the circuit NU.

  The output signal of the synapse circuit SU of the module U [1,2] is transmitted to the neurons of the modules U [3,1] and U [3,2] via the wiring groups V [2,4] and H [3,3]. Input to the circuit NU.

  The output signal of the synapse circuit SU of the module U [1,3] is transmitted to the neurons of the modules U [4,1] and U [4,2] via the wiring groups V [3,4] and H [4,3]. Input to the circuit NU.

  The output signals of the synapse circuits SU of the modules U [2,1], U [3,1], U [4,1] are sent to the module U via the wiring groups V [1,5] and H [2,2]. The signal is input to the neuron circuit NU of [2, 3].

  The output signal of the synapse circuit SU of the modules U [2, 2], U [3, 2], U [4, 2] is sent to the module U through the wiring groups V [2, 5], H [3, 2]. The signal is input to the neuron circuit NU of [2, 3].

  Output signals of the synapse circuits SU of the modules U [2, 3] and U [3, 3] are shared by the wiring group V [3, 5].

  The error signal of the synapse circuit SU of the module U [2, 3] is transmitted to the modules U [2, 1], U [3, 1], U via the wiring groups H [2, 4] and V [1, 3]. [4, 1] is input to the error circuit EU.

  The error signal of the synapse circuit SU of the module U [3, 3] is transmitted to the modules U [2, 2], U [3, 2], U via the wiring groups H [3,4], V [2, 3]. [4, 2] is input to the error circuit EU.

  The error signal of the synapse circuit SU of the modules U [2,1] and U [2,2] is the error of the module U [1,1] via the wiring groups H [2,5] and V [1,2]. Input to the circuit EU.

  The error signal of the synapse circuit SU of the modules U [3, 1] and U [3, 2] is the error of the module U [1, 2] via the wiring groups H [3, 5] and V [2, 2]. Input to the circuit EU.

  The error signal of the synapse circuit SU of the modules U [4,1] and U [4,2] is the error of the module U [1,3] via the wiring groups H [4,5] and V [3,2]. Input to the circuit EU.

  In the semiconductor device, learning data is given as an input signal of the input neuron circuit, a teacher signal corresponding to the learning data is given as an input signal of the output neuron circuit, and learning is performed by updating the data in the analog memory according to the error signal. To do. By learning, when the target data is given as an input signal of the input neuron circuit, it is possible to determine whether the target data and the learning data match or are similar. Here, by using the data of a target object (moving body) in the image data as learning data, the object can be detected in the image data. That is, it is possible to perform efficient pattern extraction of a moving object from image data, to efficiently perform motion compensation prediction, and to record a recording signal with a reduced amount of broadcast signal data using the semiconductor device, And an electronic device can be provided.

  In the configuration of the semiconductor device described above, the number of neurons, the number of neurons in the same layer, etc., in order to efficiently extract a moving body pattern according to image data or to accommodate more patterns, etc. The hierarchical structure can be changed freely.

(Embodiment 2)
In this embodiment, an operation example of the semiconductor device in FIG. 1 is described. Here, the operation of the three-layer neural network using the modules 100_1 and 100_2 illustrated in FIG. 17 will be described as the operation of the semiconductor device. That is, the neuron circuit NU of the first module 100_1 is an input neuron circuit, the error circuit EU of the first module 100_1 is a hidden error circuit, the neuron circuit NU of the second module 100_2 is a hidden neuron circuit, and the second module 100_2 is A selection circuit is set so that the error circuit EU is an output neuron circuit. The output signal of the synapse circuit SU of the first module 100_1 is the input signal of the neuron circuit NU of the second module 100_2, and the error signal of the synapse circuit SU of the second module 100_2 is the input of the error circuit EU of the first module 100_1. Signal.

<Operation example>
The operation of the semiconductor device means that learning data is input to the semiconductor device described with reference to FIG. 1 in the above embodiment, the learning data is learned to the semiconductor device, and then the target data is input to the semiconductor device. This refers to the time until the data and the target data are determined to be identical, similar, or inconsistent. 10 and 11 are flowcharts showing the operation of the semiconductor device.

<< Learning >>
First, an operation in which the semiconductor device in FIG. 1 learns data will be described with reference to FIGS.

[Step S1-1]
In step S1-1, learning data is input to the input neuron circuit, that is, the neuron circuit NU of the first module 100_1 from the outside. The learning data corresponds to the input signals I [1] to I [n] shown in FIG. The learning data here is data expressed in binary numbers, and the number of input neuron circuits NU is determined according to the number of bits of the learning data. The neuron circuit NU that is not necessary for inputting the learning data is preferably configured to input data whose output signal x is a fixed value. Further, it is preferable to apply a configuration such as cutting off the supply of power to the neuron circuit NU. Here, the amount of learning data is described as n bits. It is assumed that learning data I [1] to I [n] are input to neuron circuits NU [1] to NU [n], respectively.

[Step S1-2]
In step S1-2, the output signal x is input from the input neuron circuit, that is, the neuron circuit NU of the first module 100_1 to the synapse circuit SU of the first module 100_1. The synapse circuit SU of the first module 100_1 uses an output signal w1x obtained by multiplying the output signal x by the weighting coefficient w1 held in the analog memory AM, and a hidden error circuit, that is, the error circuit EU of the first module 100_1, and the hidden module. The data is output to the neuron circuit, that is, the neuron circuit NU of the second module 100_2.

[Step S1-3]
In step S1-3, Σw1x that is the sum of the output signals of the synapse circuit SU of the first module 100_1 is input to the hidden neuron circuit, that is, the neuron circuit NU of the second module 100_2.

  Note that the number of hidden neuron circuits, that is, the number of neuron circuits NU of the second module 100_2 can be changed according to the learning data. It is preferable to input data for which the output signal x is a fixed value to the neuron circuit NU that is not necessary. Further, it is preferable to apply a configuration such as cutting off the supply of power to the neuron circuit NU. Here, the number of neuron circuits NU of the second module 100_2 is m, and input values of the neuron circuits NU are described as Σw1x [1] to w1x [m].

[Step S1-4]
In step S1-4, the output signal x2 is input from the hidden neuron circuit, that is, the neuron circuit NU of the second module 100_2 to the synapse circuit SU of the second module 100_2. The output signal x2 corresponds to the output signal x in FIG. The synapse circuit SU of the second module 100_2 outputs an output signal w2x2 obtained by multiplying the output signal x2 by the weighting factor w2 held in the analog memory AM to the output neuron circuit, that is, the error circuit EU of the second module 100_2. . The weight coefficient w2 is a weight coefficient held in the analog memory AM of the synapse circuit SU of the second module 100_2.

[Step S1-5]
In step S1-5, Σw2x2 is input to the output neuron circuit, that is, the error circuit EU of the second module 100_2. Σw2x2 corresponds to Σwx in FIG.

[Step S1-6]
The error circuits EU [1] to EU [m] perform multiplication based on Σw2x2 and the external teacher signal e, and output a differential signal d2 to the neuron circuit NU of the second module 100_2. The difference signal d2 corresponds to d [1] to d [m] in FIG. The teacher signal e corresponds to the input signals E [1] to [n] input to the error circuits EU [1] to EU [n] of the second module.

[Step S1-7]
In step S1-7, the weighting coefficient w2 held in the analog memory AM in the synapse circuit SU of the second module 100_2 is updated based on the difference signal d2. In step S1-7, the weighting factor w2 updated in the synapse circuit SU of the second module 100_2 is multiplied by the difference signal d2, and the output signal w2d2 is output. The output signal w2d2 becomes input signals E [1] to E [n] that are output to the hidden error circuit, that is, the error circuit EU of the first module 100_1.

[Step S1-8]
In step S1-8, multiplication is performed based on Σw1x which is the sum of the output signals and the output signal w2d2, and the difference signal d1 is output to the neuron circuit NU of the first module 100_1. The difference signal d1 corresponds to d [1] to d [m] in FIG.

[Step S1-9]
In step S1-9, the weighting coefficient w held in the analog memory AM in the synapse circuit SU of the first module 100_1 is updated based on the difference signal d1. Thereafter, Steps S1-2 to S1-9 are repeated a predetermined number of times based on the updated weighting factors w1 and w2.

[Step S1-10]
In step S1-10, it is determined whether or not steps S1-2 to S1-9 are repeated a predetermined number of times. When the predetermined number of times is reached, the learning for the learning data is terminated.

  The predetermined number of times here is ideally set so as to be repeated until the error between the output signal o and the teacher signal e in the error circuit EU of the second module falls within a specified value. The number of times determined in the above may be used.

[Step S1-11]
In step S1-11, it is determined whether or not learning has been performed on all learning data. If there is unfinished learning data, steps S1-1 to S1-10 are repeated, and if learning has been completed for all the learning data, the process is terminated. In addition, about the learning data once learned, it is good also as a structure which learns again after the learning with respect to all the learning data is completed.

  In a neural network having a hierarchical perceptron architecture, it is preferable to provide multiple hidden layers. When the hidden neuron circuit and the synapse circuit corresponding to the hidden layer are provided in multiple layers, the weighting coefficient can be updated repeatedly, so that the learning efficiency can be improved.

<< Comparison >>
Next, an operation of inputting target data and outputting a result to the semiconductor device of FIG. 17 in which data has been learned first will be described with reference to FIG. Of the plurality of data learned here, the data associated with the closest to the target data is output as a result.

[Step S2-1]
In step S2-1, target data is input from the outside to the input neuron circuit, that is, the neuron circuit NU of the first module 100_1.

[Step S2-2]
In step S2-2, the output signal x corresponding to the target data is input from the neuron circuit NU of the first module 100_1 to the synapse circuit SU of the first module 100_1. The synapse circuit SU of the first module 100_1 uses the output signal w1x obtained by multiplying the output signal x by the weighting factor w1 held in the learning step S1-9, and the hidden neuron circuit, that is, the neuron circuit NU of the second module 100_2. Output to.

[Step S2-3]
In step S2-3, Σw1x, which is the sum of the output signals of the synapse circuit SU of the first module 100_1, is input to the hidden neuron circuit, that is, the neuron circuit NU of the second module 100_2.

[Step S2-4]
In step S2-4, the output signal x2 is input from the hidden neuron circuit, that is, the neuron circuit NU of the second module 100_2 to the synapse circuit SU of the second module 100_2. The synapse circuit SU of the second module 100_2 outputs an output signal w2x2 obtained by multiplying the output signal x2 by the weighting factor w2 held in the analog memory AM to the output neuron circuit, that is, the error circuit EU of the second module 100_2. .

[Step S2-5]
In step S2-5, Σw2x2, which is the sum of the output signals of the synapse circuit SU of the second module 100_2, is input to the output neuron circuit, that is, the error circuit EU of the second module 100_2. The output neuron circuit, that is, the error circuit EU of the second module 100_2 outputs an output signal o.

  Here, when there is data that matches or is very close to the data included in the output signal o that is output from among the plurality of learned data, the data included in the output signal o learns the learning data. This is the data given as a teacher signal when That is, it is possible to determine whether the learning data and the target data match (including similarity) or mismatch.

  By performing the above steps S1-1 to S1-10 and steps S2-1 to S2-5, the semiconductor device in FIG. 1 learns the learning data, and then whether the learning data and the target data match. A signal indicating whether there is a mismatch can be output. Thereby, the semiconductor device of FIG. 1 can perform processes such as pattern recognition and associative memory.

(Embodiment 3)
In this embodiment, an operation example in the case where the semiconductor device in FIG. 1 described in Embodiment 1 is used as an encoder will be described.

<Example of motion detection>
First, an example of a method for detecting the movement of an object will be described. FIG. 12 illustrates an algorithm for object motion detection executed by an encoder on image data.

  FIG. 12A shows the image data 10, and the image data 10 has a triangle 11 and a circle 12. FIG. 12B shows the image data 20, and the image data 20 is image data in which the triangle 11 and the circle 12 included in the image data 10 are moved in the upper right direction.

  Image data 30 in FIG. 12C shows an operation of extracting a region 31 including the triangle 11 and the circle 12 from the image data 10. The image data 30 is attached to the image data 10 with the upper left cell of the extracted region 31 as a reference (0, 0) and numerical values indicating the positions in the horizontal direction and the vertical direction as subscripts. Here, the region 31 extracted in FIG. 12C is shown in FIG.

  The image data 40 in FIG. 12D shows an operation of cutting out one area from the image data 20 and extracting a plurality of areas 41. The image data 40 is obtained by adding numerical values indicating the horizontal and vertical positions attached to the image data 30 to the image data 20. That is, the position where the region 31 has moved from the image data 30 and the image data 40 can be represented by a transition (movement vector). FIG. 12F shows a part of the extracted plurality of regions 41.

  After the operation of extracting a plurality of regions 41, an operation of sequentially comparing the region 31 with the plurality of regions 41 is performed in order to detect the motion of the object. By this operation, it is detected that the region 31 and the region 41 of the movement vector (1, -1) match, and the region 31 and the region 41 other than the movement vector (1, -1) do not match. Detect that Thereby, the movement vector (1, −1) from the region 31 to the region 41 can be acquired.

  In the present specification, the data in the region 31 described above may be expressed as learning data, and the data in the plurality of regions 41 described above may be expressed as target data.

  In FIG. 12, extraction, comparison, and detection operations are performed in a 4 × 4 region. However, in this operation example, the size of the region is not limited to this. The area may be changed as appropriate according to the size of the image data to be extracted. For example, the extraction, comparison, and detection operations may be performed in a 3 × 5 region. Further, the number of pixels forming the cell is not limited, and for example, 10 pixels × 10 pixels may be defined as one cell, or one pixel may be defined as one cell to constitute a region. For example, the region may be configured by defining 5 pixels × 10 pixels as one cell.

  Depending on the content of the video, the image data included in the region 31 may change. For example, the triangle 11 or the circle 12 included in the region 31 may be enlarged or reduced in the image data 40. Further, for example, the triangle 11 or the circle 12 included in the region 31 may be rotated in the image data 40. In this case, in a configuration effective for comparison between the region 31 and the plurality of regions 41, an external output signal when each region is input is detected in order to detect how much each region matches. The shift (movement vector) when the difference between these external output signals is calculated is detected. For this purpose, it is preferable that the region 31 and the plurality of regions 41 be configured to confirm that the objects are the same by feature extraction or the like. Note that motion compensation prediction can be performed by generating image data in which the region 31 is moved in the direction of the movement vector from the image data of the region 31 and acquiring the difference between the image data and the plurality of regions 41. Further, when the amount of movement of the image data in the region 31 does not match an integer multiple of the pixel pitch, each external output signal is calculated by comparing the region 31 and the plurality of regions 41, and the difference between these external output signals is minimized. It is possible to adopt a configuration in which a shift that becomes is detected and detected as a shift (movement vector) of an object.

<Determining whether image data matches, is similar, or does not match>
Next, a motion compensation prediction method using an encoder will be described with reference to FIG.

[Step S3-1]
In step S3-1, the data in the region 31 is input as learning data to the neuron circuit NU in the first module.

[Step S3-2]
In step S3-2, the same operation as in steps S1-2 to S1-10 is performed on the input data in the region 31. That is, the updating of the respective weighting factors is repeated for all the synapse circuits SU, and the weighting factors of the synapse circuits SU corresponding to the data in the region 31 are updated.

[Step S3-3]
In step S3-3, one of the plurality of areas 41 is input as target data to the semiconductor device of FIG. 1 having the weighting coefficient updated in step S3-2.

[Step S3-4]
In step S3-4, the same operation as that in steps S2-2 to S2-5 is performed on one piece of input data in the plurality of areas 41. That is, associative data is output by inputting one data of the plurality of regions 41 to the semiconductor device that has learned the data of the region 31.

  Here, it is determined whether the data in the region 31 and one of the plurality of regions 41 match or do not match.

[Step S3-5]
In step S3-5, it is determined which step to proceed according to the above determination result.

  In the determination result, when the data of the region 31 and one of the plurality of regions 41 do not match, the region 41 other than the one of the plurality of regions 41 is set as the target data, and steps S3-3 and S3-4 are performed. Is performed again.

  In addition, when the data of the region 31 matches one of the plurality of regions 41 in the determination result, one movement vector of the plurality of regions 41 with respect to the region 31 is acquired, and this operation ends. By acquiring the movement vector, motion compensated prediction using the movement vector as a difference becomes possible. By performing motion compensation prediction, video data can be efficiently compressed.

  Also, when the data in the region 31 and one of the plurality of regions 41 are similar, the determination result is the same. In addition, when the data of the plurality of areas 41 are similar to the data of the plurality of areas 41, it is determined that the data of the plurality of areas 41 and the data of the plurality of areas 41 match. In this case, by determining the degree of coincidence with the plurality of regions 41, the displacement of the object is estimated, and this is acquired as the movement vector of the object. Thereafter, this operation ends.

  Further, based on the determination result, the data of all the regions 41 are compared as the target data, and when the learning data and all the target data do not match or are not similar, the data of the region 31 and the data This operation ends when it is determined that a motion vector for performing motion compensation prediction cannot be obtained from the data in the area 41.

  By performing the above operation, a neural network having a hierarchical perceptron architecture can be used as an encoder for compressing video data. As a result, a highly efficient encoder capable of compressing a large amount of image data can be realized.

(Embodiment 4)
In this embodiment, a recording device in the case where the semiconductor device including the module in FIG. 1 described in Embodiment 1 is used as an encoder, and a configuration of the encoder included in the recording device will be described.

  FIG. 14 shows a block diagram of the recording apparatus 200. In FIG. 14, in addition to the recording apparatus 200, a tuner 201, an STB 202 (set top box), an external input device 205, a video / audio display unit 214, and a remote controller 215 are illustrated.

  The recording apparatus 200 includes a signal input unit 203, a switching unit 204, an encoder 206, an HDD 207 (hard disk drive), a switching unit 208, a disk drive 209, a playback unit 210, a decoder 211, a switching unit 212, a video / audio output unit 213, a light receiving unit. A unit 216, an I / F 217 (interface), and a control unit 218.

In FIG. 14, an antenna (not shown) receives broadcast radio waves (which can be a terrestrial wave or a satellite signal wave, or can be used as a cable broadcast receiver such as a cable TV), and outputs it to the tuner 201. The tuner 201 extracts and demodulates a signal of a channel desired to be received from the broadcast radio wave, and outputs a broadcast signal. The STB 202 (set top box) converts the broadcast signal output from the tuner 201 into data that can be viewed on a television and outputs the data. For example, when image data or audio data is compression-encoded, it is decoded and expanded, and when data broadcasting is used, the data is added. Data (first data) converted from broadcast radio waves via the antenna is input from the signal input unit 203 to the recording device 200. Data can be input not only from the broadcast radio wave via the antenna but also from the external input device 205. As the external input device 205, for example, cable broadcasting or external media (reproducing device, information terminal, etc.) can be considered. Either the first input data or the data input from the external input (second data) is selected by the switching unit 204 (external input data D _BE ).

The external input data V _BE is compressed by the encoder 206 and stored in the HDD 207 as compressed data D _AE with a reduced data amount. Here, a configuration using an encoder 206 that uses the semiconductor device for motion detection is preferable. Note that, unlike data compression used at the time of transmission of a broadcast signal that requires real-time performance, it is possible to use a data compression method that takes time. Therefore, it is preferable to use the above method that can accurately perform motion detection.

Compressed data stored in the HDD 207 (first compressed data) and compressed data stored in a disk drive 209 such as a DVD (Digital Versatile Disc) or Blu-ray disc (second compressed data, media using the playback unit) Is selected by the switching unit 208, and the selected compressed data _DBD is decompressed by the decoder 211 (internal reproduction data D _AD ).

Either the external input data D _BE or the internal reproduction data D _AD is selected by the switching unit 212 and output to the video / audio display unit 214 (such as a television) via the video / audio output unit 213.

  The switching units 204, 208, and 212 can be configured to generate from signals input by the user using the remote controller 215. Infrared light or the like output from the remote controller 215 is received by the light receiving unit 216, taken as an electrical signal via the I / F 217, and generated as a control signal by the control unit 218 using a microcomputer or the like.

FIG. 15 illustrates a block diagram of the encoder 206. The encoder 206 in FIG. 15 has a function of generating a compressed data _{D AE} from the external input data _{D BE.}

  The encoder 206 includes a block division circuit 221, a DCT (discrete cosine transform) quantization circuit 222, an entropy encoding circuit 223, a local decoder 230, and a motion detection circuit 228. The local decoder includes an inverse DCT inverse quantization circuit 224, an in-loop filter 225, an in-screen prediction circuit 226, a motion compensation circuit 227, and a switching unit 229.

In FIG. 15, an encoder 206 generates block data by dividing a block of an image signal (external input data D _BE ) by a block dividing circuit 221 (dividing the block into compression blocks). The block data is quantized by the DCT quantization circuit 222 by orthogonal transform and quantization (discretizes pixel values) such as DCT (discrete cosine transform) and DST (discrete sine transform) according to the block size. Is generated. Thereafter, the entropy encoding circuit 223 generates an encoded signal (compressed data D _AE ) by entropy encoding (reduces redundancy using statistical properties). Note that the compression rate can be improved by performing orthogonal transformation and quantization on the difference between the local decoded data subjected to the local decoding process and the block data in the local decoder 230 for the quantized data. it can.

  Here, in the local decoding process performed by the local decoder 230, the inverse DCT inverse quantization circuit 224 performs inverse quantization and inverse orthogonal transform on the quantized data to generate inverse quantized data. Then, the intra-quantity prediction circuit 226 or the motion compensation circuit 227 applies correction to the inverse quantized data by intra-screen (intra) prediction and motion compensation. In the in-screen prediction circuit 226, in-screen (intra) prediction is effective when the pixel value can be estimated from the pixel values of adjacent pixels, for example, when the in-plane change is slow. In the motion compensation circuit 227, motion compensation can be used when a moving object is detected by motion detection in the motion detection circuit 228. Since it is necessary to detect an object with high accuracy, a configuration using the semiconductor device described above is effective. For the purpose of correcting discontinuity at the boundary due to blocking, a configuration using an in-loop filter (deblocking filter) in the in-loop filter 225 is also effective. Data corresponding to intra prediction (intra) prediction and motion compensation in the encoder 206 is added to the encoded signal and transmitted.

FIG. 16 illustrates a block diagram of the decoder 211. In FIG. 16, the decoder 211 has a function of generating internal reproduction data D _AD from the compressed data D _BD .

  The decoder 211 includes an entropy decoding circuit 241, an inverse DCT inverse quantization circuit 242, an in-loop filter 243, an in-screen prediction circuit 244, a motion compensation circuit 245, and a switching unit 246.

In FIG. 16, the encoded signal (compressed data D _BD ) input to the decoder 211 is converted into entropy decoded data by the entropy decoding circuit 241 and then inverse quantized and inverse orthogonal transformed by the inverse DCT inverse quantization circuit 242. Thus, it is converted into inverse quantized data, and becomes a decoded image signal (internal reproduction data D _AD ) by deblocking processing by the in-loop filter 243. It should be noted that using the data added to the encoded signal as data corresponding to the intra prediction (intra) prediction and motion compensation in the encoder 206, the intra screen prediction circuit 244 and the motion compensation circuit 245 in the decoder 211 are used. Corrections are made by (intra) prediction and motion compensation.

  With the above configuration, efficient image data compression is possible by efficiently executing motion compensation prediction, and a moving object pattern is efficiently extracted according to the image data. Therefore, in order to cope with more patterns, it is possible to provide a semiconductor device in which the hierarchical structure such as the number of neurons and the number of neurons in the same layer can be freely changed, and an image using the semiconductor device It is possible to provide a video recording apparatus that uses an encoder capable of efficiently performing data compression and records data with a reduced amount of data of a broadcast signal.

(Embodiment 5)
<Configuration of CAC-OS>
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

  The CAC-OS is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.

  Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind selected from the above or a plurality of kinds may be included.

For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.

That, CAC-OS includes a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is the main component region is a composite oxide semiconductor having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

  The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (C Axis Aligned Crystalline) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

  On the other hand, CAC-OS relates to a material structure of an oxide semiconductor. CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

  Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component region, in some cases clear boundary can not be observed.

  In place of gallium, aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are selected. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

  The CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .

  The CAC-OS is characterized in that no clear peak is observed when it is measured using a θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

  In addition, in the CAC-OS, an electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam) has a ring-like region having a high luminance and a plurality of bright regions in the ring region. A point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

Further, for example, in a CAC-OS in an In—Ga—Zn oxide, a region in which GaO _X3 is a main component is obtained by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2} or _{InO X1,} is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.

On the other hand, areas such as _{GaO X3} is the main _component, as compared to the In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component area, it is highly regions insulating. That is, a region containing GaO _X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act in a complementary manner, resulting in high An on-current (I _on ) and high field effect mobility (μ) can be realized.

  In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is optimal for various semiconductor devices including a display.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Additional notes regarding the description of this specification etc.)
The above embodiment and description of each component in the embodiment will be added below.

  The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In addition, in the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined as appropriate.

  Note that the content described in one embodiment (may be a part of content) is different from the content described in the embodiment (may be a part of content) and / or one or more Application, combination, replacement, or the like can be performed on the content described in another embodiment (or part of the content).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part thereof) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

  Further, in the present specification and the like, in the block diagram, the constituent elements are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved over a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

  In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

  In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground voltage (ground voltage), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

  Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.

  Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state where the source and the drain of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source and drain of the transistor can be regarded as being electrically cut off. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

  An example of a mechanical switch is a switch using MEMS (micro electro mechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

  In this specification and the like, the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate overlap, or a channel is formed. This is the distance between the source and drain in the region.

  In this specification and the like, the channel width refers to, for example, a source in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed And the length of the part where the drain faces.

  In this specification and the like, “A and B are connected” includes not only those in which A and B are directly connected but also those that are electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

MUL1 multiplication circuit MUL2 multiplication circuit MUL3 multiplication circuit MUL4 multiplication circuit Tr01 transistor Tr08 transistor Tr11 transistor Tr14 transistor Tr15 transistor Tr16 transistor Tr17 transistor 10 image data 11 triangle 12 circle 20 image data 30 image data 31 area 40 image data 41 area 100 module 100_1 module 100_2 module 101 amplifier 102 selection circuit 103 differential amplifier 104 switch 105 resistor 106 unity gain buffer 107 amplifier circuit 108 buffer 111 differential amplifier 112 switch 113 resistor 114 selection circuit 115 differential amplifier 116 switch 117 resistor 121 OP amplifier 122 OP amplifier 200 Recording device 201 Tuner 202 STB
203 Signal Input Unit 204 Switching Unit 205 External Input Device 206 Encoder 207 HDD
208 switching unit 209 disk drive 210 reproducing unit 211 decoder 212 switching unit 213 video / audio output unit 214 video / audio display unit 215 remote control 216 light receiving unit 218 control unit 221 block division circuit 222 DCT quantization circuit 223 entropy coding circuit 224 inverse DCT inverse Quantization circuit 225 In-loop filter 226 In-screen prediction circuit 227 Compensation circuit 228 Detection circuit 229 Switching unit 230 Local decoder 241 Entropy decoding circuit 242 Inverse DCT inverse quantization circuit 243 In-loop filter 244 In-screen prediction circuit 245 Compensation circuit 246 Switching unit

Claims (5)

A semiconductor device having a function of encoding video data,
The semiconductor device has a plurality of modules and a plurality of programmable switches,
The module includes a neuron circuit, a synapse circuit, and an error circuit,
The neuron circuit has a function capable of switching between a function of an input neuron circuit and a function of a hidden neuron circuit,
The synapse circuit outputs a first multiplication circuit that changes data corresponding to a coupling strength, an analog memory that stores the data, and a second signal that is weighted according to the data. A second multiplication circuit that
The error circuit has a function capable of switching between the function of the output neuron circuit and the function of the hidden error circuit,
The analog memory includes a transistor including an oxide semiconductor in a channel formation region,
The programmable switch is a semiconductor device having a function of switching electrical connection between the modules. In claim 1,
The neuron circuit has a first switching circuit,
The first switching circuit includes:
When functioning as the input neuron circuit, a circuit for amplifying an input signal from the outside and outputting it to the synapse circuit;
When functioning as the hidden neuron, a circuit that converts the current output from the synapse circuit into a voltage and outputs it to a synapse circuit included in another module;
Device having a function of switching between. In claim 1,
The error circuit includes a second switching circuit;
The second switching circuit includes:
When functioning as the output neuron circuit, the current output from the synapse circuit is converted into a voltage and output as an input signal of another module, and a difference signal between a signal output as an input signal of another module and a teacher signal A circuit for outputting to the synapse circuit an error signal obtained by a product of a differential coefficient generated based on a signal output as an input signal of another module and the differential signal;
When functioning as the hidden error circuit, multiplication of a differential coefficient generated based on a signal obtained by converting the current output from the synapse circuit into a voltage and a signal obtained by the difference between the teacher signal and the reference voltage A circuit for outputting an error signal obtained by the signal to the synapse circuit;
Device having a function of switching between. A recording device having a function of storing video data,
A memory device and the semiconductor device according to any one of claims 1 to 3,
The semiconductor device has a function of generating compressed data obtained by compressing the video signal,
The storage device is a recording device having a function of storing the compressed data.   An electronic apparatus having a display unit and the recording device according to claim 4.

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