JP2018072921A - On-vehicle electronic control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute interruption processing corresponding to a load state of a CPU.SOLUTION: As a CPU 4 rewrites a jump destination address stored in a vector table according to a rotational state of an engine, the jump destination address for an interruption factor can be changed according to a load state of the CPU 4 indicated with the rotational state of the engine, and then processing details can be changed according to a situation for the same interruption factor. Consequently, proper interruption processing can be performed according to the load state of the CPU 4, so processing capability of the CPU 4 can be utilized more effectively.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an on-vehicle electronic control device.

  Conventionally, in a microcomputer, an interrupt routine executed by a CPU refers to an address value stored in a vector table set in a ROM by an interrupt control circuit installed in the microcomputer when an interrupt occurs, The processing is once saved in the stack area, and the processing at the address indicated by the vector table is performed. Then, when the interrupt process is completed, the CPU resumes from the interrupted process. At this time, the vector table cannot be changed because it exists in the ROM, and a plurality of interrupt processes cannot be set for one interrupt factor.

  On the other hand, an interrupt vector table is provided on the RAM, and the interrupt vector table is rewritten for a program executed by the CPU at that time (see Patent Document 1). In this method, a plurality of interrupt processes are set for one interrupt factor by providing an interrupt vector table at fixed addresses of a startup read-only memory and a readable / writable memory.

Japanese Patent Laid-Open No. 4-29638

  The interrupt control function of the above technique has a POWERON BIT program on the startup ROM and a normal processing program on the ROM, and when receiving an interrupt from external hardware and internal hardware, the startup program and the normal processing program By rewriting the interrupt vector table on the RAM, a plurality of interrupt processes can be set for one interrupt factor.

  However, in the above technique, since the interrupt vector table is rewritten for the program being executed by the CPU at that time, it is necessary for each program to determine which jump destination is to be statically switched. Processing according to the state, that is, the load state of the CPU cannot be performed. For example, when normal processing is entered from a startup program, the interrupt vector table is simply overwritten for normal processing at the end of startup, and the actual situation is that interrupt processing according to the load state of the CPU cannot be executed.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an in-vehicle electronic control device capable of executing an interrupt process according to a load state of a CPU.

  According to the first aspect of the present invention, when an interrupt factor occurs, the interrupt control unit (7) requests the CPU (4) for an interrupt, and sets the address that the CPU (4) is scheduled to execute next. Saved as a suspended address. When receiving an interrupt request, the CPU (4) shifts to the jump destination address stored in the storage unit (6), and shifts to the interrupt address when execution of the interrupt program at the jump destination address is completed. To do.

  Here, when the acquisition unit (4a) acquires a load state that affects the operation of the CPU (4), the scheduler (4b) determines a jump address stored in the storage unit (6) according to the load state. Is changed to the address of the interrupt program for executing the process according to the load state of the CPU (4). Thus, an appropriate interrupt program can be executed according to the load state of the CPU (4), so that the processing capability of the CPU (4) can be utilized more effectively.

Functional block diagram showing the configuration of the engine ECU in the first embodiment Diagram showing the relationship between the jump address of the interrupt vector table and the program Flow chart showing scheduler processing by CPU Flow chart showing interrupt processing by CPU The flowchart which shows the scheduler process by CPU in 2nd Embodiment. The flowchart which shows the scheduler process by CPU in 3rd Embodiment.

(First embodiment)
Hereinafter, a first embodiment applied to an engine ECU that controls a gasoline engine as a vehicle device will be described with reference to FIGS. 1 to 4.

  As shown in FIG. 1, an engine ECU 1 (corresponding to an on-vehicle electronic control device) includes a main microcomputer (hereinafter referred to as a microcomputer) 2 and an external input / output circuit 3 (corresponding to an interrupt control unit). ing. The microcomputer 2 includes a CPU 4, a ROM 5, a RAM 6 (corresponding to a storage unit), an interrupt control circuit 7, a timer 8, and an input / output port 9, and performs various processes for controlling an engine (not shown). The external input / output circuit 3 performs signal input / output processing with an external device for controlling the engine ECU 1.

  Various programs for controlling the engine are stored in the ROM 5, and the CPU 4 controls the engine by executing the various programs stored in the ROM 5. The timer 8 is provided for determining the timing for outputting various pulse signals necessary for controlling the engine. The RAM 6 has an area for temporarily storing operation data used by various programs for processing. In place of the ROM 5 and the RAM 6, a non-transitional tangible recording medium such as a semiconductor memory represented by a hard disk drive or a flash memory may be provided.

  The external input / output circuit 3 includes various actuators for controlling the engine, such as an injector 10, an igniter 11, an electronic throttle 12, a crank sensor 13, a water temperature sensor 14, and a throttle sensor 15, and various sensors for detecting the state of the engine. It is connected. The injector 10 injects fuel into the intake passage of the engine. The electronic throttle 12 adjusts the amount of air flowing through the intake passage of the engine. The igniter 11 ignites an ignition plug (not shown) of the engine.

  The crank sensor 13 outputs an edge as a crank signal at every predetermined angle (for example, every 30 ° CA) according to the rotation of the crankshaft of the engine. The water temperature sensor 14 detects the temperature of engine cooling water. The throttle sensor 15 detects the opening degree of the electronic throttle 12.

  The external input / output circuit 3 shapes the various input signals into digital signals and outputs them to the microcomputer 2. Further, the external input / output circuit 3 has a built-in A / D converter (not shown), inputs analog sensor signals from the water temperature sensor 14 and the throttle sensor 15 and converts them into digital signals using the A / D converter. The data is converted and output to the microcomputer 2.

The interrupt control circuit 7 can input a crank signal from the crank sensor 13 as an interrupt factor, and outputs an interrupt request to the CPU 4 when the crank signal is input.
As shown in FIG. 2, the ROM 5 stores a scheduler program and pattern A to D programs. When the CPU 4 executes the scheduler program, the operations of the acquisition unit 4a and the scheduler 4b shown in FIG. 1 are realized. As will be described later, the scheduler program performs processing (rewriting processing) for rewriting destination addresses stored in the interrupt vector table (hereinafter referred to as vector table) of the RAM 6 to the addresses of the patterns A to D in accordance with the engine rotation state. It is something to execute. In the present embodiment, the patterns A to D are shown as programs for controlling the engine for the sake of simplicity of explanation, but in reality, the engine is controlled by a number of programs.

  As shown in FIG. 4, the pattern A program is composed of processes A, B, and C. In order to simplify the description, the program A program will be described as being composed of processes A, B, and C, but in practice it is composed of a large number of processes. The same applies to other programs. The pattern B program includes a process A and a process D obtained by simplifying the processes B and C, and the entire processing time is shorter than that of the pattern A program. The pattern C program is composed only of the process A, and the entire processing time is shorter than that of the pattern B program. The pattern D program does not have a process to be executed. That is, the pattern D program does not execute anything, and the overall processing time is almost zero. The pattern D program is a special process that is executed when an interrupt factor occurs in a state where it is not necessary to execute an interrupt process, as will be described later.

  The RAM 6 stores a vector table, peripheral IC states, and microcomputer states. A jump address for the interrupt factor X is stored in the vector table. The interrupt factor X of this embodiment is generated every time the crankshaft rotates by a predetermined angle, and the interrupt factor is only one of the interrupt factors X. The vector table is written by a boot program that is executed when the engine ECU 1 is started up by turning on the power. The state of the peripheral IC is a state value indicating a state that affects the load state of the CPU 4, and the CPU 4 can indirectly determine the load state of the CPU 4 by acquiring the state value from the peripheral IC when executing the interrupt program. It becomes. The state of the microcomputer is a state value indicating a state that affects the load on the CPU 4, and the CPU 4 can directly determine the load state of the CPU 4 by acquiring the state value from the state of the microcomputer when the interrupt program is executed. Become. In this embodiment, the rotational state of the engine is stored in the RAM 6, and the load state of the CPU 4 is directly determined based on the rotational state. The rotation state is a low rotation, normal rotation, or high rotation of the engine. Therefore, in this embodiment, the state value stored as the state of the microcomputer is directly used to determine the load state of the CPU 4.

  Now, the CPU 4 repeatedly executes the scheduler process by the scheduler program stored in the ROM 5. This scheduler program changes the jump destination address of the vector table of the interrupt factor X stored in the vector table based on the state of the microcomputer. That is, as shown in FIG. 3, when the scheduler process is started, the status of peripheral ICs and microcomputers is acquired (S101). Thereafter, the CPU 4 switches the interrupt process for the interrupt factor according to the acquired state. Specifically, it is determined whether the state is A (S102: NO), B (S103: NO), C (104: YES), or D (S104: NO). States A, B, and C correspond to engine low speed, normal speed, and high speed. State D is a state in which shutdown processing such as data backup is being executed and processing related to engine control is stopped in response to the ignition switch being turned off. Note that the engine rotation state may be further classified.

  Here, since the crank signal is output from the crank sensor 13 every time the crankshaft rotates by a predetermined angle, the interrupt control circuit 7 outputs an interrupt request to the CPU 4 at the timing when the crank signal is input, and accordingly The CPU 4 executes interrupt processing.

  By the way, the interruption process can perform many processes necessary for engine control since the load on the CPU 4 is small when the engine is running at a low speed. However, the interruption process is necessary because the load on the CPU 4 is relatively large at normal times. Since the load on the CPU 4 is very high during high rotation, only the minimum necessary processing is executed, so that the interrupt program for the interrupt factor X can be optimally executed according to the situation. Conventionally, it was not possible to cope with a change in the load state of the CPU 4 after rewriting the jump address, but in the present embodiment, the CPU 4 executes the schedule program to manage the schedule, so that the correspondence can be made. .

  Specifically, in the case of the state A (S102: YES), the jump destination address in the vector table of the interrupt factor X is rewritten to the processing content of the pattern A (S105), and the scheduler process is terminated. In the case of the state B (S103: YES), the jump destination address of the vector table of the interrupt factor X is rewritten to the pattern B (S106), and the scheduler process is terminated. In the case of the state C (S104: YES), the jump destination address in the vector table of the interrupt factor X is rewritten to the pattern C (S107), and the scheduler process is terminated. In the state D (S104: NO), the jump destination address of the vector table of the interrupt factor X is rewritten to the pattern D (S108), and the scheduler process is terminated.

  In this way, a plurality of patterns A to D are prepared in advance as processing patterns for the interrupt factor X, and when an interrupt due to the interrupt factor X occurs, the interrupt program at the jump destination address shown in the interrupt vectorable is executed. The In this case, since the jump destination address is changed by the CPU 4, one of the patterns A to D is started when an interrupt occurs, and processing corresponding to the load state of the CPU 4 is performed according to each program. become.

  Specifically, if the jump address is a pattern A program, the pattern A interrupt processing shown in FIG. 4 is started, and after processing A, processing B, and processing C are performed in this order, the processing returns. If the jump address is a pattern B program, pattern B interrupt processing is started, processing A and processing D are performed in this order, and the process returns. If the jump address is a pattern C program, pattern C interrupt processing is started, and after processing A is executed, the process returns. If the jump address is a pattern D program, pattern D interrupt processing is started, and the process returns without performing any processing. In other words, when the ignition switch is turned off, shutdown processing such as data backup is performed while maintaining the power supply's self-holding state. However, the crank signal is input in response to the engine being driven even during the shutdown process. For this reason, since an interrupt factor is generated in response to the input of the crank signal, the CPU 4 is in a state of executing the interrupt program unnecessarily, so even if the interrupt program is executed, the processing load on the CPU 4 is reduced. It is a device to reduce.

  When the interrupt control circuit 7 outputs an interrupt request to the CPU 4, the interrupt control circuit 7 saves the next execution address as an interruption address in the stack area and outputs it. Thereafter, when the CPU 4 finishes executing the interrupt program, the CPU 4 restarts from the interrupt address, so that the processing executed before the interrupt can be restarted.

According to such an embodiment, the following effects can be produced.
Since the CPU 4 rewrites the jump address stored in the vector table according to the engine rotation state, the jump address for the interrupt factor X can be changed according to the load state of the CPU 4 indicated by the engine rotation state. The processing content can be changed according to the situation for the same interrupt factor X. As a result, appropriate interrupt processing can be executed in accordance with the load state of the CPU 4, so that the processing capability of the CPU 4 can be utilized more effectively.

Since no branching occurs depending on the load state of the CPU 4 in the interrupt process, the processing load for branch determination can be reduced when the interrupt process is executed.
When the engine is running at high speed, the interrupt request interval is shortened and the processing load on the CPU 4 is high. Therefore, only necessary processing is performed by changing the interrupt processing content, especially when the engine is running at high speed. The effect can be exhibited remarkably.

(Second Embodiment)
The second embodiment will be described with reference to FIG. 5. The same steps as those in the first embodiment are denoted by the same step numbers. The second embodiment is characterized in that interrupt processing is executed for a plurality of interrupt factors.

  The interrupt control circuit 7 can input a plurality of interrupt factors from the outside. When any interrupt factor is input, the interrupt control circuit 7 outputs an interrupt request to the CPU 4 and at the same time outputs information that can identify the input interrupt factor to the CPU 4. To do. In the present embodiment, two interrupt factors, interrupt factors X and Y, will be described for the sake of simplicity of explanation, but three or more interrupt factors may be input.

  When starting the scheduler process as shown in FIG. 5, the CPU 4 acquires the load state of the CPU 4 (S101) and interrupts according to the states A to D (S102 to S104), as in the first embodiment. Switch the interrupt processing for the cause. That is, in the state A (S102: YES), the jump destination address of the vector table of the interrupt factor X is rewritten to the processing contents of the pattern A (S105), and the jump destination address of the vector table of the interrupt factor Y is changed to the pattern A. After rewriting (S201), the scheduler process is terminated. In the case of state B (S103: YES), the jump destination address of the vector table for interrupt factor X is rewritten to pattern B (S106), and the jump destination address of the vector table for interrupt factor Y is rewritten to pattern B ( S202), the scheduler process is terminated. In the case of the state C (S104: YES), the jump destination address of the interrupt factor X vector table is rewritten to the pattern C (S107), and the jump destination address of the interrupt factor Y vector table is rewritten to the pattern C ( S203), the scheduler process is terminated. In the state D (S104: NO), the jump destination address of the interrupt factor X vector table is rewritten to the pattern D (S108), and the jump destination address of the interrupt factor Y vector table is rewritten to the pattern D ( S204), the scheduler process is terminated.

  According to such an embodiment, the CPU 4 collectively rewrites the jump destination addresses for a plurality of interrupt factors in accordance with the load state of the CPU 4, so that the burden required for rewriting the jump destination address can be suppressed. Thus, it is not necessary to determine the next jump destination in each interrupt program, and the processing load can be reduced. In particular, as the number of interrupt factors increases, the effect can be remarkably exhibited.

(Third embodiment)
A third embodiment will be described with reference to FIG. The third embodiment is characterized in that the jump destination address is changed only when the load state of the CPU 4 changes. In the first embodiment and the second embodiment, the jump destination address of the vector table is rewritten according to the load state of the CPU 4 every time the scheduler process is started, but even if the load state of the CPU 4 does not change, Since the jump destination address of the vector table is rewritten to the same jump destination address, useless processing is executed.

  Therefore, when starting the scheduler process as shown in FIG. 6, the CPU 4 executes the same operation as in the first embodiment, and then updates and stores the currently acquired engine rotation state as a state value in the RAM 6 (S302). .

  When the scheduler process is executed at the next timing, the previous state value stored and updated as described above is compared with the current state value (S301), and if there is no change from the previous state value (S301: NO), it ends without doing anything. On the other hand, when there is a change from the previous state value (S301: YES), after executing the processing corresponding to the states A to D (S102 to S108), the state value stored in the RAM 6 is updated and stored. (S302), the scheduler process is terminated.

  According to such an embodiment, since the jump address of the vector table is rewritten only when the load state of the CPU 4 changes, the processing load on the CPU 4 can be greatly reduced. In particular, the effect is remarkable when the load state of the CPU 4 is constant, that is, when the engine rotation state is maintained.

(Other embodiments)
The present invention is not limited to the above-described embodiment, but may be modified or expanded as follows, each modified example may be combined with the above-described embodiment, or each modified example may be combined.

Instead of executing the scheduler process at a timing synchronized with the rotation of the crankshaft, it may be executed at a timing synchronized with the occurrence of an event by the timer 8.
The drive source is not limited to a gasoline engine, and may be applied to a diesel engine, or may be applied to a motor serving as a drive source such as an electric vehicle or a hybrid vehicle.

  Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

In the drawings, 1 is an engine ECU (on-vehicle electronic control device), 2 is a microcomputer, 4 is a CPU, 4a is an acquisition unit, 4b is a scheduler, 6 is a storage unit, and 7 is an interrupt control circuit (interrupt control unit).

Claims (4)

A storage unit (6) that stores the jump address corresponding to the interrupt factor in an updatable manner, and when an interrupt request is received, moves to the jump address stored in the storage unit and interrupts the jump address In the in-vehicle electronic control device that controls the vehicle equipment mainly by the microcomputer (2) including the CPU (4) that shifts to the interruption address when the execution of the program is finished,
The microcomputer is
When an interrupt factor occurs, an interrupt control unit (7) that requests an interrupt from the CPU and saves an address that the CPU is scheduled to execute next as the interrupt address;
An acquisition unit (4a) for acquiring a load state affecting the operation of the CPU;
A scheduler (4b) for executing a rewrite process for changing a jump destination address stored in the storage unit to an address of an interrupt program for executing a process corresponding to the load state of the CPU according to the load state;
A vehicle-mounted electronic control device comprising:   The in-vehicle electronic control device according to claim 1, wherein at least one of processing reduction, processing change, and processing stop when the CPU executes the interrupt program is executed as the processing according to the load state. Multiple interrupt factors are set,
The on-vehicle electronic control device according to claim 1, wherein the scheduler collectively executes rewrite processing for all interrupt factors affecting the operation of the CPU.   The in-vehicle electronic control device according to any one of claims 1 to 3, wherein the scheduler executes the rewriting process when the load state acquired by the acquisition unit changes.

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