JP2018072896A - Bus control device and control method thereof - Google Patents

Abstract

The present invention provides a technique capable of reducing power consumption in a portion that is not operating and preventing an apparatus from hanging up. In a bus control device, a bus arbitration unit arbitrates access requests from a plurality of bus masters that output an access request, receives an access request from the bus master, and receives a first access request that has been received. The frequency of the clock signal supplied to the bus master is a first frequency, and the frequency of the clock signal supplied to a bus master other than the first bus master among the plurality of bus masters is a second frequency lower than the first frequency. [Selection] Figure 1

Description

  The present invention relates to a bus control device and a control method therefor.

  In power saving control of a semiconductor integrated circuit, a clock gating technique for cutting off supply of a clock signal to a non-operating part is widely used as a technique for reducing power consumption of the entire circuit. For example, Patent Document 1 proposes a technique for adopting this clock gating method in a bus control device and reducing the power consumption of the device in accordance with the bus usage status. According to this, in the bus arbitration circuit, a competition state of access requests to the same bus slave from a plurality of bus masters is detected, and the clock is sent to the request holding circuit in the bus arbitration circuit corresponding to the bus master that cannot acquire the bus right. The signal supply is stopped. Thereby, when the bus master does not issue a waiting state or a transfer request, the power consumption of the transfer circuit corresponding to the bus master in the bus arbitration circuit can be reduced.

JP 2004-185375 A

  However, when the supply of the clock signal to the non-operating part is stopped, for example, when an access request is generated from the CPU to a register in the circuit to which the clock signal is not supplied, a response signal to the access request is given. It cannot be issued. For this reason, since the CPU cannot receive a response signal to the access request, the CPU enters a waiting state, and the operation hangs up. In such a case, there is a problem that control by the operating OS and software becomes impossible, and the apparatus cannot be restored unless the power of the apparatus is shut off or a reset operation is performed.

  An object of the present invention is to solve the above-described problems of the prior art.

  The objective of this invention is providing the technique which can prevent the hang-up of an apparatus while reducing the power consumption of the location which is not operate | moving.

In order to achieve the above object, a bus control device according to an aspect of the present invention has the following configuration. That is,
Multiple bus masters that output access requests;
Arbitration means for arbitrating access requests from the plurality of bus masters and receiving access requests from the bus masters;
The frequency of the clock signal supplied to the first bus master for which the access request has been accepted by the arbitration means is the first frequency, and the frequency of the clock signal supplied to the bus masters other than the first bus master among the plurality of bus masters is the first frequency. And a clock control means for setting a second frequency lower than the first frequency.

  According to the present invention, the frequency of the clock supplied to the bus master that does not perform data transfer is lowered, and the frequency of the clock that is supplied to the bus master that performs data transfer is set to a higher frequency. Thereby, there is an effect that it is possible to prevent the hang-up of the operation while reducing the power consumption.

  Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. In the accompanying drawings, the same or similar components are denoted by the same reference numerals.

The accompanying drawings are included in the specification, constitute a part thereof, show an embodiment of the present invention, and are used together with the description to explain the principle of the present invention.
The block diagram explaining the structure of the bus control apparatus which concerns on Embodiment 1 of this invention. FIG. 3 is a block diagram illustrating a configuration of a clock control unit according to the first embodiment. FIG. 6 is a diagram for explaining a clock frequency selection table stored in each LUT of the frequency change control unit according to the first embodiment. 6 is a flowchart for explaining control of initial setting of the frequency of the operation clock signal of the bus master and slave, which is performed immediately after the reset by the bus control device according to the first embodiment. 5 is a flowchart for explaining control processing by a bus arbitration unit and a clock control unit according to the first embodiment. 3 is a timing chart for explaining an operation example of a bus arbitration unit, a clock control unit, and a bus master according to the first embodiment. FIG. 3 is a diagram illustrating an example of a timing chart of a register access bus when the CPU performs register access to the bus master in the bus control device according to the first embodiment. 9 is a flowchart for explaining control processing by a bus arbitration unit and a clock control unit according to the second embodiment. 9 is a timing chart for explaining an operation example of a bus arbitration unit, a clock control unit, and a bus master according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the present invention. .

[Embodiment 1]
FIG. 1 is a block diagram illustrating the configuration of the bus control device 100 according to the first embodiment of the present invention.

  The bus control device 100 includes a CPU 101, bus masters 102 to 104, a bus arbitration unit 105, a bus slave 106, a reference clock generation unit 107, and a clock control unit 108. The bus masters 102 to 104 are modules that control data transfer on the bus. Each of the bus masters 102 to 104 is connected to the bus arbitration unit 105 via a bus. As a result of arbitration in the bus arbitration unit 105, the bus masters 102 to 104 become targets. Data transfer is performed to the bus slave 106.

  The bus arbitration unit 105 is a module that adjusts competition for use requests to the bus, and is connected to the bus masters 102 to 104 and the bus slave 106 via the bus. Here, in accordance with a predetermined arbitration method (priority order, first-come-first-served order, etc.), the right to use the bus is given to one of the bus masters 102 to 104, and data transfer to the bus slave 106 is permitted. The bus slave 106 is a module that controls data transfer on the bus, is connected to the bus arbitration unit 105 via the bus, and is transferred from the bus master that has obtained the right to use the bus as a result of arbitration in the bus arbitration unit 105. Receive data.

  The CPU 101 is a data processing unit that executes processing according to a predetermined instruction set, and is connected to the bus masters 102 to 104, the bus arbitration unit 105, the bus slave 106, the clock control unit 108, and the register access bus 110. . The CPU 101 controls the operation of each module by setting an instruction to the register of each connected module via the register access bus 110.

  The reference clock generation unit 107 includes a crystal oscillator, a crystal oscillator that can change the frequency of the output signal to an arbitrary value, and the like. A reference clock signal that serves as a reference of the clock signal used in the bus control device 100 is obtained. Generate. The reference clock signal generated by the reference clock generation unit 107 is supplied to the clock control unit 108. The clock control unit 108 generates clock signals 1 to 4 from the frequency change requests 1 to 4 and the frequency information 1 to 4 supplied from the bus arbitration unit 105 and the reference clock signal supplied from the reference clock generation unit 107. . Details of the operation of the clock controller 108 will be described later.

  In FIG. 1, the number of bus masters and the number of bus slaves are shown as three as the bus master and the bus slave included in the bus control device 100 for simplification of description. It does not matter.

  FIG. 2 is a block diagram illustrating the configuration of the clock control unit 108 according to the first embodiment.

  The clock control unit 108 includes four clock control module units 210, 220, 230, and 240. In the first embodiment, since there are four clock signals to be controlled, the number of clock control module units is four, and the internal configurations of the clock control module units 210, 220, 230, and 240 are the same.

  Each of the PLL synchronization control units 211, 221, 231, and 241 includes a phase comparator, a loop filter, a voltage control oscillator, and the like (not shown), and outputs a clock signal synchronized with the phase of the reference clock signal input from the reference clock generation unit 107. Generate. Each of the frequency dividers 212 to 215, 222 to 225, 232 to 235, and 242 to 245 reduces the frequency of the clock signal supplied from each corresponding PLL synchronization control unit 211, 221, 231, 241 to an integer. Let (divide). These frequency dividers are programmable frequency dividers that divide the frequency of the clock signal in accordance with an arbitrary integer value (frequency division value) set by the CPU 101. In the first embodiment, since “2” is set as the frequency division value in the frequency dividers 212, 222, 232, and 242, the frequency of the reference clock signal is set from these frequency dividers 212, 222, 232, and 242. A clock signal having a frequency ½ of the above is output. Since the frequency dividers 213, 223, 233, and 243 are set to “4” as frequency division values, the frequency dividers 213, 223, 233, and 243 provide a frequency that is ¼ of the frequency of the reference clock signal. Clock signal is output. Since the frequency dividers 214, 224, 234, and 244 are set to "10" as the frequency dividing value, the frequency from the frequency dividers 214, 224, 234, and 244 is 1/10 the frequency of the reference clock signal. Clock signal is output. Further, since “20” is set as the frequency division value in the frequency dividers 215, 225, 235, and 245, the frequency dividers 215, 225, 235, and 245 provide 1/20 of the frequency of the reference clock signal. A clock signal having a frequency of is output. In the clock control module sections 210, 220, 230, and 240 in FIG. 2, four frequency dividers 212 to 215, 222 to 225, 232 to 235, and 242 to 245 are provided, respectively.

  Each of the MUXs 216, 226, 236, and 246 is a 5-input 1-output multiplexer, and is generated as an input signal by one of the corresponding PLL synchronization control units 211, 221, 231, 241 and four frequency dividers. A clock signal is input. That is, each of the MUXs 216, 226, 236, and 246 is input with five clock signals having different frequencies supplied from the corresponding PLL synchronization control unit and frequency divider. Selection signals 218, 228, 238, and 248 supplied from the corresponding frequency change control units 217, 227, 237, and 247 are input as selection signals for the MUXs 216, 226, 236, and 246, respectively. Then, clock signals selected from the five clock signals according to the value of the selection signal are output as clock signals 1 to 4, respectively.

  Here, for example, the frequency change control unit 217 outputs the selection signal 218 to the MUX 216 based on the frequency change request 1 and the frequency information 1 supplied from the bus arbitration unit 105. The frequency change control unit 217 has an LUT (not shown) inside, and a frequency selection table created in advance is stored in the LUT. When the frequency change request 1 is received, the address stored in the address corresponding to the frequency information 1 is output to the MUX 216 as the selection signal 218. The operations of the other frequency change control units 227, 237, and 247 basically perform the same operation except that the frequency change request, the frequency information, and the MUX are different.

  FIG. 3 is a diagram for explaining a data example of a frequency selection table stored in each LUT of the frequency change control units 217, 227, 237, and 247 according to the first embodiment.

  Here, when “200” is input as frequency information, the frequency change control unit outputs “1” as a selection signal. When “100” is input as the frequency information, the frequency change control unit outputs “2” as the selection signal. Similarly, when “50” is input as frequency information, “3” is output as a selection signal. Further, when “20” is input as the frequency information, “4” is output as the selection signal, and when “10” is input as the frequency information, “5” is output as the selection signal.

  The frequency change control units 217, 227, 237, and 247 output selection signals, respectively, and after the phases of the clock signals 1 to 4 whose frequencies have been changed are synchronized with the phases of the reference clock signals, the frequency change responses 1 to 4 are output. Output to the bus arbitration unit 105. The time until the phase of the clock signals 1 to 4 whose frequency has been changed is synchronized with the phase of the reference clock signal is determined by the time constant of the loop filter by the corresponding PLL synchronization control unit 211, 221, 231, 241. The

  Therefore, after the frequency change requests 1 to 4 are issued, the frequency change responses 1 to 4 are sent to the bus arbitration unit 105 at a timing when a predetermined time including the time constant of the loop filter and the frequency change amount has elapsed. returned.

  Next, a control that changes the frequency of the operation clock signal of the bus master and the bus slave according to the bus use status, which is a feature of the first embodiment, will be described.

  FIG. 4 is a flowchart for explaining the initial setting control of the frequency of the operation clock signal of the bus masters 102 to 104 and the slave 106 performed immediately after the reset by the bus control device 100 according to the first embodiment.

  First, in S401, it waits for the reset signal applied to the entire bus control device 100 to be released. In step S402, the process waits for the reset signal to be released. If the reset signal is released, the process proceeds to step S403. If the reset is not released, the process proceeds to step S401. The reset signal is input to all modules except the reference clock generation unit 107 of the bus control device 100. Therefore, the reference clock signal continues to be output from the reference clock generation unit 107 even when the reset signal is applied. Note that the reset signal is canceled when a predetermined time elapses after the reset signal is output to the bus control device 100. In S403, the bus arbitration unit 105 sets the frequency of the operation clock signal of all bus masters and bus slaves to be lower than the frequency at the time of data transfer.

  When the reset signal is released, the selection signals 218, 228, 238, and 248 having predetermined values are respectively sent from the frequency change control units 217, 227, 237, and 247 at the timing when the reference clock signal rises next. , Output to each corresponding MUX. By this selection signal, the frequencies of the clock signals 1 to 4 that are operation clock signals supplied from the clock control unit 108 to the bus masters 102 to 104 and the bus slave 106 are determined. In S403, the frequency is lower than the frequency at the time of data transfer. Is set as follows.

  For example, in the first embodiment, for simplification of description, the frequency of the clock signals 1 to 4 at the time of data transfer is set to 200 MHz, and the frequency of the reference clock signal supplied from the reference clock generation unit 107 is also 200 MHz. A case will be described as an example.

  In the first embodiment, for example, the clock control module unit 210 will be described as an example. In the frequency divider 212, the frequency divider 213, the frequency divider 214, and the frequency divider 215, as described above, “2”, “4”, “10”, and “20” are set as the frequency division values, respectively. ing. At this time, the frequencies of the clock signals output from these frequency dividers 212, 213, 215, and 215 are 100 MHz, 50 MHz, 20 MHz, and 10 MHz, respectively. If the selection signal 218 output in the initial state is “2”, the MUX 216 is supplied from the frequency divider 212 connected to the input terminal (2) corresponding to the value of the selection signal 218. The clock signal is selected and output as the clock signal 1. As a result, the frequency of the clock signal 1 becomes 100 MHz, which is a lower frequency than 200 MHz that is the frequency at the time of data transfer. This also operates in the case of the other clock control module units 220, 230, and 240.

  FIG. 5 is a flowchart for explaining control processing by the bus arbitration unit 105 and the clock control unit 108 according to the first embodiment. Here, processing related to change control of the frequency of the operation clock signal of the bus masters 102 to 104 and the bus slave 106 at the time of data transfer is shown. The job for transferring data will be described by taking as an example a case where data for three cycles, two cycles, and three cycles are transferred from the bus masters 102, 103, and 104 to the bus, respectively.

  First, in S501 and S502, the bus arbitration unit 105 waits for a request signal for requesting data transfer from any of the bus masters 102 to 104. If it is determined in S502 that a request signal has been issued, the process proceeds to S503. Here, when the CPU 101 executes a job for transferring data using the bus, the CPU 101 relates to address information, transfer size information, and the like of a transfer destination necessary for data transfer to the bus masters 102 to 104 used in the job. Register settings are made. As a result, the transfer request signal is turned on in order to request the right to use the bus from the bus master to the bus arbitration unit 105.

  In step S <b> 503, the bus arbitration unit 105 determines whether a transfer request from a plurality of bus masters among the bus masters 102 to 104 to the same bus slave is generated and conflicts. If it is determined that the transfer requests are in conflict, the process proceeds to S505. If not, the process proceeds to S506.

  Here, the state in which a plurality of bus masters issue data transfer requests to the same bus slave and the transfer requests are in conflict is the number of bus slaves 106 here. This means that the transfer request signals from 102 to 104 are all turned on.

  FIG. 6 is a timing chart for explaining an operation example of the bus arbitration unit 105, the clock control unit 108, and the bus masters 102 to 104 according to the first embodiment.

  For example, at timing T1, transfer request signal 1 from bus master 102, transfer request signal 2 from bus master 103, and transfer request signal 3 from bus master 104 are all turned on, and transfer request signals from three bus masters are issued. ing.

  The flowchart of FIG. 5 will be described below with reference to the timing chart of FIG.

  At timing T1 in FIG. 6, since all the transfer request signals 1 to 3 from the bus masters 102 to 104 are output (transfer requests are in conflict), the transfer requests are in conflict in the conditional branch of S504. And the process proceeds to S505. In S505, the bus arbitration unit 105 arbitrates the right to use the bus according to a predetermined arbitration method. There are a plurality of bus arbitration methods, such as a first-come-first-served method and a priority method (fixed type, variable type), and an appropriate arbitration method is adopted according to the characteristics and purpose of the bus control device 100 according to the first embodiment. The Here, a variable priority method is adopted, priority is assigned to all bus masters in order, and the bus master that has acquired the right to use the bus next assigns it to the lowest priority. A method will be described as an example.

  At timing T1, the priority order when the transfer requests from the bus masters 102 to 104 are competing is 1> 2> 3. Accordingly, the priority order of the bus master 102 is “1”, the priority order of the bus master 103 is “2”, and the priority order of the bus master 103 is “3”. Thus, “1> 2> 3” in the priority order information indicates that the priority order is higher in the order of bus master 102> bus master 103> bus master 104.

  Therefore, of the bus masters 102 to 104 whose transfer request signals 1 to 3 are on at the timing T1, the bus master 102 has the highest priority. Accordingly, in step S507, the bus arbitration unit 105 selects the bus master 102 as the bus master that gives the right to use the bus, and advances the processing to step S508.

  In S508, the bus arbitration unit 105 sets the frequency of the clock signal of the bus master 102 and the bus slave 106 to which the right to use the bus is given (200 MHz in the first embodiment). In the example of FIG. 6, when the bus arbitration unit 105 selects the bus master 102 as the bus master to which the right to use the bus is selected at the timing T1, the frequency change request 1 for the bus master 102 is turned on to the clock control unit 108. At the same time, frequency information 1 indicating the frequency information to be changed is transmitted.

  In the first embodiment, the frequencies of the clock signals 1 to 4 when data is not transferred are all 100 MHz, and the frequency of the clock signals 1 to 4 when data is transferred is 200 MHz. Therefore, “200” corresponding to 200 MHz is transmitted as the frequency information 1 at the timing T1 in FIG.

  When the frequency change request 1 is turned on in this way, the frequency change control unit 217 of the clock control unit 108 refers to the frequency selection table corresponding to the frequency information 1 (here, “200”) and sets “1” as the selection signal 218. Is output. When this selection signal “1” is supplied to the MUX 216, the MUX 216 selects the clock signal supplied from the PLL synchronization control unit 211 that is input to the input terminal (1) of the MUX 216 and outputs it as the clock signal 1. Here, since the frequency of the clock signal supplied from the PLL synchronization control unit 211 is 200 MHz, the frequency of the clock signal 1 is 200 MHz.

  After changing the frequency of the clock signal 1 in this way, the frequency change control unit 217 turns on the frequency change response 1 to the bus arbitration unit 105 at the timing when the phase of the changed clock signal 1 is synchronized with the reference clock signal. (Timing T2 in FIG. 6). In this way, when the bus arbitration unit 105 confirms that the frequency change response 1 from the frequency change control unit 217 of the clock control unit 108 is on, the bus arbitration unit 105 turns on the transfer permission signal 1 for the bus master 102 (timing in FIG. 6). T3). As a result, data is transferred from the bus master 102 to the bus slave 106 via the bus arbitration unit 105 in synchronization with the clock signal 1 having a frequency of 200 MHz.

  When changing the frequency of the clock signal 1 that is the operation clock signal of the bus master 102, the bus arbitration unit 105 controls to change the frequency of the clock signal 4 that is the operation clock signal of the bus slave 106 at the same time. The process of changing the frequency of the clock signal 4 is performed by the clock control module unit 240 of the clock control unit 108, but the process is the same as that of the clock control module unit 210, and the timing is also the same. Therefore, the explanation is omitted.

  In step S509, data transfer from the bus master 102 to which the right to use the bus is given to the bus slave 106 is executed. In the example shown in FIG. 6, after the transfer permission signal 1 is turned on, data transfer for three cycles of the clock signal 1 is executed from the bus master 102 to the bus slave 106 as indicated by the data signal 1.

  When this data transfer is completed, the process proceeds to S510, where the bus arbitration unit 105 restores the frequencies of the operation clock signals of the bus master 102 and the bus slave 106 to which the right to use the bus is given.

  In the first embodiment, the end signal 1 is turned on at the timing when the last data transferred from the bus master 102 is transferred as the data signal 1 as a protocol for performing data transfer using the bus. When the end signal 1 from the bus master 102 is turned on in this way, the bus arbitration unit 105 turns on the frequency change request 1 and transmits “100” as frequency information 1 to the clock control unit 108 at timing T4 in FIG. Accordingly, the frequency change control unit 217 of the clock control unit 108 refers to the clock frequency selection table corresponding to the frequency information 1 and outputs a selection signal. That is, when the frequency selection table shown in FIG. 3 is set in the LUT, when “100” is input as the frequency information 1, “2” is selected as the selection signal and supplied as the selection signal 218 of the MUX 216. Is done. Accordingly, since “2” is input as the selection signal 218, the MUX 216 selects the clock signal supplied from the frequency divider 212 that is input to the input terminal (2) of the MUX 216 and outputs it as the clock signal 1. . At this time, since the frequency of the clock signal supplied from the frequency divider 212 is 100 MHz, the frequency of the clock signal 1 is changed from 200 MHz to 100 MHz.

  After changing the frequency of the clock signal 1 in this way, the frequency change control unit 217 turns on the frequency change response 1 to the bus arbitration unit 105 at the timing when the phase of the changed clock signal 1 is synchronized with the reference clock signal. (Timing T5 in FIG. 6). In step S511, the bus arbitration unit 105 determines whether or not the data transfer by all the bus masters that have issued the transfer requests has been completed. If the data has been completed, the bus arbitration unit 105 ends the processing. Proceed to

  After the data transfer from the bus master 102 is completed, the transfer request signal 2 and the transfer request signal 3 from the bus master 103 and the bus master 104 are turned on at a timing T6 in FIG. Therefore, in S504, it is determined that the transfer requests are in conflict, and the process proceeds to S505. In step S505, the bus arbitration unit 105 arbitrates the right to use the bus according to the above-described arbitration method. Here, the priority is 2> 3> 1 at the timing T6. That is, at the timing T6, the bus master 103 has the highest priority among the bus masters 103 and 104 that have turned on the transfer request signals 2 to 3. Accordingly, the bus arbitration unit 105 selects the bus master 103 as a bus master that gives the right to use the bus in S507. In step S508, the frequency of the operation clock signal of the bus master 103 and the bus slave 106 to which the right to use the bus is given is set high.

  That is, at timing T6, the frequency change request 2 for the bus master 103 is turned on to the clock control unit 108, and “200” is issued as the frequency change request 2. Accordingly, the frequency change control unit 227 of the clock control unit 108 outputs the selection signal 228 with reference to the frequency selection table (FIG. 3) corresponding to the frequency information 2. Here, since the frequency selection table shown in FIG. 3 is set in the LUT, when the frequency information 2 is “200”, “1” is selected as the selection signal and supplied to the MUX 226 as the selection signal 228. As a result, the MUX 226 selects the clock signal supplied from the PLL synchronization control unit 221 that is input to the input terminal (1) of the MUX 226 corresponding to the selection signal “1”, and outputs it as the clock signal 2. At this time, since the frequency of the clock signal supplied from the PLL synchronization control unit 221 is 200 MHz, the frequency of the clock signal 2 is changed to 200 MHz. After changing the frequency of the clock signal 2 in this way, the frequency change control unit 227 turns on the frequency change response 2 to the bus arbitration unit 105 at the timing when the phase of the changed clock signal 2 is synchronized with the reference clock signal. (Timing T7 in FIG. 6). In this way, when the bus arbitration unit 105 confirms that the frequency change response 2 is on from the frequency change control unit 227 of the clock control unit 108, the bus arbitration unit 105 turns on the transfer permission signal 2 for the bus master 103 (timing T8 in FIG. 6). Thereby, in S509, data transfer from the bus master 103 to which the right to use the bus is given to the bus slave 106 is executed.

  In the example shown in FIG. 6, after the transfer permission signal 2 is turned on, transfer data for two cycles of the clock signal 1 is transferred from the bus master 103 to the bus slave 106 as the data signal 2. When the data transfer is completed, the process proceeds to S510, and the bus arbitration unit 105 restores the frequency of the operation clock signal of the bus master 103 and the bus slave 106 to which the right to use the bus is given. Here, when the end signal 2 from the bus master 102 is turned on, the bus arbitration unit 105 turns on the frequency change request 2 and transmits the frequency information 2 to “100” to the clock control unit 108 at timing T9 in FIG. To do. When the frequency change request 2 is turned on in this way, the frequency change control unit 227 of the clock control unit 108 outputs a selection signal 228 to the MUX 226 with reference to the frequency selection table corresponding to the frequency information 1. When the frequency selection table shown in FIG. 3 is set in the LUT, when “100” is input as the frequency information 2, “2” is selected as the selection signal, and this is supplied to the MUX 226 as the selection signal 228. . Upon receiving this selection signal 228, the MUX 226 selects the clock signal supplied from the frequency divider 222 that is input to the input terminal (2) of the MUX 226, and outputs it as the clock signal 2 that is the output signal of the MUX 226. At this time, since the frequency of the clock signal supplied from the frequency divider 222 is 100 MHz, the frequency of the clock signal 2 is changed from 200 MHz to 100 MHz. After changing the frequency of the clock signal 2 in this way, the frequency change control unit 227 turns on the frequency change response 2 for the bus arbitration unit 105 at a timing when the phase of the changed clock signal 2 is synchronized with the reference clock signal. (Timing T10 in FIG. 6).

  After the data transfer from the bus master 103 is thus completed, only the transfer request signal 3 from the bus master 104 is turned on at a timing T11 in FIG. Therefore, in the conditional branch of S504, it is determined that the transfer request is not competing, and the process proceeds to S506. In S506, only the bus master 104 makes a data transfer request to the bus slave 106, and there is no transfer request contention. Therefore, the bus master 104 is selected as the bus master that gives the right to use the bus. In step S508, the bus arbitration unit 105 sets the frequency of the operation clock signal of the bus master 104 and the bus slave 106 to which the bus use right is given to be high.

  At timing T11 in FIG. 6, the frequency change request 3 for the bus master 104 is turned on and the frequency change request 2 is set to “200” for the clock control unit 108. When the frequency change request 3 is turned on in this way, the frequency change control unit 237 of the clock control unit 108 outputs a selection signal 238 with reference to the frequency selection table corresponding to the frequency information 3. Here, when “200” is input as the frequency information 3, “1” is selected as the selection signal, and the selection signal “1” is supplied to the MUX 236. As a result, the MUX 236 selects the clock signal supplied from the PLL synchronization control unit 231 that is input to the input terminal (1) of the MUX 236 according to the selection signal “1”, and outputs it as the clock signal 3. Here, since the frequency of the clock signal supplied from the PLL synchronization control unit 231 is 200 MHz, the frequency of the clock signal 3 is changed from 100 MHz to 200 MHz. After changing the frequency of the clock signal 3 in this way, the frequency change control unit 237 turns on the frequency change response 3 to the bus arbitration unit 105 at the timing when the phase of the changed clock signal 3 is synchronized with the reference clock signal. (Timing T12 in FIG. 6). As a result, when the bus arbitration unit 105 confirms that the frequency change response 3 from the frequency change control unit 237 of the clock control unit 108 is turned on, the bus arbitration unit 105 turns on the transfer permission signal 3 for the bus master 104 (FIG. 6). Timing T13).

  Thus, in S509, data transfer from the bus master 104 to which the right to use the bus is given to the bus slave 106 is executed. In the example shown in FIG. 6, data for three cycles of the clock signal 3 is transferred from the bus master 104 as the data signal 3 after the transfer permission signal 3 is turned on. When the data transfer is completed in this way, in S510, the bus arbitration unit 105 restores the frequencies of the operation clock signals of the bus master 104 and the bus slave 106 to which the right to use the bus is given. When the end signal 3 from the bus master 104 is turned on, the bus arbitration unit 105 turns on the frequency change request 3 at timing T14 in FIG. 6 and sets the frequency information 3 to “100” and transmits it to the clock control unit 108. . As a result, the frequency change control unit 237 of the clock control unit 108 refers to the frequency selection table corresponding to the frequency information 3 and outputs the selection signal 238 to the MUX 236. Here, the selection signal “2” corresponding to the frequency information “100” is acquired and supplied to the MUX 236 as the selection signal 238. As a result, the MUX 236 selects the clock signal supplied from the frequency divider 232 input to the input terminal (2) corresponding to the selection signal “2”, and outputs it as the clock signal 3 from the MUX 236. At this time, since the frequency of the clock signal supplied from the frequency divider 232 is 100 MHz, the frequency of the clock signal 3 is changed from 200 MHz to 100 MHz.

  After changing the frequency of the clock signal 3 in this way, the frequency change control unit 237 turns on the frequency change response 3 for the bus arbitration unit 105 at a timing when the phase of the changed clock signal 3 is synchronized with the reference clock signal. (Timing T15 in FIG. 6). Then, after the data transfer from the bus master 104 is completed, the data transfer by all the bus masters that have issued the transfer requests is completed in the conditional branch of S512.

  As described above, according to the first embodiment, when performing data transfer via the bus, the frequency of the clock signal supplied to the bus master is increased to, for example, 200 MHz, and the frequency of the clock signal other than the bus master is set. Lower. As a result, it is possible to suppress power consumption at a location where data transfer is not performed, and to return a response to any request issued to the location where the power consumption is suppressed. Thereby, the occurrence of hang-up can be prevented.

  Here, in the bus control device 100, the dynamic power consumption P generated during data transfer can be expressed by the following equation 1 where C is the load capacity of the circuit, Vdd is the power supply voltage, and F is the frequency of the clock signal.

P = C × (square of Vdd) × F (Formula 1)
As is apparent from Equation 1, the dynamic power consumption is proportional to the frequency of the clock signal. In the first embodiment, the frequency of the clock signal at a location where data transfer is not performed is set to, for example, ½ of the frequency during data transfer, so that the dynamic power consumption when data transfer is not performed is reduced to about the same as that during data transfer. It can be reduced to 1/2.

  In the first embodiment, for the sake of convenience of explanation, the example in which the frequency of the clock signal of the bus master at the time of data transfer is doubled when the data transfer is not performed has been described. However, it is expected that the dynamic power consumption can be further reduced by lowering the frequency of the clock signal when data transfer is not performed. For example, a process executed by a bus master in which data transfer is not performed may be a response to a register access from the CPU for confirming the progress of data transfer. In this case, the CPU may supply a clock signal having a frequency that does not hang up because it does not receive a response. Therefore, the frequency of the clock signal other than during data transfer can be further reduced. Thereby, it is considered that the dynamic power consumption other than during data transfer can be further reduced.

  FIG. 7 is a diagram illustrating an example of a timing chart of the register access bus when register access is performed from the CPU 101 to the bus masters 102 to 104 in the bus control device 100 according to the first embodiment. Here, an example is shown in which the frequency of the clock signal is reduced to ½ as described above at the timing T1.

  As shown in FIG. 7, after the timing T1, the clock signal continues to be supplied although the frequency is lowered. Therefore, a response signal to the register access request issued by the CPU 101 can be issued. Therefore, even when a register access from the CPU 101 occurs, a response to the register access can be returned, so that the above-described hang-up can be prevented.

[Embodiment 2]
In the first embodiment described above, the control for increasing the frequency of the clock signals 1 to 3 of the bus masters 102 to 104 that have acquired the right to use the bus to the frequency required for data transfer only during data transfer via the bus has been described. . On the other hand, in the second embodiment of the present invention, the data transfer amount in the data transfer from the bus master that has acquired the right to use the bus is referred to, and only when the transfer amount is larger than a predetermined value, the corresponding clock is The frequency of the signal is controlled to increase to a frequency necessary for data transfer.

  This is because when the amount of data to be transferred is small, considering the processing time required for changing the frequency of the clock signal, the data transfer may be completed quickly even if the frequency of the clock signal remains low. Therefore, when the amount of data to be transferred is small, an example will be described in which data is transferred at the same frequency without changing the frequency of the clock signals 1 to 3 to a higher frequency.

  FIG. 8 is a flowchart for explaining control processing by the bus arbitration unit 105 and the clock control unit 108 according to the second embodiment. The flowchart of the second embodiment shown in FIG. 8 is substantially the same as the flowchart of FIG.

  Here, the burst length is described as an example as information indicating the data transfer amount. Other information representing the data transfer amount may include a beat length, the number of bytes, a transfer type signal that expects transfer for a plurality of cycles, and the like.

In the following description of the flowchart shown in FIG.
An example will be described in which data of burst lengths 1, 2, and 3 are transferred from the bus master onto the bus. The processes from S801 to S807 in FIG. 8 are the same as the processes from S501 to S507 in FIG.

  In S808, the bus arbitration unit 105 acquires the burst length of data in the data transfer from the bus master given the right to use the bus, and determines in S809 whether the burst length is larger than a predetermined value. In the second embodiment, a case where the predetermined value in S808 is “1” will be described as an example.

  FIG. 9 is a timing chart illustrating exemplary operations of the bus arbitration unit 105, the clock control unit 108, and the bus masters 102 to 104 according to the second embodiment.

  In the second embodiment, as a protocol for performing data transfer using the bus, the burst length value of the data transfer is set as the burst length signals 1 to 4 together with the timing at which the transfer request signals 1 to 4 are issued. It is transmitted to the arbitration unit 105.

  At timing T1 in FIG. 9, the bus arbitration unit 105 refers to the burst length signal 1 of the bus master 102 to which the right to use the bus is given, and confirms that the burst length of the bus master 102 is “1”. Thereby, in the branch of S809, the burst length “1” of the bus master 102 is not larger than the predetermined value “1” determined in advance, that is, not more than the predetermined value, so the process of increasing the frequency of S810 is performed. Skip to S811. Since the processing from S810 to S811 is the same as the processing from S508 to S509 in FIG. 5 in the first embodiment, description thereof will be omitted.

  When the data transfer in S811 is completed, the process proceeds to S812, where the burst length of the transfer from the bus master to which the right to use the bus is given is compared with the predetermined value. If the burst length is larger than the predetermined value, the process proceeds to S813. Otherwise, the process proceeds to S814. As a result, in the data transfer from the bus master 102 to which the right to use the bus is first given, the process proceeds to S814 without executing the process of returning the frequency of the clock signal in S813. The processing from S813 to S815 is the same as the processing from S510 to S512 in FIG.

  After the data transfer from the bus master 102 is completed in this way, at the timing T2 in FIG. 9, both the transfer request signal 2 and the transfer request signal 3 from the bus master 103 and the bus master 104 are turned on to compete. As a result of the arbitration by the bus arbitration unit 105, the bus master 103 is selected as a bus master to which a bus use right is given (S805, S807).

  At timing T2 in FIG. 9, the bus arbitration unit 105 refers to the burst length signal 2 of the bus master 103 to which the bus use right is given, and confirms that the burst length of the bus master 103 is “2” (S808). In the conditional branch of S809, since the burst length “2” of the bus master 103 is larger than “1” which is a predetermined number, the process proceeds to S810. In S810, the bus arbitration unit 105 turns on the frequency change request 2 for the bus master 103 to the clock control unit 108, issues “200” as the frequency change request 2, and increases the frequency of the clock signal 2. Set up.

  In this way, the data transfer from the bus master 103 to the bus slave 106 is executed in S811, and when this is completed, the burst length is compared with a predetermined value in S812. Here, since the burst length “2” of the bus master 103 is larger than “1” which is a predetermined number, the process proceeds to S813, and the bus arbitration unit 105 and the bus master 103 and the bus slave to which the right to use the bus is given. The frequency of the operation clock signal 106 is restored.

  Next, at timing T3 in FIG. 9, only the transfer request signal 3 from the bus master 104 is turned on. In this case, since the transfer requests are not competing, the bus arbitration unit 105 selects the bus master 104 as the bus master to which the right to use the bus is given (S806).

  Accordingly, at timing T3 in FIG. 9, the bus arbitration unit 105 refers to the burst length signal 3 for the bus master 104 to which the right to use the bus is given, and confirms that the burst length of the bus master 104 is “3”. (S808). In this case, since the burst length “3” of the bus master 103 is greater than the predetermined number “1” in the conditional branch of S809, the process proceeds to S810. In S810, the bus arbitration unit 105 turns on the frequency change request 3 for the bus master 104 to the clock control unit 108, issues "200" as the frequency change request 3, and increases the frequency of the clock signal 3. Set. In this way, data transfer from the bus master 104 to the bus slave 106 is executed in S811, and when this is completed, the burst length is compared with a predetermined value in S812. Here, since the burst length “3” of the bus master 104 is larger than the predetermined number “1”, the process proceeds to S813, and the bus arbitration unit 105 and the bus master 104 and the bus slave to which the right to use the bus is given. The frequency of the operation clock signal 106 is restored. Then, the process proceeds to S814, and if the bus arbitration unit 105 determines that the data transfer by all the bus masters that have issued the transfer request has been completed, this process ends.

  As described above, according to the second embodiment, when the burst length of data to be transferred is smaller than a predetermined value, the frequency of the clock signal supplied to the bus master that performs the data transfer is not changed. In other words, if the amount of data transfer is small and the time required for the entire data transfer is shortened without changing the frequency of the clock signal, the frequency of the clock signal of the bus master related to the data transfer is changed to a higher frequency. Do not. Thus, there is an effect that the dynamic power consumption at the time of data transfer can be reduced while considering the entire data transfer time.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

  The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, in order to make the scope of the present invention public, the following claims are attached.

  DESCRIPTION OF SYMBOLS 101 ... CPU, 102-104 ... Bus master, 105 ... Bus arbitrator, 106 ... Bus slave, 107 ... Reference clock generator, 108 ... Clock controller

Claims (13)

Multiple bus masters that output access requests;
Arbitration means for arbitrating access requests from the plurality of bus masters and receiving access requests from the bus masters;
The frequency of the clock signal supplied to the first bus master for which the access request has been accepted by the arbitration means is the first frequency, and the frequency of the clock signal supplied to the bus masters other than the first bus master among the plurality of bus masters is the first frequency. Clock control means having a second frequency lower than one frequency;
A bus control device comprising: The clock control means includes
A plurality of frequency dividing means for generating a plurality of clock signals having different frequencies from the reference clock signal;
Selecting means for selecting one of the plurality of clock signals based on frequency information from the arbitrating means;
The bus control device according to claim 1, comprising:   The selection means includes a multiplexer for inputting the plurality of clock signals output from the plurality of frequency dividing means, and the multiplexer is in response to a selection signal generated based on frequency information from the arbitration means, The bus control device according to claim 2, wherein one of the plurality of clock signals is selected.   The arbitration unit determines a bus master that receives an access request according to a variable priority method when access requests from the plurality of bus masters compete with each other. The bus control device described.   The arbitration unit determines a bus master that receives an access request in the order of arrival of the access requests when access requests from the plurality of bus masters compete with each other. Bus control device.   3. The bus control device according to claim 2, wherein the arbitration unit outputs a frequency change request of the clock signal supplied to the bus master that receives the access request and the frequency information to the clock control unit.   The arbitration means further controls the clock control means so as to lower the frequency of the clock signal supplied to the bus master that has completed the processing accompanying the access request from the first frequency to the second frequency. The bus control device according to any one of claims 1 to 6.   The arbitration means further supplies the clock control means to the first bus master from which the access request has been accepted by the arbitration means when the amount of data transferred in the data transfer accompanying the access request is less than or equal to a predetermined value. 2. The bus control device according to claim 1, wherein control is performed so as not to change a frequency of the clock signal.   9. The bus control device according to claim 8, wherein the data amount is a burst length of data transferred by the data transfer.   10. The clock control unit according to claim 1, wherein the clock control means further sets the frequency of a clock signal supplied to a bus slave that receives data transferred from the first bus master as the first frequency. The bus control device described in 1.   The arbitration unit further controls the clock control unit to lower the frequency of the clock signal supplied to the bus slave from the first frequency to the second frequency when the data transfer accompanying the access request is completed. The bus control device according to claim 10.   3. The bus control device according to claim 2, wherein the clock control unit further includes a PLL synchronization control unit that generates a clock signal synchronized with a phase of the reference clock signal. A control method of a bus control device that controls access requests from a plurality of bus masters that output access requests,
Arbitration means arbitrates access requests from the plurality of bus masters, and receives an access request from the bus master; and
The clock control means sets the frequency of the clock signal supplied to the first bus master for which the access request is accepted in the arbitration step as the first frequency, and the clock signal supplied to the bus masters other than the first bus master among the plurality of bus masters A clock control step of setting the frequency of the second frequency lower than the first frequency;
A control method for a bus control device comprising:

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