JP2018060981A - Semiconductor device - Google Patents

Abstract

Semiconductor device in which "FET region and diode region and peripheral breakdown voltage region", "FET region and diode region", "FET region and peripheral breakdown voltage region" or "diode region and peripheral breakdown voltage region" are formed in a common semiconductor substrate In this case, electric field concentration tends to occur around the p-type region extending in the boundary region. An n-type impurity low concentration region having an impurity concentration lower than that of an n-type drift layer is provided in a boundary region. A p-type region extending from the adjacent region into the boundary region is in contact with the n-type impurity low concentration region. [Selection] Figure 1

Description

  The present specification discloses a semiconductor device.

  As disclosed in Patent Document 1, combinations of various regions on a common semiconductor substrate, for example, “a combination of an FET region, a diode region, and a peripheral breakdown voltage region”, “a combination of an FET region and a diode region”, “FET region” And “peripheral breakdown voltage region combination” or “diode region and peripheral breakdown voltage region combination” may be formed.

  A p-type region serving as a body region is formed in the FET region. Electric field concentration is likely to occur around the p-type region extending from the FET region to the “boundary region located between the FET region and the diode region” or from the FET region to the “boundary region located between the FET region and the peripheral breakdown voltage region”. .

  A p-type region serving as a guard ring or a RESURF layer is formed in the peripheral withstand voltage region. Electric field concentration around the p-type region extending from the peripheral withstand voltage region to the “boundary region located between the peripheral withstand voltage region and the FET region” or from the peripheral withstand voltage region to the “boundary region located between the peripheral withstand voltage region and the diode region” Is likely to occur.

  Among the diodes, there are diodes using a p-type region, such as a JBS diode (Junction Barrier Schottky Diode) or an MPS diode (Merged PIN Schottky Diode). In the case of a diode using a p-type region, the p extending from the diode region to the “boundary region located between the diode region and the FET region” or from the diode region to the “boundary region located between the diode region and the peripheral breakdown voltage region”. Electric field concentration tends to occur around the mold region.

JP 2002-373890 A

  The present specification discloses a technique for alleviating electric field concentration that tends to occur around a p-type region extending into a boundary region from a region adjacent to the boundary region (that is, an FET region, a diode region, or a peripheral breakdown voltage region).

  In the semiconductor device disclosed in this specification, in a common semiconductor substrate, “a combination of an FET region, a diode region, and a peripheral breakdown voltage region”, “a combination of an FET region and a diode region”, and “a combination of an FET region and a peripheral breakdown voltage region”. Alternatively, either “a combination of a diode region and a peripheral breakdown voltage region” is formed. In this semiconductor device, “a boundary region positioned between the FET region and the diode region”, “a boundary region positioned between the FET region and the peripheral breakdown voltage region”, “a boundary region positioned between the diode region and the peripheral breakdown voltage region” An n-type impurity low concentration region having an impurity concentration lower than that of the n-type drift layer is added to any of the above. Further, the p-type region extending from the adjacent region (that is, any one of the FET region, the diode region, and the peripheral withstand voltage region) into the boundary region is in contact with the n-type impurity low concentration region.

If an n-type impurity low-concentration region having an impurity concentration lower than that of the n-type drift layer is added to the boundary region, a depletion layer spreads over a wide range of the n-type impurity low-concentration region when the semiconductor device is turned off. The distortion is corrected. That is, electric field concentration hardly occurs in the n-type impurity low concentration region.
In the semiconductor device disclosed in this specification, since an n-type impurity low-concentration region is arranged around a region where electric field concentration is likely to occur, that is, a p-type region extending from an adjacent region into a boundary region, electric field concentration. Is unlikely to occur.

1 is a longitudinal sectional view of a semiconductor device of Example 1. FIG. FIG. 5 is a longitudinal sectional view of a semiconductor device according to a second embodiment. FIG. 6 is a plan view of a semiconductor device according to Example 3. FIG. 4 is a sectional view taken along line IV-IV in FIG. 3. FIG. 5 is a sectional view taken along line VV in FIG. 3.

Features of the embodiments described below are listed (Feature 1) An n-type impurity low concentration region is formed in a boundary region located between the FET region and the diode region having the p-type region. The p-type body region of the FET and the p-type region of the diode are in contact with the n-type impurity low concentration region.
(Feature 2) An n-type impurity low concentration region is formed in a boundary region located between the FET region and the peripheral breakdown voltage region. The p-type body region of the FET and the p-type region for peripheral breakdown voltage are in contact with the n-type impurity low concentration region.
(Feature 3) An n-type impurity low concentration region is formed in a boundary region located between the diode region having the p-type region and the peripheral breakdown voltage region. The p-type region of the diode and the p-type region for peripheral breakdown voltage are in contact with the n-type impurity low concentration region.
(Feature 4) An n-type impurity low concentration region is formed in a boundary region located between the FET region and the diode region. The p-type body region of the FET is in contact with the n-type impurity low concentration region.
(Feature 5) An n-type impurity low concentration region is formed in a boundary region located between the diode region and the peripheral breakdown voltage region. The peripheral breakdown voltage p-type region is in contact with the n-type impurity low concentration region.
(Feature 6) The n-type impurity low concentration region penetrates the drift layer.
(Feature 7) The n-type impurity low concentration region penetrates the drift layer and is in contact with the n ⁺ type drain / cathode layer having a higher concentration than the drift layer.
(Feature 8) Of the trench gate electrodes constituting the FET, the bottom surface of the trench gate electrode adjacent to the boundary region is located in the n-type impurity low concentration region.
(Characteristic 9) The p-type region that goes around the formation range of the trench gate electrode is located in the n-type impurity low concentration region.
(Feature 10) The end of the Schottky electrode is located within the formation range of the n-type impurity low concentration region.
(Feature 11) The FET is either a MOSFET, a MISFET, or an IGBT.

(Example 1)
FIG. 1 shows a part of a cross section of the semiconductor device according to the first embodiment. In the drawing, A indicates an FET region, C indicates a diode region, E indicates a peripheral breakdown voltage region, B indicates a boundary region located between the FET region and the diode region, and D indicates a diode region and the peripheral breakdown voltage region. A boundary region located between them is shown. The actual cross section extends leftward from FIG. 1, and the FET region A extends leftward in FIG. When the semiconductor substrate 4 is viewed in plan, the FET region A is formed in the central region of the semiconductor substrate 4, the diode region C is formed in a range that goes around the FET region A, and the peripheral withstand voltage region E is the diode region. It is formed in a range that goes around C (region extending along the outer periphery of the outer periphery of the semiconductor substrate 4). When the entire cross section of FIG. 1 is observed, the regions B, C, D, and E are symmetrical with respect to the center line of the region A. In this specification, the side close to the central region of the semiconductor substrate is referred to as the inside, and the side close to the peripheral region is referred to as the outside.

  A lower electrode (drain / cathode electrode) 2 is formed on the lower surface of the semiconductor substrate 4. The range facing the lower surface of the semiconductor substrate 4 is the drain / cathode layer 6 containing n-type impurities at a high concentration. The drain / cathode layer 6 and the drain / cathode electrode 2 are in ohmic contact.

  A portion of the semiconductor substrate 4 other than the drain / cathode layer 6 and a body region 10 to be described later contains an n-type impurity at a medium concentration and forms an n-type drift layer 8. The semiconductor substrate 4 before processing contains an n-type impurity having a concentration suitable for operating as the n-type drift layer 8.

The drain / cathode layer 6 is a region in which n-type impurities are implanted and diffused from the lower surface of the semiconductor substrate 4 before processing.
On the upper surface side of the semiconductor substrate 4 in the FET region A, a region is formed by injecting and diffusing p-type impurities from the upper surface of the semiconductor substrate 4 before processing. This region is formed in a part of the range facing the upper surface of the semiconductor substrate 4 and functions as the p-type body region 10. Of the semiconductor substrate 4, regions other than the drain / cathode layer 6 and the p-type body region 10 are left unprocessed, and operate as the n-type drift layer 8.

  The p-type impurity concentration of the p-type body region 10 is low, and the ohmic contact with the source electrode 16a described later is not made as it is. A contact region 12 having a high p-type impurity concentration is formed in a part of the p-type body region 10 and facing the upper surface of the semiconductor substrate 4. Contact region 12 is in ohmic contact with source electrode 16a. The potential of p type body region 10 is maintained equal to the potential of source electrode 16a.

A source region 14 containing an n-type impurity at a high concentration is formed in a part of the p-type body region 10. The source region 14 is formed in a range facing the upper surface of the semiconductor substrate 4 and is in ohmic contact with the source electrode 16a.
The p-type body region 10, the contact region 12, and the source region 14 extend in a direction perpendicular to the paper surface.

  N-type source region 14 and n-type drift layer 8 are separated by p-type body region 10. A gate insulating film 18 is formed on the upper surface of the p-type body region 10 that separates the n-type source region 14 and the n-type drift layer 8, and a gate electrode 20 is formed on the upper surface. The gate electrode 20 and the source electrode 16a are insulated by an interlayer insulating film (not shown). A gate electrode 20 is opposed to the p-type body region 10 that separates the n-type source region 14 and the n-type drift layer 8 through a gate insulating film 18.

  While no positive voltage is applied to the gate electrode 20, the n-type source region 14 and the n-type drift layer 8 are insulated from each other by the p-type body region 10, and no current flows between the source electrode 16 a and the drain / cathode electrode 2. Not flowing. While a positive voltage is applied to the gate electrode 20, an inversion layer is formed in the p-type body region 10 that separates the n-type source region 14 and the n-type drift layer 8, and the n-type source region 14 and the n-type drift layer 8. The resistance is low. When the semiconductor device is used, the source electrode 16a is grounded, and the drain / cathode electrode 2 is connected to a positive potential. While a positive voltage is applied to the gate electrode 20, a current flows between the source electrode 16 a and the drain / cathode electrode 2. An FET (Field Effect Transistor) is even formed between the drain / cathode electrode 2 and the source electrode 16a. The FET may be a MOS type or a MIS type.

  A Schottky electrode 16 b is formed on the upper surface of the semiconductor substrate 4 in the diode region C. Schottky electrode 16b is formed of a metal that is in Schottky contact with n-type drift layer 8. In a region facing the upper surface of the semiconductor substrate 4 in the diode region C, p-type diffusion regions 22 are formed at a constant pitch. The p-type diffusion region 22 extends in the direction perpendicular to the paper surface.

  When a high potential is applied to the source electrode 16a, a current flows from the source electrode 16a to the drain / cathode electrode 2. When a reverse voltage is applied to the Schottky diode (the source electrode 16a is grounded and the drain / cathode electrode 2 is connected to a positive potential), the Schottky diode is positioned between adjacent p-type diffusion regions 22. A depletion layer extends to the n-type drift layer 8 so that no current flows. The p-type diffusion region 22 improves the withstand voltage capability of the Schottky diode.

  Multiple p-type guard rings 24 are formed in the peripheral breakdown voltage region E. A field plate 16c is formed on the uppermost guard ring 24a. The p-type guard ring 24 extends a depletion layer around the semiconductor substrate 4 and increases the breakdown voltage of the semiconductor device. An interlayer insulating film may be disposed between the field plate 16 c and the semiconductor substrate 4. The field plate 16c, the Schottky electrode 16b, and the source electrode 16a are electrically connected. The field plate 16 c, the Schottky electrode 16 b, and the source electrode 16 a can be formed by upper surface electrodes formed on the upper surface of the semiconductor substrate 4.

  In a boundary region B located between the FET region A and the diode region C, an n-type impurity low concentration region 30 is formed. The n-type impurity low concentration region 30 is an n-type region having an impurity concentration lower than that of the n-type drift layer 8.

  The p-type body region 10 a located closest to the diode region C extends from the FET region A into the boundary region B. An end portion in the boundary region B of the p-type body region 10 a is in contact with the n-type impurity low concentration region 30. The vicinity of the end portion in the boundary region B of the p-type body region 10a is a portion where electric field concentration is likely to occur. In the present embodiment, since the n-type impurity low concentration region 30 is formed at that portion, the electric field concentration hardly occurs.

  The p-type diffusion region 22 a located closest to the FET region A extends from the diode region C into the boundary region B. An end portion in the boundary region B of the p-type diffusion region 22 a is in contact with the n-type impurity low concentration region 30. The vicinity of the end portion in the boundary region B of the p-type diffusion region 22a is a portion where electric field concentration is likely to occur. In the present embodiment, since the n-type impurity low concentration region 30 is formed at that portion, the electric field concentration hardly occurs.

  In the boundary region D located between the diode region C and the peripheral breakdown voltage region E, an n-type impurity low concentration region 32 is formed. The n-type impurity low concentration region 32 is an n-type region having an impurity concentration lower than that of the n-type drift layer 8.

  The p-type diffusion region 22 b located closest to the peripheral breakdown voltage region E side extends from the diode region C into the boundary region D. The lower end portion in the boundary region D of the p-type diffusion region 22 b is in contact with the n-type impurity low concentration region 32. The vicinity of the lower end in the boundary region D of the p-type diffusion region 22b is a region where electric field concentration is likely to occur. In the present embodiment, since the n-type impurity low concentration region 32 is formed at that portion, the electric field concentration hardly occurs.

  The p-type guard ring 24 a located closest to the diode region C extends from the peripheral withstand voltage region E into the boundary region D. The lower end portion in the boundary region D of the p-type guard ring 24 a is in contact with the n-type impurity low concentration region 32. The vicinity of the lower end portion in the boundary region D of the p-type guard ring 22ba is a portion where electric field concentration is likely to occur. In the present embodiment, since the n-type impurity low concentration region 32 is formed at that portion, the electric field concentration hardly occurs.

  The left end portion of the boundary region B is not necessarily determined uniquely, but an inversion layer is formed on the left side of the left end portion of the rightmost source region 14a. Since the inversion layer is not formed on the right side of the right end of the contact region 12a, it is not an FET region. The left end portion of the boundary region B is located anywhere between the left end portion of the rightmost source region 14a and the right end portion of the rightmost contact region 12a. In FIG. 1, the right end of the rightmost source electrode is the left end of the boundary region B. The left end portion of the boundary region B shown in FIG. 1 is between the left end portion of the rightmost source region 14a and the right end portion of the rightmost contact region 12a. Regardless of how the end of the boundary region B is defined, the rightmost p-type body region 10 a extends from the FET region A into the boundary region B and is in contact with the n-type impurity low concentration region 30.

  The right end portion of the boundary region B is located between the left end portion and the right end portion of the leftmost p-type diffusion region 22a. In FIG. 1, the left end of the Schottky electrode 16b is the right end of the boundary region B. The right end portion of the boundary region B shown in FIG. 1 is between the left end portion and the right end portion of the leftmost p-type diffusion region 22a. Regardless of how the right end portion of the boundary region B is defined, the leftmost p-type diffusion region 22 a extends from the diode region C into the boundary region B and is in contact with the n-type impurity low concentration region 30.

  The left end portion of the boundary region D is anywhere between the left end portion and the right end portion of the rightmost p-type diffusion region 22b. In FIG. 1, the right end of the Schottky electrode 16 b is the left end portion of the boundary region D. The left end portion of the boundary region D shown in FIG. 1 is between the left end portion and the right end portion of the rightmost p-type diffusion region 22a. Regardless of how the left end portion of the boundary region D is defined, the rightmost p-type diffusion region 22 a extends from the diode region C into the boundary region D and is in contact with the n-type impurity low concentration region 32.

  The right end portion of the boundary region D is located between the left end portion and the right end portion of the leftmost p-type guard ring 24a. In FIG. 1, the left end of the field plate 16 c is the right end of the boundary region D. The left end portion of the boundary region D shown in FIG. 1 is between the left end portion and the right end portion of the leftmost p-type guard ring 24a. Regardless of how the right end of the boundary region D is defined, the leftmost p-type guard ring 24 a extends from the peripheral breakdown voltage region E into the boundary region D and is in contact with the n-type impurity low concentration region 32.

  The rightmost p-type diffusion region 22 b and the leftmost p-type guard ring 24 a are in contact with each other within the formation range of the n-type impurity low concentration region 32. Electric field concentration tends to occur near the position where the p-type diffusion region 22b and the p-type guard ring 24a are in contact with each other. In this embodiment, the n-type impurity low concentration region 32 is arranged at a position where electric field concentration is likely to occur, and electric field concentration is difficult to occur.

In this embodiment, a diode region C exists between the FET region A and the peripheral breakdown voltage region E. The technique disclosed in this specification is also effective when the FET region A and the peripheral withstand voltage region E are adjacent to each other. An n-type impurity low-concentration region is provided in a boundary region located between the FET region and the peripheral breakdown voltage region, and a p-type region extending from the FET region to the boundary region is in contact with the n-type impurity low-concentration region. If the p-type region extending in contact with the n-type impurity low concentration region is relaxed, the electric field concentration is reduced.
When electric field concentration occurs, the withstand voltage of the semiconductor device decreases, and current may concentrate during avalanche breakdown, causing the semiconductor device to be thermally destroyed. The techniques described herein can address that problem.

  In the above description, the range of the boundary regions B and D has been described as the formation range of the source electrode 16a, the Schottky electrode 16b, and the field plate 16c. Instead of the above, the boundary regions B and D may be determined from the formation region of the body region 10, the formation region of the source region 14, the formation region of the p-type diffusion region 22, and the formation region of the p-type guard ring 24. . The technique described in the present specification is not limited to the method of determining the boundary regions B and D.

(Example 2)
A second embodiment will be described with reference to FIG. Components common to the members / parts described are given the same reference numerals, and redundant description is omitted. Only the differences from the first embodiment will be described below.

Difference 1: The FET of Example 1 was a monopolar transistor. The FET of Example 2 is a bipolar transistor, which is a so-called IGBT. A monopolar transistor is called an FET and may be distinguished from a bipolar IGBT. In this specification, transistors that switch using an insulated gate are collectively called an FET. According to the definition, IGBT is also a kind of FET. In the second embodiment, in the transistor region, a collector region 5 containing a p-type impurity at a high concentration is added at a position in contact with the lower surface electrode 2. Due to the difference between monopolar and bipolar, the bottom electrode 2 of Example 2 is a collector and cathode electrode, the n-type region 14 is an emitter region, and the top electrode 16a is an emitter electrode. The n-type impurity high concentration layer 6 serves as both a buffer region and a cathode layer.
Difference 2: The diode of Example 2 does not include a p-type diffusion region (22 in FIG. 1) that increases the breakdown voltage.
Difference 3: The n-type impurity low-concentration regions 30a and 32a penetrate the n-type drift layer 8 and reach the n-type impurity high-concentration layer 6 that serves as both a buffer region and a cathode layer. Due to the difference 3, the effect of mitigating the electric field concentration is higher than that in the first embodiment.
In this embodiment, the n-type drift layer 8 is formed of SiC or a nitride semiconductor having a wider band gap than silicon. Therefore, the n-type drift layer 8 is shallower than in the case of silicon (in the embodiment, about 10 μm), and the n-type impurity low concentration regions 30a and 32a penetrating the drift layer 8 are easy to manufacture. A technique for providing the n-type impurity low concentration regions 30a and 32a penetrating the drift layer 8 is a wide gap semiconductor (having a band gap of about 2.2 eV or more. III-V group semiconductor such as nitride semiconductor, silicon carbide, etc. This is particularly useful when applied to diamond.
Difference 4: The left end portion of the Schottky electrode 16b is located within the formation range of the n-type impurity low concentration region 30a, and the right end portion of the Schottky electrode 16b is located within the formation range of the n-type impurity low concentration region 32a. doing. The difference 4 addresses the problem that electric field concentration tends to occur near the end of the Schottky electrode 16b.

  In Example 2, there is no p-type region in the diode region. Therefore, there is no restriction on the relationship between the p-type region in the diode region and the n-type impurity low concentration region 30a, or the relationship between the p-type region in the diode region and the n-type impurity low concentration region 32a. If the p-type body region 10a in the transistor region on the boundary region side is in contact with the n-type impurity low-concentration region 30a, the problem that electric field concentration tends to occur near the p-type body region 10a can be dealt with. If the n-type impurity low concentration region 32a is in contact with the p-type guard ring 24a in the peripheral breakdown voltage region on the boundary region side, it is possible to cope with the problem that electric field concentration is likely to occur in the vicinity of the p-type guard ring 24a.

  Also in Example 2, a diode region exists between the transistor region and the peripheral breakdown voltage region. The technique disclosed in this specification is also effective when the transistor region and the peripheral breakdown voltage region are adjacent to each other. An n-type impurity low concentration region is provided in the boundary region, a p-type region extending from the transistor region to the boundary region is in contact with the n-type impurity low concentration region, and a p-type region extending from the peripheral breakdown voltage region to the boundary region is the n-type impurity low concentration region If it is in contact with, the electric field concentration is reduced.

(Example 3)
Embodiment 3 will be described with reference to FIGS. 4 shows the IV-IV cross section of FIG. 3, and FIG. 5 shows the VV cross section of FIG. Components having the same members / parts as described are denoted by the same reference numerals, and redundant description is omitted. Only the differences from the first and second embodiments will be described below.
Difference 1: The FETs of Examples 1 and 2 were planar gates. The FET of Example 3 is a trench gate type transistor. In Example 3, it is monopolar, but it may be bipolar. 4 and 5, 20 a is a trench gate electrode, and 18 a is a trench gate insulating film that covers the inner surface of the trench and insulates the trench gate electrode 20 a from the semiconductor substrate 4. As shown in FIGS. 4 and 5, p-type region 11 is formed along the outer periphery of body region 10. The p-type region 11 is formed deeper than the body region and covers the longitudinal end of the trench gate electrode 20a as shown in FIG. The p-type region 11 makes a round of the trench formation range when the semiconductor substrate is viewed in plan. The p-type region 11 is formed inside the n-type impurity low concentration region 30a formed in the boundary region. It deals with electric field concentration that tends to occur in the vicinity of the p-type region 11.
Difference 2: A RESURF structure is formed in the peripheral withstand voltage region instead of the guard ring. The RESURF structure is formed of a plurality of p-type regions 26a, 26b, and 26c. It is formed as shallow as possible with a low concentration. The end of the inner p-type layer on the boundary region side is located inside the n-type impurity low concentration region 32a.
Difference 3: Of the trench gate electrode 20a, the bottom surface of the trench gate electrode adjacent to the boundary region is located in the n-type impurity low concentration region 30a. This prevents electric field concentration from occurring near the bottom surface of the trench gate electrode adjacent to the boundary region, where electric field concentration is likely to occur.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Bottom electrode (drain / cathode electrode, collector / cathode electrode)
4: Semiconductor substrate 5: Collector region 6: High concentration layer of n-type impurity (drain layer, buffer layer, cathode region)
8: n-type impurity medium concentration layer (drift layer)
10: body region 11: p-type region 12: contact region 14: source region (emitter region)
16: Upper surface electrode 16a: Source electrode (emitter electrode)
16b: Schottky electrode 16c: field plate 18: gate insulating film 20: gate electrode 22: p-type diffusion region 24: guard ring 26: RESURF layer 30, 30a: n-type impurity low concentration region 32, 32a: n-type impurity low Concentration area

Claims (1)

Within the common semiconductor substrate, a combination of “FET region and diode region and peripheral breakdown voltage region”, “FET region and diode region”, “FET region and peripheral breakdown region”, “diode region and peripheral breakdown region” A semiconductor device in which any combination of combinations is formed,
An n-type impurity low concentration region having an impurity concentration lower than that of the n-type drift layer is added to the boundary region,
A p-type region extending into the boundary region is in contact with the n-type impurity low concentration region.

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