JP2018042117A - Oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of outputting a rectangular wave having a stable oscillation frequency. SOLUTION: A series circuit in which two voltage output type inverter circuits are connected in series, one current output type inverter circuit connected in a ring shape to the series circuit, and an input / output terminal of the series circuit. A first capacitor provided between them and a second capacitor provided between the output terminal and the ground terminal of the current output type inverter circuit are provided. Further, a current adjusting circuit for adjusting the current of the current output type inverter circuit to change the oscillation frequency is provided. [Selection diagram] Fig. 2

Description

  The present invention relates to an oscillation circuit that can output a rectangular wave having a stable oscillation frequency.

  Various semiconductor integrated circuits are often provided with an oscillation circuit that generates a rectangular wave having a constant frequency for use in setting the time within the semiconductor integrated circuit. FIG. 5 shows a configuration example of a so-called ring type oscillation circuit OSC in which [2n + 1] (n is a natural number), generally three inverter circuits INV1, INV2, and INV3 are connected in a ring shape.

  The oscillation circuit OSC feeds back an output signal of a series circuit including an odd number (three) of inverter circuits INV1, INV2, and INV3 to the input side. The oscillation circuit OSC generates an oscillation output signal OUT composed of a rectangular wave by using the operation delay time (gate delay time) of each inverter circuit INV1, INV2, INV3. Therefore, the oscillation frequency of the oscillation circuit OSC is determined solely by the operation delay times of the inverter circuits INV1, INV2, and INV3.

  Conventionally, in order to stabilize the oscillation frequency in this type of oscillation circuit OSC, it has been proposed to drive the inverter circuits INV1, INV2, and INV3 with a constant current as disclosed in Patent Document 1, for example. Patent Document 1 also discloses that a control current is superimposed on a constant current that drives inverter circuits INV1, INV2, and INV3, and the oscillation frequency is changed by changing the magnitude of the control current.

  On the other hand, in Patent Document 2, an odd number of constant current inverters (current-driven inverter circuits) connected in a ring shape, a capacitor connected between an output terminal and a ground terminal of a predetermined constant current inverter, And a ring-type oscillation circuit that determines an oscillation frequency by using a delay time associated with charging and discharging of a capacitor. Patent Document 2 discloses that the delay time due to the capacitor is shortened and the oscillation frequency is increased by increasing the current passed through a predetermined constant current inverter during the test.

JP 2012-191275 A JP 2001-268810 A

  By the way, the oscillation frequency in the ring type oscillation circuit described above is determined exclusively by the operation delay time (gate delay time) of the inverter circuits INV1, INV2, and INV3, as described above. In the oscillation circuit disclosed in Patent Document 2, the oscillation frequency is determined by the operation delay time of the inverter circuits INV1, INV2, and INV3 and a capacitor as a delay element.

  For this reason, in the conventional ring-type oscillation circuit, the oscillation frequency is likely to vary due to a shift in the operation delay time depending on the characteristics of the circuit elements constituting the inverter circuits INV1, INV2, and INV3. In addition, the constant current inverters as shown in Patent Documents 1 and 2, respectively, are driven by constant current driving an inverting circuit composed of, for example, a pair of MOS-FETs that are cascade-connected and turned on and off, and the level of the output voltage. Is reversed. For this reason, even if a ring-type oscillation circuit is configured using a constant current inverter, there is a problem that it is generally difficult to increase the variable setting width of the oscillation frequency.

  The present invention has been made in consideration of such circumstances, and an object thereof is to provide an oscillation circuit capable of outputting a rectangular wave having a stable oscillation frequency without depending on the operation delay time of a plurality of inverter circuits. It is to provide.

An oscillation circuit according to the present invention includes:
A series circuit composed of 2n (n is a natural number) voltage output type inverter circuits;
A current output type inverter circuit connected in a ring with this series circuit;
A first capacitor provided between the input and output terminals of the series circuit;
A second capacitor provided between an output terminal and a ground terminal of the current output type inverter circuit;
It is characterized by having.

  Incidentally, the first capacitor charges the second capacitor when the voltage value of the output terminal of the series circuit reaches the power supply voltage value, and the voltage when the voltage value of the output terminal reaches the ground potential. The second capacitor is discharged. Preferably, the first capacitor and the second capacitor have the same capacitance value.

  The voltage output type inverter circuit includes, for example, a P-channel type MOS-FET and an N-channel type MOS-FET which are connected in cascade between a power supply voltage terminal and a ground terminal and which are turned on and off in opposition to each other. Configured. The oscillation circuit preferably includes a current adjustment circuit that changes a current value of a constant current source for supplying a current to the current output type inverter circuit according to a control signal from the outside.

  Specifically, the current output type inverter circuit includes, for example, a first P-channel MOS-FET and an N-channel MOS-FET connected in cascade, and a first current that flows through the P-channel MOS-FET. And a second constant current source for supplying a current to the N-channel MOS-FET. Preferably, the first and second constant current sources are configured such that a current value flowing through the P-channel MOS-FET and a current value flowing through the N-channel MOS-FET are set equal to each other.

  Specifically, the first constant current source includes, for example, a first MOS-FET for current setting connected between the P-channel type MOS-FET and a power supply voltage terminal. The second constant current source is composed of, for example, a second MOS-FET for current setting connected between the N-channel type MOS-FET and a ground terminal.

  The current adjustment circuit plays a role of adjusting the current value input and output by the current output type inverter circuit to change the oscillation frequency.

  Here, for example, if the current values of the currents input and output by the current output type inverter circuit are set equal to each other, the input voltage of the series circuit is symmetrical with the voltage value of (1/2) of the power supply voltage as a threshold value It can be reversed quickly with good quality. Therefore, a rectangular wave with a duty of 50% can be stably generated as the output of the oscillation circuit.

  In the oscillation circuit according to the present invention, the oscillation output frequency of the oscillation circuit can be easily changed, for example, by variably setting the current value of the current input / output by the current output type inverter circuit.

  According to the oscillation circuit of the present invention having the above configuration, when the oscillation frequency is determined by the capacitance values of the first and second capacitors and the current value of the current input and output by the current output type inverter circuit It can be determined as a constant. Therefore, the oscillation frequency of the oscillation circuit can be stabilized.

  According to the oscillation circuit of the present invention, the input voltage of the series circuit is changed to the power supply voltage in accordance with the change in the output voltage value of the series circuit by using the charge and discharge of the first and second capacitors. Can be switched to the voltage value or the ground potential. Therefore, a rectangular wave that fully swings between the voltage value of the power supply voltage and the ground potential can be stably generated as the output voltage value of the series circuit.

1 is a schematic configuration diagram of an oscillation circuit according to an embodiment of the present invention. The figure which shows the specific structural example of the oscillation circuit which concerns on one Embodiment of this invention. FIG. 3 is a voltage waveform diagram for explaining the operation of the oscillation circuit shown in FIG. 2. The figure which shows the mode of a change of the oscillation frequency when changing the output current of the current output type inverter circuit in the oscillation circuit which concerns on this invention. The figure which shows the structural example of the conventional general ring-type oscillation circuit.

  Hereinafter, an oscillation circuit according to an embodiment of the present invention will be described with reference to the drawings. This oscillation circuit is basically configured by connecting [2n + 1] (n is a natural number) inverter circuits that invert and output the level of the input voltage in a ring shape.

  FIG. 1 is a schematic configuration diagram of an oscillation circuit OSC according to an embodiment of the present invention. The oscillation circuit OSC is configured by connecting three inverter circuits INV1, INV2, and INV3 in a ring shape. Incidentally, the first inverter circuit INV1 is of a current output type, and the second and third inverter circuits INV2 and INV3 are of voltage output type.

  Specifically, the oscillation circuit OSC according to the present invention includes a series circuit in which voltage output type second and third inverter circuits INV2 and INV3 are connected in series. The oscillation circuit OSC includes a first capacitor C1 that feeds back the output voltage V3 of the third inverter circuit INV3 in the series circuit to the input terminal of the second inverter circuit INV2. Furthermore, the oscillation circuit OSC includes a second capacitor C2 provided between the input terminal of the second inverter circuit INV2, which is the input terminal of the series circuit, and the ground terminal.

  The current output type first inverter circuit INV1 inputs and outputs a constant current according to the voltage value of the output voltage V3 of the third inverter circuit INV3 to charge and discharge the second capacitor C2. The charging voltage of the second capacitor C2 accompanying the charging / discharging of the second capacitor C2 is generated as the input voltage of the second inverter circuit INV2. The input voltage of the second inverter circuit INV2 can be equivalently regarded as the output voltage V1 of the first inverter circuit INV1.

  Here, the first inverter circuit INV1 of the current output type particularly includes the first and second constant current sources for generating the current input / output by the first inverter circuit INV1 according to the voltage value of the output voltage V3. I1 and I2 are provided. The first constant current source I1 regulates the current discharged from the output terminal of the first inverter circuit INV1 as a constant current value. The second constant current source I2 regulates the current that the first inverter circuit INV1 draws from its output terminal as a constant current value. This current output type first inverter circuit INV1 is introduced in Patent Documents 1 and 2 in that a constant current is inputted and outputted according to the voltage value of the output voltage V3 of the third inverter circuit INV3 as described above. This is different from the current driven constant current inverter.

  Specifically, the oscillation circuit OSC according to the present invention is configured, for example, as shown in FIG. That is, the voltage output type second inverter circuit INV2 includes a P-type MOS-FET (P2) and an N-type MOS-FET (N2) provided in cascade by connecting gates and drains, respectively. Configured. The source of the P-type MOS-FET (P2) is connected to the power supply voltage terminal to which the power supply voltage VDD is applied, and the source of the N-type MOS-FET (N2) is grounded at the ground potential GND (0 V). Connected to the terminal. Each gate of the P-type MOS-FET (P2) and the N-type MOS-FET (N2) constitutes an input terminal of the second inverter circuit INV2. The drains of the P-type MOS-FET (P2) and the N-type MOS-FET (N2) connected to each other constitute an output terminal of the second inverter circuit INV2.

  The P-type MOS-FET (P2) and the N-type MOS-FET (N2) are input with the voltage value of (1/2) of the power supply voltage VDD applied to the power supply voltage terminal as the inversion threshold (VDD / 2). Depending on the voltage value of the input voltage applied from the terminal to each gate, they are turned on and off in opposition to each other.

  Specifically, when the voltage value of the input voltage (the output voltage V1 of INV1 of the first inverter circuit) becomes higher than the inversion threshold value (VDD / 2), the second inverter circuit INV2 -The FET (P2) is turned off and the N-type MOS-FET (N2) is turned on, whereby the output voltage V2 is dropped to the ground potential GND. Further, when the voltage value of the input voltage (output voltage V1) is less than the inversion threshold value (VDD / 2), the second inverter circuit INV2 turns on the P-type MOS-FET (P2) and turns on the N-type The MOS-FET (N2) is turned off, thereby raising the voltage value of the output voltage V2 to the power supply voltage VDD. That is, the second inverter circuit INV2 obtains the output voltage V2 having a value corresponding to the voltage value of the input voltage (output voltage V1).

  Similarly, the voltage output type third inverter circuit INV3 includes a P-type MOS-FET (P3) and an N-type MOS-FET (N3) provided in cascade by connecting the gates and the drains respectively. Is done. The P-type MOS-FET (P3) and the N-type MOS-FET (N3) are connected between the power supply voltage terminal and the ground terminal in the same manner as the second inverter circuit INV2. Each gate of the P-type MOS-FET (P3) and the N-type MOS-FET (N3) connected in cascade constitutes an input terminal of the third inverter circuit INV3. The drains of the P-type MOS-FET (P3) and the N-type MOS-FET (N3) connected to each other constitute an output terminal of the third inverter circuit INV3.

  When the voltage value of the input voltage (the output voltage V2 of the second inverter circuit INV2) becomes higher than the inversion threshold value (VDD / 2), the third inverter circuit INV3 has a P-type MOS-FET ( P3) is turned off and the N-type MOS-FET (N3) is turned on. As a result, the third inverter circuit INV3 drops the output voltage V3 to the ground potential GND. When the voltage value of the input voltage (output voltage V2) is less than the inversion threshold value (VDD / 2), the third inverter circuit INV3 turns on the P-type MOS-FET (P3) and turns on the N-type The MOS-FET (N3) is turned off. As a result, the third inverter circuit INV3 raises the voltage value of the output voltage V3 to the power supply voltage VDD. That is, the third inverter circuit INV3 is configured to obtain an output voltage V3 obtained by inverting the level of the output voltage V2 in accordance with the voltage value of the input voltage (output voltage V2).

  On the other hand, the first inverter circuit INV1 of the current output type is provided in a cascade by connecting the gates and the drains respectively, and includes a P-type MOS-FET (P1) and an N-type MOS-FET (N1). Configured as the subject. Further, a first constant current source I1 that stabilizes the value of the current flowing through the P-type MOS-FET (P1) is connected in series between the source of the P-type MOS-FET (P1) and the power supply voltage terminal. . The first constant current source I1 is connected to the source of a P-type MOS-FET (P1), the drain thereof, and the P-type MOS-FET (with the source connected to a power supply voltage terminal to which a power supply voltage VDD is supplied) P4). The first constant current source I1 applies a current having a value set according to a bias voltage applied from the outside to the gate of the P-type MOS-FET (P4) between the source and drain of the P-type MOS-FET (P1). Play the role of flowing.

  A second constant current source I2 that stabilizes the value of the current flowing through the N-type MOS-FET (N1) is connected in series between the source of the N-type MOS-FET (N1) and the ground terminal. The second constant current source I2 includes an N-type MOS-FET (N4) having a drain connected to the source of the N-type MOS-FET (N1) and a source connected to the ground terminal. The second constant current source I2 supplies a current having a value set according to a bias voltage applied from the outside to the gate of the N-type MOS-FET (N4) between the source and drain of the N-type MOS-FET (N1). Play the role of flowing.

  By these first constant current source I1 and second constant current source I2, the values of the currents flowing in the P-type MOS-FET (P1) and the N-type MOS-FET (N1) which are turned on and off are constant. It becomes. The first inverter circuit INV1 turns off the P-type MOS-FET (P1) and turns off the N-type when the voltage value of the input voltage (output voltage V3) exceeds the inversion threshold value (VDD / 2). The MOS-FET (N1) is turned on. As the N-type MOS-FET (N1) is turned on, the output terminal of the first inverter circuit INV1 is grounded, and a constant current is sucked from the output terminal of the first inverter circuit INV1.

  The first inverter circuit INV1 turns on the P-type MOS-FET (P1) and turns on the N-type when the voltage value of the input voltage (output voltage V3) is less than the inversion threshold (VDD / 2). The MOS-FET (N1) is turned off. As a result, a constant current is discharged from the output terminal of the first inverter circuit INV1 through the P-type MOS-FET (P1). That is, the current output type first inverter circuit INV1 inputs (sucks) a constant output current from its output terminal or outputs a constant output current according to the voltage value of the input voltage (output voltage V3). It is comprised so that (it exhales).

  Incidentally, the first capacitor C1 basically has a difference between the voltage value of the voltage (output voltage V1) applied to the input terminal of the second inverter circuit INV2 and the voltage value of the output voltage V3 of the third inverter circuit INV3. Charge and discharge accordingly. By charging / discharging of the first capacitor C1, the output voltage V3 of the third inverter circuit INV3 is fed back to the input terminal of the second inverter circuit INV2. On the other hand, the second capacitor C2 is basically charged and discharged with a current input and output by the first inverter circuit INV1. The second capacitor C2 charges and discharges the first capacitor C1 according to the voltage difference between the charge voltage value and the output voltage V3 of the third inverter circuit INV3 fed back by the first capacitor C1. Assist. Incidentally, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are set to be equal to each other.

  FIG. 3 shows the voltage applied to the input terminal of the second inverter circuit INV2 (obtained from the first inverter circuit INV1) in the operation of the oscillation circuit OSC configured with the first and second capacitors C1 and C2. The output voltage V1) is shown as changes in the output voltages V2 and V3 of the second and third inverter circuits INV2 and INV3.

  In FIG. 3, in the section t1 where the voltage value of the output voltage V3 is at a low level (ground potential GND), the P-type MOS-FET (P1) in the first inverter circuit INV1 is turned on, and the N-type MOS-FET (N1) ) Turns off. Then, the first and second capacitors C1 and C2 are charged by the output current discharged from the first inverter circuit INV1, respectively. As a result, the voltage value of the output voltage V1 increases linearly with a time constant determined by the capacitance values of the first and second capacitors C1 and C2 and the output current value. When the voltage value of the output voltage V1 exceeds the inversion threshold value (VDD / 2), the level of the output voltage V2 of the second inverter circuit INV2 is inverted to become a low level (ground potential GND). The level of the output voltage V3 of the inverter circuit INV3 is inverted and becomes high level (power supply voltage VDD).

  Then, charging of the first and second capacitors C1 and C2 by the output current discharged from the first inverter circuit INV1 with the inversion of the level of the output voltage V3 is completed. At this time, the output voltage V3 of the inverter circuit INV3 is fed back to the input terminal of the second inverter circuit INV2. As a result, the potential at both ends of the first capacitor C1 increases with the inversion of the level of the output voltage V3. Then, the charge of the first capacitor C1 is discharged by the potential difference between the first capacitor C1 and the second capacitor C2, and the second capacitor C2 is rapidly charged by the discharge charge. As a result, as shown in FIG. 3, the voltage value of the output voltage V1 changes from the inversion threshold value (VDD / 2) to the power supply voltage VDD.

  On the other hand, in a section t2 where the voltage value of the output voltage V3 is at a high level (power supply voltage VDD), the P-type MOS-FET (P1) in the first inverter circuit INV1 is turned off, and the N-type MOS-FET (N1). Turns on. Then, the charge charges of the first and second capacitors C1 and C2 are respectively discharged by the output current drawn by the first inverter circuit INV1. As a result, the voltage value of the output voltage V1 linearly decreases with a time constant determined by the capacitance values of the first and second capacitors C1 and C2 and the output current value. When the voltage value of the output voltage V1 falls below the inversion threshold (VDD / 2), the level of the output voltage V2 of the second inverter circuit INV2 is inverted and becomes a high level (power supply voltage VDD). As a result, the level of the output voltage V3 of the third inverter circuit INV3 is inverted to become a low level (ground potential GND).

  Then, the discharge of the first and second capacitors C1 and C2 due to the output current sucked by the first inverter circuit INV1 with the inversion of the level of the output voltage V3 is completed. At this time, the output voltage V3 of the inverter circuit INV3 is fed back to the input terminal of the second inverter circuit INV2. As a result, the potential across the first capacitor C1 becomes lower as the level of the output voltage V3 is inverted. Then, the first capacitor C1 is charged by the potential difference between the first capacitor C1 and the second capacitor C2, and the second capacitor C2 is rapidly discharged by the charged charge. As a result, as shown in FIG. 3, the voltage value of the output voltage V1 changes from the inversion threshold (VDD / 2) to the ground potential GND.

  Therefore, in the oscillation circuit OSC according to the present embodiment, it changes linearly with a time constant determined by the value of the current input and output by the first inverter circuit INV1 and the capacitance values of the first and second capacitors C1 and C2. The level of the output voltage V3 is inverted at the timing when the voltage value of the output voltage V1 to be changed changes across the inversion threshold (VDD / 2). Here, the output voltage V3 inverted by the voltage value of the output voltage V1 changing across the inversion threshold (VDD / 2) is fed back to the input terminal of the second inverter circuit INV2 via the first capacitor C1. The As a result, sufficient charging / discharging between the first capacitor C1 and the second capacitor C2 is performed. Therefore, it is necessary and sufficient if the capacitance value c1 of the first capacitor C1 is the same as the capacitance value c2 of the second capacitor C2.

Incidentally, in a section t1 where the voltage value of the output voltage V3 is at a low level (ground potential GND), the current input and output by the first inverter circuit INV1 is I, and the capacitance values of the first and second capacitors C1 and C2 C1 and c2,
I = (c1 + c2) × (VDD / 2−GND) / t1
To t1 = (c1 + c2) × (VDD / 2) / I
As required.

The section t2 in which the voltage value of the output voltage V3 is at a high level (power supply voltage VDD)
I = (c1 + c2) × (VDD−VDD / 2) / t2
To t2 = (c1 + c2) × (VDD / 2) / I
As required.

Therefore, the period in which the voltage value of the output voltage V3 changes, that is, the oscillation frequency period t is
t = t1 + t2
= (C1 + c2) × (VDD / 2) / I
+ (C1 + c2) × (VDD / 2) / I
= 2 × (c1 + c2) × (VDD / 2) / I
It becomes.

  That is, the period t (= t1 + t2) of the oscillation frequency of the rectangular wave output by the oscillation circuit OSC is inversely proportional to the current value of the current I input / output by the first inverter circuit INV1, and the first and second capacitors C1, C2 Is proportional to the combined capacitance value (c1 + c2). In other words, the oscillation frequency of the oscillation circuit OSC is proportional to the current value of the current I input / output by the first inverter circuit INV1, and inversely proportional to the combined capacitance value (c1 + c2) of the first and second capacitors C1, C2. To do.

  Here, if the current input / output by the first inverter circuit INV1 has a proportional relationship, the oscillation frequency of the oscillation circuit OSC is proportional to the current value input / output by the first inverter circuit INV1 as described above. . However, in order to simplify the setting of circuit constants and the like, it is desirable to set the current values input and output by the first inverter circuit INV1 to be equal.

  Therefore, according to the oscillation circuit OSC according to the present invention, the oscillation frequency can be determined regardless of the operation delay time (gate delay time) of the first to third inverter circuits INV1, INV2, and INV3. That is, the current value of the current I input and output by the current output type first inverter circuit INV1 and the capacitance values c1 and c2 of the first and second capacitors C1 and C2 (combined capacitance value; c1 + c2) Thus, the oscillation frequency of the oscillation circuit OSC can be determined accurately and stably.

  Incidentally, since the first and second capacitors C1 and C2 are usually fixed on the circuit board forming the oscillation circuit OSC, it is generally difficult to change the capacitance values c1 and c2. . However, changing the magnitude of the current I input / output by the first inverter circuit INV1 by adjusting the bias current that sets the current value output from each of the first and second constant current sources I1 and I2 is a comparison. Easy.

  The current setting circuit CONT in FIG. 2 variably sets the value of the current I output from each of the first and second constant current sources I1 and I2 according to the voltage value of the control voltage Vin given from outside. The current setting circuit CONT is realized by, for example, a voltage / current conversion circuit. The current setting circuit CONT includes, for example, an NPN bipolar transistor TR that provides a resistor R1 between a ground terminal and an emitter, grounds the emitter, and determines an output current value according to the output of the operational amplifier OP. The operational amplifier OP inputs a voltage generated in the resistor R1 to the inverting input terminal according to the voltage value of the control voltage Vin given to the non-inverting input terminal and the value of the current flowing through the bipolar transistor TR. The operational amplifier OP controls the value of the current flowing in the bipolar transistor TR so that the voltage difference applied between these terminals becomes zero (0).

  In this way, the value of the current flowing through the bipolar transistor TR controlled by the operational amplifier OP is detected by the first current mirror circuit composed of P-type MOS-FETs (P6, P7) provided on the power supply voltage terminal side. The The first current mirror circuit then outputs a bias current that determines the value of the current flowing through the second constant current source I2 in the first inverter circuit INV1. Further, the current value detected by the first current mirror circuit is further detected by the second current mirror circuit composed of an N-type MOS-FET (N5, N6) provided on the ground potential GND side. The current value detected by the second current mirror circuit is applied to an output circuit composed of a P-type MOS-FET (P5) provided on the power supply voltage terminal side. This output circuit outputs a bias current that determines the value of the current flowing through the first constant current source I1 in the first inverter circuit INV1.

  If the element sizes of the MOS-FETs (P4, P5, P6, P7, N4, N5, N6) are set to be equal, the value of the current flowing through the first constant current source I1 and the second constant current source The current flowing through I2 can be easily set to the same current value (I).

  Here, the operational amplifier OP operates so that each voltage value of the voltage generated in the resistor R1 and the control voltage Vin input to the non-inverting terminal are equal. As a result, the bias currents applied to the first and second constant current sources I1 and I2 respectively change according to the voltage value of the control voltage Vin. Therefore, by changing the voltage value of the control voltage Vin, the bias current values to be applied to the first and second constant current sources I1 and I2 are changed. As the bias current value changes, the current values of the currents I output from the first and second constant current sources I1 and I2 are changed and set.

  As described above, the oscillation frequency of the oscillation circuit OSC can be changed in accordance with the change in the current value of the current I output from each of the first and second constant current sources I1 and I2. FIG. 4 shows a simulation result for confirming the change in the oscillation frequency of the oscillation circuit OSC when the current value of the bias current I applied to the first and second constant current sources I1 and I2 is changed. This simulation shows an example when the capacitance values c1 and c2 of the first and second capacitors C1 and C2 are set to 0.5 pF, and an example when the capacitance values c1 and C2 are set to 5 pF, respectively.

  As shown in FIG. 4, the oscillation frequency linearly changes in accordance with the change in the current value of the current I output from each of the first and second constant current sources I1 and I2. Further, by reducing the capacitance values c1 and c2 of the first and second capacitors C1 and C2, oscillations with respect to changes in the current value of the current I output from the first and second constant current sources I1 and I2, respectively. The rate of frequency change can be set large. In particular, according to the oscillation circuit OSC, the oscillation frequency can be determined without being concerned with the operation delay time (gate delay time) of each inverter circuit INV1, INV2, INV3 as described above. Therefore, effects such as very good stability of the oscillation frequency can be obtained.

  The present invention is not limited to the embodiment described above. Here, the oscillation circuit OSC configured by connecting the three inverter circuits INV1, INV2, and INV3 in a ring shape has been described. However, the present invention can be similarly applied to the case where the oscillation circuit OSC is configured by connecting three or more odd number of inverter circuits INV1, INV2,... INV (2n + 1) in a ring shape. Further, the circuit configurations conventionally proposed for the specific configurations of the voltage output type inverter circuit and the current output type inverter circuit can be adopted as appropriate, and are not limited to the circuit configurations exemplified as the embodiments.

  Furthermore, the configuration of the current adjustment circuit CONT for variably setting the value of the current flowing through the first and second constant current sources I1 and I2 can be variously modified. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

OSC oscillator circuit INV1 current output type inverter circuit INV2, INV3 voltage output type inverter circuit C1 first capacitor C2 second capacitor I1 first constant current source I2 second constant current source CONT current adjustment circuit P1, P2, P3, P4, P5, P6, P7 P-type MOS-FET
N1, N2, N3, N4, N5, N6 N-type MOS-FET
OP operational amplifier

Claims (8)

A series circuit composed of 2n (n is a natural number) voltage output type inverter circuits;
A current output type inverter circuit connected in a ring with this series circuit;
A first capacitor provided between the input and output terminals of the series circuit;
A second capacitor provided between an output terminal and a ground terminal of the current output type inverter circuit;
An oscillation circuit comprising:   The first capacitor charges the second capacitor when the voltage value of the output terminal of the series circuit reaches the power supply voltage value, and when the voltage value of the output terminal of the series circuit reaches the ground potential 2. The oscillation circuit according to claim 1, wherein the second capacitor is discharged.   The oscillation circuit according to claim 1, wherein the first capacitor and the second capacitor have the same capacitance value.   2. The oscillation according to claim 1, wherein the oscillation circuit includes a current adjustment circuit that changes a current value of a constant current source that supplies current to the current output type inverter circuit according to a control signal from the outside. circuit.   The current output type inverter circuit includes a P-channel type MOS-FET and an N-channel type MOS-FET connected in cascade, and a first constant current source for passing a current through the P-channel type MOS-FET, 5. The oscillation circuit according to claim 1, further comprising: a second constant current source that supplies current to the N-channel MOS-FET.   The first constant current source and the second constant current source have a current value of the P-channel type MOS-FET and a current value of the N-channel type MOS-FET set equal to each other. Item 6. The oscillation circuit according to Item 5. The first constant current source includes a first MOS-FET for current setting connected between the P-channel type MOS-FET and a power supply voltage terminal,
6. The oscillation circuit according to claim 5, wherein the second constant current source includes a second MOS-FET for current setting connected between the N-channel MOS-FET and a ground terminal.   5. The oscillation circuit according to claim 4, wherein the current adjustment circuit plays a role of changing an oscillation frequency by adjusting a current value input and output by the current output type inverter circuit.