JP2017521788A - Bridging interbus communication - Google Patents

Abstract

A strategy for bridging communications between a first bus and a second bus is disclosed. The address translation information and the associated security index are stored in memory (202). Each access request from the first bus includes a first requester security indicator and the requested address. Based on the requester security indicator and the security indicator associated with the address translation information for the requested address, each access request directed from the first bus to the second bus is denied (214); Alternatively, it is converted (210) and transmitted to the second bus (212). Each access request from the second bus to the first bus includes the requested address. This access request is translated (226) and transmitted to the first bus along with the security indicator associated with the address translation information for the requested address (228).

Description

The present disclosure relates generally to bridging communication between buses.

Background A bus is an interconnect subsystem or circuit that transfers data between different devices in an electronic circuit. In order to communicate effectively over a bus, the bus defines a set of rules and connections that each device connected to the bus must follow. Examples of devices that may be connected to the bus may include, but are not limited to, for example, a processor, memory, and a bridge to an external system. Unlike a point-to-point connection, a bus can connect a plurality of peripheral devices via a common set of lines.

  Many electronic systems include multiple buses, making it easier to transfer data between multiple devices in parallel. In some systems, data may be transferred from a bus that implements one protocol to a bus that implements a different protocol. By connecting buses that implement different protocols, compatibility issues may arise. For example, Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) supports secure isolation controlled by software and implemented by hardware and non-secure resources connected to the bus . On the other hand, the PCI Express (PCIe: Peripheral Component Interconnect express) bus architecture does not provide similar security. Because different buses have different characteristics, connecting the buses can be problematic.

Overview In one embodiment, a method for bridging communication between a first bus and a second bus includes storing address translation information and an associated security indicator in memory. Each first access request received from the first bus includes a first requester security indicator and a first address. In response to each first access request, the method includes the first requester security indicator representing a non-secure requester and the security indicator associated with the address translation information for the first address being a secure address. In response to representing the range, the first access request is denied. In response to the first requester security indicator representing a secure requester, the first access request is translated into a second access request for the second bus using the address translation information, and the second access The request is communicated to the second bus. Each third access request received from the second bus includes a third address. In response to each third access request, the method uses the address translation information to convert the third access request into a fourth access request for the first bus. The method communicates the fourth access request to the first bus along with a security indicator associated with the address translation information for the fourth address.

  In another embodiment, a bridge circuit for communication between a first bus and a second bus comprises a memory that is configurable to store address translation information and an associated security indicator. . A delivery circuit is coupled to the memory and the first and second buses. The sending circuit is configured to receive a first access request from a first bus, each first access request including a first requester security indicator and a first address. For each first access request, the sending circuit indicates that the first requester security indicator represents a non-secure requester, and the security indicator associated with the address translation information for the first address represents a secure address range. In response, the first access request is configured to be rejected. In response to the first requestor security indicator representing a secure requester, the sending circuit uses the address translation information to convert the first access request to a second access request for the second bus, and The second access request is transmitted to the second bus. An incoming circuit is coupled to the memory and the first and second buses. The incoming circuit is configured to receive a third access request from the second bus, and each third access request includes a third address. The incoming circuit is further configured to convert the third access request into a fourth access request for the first bus using the address translation information. The incoming circuit is configured to communicate the fourth access request to the first bus along with a security indicator associated with the address translation information for the fourth address.

  In another embodiment, a system is provided. The system is coupled between a first bus, a first set of master / slave circuits coupled to the first bus, a second bus, and the first bus and the second bus. And a second set of master / slave circuits coupled to the second bus. The bridge circuit comprises a memory that can be configured to store address translation information and associated security indicators. A delivery circuit is coupled to the memory and the first and second buses. The sending circuit is configured to receive a first access request from a first bus, each first access request including a first requester security indicator and a first address. For each first access request, the sending circuit indicates that the first requester security indicator represents a non-secure requester, and the security indicator associated with the address translation information for the first address represents a secure address range. In response, the first access request is configured to be rejected. In response to the first requestor security indicator representing a secure requester, the sending circuit uses the address translation information to convert the first access request to a second access request for the second bus, and The second access request is transmitted to the second bus. An incoming circuit is coupled to the memory and the first and second buses. The incoming circuit is configured to receive a third access request from the second bus, and each third access request includes a third address. The incoming circuit is further configured to convert the third access request into a fourth access request for the first bus using the address translation information. The incoming circuit is configured to communicate the fourth access request to the first bus along with a security indicator associated with the address translation information for the fourth address.

  Other features will be understood by consideration of the following detailed description and claims.

  Various aspects and features of the methods and systems will become apparent upon review of the following detailed description and upon reference to the drawings.

Bridge for communicating between a first bus that provides control implemented by hardware to secure and non-secure resources and a second bus that does not recognize the security mechanism of the first bus 1 is a diagram showing a system including a circuit. FIG. It is a flowchart of the example of the process regarding bridging of communication between the 1st bus and the 2nd bus. FIG. 3 is a diagram showing a programmable integrated circuit (IC) in which the bridging circuit of FIG. 1 and the processing of FIG. 2 can be realized.

DETAILED DESCRIPTION OF THE DRAWINGS In the following description, numerous specific details are set forth in order to describe the specific examples presented herein. However, it should be apparent to one skilled in the art that one or more other examples and / or variations on these examples may be practiced without all of the specific details described below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of explanation, the same reference numerals may be used in different figures to refer to the same items. On the other hand, in another example, matters may be different.

  The disclosed bridge circuit accommodates security means implemented by the first bus in bridging communication with the second bus. The second bus does not implement the security mechanism of the first bus. According to one strategy, the bridge circuit stores address translation information and associated security indicators. Using the address translation information, an address is translated between the address space of the first bus and the address space of the second bus. The security indicator associated with the address translation information can be configured such that different address ranges can have different security designations.

  The access request received from the first bus by the bridge circuit refers to the requested address and has an associated requester security indicator. The requested address refers to an address in the first address space of the first bus. The requester security indicator represents the security setting of the requester. For example, the requester's security settings may be secure or non-secure.

  In response to the requester security indicator indicating that the requester is non-secure and the security indicator associated with the address translation information for the requested address represents a secure address range, the bridge circuit includes a first Request from the requester on the second bus to the destination on the second bus is rejected. If the requester security indicator indicates that the requester is non-secure and the requested address range is non-secure, the bridge circuit uses the address translation information to turn the access request into an access request for the second bus. Convert. If the requester security indicator indicates that the requester is secure, the bridge circuit uses the address translation information to turn the access request into an access request for the second bus for both the secure address range and the non-secure address range. Convert. The converted access request is transmitted to the second bus.

  The access request received from the second bus by the bridge circuit refers to the requested address, but there is no associated requester security indicator. The requested address refers to an address in the second address space of the second bus. For a request received via the second bus, the bridge circuit converts the request into an access request for the first bus using the address translation information. The bridge circuit then communicates the translated access request to the first bus along with a security indicator associated with the address translation information.

  FIG. 1 illustrates communication between a first bus that provides control implemented by hardware to secure and non-secure resources and a second bus that does not recognize the security mechanism of the first bus. 1 shows a system 100 that includes a bridge circuit for Although not shown, it will be understood that the bridge and bus provide a data channel in addition to the illustrated address channel.

  The system 100 is coupled to a first set of master / slave circuits 102, a bridge circuit 106, a bus controller 108, a second bus 110, and a second bus coupled to a first bus 104. And a second set of master / slave circuits 112. The first set of master / slave circuits 102 may include one or more master circuits and one or more slave circuits, and the second set of master / slave circuits 112 may include one or more master circuits and One or more slave circuits may be included. Examples of a master circuit include a microprocessor, a direct memory access (DMA) circuit, and / or a digital signal processor (DSP). Examples of slave circuits include flash memory devices, solid state drives, or hard disk drives. The bridge circuit 106 is an example of a slave circuit on the first bus 104.

  The bridge circuit 106 translates requests between the first bus 104 and the second bus 110. The bus may have different address spaces, different physical configurations, and different security mechanisms. For example, the bus 104 may be a parallel bus such as an AXI bus, and the bus 110 may be a serial bus such as PCIe. The AXI bus separates secure resources and non-secure resources. On the AXI bus, each device may be assigned a security profile that indicates whether the device is secure or non-secure. Memory access transactions are tagged to represent the requester's security level and the tag is communicated across the interconnect system. Non-secure master devices or non-secure software tasks are allowed access only to non-secure memory regions or non-secure slave devices. A secure master device or secure software task is allowed access to both secure and non-secure memory areas. On the AXI bus, transaction security is represented by the state of the AxPROT [1] signal corresponding to security indicator 142 (where x represents R for read channel and W for write channel). There is no similar security information sent with the transaction on the PCIe bus.

  The sending circuit 122 converts the request from the requester (master circuit) on the first bus 104 into a request suitable for the slave circuit on the second bus 110. The incoming circuit 124 converts the request from the requester on the second bus 110 into a request suitable for the slave circuit on the first bus 104. The send translation circuit and the incoming translation circuit translate the address between the two address spaces and implement the first bus security mechanism using the address range map 126. The address range map may be implemented with one or more dual port memories 128, for example. In one example implementation, address range map 126 may be configurable via configuration signal 130.

  Each address range map describes the range of each address. The information in the address range map specifies an address range size 132, a remote base address 134, a local base address 136, and a security index 138. The size of the address range represents, for example, the number of addressable words within the range. The remote base address represents the base address within the address space of the second bus 110 where the address range begins. The local base address represents the base address within the address space of the first bus 104 where the address range begins. Security indicator 138 represents whether the address range is secure or non-secure.

  The sending circuit receives an access request from the first bus 104. Each access request (sometimes referred to herein as a transaction) includes a requester security indicator 142 and an address 144. The security indicator specifies the security level of the master circuit that initiated the request, for example, secure or non-secure. The address refers to an address in the address space of the first bus 104. In response to the access request, the sending circuit determines whether to convert the request and transmit it to the second bus 110 based on the requester security index and the security index associated with the requested address. . If the requester security indicator indicates that the requester is secure, the sending circuit converts the access request from the first bus into an access request for the second bus. In particular, the requested address is translated using one of the address maps 126 that specify the address range to which the requested address falls (local base address <= requested address <= (local Base address + size)). The address 146 output by the sending circuit is an address in the address space of the second bus 110 and is equal to (requested address−local base address) + remote base address. If the requester security indicator represents a non-secure requester and the address translation information for the requested address represents a non-secure address range, the sending circuit translates the access request as described above. In response to the requester security indicator indicating that the requester is non-secure and the security indicator associated with the address range indicating that the requested address is within the secure address range, the sending circuit is Deny access request. This rejection may be represented by a rejection signal 148 from the sending circuit.

  Incoming circuit 124 receives and processes requests from requesters on second bus 110 addressed to devices on first bus 104. The request from the second bus includes the requested address 152 but does not include the requester security indicator as the request from the first bus 104 includes. The incoming circuit uses one of the address range maps to convert an access request from the second bus 110 into an access request for the first bus 104. The one address range map is (remote base address <= requested address <= (remote base address + size)). The address 154 output by the incoming circuit is an address in the address space of the first bus 104 and is (requested address−remote base address) + local base address. Along with the address 154, the incoming circuit communicates a security indicator 156 associated with the address range of the requested address. Thus, the security index associated with the address range represents the requester's security level for all master circuits 112 that send access requests to the first bus 104. The approval signal and the rejection signal are provided to the bus controller 108 through the signal line 158.

  The bus controller provides an interface between the bridge circuit 106 and the second bus 110. In embodiments where the bus 110 provides a serial link, such as PCI Express (PCIe), the bus controller may include the physical layers of transactions, links, and circuits.

  FIG. 2 is a flowchart of an example of processing related to bridging of communication between the first bus and the second bus. In block 202, the address map consists of address translation information for translating requests between the first bus and the second bus. Each address range map specifies a size, a remote base address, a local base address, and a security index for each address range.

  For an access request from the first bus (the bus that implements the security measure), processing proceeds to block 204. At block 204, an address range of addresses in the access request is determined. Decision block 206 determines whether the range has been designated as secure. If the range is secure, decision block 208 determines whether the requester is secure, as represented by the signal accompanying the access request. If the requester is secure, at block 210, the process converts the requested address from the address space of the first bus to the address space of the second bus. At block 212, an access request is created using the translated address and communicated to the second bus. If the requester is not secure and the requested address is within the address range specified as secure, decision block 208 proceeds to block 214. At block 214, the access request is denied using a signal to the requester.

  At block 220, for an access request from a second bus (a bus that does not implement the security measures of the first bus), an address range of addresses in the access request is determined. At block 226, the address range map is used to convert the address from the address space of the second bus to the address of the address space of the first bus. At block 228, an access request is created using the translated address, and the address request and the status of the security indicator based on the address range map are communicated to the first bus. A device on the first bus that receives the access request can determine whether to grant access or reject the request.

  FIG. 3 shows a programmable integrated circuit (IC) in which the bridging circuit of FIG. 1 and the process of FIG. 2 can be implemented. The programmable IC of FIG. 3 shows an FPGA architecture (300) that includes a number of different programmable tiles. Various programmable tiles include multi-gigabit transceiver (MGT) 301, configurable logic block (CLB) 302, random access memory block (BRAM) 303, input / An input / output block (lOB) 304, a configuration and clocking logic (CONFIG / CLOCKS) 305, a digital signal processing block (DSP) 306, a special input / output block (I / O: input / output block) 307 (eg, clock port), and other programmable logic 308 (eg, digital clock manager, analog-to-digital converter, and system monitoring logic) and the like. Some FPGAs also include a dedicated processor block (PROC) 310, and internal and external reconfiguration ports (not shown).

  In some FPGAs, each programmable tile includes a programmable interconnect element (INT) 311. This programmable interconnect element 311 has a standardized connection to the corresponding interconnect element in each adjacent tile and a standardized connection from the corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect structure of the illustrated FPGA is realized by a set of programmable interconnect elements. As shown in the example included at the top of FIG. 3, programmable interconnect element INT 311 also includes connections to and from programmable logic elements within the same tile.

  For example, CLB 302 may include a configurable logic element (CLE) 312 that may be programmed to implement user logic and a single programmable interconnect element INT 311. BRAM 303 may include a BRAM logic element (BRL) 313 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the illustrated embodiment, the BRAM tile has the same height as five CLBs, but other numbers (eg, four) may be used. The DSP tile 306 may include a DSP logic element (DSPL) 314 in addition to an appropriate number of programmable interconnect elements. IOB 304 may include two instances of input / output logic element (IOL) 315 in addition to one instance of programmable interconnect element INT311, for example. As will be apparent to those skilled in the art, for example, the actual I / O bond pads connected to the I / O logic element 315 are fabricated on the various logic blocks shown, typically using metal layers. Specifically, the region is not limited to the input / output logic element 315.

  In the illustrated embodiment, the column area near the center of the die (the area shaded in FIG. 3) is used for configuration, clock, and other control logic. A horizontal region 309 extending from this column is used to distribute clock and configuration signals across the width of the FPGA.

  Some FPGAs using the architecture shown in FIG. 3 include additional logic blocks that disrupt the regular column structure that makes up the bulk of the FPGA. The additional logic block can be a programmable block and / or dedicated logic. For example, the processor block PROC 310 shown in FIG. 3 spans several CLB columns and BRAM columns.

  Note that FIG. 3 is intended to show an FPGA architecture, which is merely an example. The number of logical blocks in a column, the relative width of the column, the number and order of the columns, the type of logical block contained in the column, the relative size of the logical block, and the interconnect / logic implementation included at the top of FIG. Is a complete illustration. For example, in an actual FPGA, typically, when CLB appears, one or more adjacent columns of CLB are always included. This facilitates efficient realization of user logic.

  The exemplary methods described herein relate to bridging communication between a first bus and a second bus. Such a method for communication bridging may include storing address translation information and associated security indicators in a memory. The method further includes the first requester security index is non-secure in response to each first access request received from the first bus, the first requester security index and the first address. Refusing the first access request in response to representing the requester and the security indicator associated with the address translation information for the first address representing a secure address range; and first requester security In response to the index representing a secure requester, the address translation information is used to translate the first access request into a second access request for the second bus, and the second access request is translated to the second bus. Communicating to the network. The method further includes responding to each third access request received from the second bus, including the third address, using the address translation information to route the third access request for the first bus. Translating to a fourth access request, and communicating the fourth access request and the security indicator associated with the address translation information for the fourth address to the first bus.

  In such a method, the address translation information includes a plurality of address range maps, each address range map mapping a first address range of a first bus to a second address range of a second bus, and security Each of the indicators may be associated with one of the address range maps.

  Such a method is responsive to the first requester security indicator representing a non-secure requester and the address translation information for the first address representing a non-secure address range. Can be further converted to a second access request for the second bus and communicating the second access request to the second bus.

  In such a method, the address translation information includes a plurality of address range maps, each address range map mapping a first address range of a first bus to a second address range of a second bus, and security Each of the indicators may be associated with one of the address range maps, and each address range map may further include designating a first base address and a second base address.

Such a method may further include each address range map specifying a size.
Such a method may further include the first base address being in the first address space of the first bus and the second base address being in the second address space of the second bus. .

Such a method may further include that the security indicator is programmable.
The exemplary apparatus described herein generally relates to a bridge circuit. In such a device, a bridge circuit for communication between the first bus and the second bus comprises a memory that is configurable to store address translation information and associated security indicators. obtain. The bridge circuit may further comprise a delivery circuit coupled to the memory and the first and second buses. The sending circuit is configured to receive a first access request from a first bus, each first access request including a first requester security indicator and a first address. For each first access request, the sending circuit indicates that the first requester security indicator represents a non-secure requester, and the security indicator associated with the address translation information for the first address represents a secure address range. In response, the first access request is rejected, and in response to the first requester security indicator representing a secure requester, the first access request is routed to the second bus using the address translation information. The second access request is converted to a second access request, and the second access request is transmitted to the second bus. The bridge circuit may further comprise an incoming circuit coupled to the memory and the first and second buses. The incoming circuit is configured to receive a third access request from the second bus, and each third access request includes a third address. The incoming circuit further converts the third access request into a fourth access request for the first bus using the address conversion information, and converts the fourth access request and the address conversion information related to the fourth address. The associated security indicator is configured to communicate to the first bus.

  In such a device, the address translation information includes a plurality of address range maps, each address range map mapping a first address range on a first bus to a second address range on a second bus, and security Each of the indicators may be associated with one of the address range maps.

  In such an apparatus, in response to the first requester security indicator representing a non-secure requester and the address translation information for the first address representing a non-secure address range, the sending circuit further includes: , May be configured to convert the first access request into a second access request for the second bus and to communicate the second access request to the second bus.

  In such a device, the address translation information includes a plurality of address range maps, each address range map mapping a first address range on a first bus to a second address range on a second bus, and security Each of the indicators is associated with one of the address range maps, and each address range map may specify a first base address and a second base address.

In such a device, each address range map may specify a size.
In such a device, the first base address may be in the first address space of the first bus and the second base address may be in the second address space of the second bus.

In such a device, the security indicator can be programmable.
As another example, a system is provided. The system is coupled between a first bus, a first set of master / slave circuits coupled to the first bus, a second bus, and the first bus and the second bus. And a second set of master / slave circuits coupled to the second bus. The bridge circuit comprises a memory that can be configured to store address translation information and associated security indicators. The bridge circuit further comprises a delivery circuit coupled to the memory and the first and second buses. The sending circuit is configured to receive a first access request from a first bus, each first access request including a first requester security indicator and a first address. For each first access request, the sending circuit indicates that the first requester security indicator represents a non-secure requester, and the security indicator associated with the address translation information for the first address represents a secure address range. In response, the first access request is rejected, and in response to the first requester security indicator representing a secure requester, the first access request is routed to the second bus using the address translation information. The second access request is converted to a second access request, and the second access request is transmitted to the second bus. The bridge circuit further comprises an incoming circuit coupled to the memory and the first and second buses. The incoming circuit is configured to receive a third access request from the second bus, and each third access request includes a third address. The incoming circuit further converts the third access request into a fourth access request for the first bus using the address conversion information, and converts the fourth access request and the address conversion information related to the fourth address. The associated security indicator is configured to communicate to the first bus.

  In such a system, the address translation information includes a plurality of address range maps, each address range map mapping a first address range on a first bus to a second address range on a second bus, and security Each of the indicators may be associated with one of the address range maps.

  In such a system, in response to the first requester security indicator representing a non-secure requester and the address translation information for the first address representing a non-secure address range, the sending circuit further includes: , May be configured to convert the first access request into a second access request for the second bus and to communicate the second access request to the second bus.

  In such a system, the address translation information includes a plurality of address range maps, each address range map mapping a first address range on a first bus to a second address range on a second bus, and security Each of the indicators is associated with one of the address range maps, and each address range map may specify a first base address and a second base address.

  In such a system, each address range map may specify a size. In such a system, the first base address may be in the first address space of the first bus and the second base address may be in the second address space of the second bus.

  In some cases, aspects and features may be described in separate drawings, but some combinations may not be explicitly illustrated or described as combinations. It will be understood that features in it may be combined with features in other figures.

  The methods and systems described above are considered applicable to a variety of systems for bridging communications between different buses. Other aspects and features will be apparent to those skilled in the art from consideration of the specification. The methods and systems may be implemented as one or more processors configured to execute software as application specific integrated circuits (ASICs) or as logic on a programmable logic device. Good. The specification and drawings are to be considered merely as examples and the true scope of the invention is intended to be represented by the following claims.

Claims (14)

A method of bridging communication between a first bus and a second bus, comprising:
Storing address translation information and associated security indicators in memory;
In response to each first access request received from the first bus, including a first requester security indicator and a first address;
In response to the first requestor security indicator representing a non-secure requester and the security indicator associated with the address translation information for the first address representing a secure address range. Denying the access request of 1;
In response to the first requester security indicator representing a secure requester, the first translation request is converted to a second access request for the second bus using the address translation information; Communicating a second access request to the second bus;
In response to each third access request received from the second bus, including a third address,
Converting the third access request into a fourth access request for the first bus using the address translation information;
Communicating the fourth access request and the security indicator associated with the address translation information for a fourth address to the first bus.   The address translation information includes a plurality of address range maps, wherein each address range map maps a first address range of the first bus to a second address range of the second bus, and The method of claim 1, wherein each is associated with one of the address range maps.   In response to the first requester security indicator representing a non-secure requester and the address translation information relating to the first address representing a non-secure address range, 3. The method according to claim 1 or 2, further comprising the step of converting to the second access request for a second bus and communicating the second access request to the second bus. The address translation information includes a plurality of address range maps, wherein each address range map maps a first address range of the first bus to a second address range of the second bus, and Each associated with one of the address range maps;
The method of claim 1, wherein each address range map specifies a first base address and a second base address.   The method of claim 4, wherein each address range map specifies a size.   The first base address is in a first address space of the first bus, and the second base address is in a second address space of the second bus. Method.   The method according to claim 1, wherein the security indicator is programmable. A bridge circuit for communication between a first bus and a second bus,
A memory configurable to store address translation information and associated security indicators;
A sending circuit coupled to the memory and the first and second buses, wherein the sending circuit is configured to receive a first access request from the first bus; The access request includes a first requester security indicator and a first address, and for each first access request, the sending circuit includes:
In response to the first requestor security indicator representing a non-secure requester and the security indicator associated with the address translation information for the first address representing a secure address range. Deny access request of 1,
In response to the first requester security indicator representing a secure requester, the first translation request is converted to a second access request for the second bus using the address translation information; Configured to communicate a second access request to the second bus, the bridge circuit further comprising:
An incoming circuit coupled to the memory and the first and second buses, wherein the incoming circuit is configured to receive a third access request from the second bus; The access request includes a third address, and the incoming circuit further includes:
Using the address translation information to convert the third access request into a fourth access request for the first bus;
A bridge circuit configured to communicate the fourth access request and the security indicator associated with the address translation information relating to a fourth address to the first bus.   The address translation information includes a plurality of address range maps, wherein each address range map maps a first address range of the first bus to a second address range of the second bus, and The circuit of claim 8, wherein each is associated with one of the address range maps.   In response to the first requester security indicator representing a non-secure requester and the address translation information for the first address representing a non-secure address range, the sending circuit further includes: 10. The system according to claim 8, wherein the first access request is converted into the second access request for the second bus, and the second access request is transmitted to the second bus. Circuit described in. The address translation information includes a plurality of address range maps, wherein each address range map maps a first address range of the first bus to a second address range of the second bus, and Each associated with one of the address range maps;
9. The circuit of claim 8, wherein each address range map specifies a first base address and a second base address.   The circuit of claim 11, wherein each address range map specifies a size.   13. The first base address is in a first address space of the first bus and the second base address is in a second address space of the second bus. circuit.   The circuit according to claim 8, wherein the security index is programmable.

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