JP2017220581A - Semiconductor device, method for manufacturing the same, and optical interconnect system - Google Patents

Abstract

For example, dark current is reduced while sufficient response characteristics can be obtained even when the height of a mesa structure is lowered.
A semiconductor device is provided above a substrate and provided on one of an n-type and p-type Si layer and one of an n-type and p-type Si layer, and an i-type Ge or SiGe layer. 2 and a mesa structure 10 consisting of the other n-type and p-type Ge or SiGe layer 3 covering the entire surface of the i-type Ge or SiGe layer, one n-type and p-type Si layer, n-type and An i-type Si layer 8B provided between the other p-type Ge or SiGe layer is provided.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and an optical interconnect system.

For example, with the increase in the amount of data transmission between CPUs of servers, the correspondence in the transmission by the electric signal using the conventional Cu wiring is approaching the limit.
In order to eliminate this bottleneck, an optical interconnect, that is, data transmission using an optical signal is required.
Furthermore, from the viewpoint of low power consumption and small area, various optical components (optical modulators, optical receivers, multiplexers, demultiplexers, etc. provided in optical transmitters and optical receivers required for optical transmission / reception) Device) is integrated on the Si substrate.

In this case, it is preferable to use a wavelength of 1.30 to 1.55 μm with a small loss in the optical waveguide formed on the Si substrate as the transmission wavelength band.
It is preferable that the same group IV Ge having an absorption edge in the vicinity of 1.55 μm is applied to the absorption layer in the photodetector (photodetector; PD) on the Si substrate applied in the optical transmission in the above wavelength band.

  So far, for example, a PIN-type Ge photodetector as shown in Non-Patent Document 1 has been reported.

JP 2014-192472 A JP 2014-216389 A

Sungbong Park et al., “Monolithic integration and synchronous operation of germanium crystals and silicon variable optical attenuators”, OPTICS EXPRESS, Vol. 18, No. 8, 2010, pp. 8412-8421

Incidentally, in order to increase the transmission capacity, it is necessary to increase the response speed of the photodetector.
In addition, it is important to reduce noise in signal processing. For that purpose, it is also necessary to reduce the dark current of the photodetector.
In addition, from the viewpoint of manufacturing a silicon photonics integrated device, it is necessary to reduce the level difference generated when forming the interlayer insulating film. Therefore, it is necessary to reduce the height of the mesa structure constituting the photodetector as much as possible.

For example, in the PIN type Ge photodetector as shown in Non-Patent Document 1 described above, phosphorus (P) is selectively ion-implanted into the upper part of the selectively grown Ge mesa structure. For this reason, the side surface of the Ge mesa structure is i-type, and the current leakage path is suppressed, so that dark current can be reduced.
However, when the height of the Ge mesa structure is lowered, the response characteristics are deteriorated due to an increase in device capacitance due to a reduction in the thickness of the depletion layer (i-type Ge layer). It is also difficult to secure a sufficiently thick Ge depletion layer (i-type Ge layer) in order to prevent deterioration of response characteristics.

  An object of the present invention is to reduce dark current while ensuring sufficient response characteristics even when the height of a mesa structure is lowered, for example.

  In one aspect, the semiconductor device is provided above the substrate, and is provided on one of the n-type and p-type Si layers and one of the n-type and p-type Si layers, and is provided with an i-type Ge or SiGe layer. A mesa structure consisting of the other n-type and p-type Ge or SiGe layers covering the entire surface of the i-type Ge or SiGe layer, one n-type and p-type Si layer, and n-type and p-type And an i-type Si layer provided between the other Ge or SiGe layer.

In one aspect, an optical interconnect system includes an optical transmitter and an optical receiver connected to the optical transmitter via an optical transmission path, and the optical receiver includes the semiconductor device.
In one aspect, in a method of manufacturing a semiconductor device, one of n-type and p-type Si layers is formed by ion-implanting one of n-type and p-type dopants into a Si layer provided above a substrate. Ion implantation of the other n-type and p-type dopants partially in the thickness direction in a region where the outer periphery of the mesa structure of one of the n-type and p-type Si layers is provided. A step of forming an Si layer, an i-type Ge or SiGe layer on one of the n-type and p-type Si layers, and the other of the n-type and p-type covering the entire surface of the i-type Ge or SiGe layer Forming a mesa structure comprising a Ge or SiGe layer, and in the step of forming a mesa structure, one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer In order to provide an i-type Si layer in between, n-type and Forming a p-type other Ge or SiGe layer.

  As one aspect, for example, the dark current can be reduced while sufficient response characteristics can be obtained even when the height of the mesa structure is lowered.

(A), (B) is a schematic diagram which shows the structure of the semiconductor device concerning this embodiment, (A) is sectional drawing, (B) is a top view. It is a schematic plan view for demonstrating the manufacturing method of the semiconductor device (waveguide coupling type PIN type PD) concerning this embodiment. It is a schematic plan view for demonstrating the manufacturing method of the semiconductor device (waveguide coupling type PIN type PD) concerning this embodiment. It is a schematic plan view for demonstrating the manufacturing method of the semiconductor device (waveguide coupling type PIN type PD) concerning this embodiment. (A), (B) is a schematic diagram for demonstrating the manufacturing method of the semiconductor device (waveguide coupling type PIN type PD) concerning this embodiment, (A) is sectional drawing, (B ) Is a plan view. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (waveguide coupling | bonding type PIN type PD) concerning this embodiment. (A), (B) is a schematic diagram for demonstrating the manufacturing method of the semiconductor device (waveguide coupling type PIN type PD) concerning this embodiment, (A) is sectional drawing, (B ) Is a plan view. (A), (B) is a schematic diagram for demonstrating the structure of the semiconductor device (waveguide coupling type PIN type PD) concerning this embodiment, and its manufacturing method, (A) is sectional drawing. , (B) are plan views. (A), (B) is a schematic diagram which shows the structure of the semiconductor device (surface type PIN type PD) concerning this embodiment, (A) is sectional drawing, (B) is a top view. . It is a typical sectional view showing other composition of the semiconductor device concerning this embodiment (waveguide coupling type PIN type PD). It is typical sectional drawing which shows the other structure of the semiconductor device (surface type PIN type PD) concerning this embodiment. It is a mimetic diagram showing composition of an optical interconnect system concerning this embodiment.

Hereinafter, a semiconductor device, a manufacturing method thereof, and an optical interconnect system according to embodiments of the present invention will be described with reference to FIGS.
The semiconductor device according to the present embodiment is a semiconductor device applicable to, for example, an optical receiver for optical communication or data communication, in particular, an optical receiver constituting an optical interconnect system, and includes, for example, a light receiver and a modulator. An optical integrated device including a semiconductor optical device.

In particular, it is preferable to apply to a silicon photonics integrated device including a semiconductor optical device such as a light receiver or a modulator integrated on a Si substrate or SOI (Silicon on Insulator) substrate from the viewpoint of low power consumption and small area. .
In this embodiment, the semiconductor optical device is a PIN type Ge photodetector (photodetector; PD) 5 using Ge as an absorption layer, as shown in FIGS. 6, a mesa structure comprising a p-type Si layer 8A provided above 6, an i-type Ge layer 2 provided on the p-type Si layer 8A, and an n-type Ge layer 3 covering the entire surface of the i-type Ge layer 2. (Ge mesa structure) 10 and an i-type Si layer 8B provided between the p-type Si layer 8A and the n-type Ge layer 3 are provided. This is also referred to as a vertical PIN type PD.

  In the present embodiment, the insulating film 9 covering the p-type Si layer 8A and the n-type Ge layer 3, and the p-side electrode (first metal electrode) 4A penetrating the insulating film 9 and in contact with the p-type Si layer 8A And an n-side electrode (second metal electrode) 4B provided above the mesa structure 10 so as to penetrate the insulating film 9 and be in contact with the n-type Ge layer 3. Here, the mesa structure 10 provided on the p-type Si layer 8 </ b> A is buried with the insulating film 9.

The Ge light receiver 5 is also referred to as a silicon photonics Ge light receiver, a Ge based semiconductor optical device, or a Ge based semiconductor light receiving device. In FIG. 1B, the insulating film 9 is not shown for easy understanding.
In the present embodiment, the substrate 6 is a Si substrate provided in the SOI substrate 1.
The SOI substrate 1 includes a BOX layer 7 and an SOI layer (Si layer) 8 on an Si substrate 6.

Here, the plane orientation of the Si substrate 6 is (001).
The Si layer as the SOI layer 8 includes a p-type region doped with a p-type dopant (p-type Si layer 8A), and an i-type region doped with a p-type dopant and an n-type dopant (i-type Si layer 8B). ).
Here, in the Si layer as the SOI layer 8, the region where the outer peripheral portion (peripheral portion) of the mesa structure 10 is provided is the i-type Si layer 8B, and the region where the central portion of the mesa structure 10 is provided is the p-type. Si layer 8A is formed.

That is, the Si layer as the SOI layer 8 is the i-type Si layer 8B in the portion in contact with the outer peripheral portion of the bottom surface of the mesa structure 10, and the p-type Si layer 8A in the portion in contact with the center portion of the bottom surface of the mesa structure 10. It has become.
Specifically, in the Si layer as the SOI layer 8, a region where the outer peripheral portion of the mesa structure 10 is provided is partially an i-type Si layer 8B in the thickness direction, and the other portion is p-type Si. It is layer 8A.

Here, the other portions are the entire thickness direction of the region where the central portion of the mesa structure 10 is provided, and between the i-type Si layer 8B and the BOX layer 7 in the region where the outer peripheral portion of the mesa structure 10 is provided. This is the entire region in the thickness direction of the region in contact with the p-side electrode 4A outside the region where the mesa structure 10 is provided.
Thus, the p-type Si layer 8A in the region where the central portion of the mesa structure 10 is provided and the p-type Si layer 8A in the region where the p-side electrode 4A outside the region where the mesa structure 10 is provided are in contact with each other. 10 is connected by the p-type Si layer 8A between the i-type Si layer 8B and the BOX layer 7 in the region where the outer peripheral portion is provided, that is, the p-type Si layer 8A below the i-type Si layer 8B. It has a structure that is electrically connected to.

In the present embodiment, the upper and side portions of the mesa structure 10 are the n-type Ge layer 3. That is, not only the upper part of the mesa structure 10 but also the entire surface part including the side part is the n-type Ge layer 3.
In the present embodiment, the p-side electrode (first metal electrode) 4A and the n-side electrode (second metal electrode) are Al electrodes.

In the present embodiment, the insulating film 9 is a SiO ₂ film (oxide insulating film). The insulating film 9 may not be an oxide insulating film, and may be a nitride insulating film such as SiN.
In the present embodiment, the SOI substrate 1 is used. However, the present invention is not limited to this, and another substrate such as a Si substrate may be used.
That is, although the PIN type PD5 is provided above the Si substrate 6 provided in the SOI substrate 1, the present invention is not limited to this. For example, the PIN type PD5 may be provided above the Si substrate.

As described above, the substrate on which the PIN type PD 5 is provided may not be the Si substrate provided in the SOI substrate, and may be another substrate such as a Si substrate.
In the present embodiment, the Si layer 8 below the mesa structure 10 is the p-type Si layer 8A, but is not limited to this, and one of the n-type and p-type Si layers, that is, the n-type is used. And a Si layer (n-type Si layer or p-type Si layer) doped with one of the p-type dopants.

In the present embodiment, the mesa structure 10 including the i-type Ge layer 2 and the n-type Ge layer 3 is used. However, the present invention is not limited to this.
For example, even a mesa structure composed of an i-type SiGe layer and an n-type SiGe layer, a mesa structure composed of an i-type Ge layer and an n-type SiGe layer, or a mesa structure composed of an i-type SiGe layer and an n-type Ge layer good.

  For example, the Ge or SiGe layer covering the entire surface of the i-type Ge or SiGe layer may be a Ge or SiGe layer doped with the other dopant of n-type and p-type. That is, the Ge or SiGe layer provided above the i-type Ge or SiGe layer, that is, the upper part of the mesa structure 10 is n-type or n-type when the Si layer below the mesa structure 10 is a p-type Si layer. In the case of the Si layer, it may be p-type.

As described above, the mesa structure 10 is a mesa structure including an i-type Ge or SiGe layer and the other n-type or p-type Ge or SiGe layer covering the entire surface of the i-type Ge or SiGe layer. good.
The semiconductor device manufacturing method configured as described above may include the following steps.

  That is, a step of ion-implanting one of n-type and p-type dopants into the Si layer 8 provided above the substrate 6 to form one of the n-type and p-type Si layers 8A; The i-type Si layer 8B is formed by ion-implanting the other n-type and p-type dopants partially in the thickness direction in the region where the outer periphery of the mesa structure 10 of the one Si layer 8A is provided. On the one of the n-type and p-type Si layers 8A, the i-type Ge or SiGe layer 2, and the other n-type and p-type Ge covering the entire surface of the i-type Ge or SiGe layer 2. Alternatively, it may include a step of forming a mesa structure 10 including the SiGe layer 3 [see, for example, FIGS. 1A and 1B].

In the step of forming the mesa structure 10, the i-type Si layer 8B is provided between one n-type and p-type Si layer 8A and the other n-type and p-type Ge or SiGe layer 3. In addition, the other n-type and p-type Ge or SiGe layer 3 may be formed by co-doping.
By the way, the reason why the configuration and the manufacturing method are adopted as described above is as follows.

For example, in the PIN type Ge photodetector as shown in Non-Patent Document 1 described above, phosphorus (P) is selectively ion-implanted into the upper part of the selectively grown Ge mesa structure. For this reason, the side surface of the Ge mesa structure is i-type, and the current leakage path is suppressed, so that dark current can be reduced.
However, when the height of the Ge mesa structure is lowered, the response characteristics are deteriorated due to an increase in device capacitance due to a reduction in the thickness of the depletion layer (i-type Ge layer).

It is also difficult to secure a sufficiently thick Ge depletion layer (i-type Ge layer) in order to prevent deterioration of response characteristics.
That is, in order to prevent deterioration of response characteristics, it is necessary to ensure the thickness of the i-type Ge layer.
For this purpose, it is necessary to reduce the profile (depth) of phosphorus (P), which is a dopant ion-implanted into the upper portion of the Ge mesa structure.

However, in ion implantation, for example, the carrier concentration of about 1.0 × 10 ¹⁹ cm ⁻³ or more capable of forming a tunnel junction with the contact electrode is limited to a region of about 100 nm or less in thickness P. Difficult due to atomic diffusion.
For this reason, it is difficult to secure a sufficient thickness of the Ge depletion layer (i-type Ge layer), and the response characteristics deteriorate due to an increase in device capacitance.

Therefore, even when the height of the Ge mesa structure is lowered, a sufficient Ge depletion layer (i-type Ge layer) can be secured, and a sufficient response characteristic can be obtained without increasing the device capacity. I want to realize a type Ge photo detector.
Therefore, for example, the above-described configuration and manufacturing method are adopted so that the dark current can be reduced while sufficient response characteristics can be obtained even when the height of the mesa structure is lowered.

That is, in order to increase the thickness controllability of the i-type Ge layer 2 and to obtain sufficient response characteristics even when the height of the mesa structure 10 is lowered, for example, the n-type is formed on the upper part of the mesa structure 10 by simultaneous doping. A Ge layer 3 is formed.
Here, when the n-type Ge layer 3 is formed, an n-type dopant is implanted by simultaneous doping in the same apparatus during the growth of the Ge layer.

Since the co-doping method simultaneously introduces a dopant material gas during Ge growth, it is possible to form a steep profile as compared with the ion implantation method, and a thin range (for example, a region of about 100 nm or less). It is possible to form an n-type region.
On the other hand, in the co-doping method, a doped region cannot be selectively formed only in a certain region as in the ion implantation method, and the n-type Ge layer 3 is a surface portion including not only the upper portion of the mesa structure 10 but also the side portion. It will be formed to cover the whole.

For this reason, the lower part (bottom part) of the n-type Ge layer 3 formed on the side part of the mesa structure 10 is in contact with the p-type Si layer, thereby forming a current path and increasing the dark current.
Therefore, as described above, the i-type Si layer 8B is provided between the p-type Si layer 8A and the n-type Ge layer 3.
Here, a donut shape is formed only between the p-type Si layer 8 </ b> A below the mesa structure 10 and the n-type Ge layer 3 constituting the surface portion of the mesa structure 10, that is, just below the outer peripheral portion of the mesa structure 10. An i-type Si layer 8B is provided.

As a result, a voltage drop is caused in the i-type Si layer 8B, and the potential difference between the n-type Ge layer 3 and the i-type Si layer 8B is reduced, thereby suppressing the leakage current and reducing the dark current. Is possible.
In the case where the i-type Si layer 8B is provided in this way, the p-type Si layer 8A is provided between the i-type Si layer 8B and the BOX layer 7 as described above. The p-type Si layer 8A in contact with the central portion of the electrode and the p-type Si layer 8A in contact with the p-side electrode 4A outside the region where the mesa structure 10 is provided are electrically connected.

In this way, for example, when the n-type Ge layer 3 is formed by co-doping so that sufficient response characteristics can be obtained even when the height of the mesa structure 10 is lowered, the dark current can be reduced. ing.
For example, when the height of the mesa structure is about 300 nm, in the conventional ion implantation method, the thickness of the n-type Ge layer is about 200 nm, and the thickness of the i-type Ge layer is about 100 nm.

On the other hand, when the co-doping method is applied as described above with the same mesa structure height, the thickness of the n-type Ge layer can be reduced to about 100 nm or less. Thereby, the thickness of the i-type Ge layer can be about 200 nm or more. As a result, the element capacity of the PD can be reduced to ½ or less.
As described above, by adopting the configuration and the manufacturing method as described above, it is possible to increase the response characteristic by about twice or more while maintaining the dark current value equivalent to that of the conventional technique.

By the way, for example, as shown in FIGS. 8A and 8B, the Si waveguide core layers 8Y and 8Z are optically connected to the Si layer 8 (here, the Si pedestal portion 8X) provided below the mesa structure 10. It is good also as what is joined. That is, Si waveguide core layers 8Y and 8Z optically coupled to one of the n-type and p-type Si layers 8A may be provided.
For example, the SOI layer 8 of the SOI substrate 1 is patterned to form a Si pedestal portion 8X for forming the PIN type PD5, and a Si taper portion 8Y and a Si thin wire portion 8Z as a Si waveguide core layer connected thereto. The Si waveguide may be connected to the PIN type PD5. This is also called a waveguide coupled PIN type PD or a waveguide coupled vertical PIN type PD.

In FIG. 8B, the insulating film 9 is not shown for easy understanding.
Hereinafter, a method for manufacturing a waveguide-coupled PIN type PD5 on an SOI wafer will be described as an example with reference to FIGS.
Here, as the SOI substrate 1, a silicon substrate 6 having a (001) plane orientation, a BOX layer 7 having a thickness of about 3.0 μm, and an SOI layer 8 having a thickness of about 0.3 μm is used (for example, (See FIG. 5A).

First, a resist is applied on the SOI substrate 1, and exposure and development are performed by EB lithography to form a Si base portion 8X that becomes a base layer of the PD and a Si waveguide core layer (here, the Si taper portion 8Y). And a resist pattern for forming the Si thin wire portion 8Z).
Next, as shown in FIG. 2, the SOI layer (Si layer) 8 of the SOI substrate 1 is patterned by, for example, inductively coupled plasma (ICP) dry etching to form a Si pedestal portion 8X and a Si waveguide for Ge growth. Core layers 8Y and 8Z are formed.

A waveguide constituted by the Si waveguide core layers 8Y and 8Z is referred to as a Si passive waveguide or a Si fine wire waveguide.
Next, B (boron) ions are implanted into the Si layer 8 in the region where the PIN type PD 5 of the Si pedestal portion 8X is provided to form the p-type Si layer 8A.
Here, B is used as the p-type dopant, but the present invention is not limited to this. For example, Ga or the like may be used.

For example, first, a resist pattern (not shown) having an opening of about 50 μm × about 50 μm is formed on the Si base portion 8X.
Next, using a resist pattern, for example, B ₂ H ₆ (diborane) is used as a raw material, a dose is set to about 1.0 × 10 ¹⁵ cm ⁻² , an acceleration voltage is set to about 30 keV, and B ion implantation is performed. Do.

Next, the resist is removed, and annealing is performed at, for example, about 1000 ° C. to activate the implanted B ions.
After such B ion implantation and activation annealing steps, as shown in FIG. 3, a p-type Si layer 8A having a uniform doping amount, that is, about 1 in the region where the PIN type PD5 of the Si base portion 8X is provided. A p-type Si layer 8A having a carrier concentration of 0.0 × 10 ¹⁹ cm ⁻³ is formed. The region where the p-type Si layer 8A is formed is a region where B is ion-implanted.

Next, ion implantation of P (phosphorus) is performed on the p-type Si layer 8A formed in the region where the outer peripheral portion of the mesa structure 10 of the Si pedestal portion 8X is provided to form the i-type Si layer 8B.
Here, P is used as the n-type dopant, but the present invention is not limited to this. For example, As may be used.
For example, a rectangular donut-shaped opening having an inner diameter of about 26 μm × about 6 μm and an outer diameter of about 34 μm × about 14 μm is first formed on the p-type Si layer 8A formed in the region where the PIN type PD5 of the Si base portion 8X is provided. A resist pattern (not shown) is formed.

Next, using a resist pattern, for example, PH ₃ (phosphine) is used as a raw material, a dose is set to about 1.0 × 10 ¹⁵ cm ⁻² , an acceleration voltage is set to about 10 keV, and P ions are implanted.
Next, the resist is removed, and annealing is performed at about 1000 ° C., for example, to activate the implanted P ions.

Through such P ion implantation and activation annealing process, as shown in FIG. 4, a rectangular donut shape is formed inside the p-type Si layer 8A formed in the region where the PIN-type PD5 of the Si base portion 8X is provided. The i-type Si layer 8B having a depth of about 0.2 μm is formed.
That is, both the B and P ions are implanted into the Si layer 8 constituting the Si pedestal portion 8X to form the rectangular donut-shaped i-type Si layer 8B. The region where the i-type Si layer 8B is formed is a region where both B and P are ion-implanted.

  In this manner, B is ion-implanted with high dose and medium energy into the Si layer 8 in the region where the PIN type PD 5 of the Si pedestal portion 8X is provided, and the region where the outer peripheral portion of the mesa structure 10 of the Si pedestal portion 8X is provided. By ion-implanting P into the formed p-type Si layer 8A with high dose and low energy, the p-type Si layer 8A is formed in the region where the PIN-type PD 5 is provided, and the outer periphery of the mesa structure 10 is provided. An i-type Si layer 8B is partially formed in the region in the thickness direction.

Thus, the p-type Si layer 8A below the i-type Si layer 8B contacts the p-type Si layer 8A in contact with the central portion of the mesa structure 10 and the p-side electrode 4A outside the region where the mesa structure 10 is provided. The type Si layer 8A is electrically connected.
Next, as shown in FIGS. 5A and 5B, an insulating film (SiO ₂ film; oxide film) mask for Ge selective growth is formed on the region where the PIN type PD5 of the Si base portion 8X is provided. 9A is patterned, and the i-type Ge layer 2 and the n-type Ge layer 3 are selectively grown to form the mesa structure 10.

In FIG. 5B, the insulating film 9 is not shown for easy understanding.
Here, the size of the Ge selective growth area (Ge epitaxial growth area) is, for example, about 10 μm × about 30 μm. Further, the insulating film mask 9A having an opening is patterned so that the peripheral portion of the mesa structure 10 is located in a region where the i-type Si layer 8B is formed in a donut shape. The selective growth of the i-type Ge layer 2 and the n-type Ge layer 3 is performed by, for example, a low pressure chemical vapor deposition (LP-CVD) method.

Here, first, selective growth of the i-type Ge layer 2 is performed.
Here, for example, GeH ₄ (german) may be used as the Ge source (source gas), and H ₂ (hydrogen) may be used as the carrier gas. Here, the i-type Ge layer 2 is grown to about 200 nm, for example.
Next, selective growth of the n-type Ge layer 3 is performed.

Here, for example, GeH ₄ (germane) is used as the Ge source, H ₂ (hydrogen) is used as the carrier gas, and PH ₃ (phosphine) is used as the source (source gas) of P (phosphorus) that is the n-type dopant. Use it. Here, the n-type Ge layer 2 having a doping concentration of about 1.0 × 10 ¹⁹ cm ⁻³ is grown by about 100 nm.
That is, first, the source gas is supplied with only GeH ₄ (germane) to form an i-type Ge layer 2 of about 200 nm, and then simultaneously doped with GeH ₄ (germane) and PH ₃ (phosphine) simultaneously. Thus, the n-type Ge layer 3 having a doping concentration of about 1.0 × 10 ¹⁹ cm ⁻³ is formed to about 100 nm.

Thus, the mesa structure 10 composed of the i-type Ge layer 2 and the n-type Ge layer 3 is formed.
Thus, when the n-type Ge layer 3 is formed by co-doping, the n-type Ge layer 3 is formed so as to cover not only the upper part of the mesa structure 10 but also the entire surface part including the side part. In this case, the n-type Ge layer 3 is formed so as to surround the periphery of the mesa structure 10.
Further, here, the mesa structure 10 composed of the i-type Ge layer 2 and the n-type Ge layer 3 is formed so that the peripheral portion is in contact with the i-type Si layer 8B partially formed in the thickness direction in a donut shape. It is formed. That is, the n-type Ge layer 3 is formed by simultaneous doping so that the i-type Si layer 8B is provided between the p-type Si layer 8A and the n-type Ge layer 3, and the i-type Ge layer 2 and the n-type Ge layer 2 are formed. A mesa structure 10 composed of the Ge layer 3 is formed.

Next, as shown in FIG. 6, an SiO ₂ film (insulating film) 9B is formed to a thickness of about 1 μm by, for example, plasma CVD. As a result, a SiO ₂ film (insulating film) 9 covering the n-type Ge layer 3 and the Si layer 8 (p-type Si layer 8A and i-type Si layer 8B) is formed.
Next, after applying a resist and forming a resist pattern for contact holes immediately above the mesa structure 10, as shown in FIGS. 7A and 7B, for example, inductively coupled plasma (ICP) dry process is performed. By etching, the SiO ₂ film 9 is etched by about 1 μm to form, for example, a contact hole 11 of about 5 μm × about 25 μm immediately above the mesa structure 10. Here, for example, a CF ₄ system may be used as the etching gas. Thereafter, the resist is peeled off.

Next, after applying a resist and forming a resist pattern for contact holes to the p-type Si layer 8A formed in the Si layer 8, the SiO ₂ film 9 is etched by about 1 μm by, for example, ICP dry etching, For example, contact holes 12 of about 3 μm × about 34 μm are formed on both sides of the mesa structure 10. Here, for example, a CF ₄ system may be used as the etching gas. Thereafter, the resist is peeled off.

Next, in order to form the p-side electrode 4A as the first metal electrode and the n-side electrode 4B as the second metal electrode, for example, by sputtering, an Al layer is formed to a thickness of about 0.5 μm. .
Next, a resist is applied and patterned, and as shown in FIGS. 8A and 8B, Al electrodes are formed as the p-side electrode 4A and the n-side electrode 4B, for example, by ICP dry etching.

In this way, the waveguide coupled PIN type PD5 on the SOI wafer can be manufactured.
In this case, it is possible to increase the response characteristic by about twice or more while maintaining a dark current value equivalent to that in the case of the prior art in which the n-type Ge layer is formed by ion implantation.
By the way, as shown to FIG. 9 (A) and FIG. 9 (B), the n side electrode 4B as a 2nd metal electrode is good also as what is provided with the opening part 4X. For example, the n-side electrode 4B as the second metal electrode in contact with the upper part of the mesa structure 10 may be provided with an opening 4X at the center thereof, and may be a surface PIN type PD5. This is also called a surface type vertical PIN type PD. In this case, the n-side electrode 4B as the second metal electrode is provided in a ring shape along the peripheral portion at the top of the mesa structure 10. Further, light from above the mesa structure 10 enters through the opening 4X of the n-side electrode 4B as the second metal electrode.

As shown in FIGS. 10 and 11, the insulating film 9 may be provided between the p-type Si layer 8 </ b> A and the n-type Ge layer 3. In this case, the i-type Si layer 8B and the insulating film 9 are provided between the p-type Si layer 8A and the n-type Ge layer 3.
It should be noted that when the mesa structure 10 is selectively grown, such a configuration is used when at least the n-type Ge layer 3 runs on the insulating film 9 [here, the insulating film mask 9A; see, for example, FIG. 5A]. It becomes.

  In order to achieve such a configuration, for example, in the above-described method for manufacturing a waveguide-coupled PIN type PD5, Ge may be selectively grown under higher pressure conditions, whereby a selective growth mask is used. Only the n-type Ge layer 3 or the i-type Ge layer 2 and the n-type Ge layer 3 rides on the periphery of an insulating film 9A. In this case, the manufacturing method includes a step of forming the insulating film 9 (here, the insulating film mask 9A) so as to extend between the p-type Si layer 8A and the n-type Ge layer 3.

In this way, not only the i-type Si layer 8B but also the insulating film 9 is sandwiched between the p-type Si layer 8A and the n-type Ge layer 3 (specifically, the bottom of the n-type Ge layer 3). Thus, the response characteristic can be increased by about twice or more, and a further voltage drop can be caused to further reduce the dark current.
However, the present invention is not limited to this, and the insulating film 9 only needs to be provided between one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer. In this case, an i-type Si layer and an insulating film are provided between one n-type and p-type Si layer and the other n-type and p-type Ge or SiGe layer. Further, the manufacturing method includes a step of forming an insulating film so as to extend between one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer.

Further, the PIN type photoreceiver 5 configured as described above can be used for an optical receiver constituting an optical interconnect system.
That is, in an optical interconnect system including an optical transmitter and an optical receiver connected to the optical transmitter via an optical transmission line (here, an optical fiber), the optical receiver is configured as described above. A PIN type light receiver 5 as a semiconductor optical element provided in the apparatus can be provided. In this case, the optical receiver may be provided with a PIN light receiver 5 as a semiconductor optical element provided in the semiconductor device configured as described above as a light receiver.

  For example, as shown in FIG. 12, an optical transmitter constituting the optical interconnect system 20 is a Si optical element integrated substrate (Tx) 21 in which optical elements are integrated on a Si substrate, and a laser 22 and a ring type are used as the optical elements. The modulator 23 and the multiplexer 24 may be integrated. The optical receiver constituting the optical interconnect system 20 is an Si optical element integrated substrate (Rx) 25 in which optical elements are integrated on a Si substrate, and the PIN type light receiver 5 (for example, the optical receiver) of the above-described embodiment (for example, PIN type Ge light receiver; semiconductor light receiving element) and duplexer 26 may be used. Then, the optical interconnect system 20 may be configured by connecting these Si optical element integrated substrates 21 and 25 with an optical fiber 27. Here, a description will be given of an example in which four lasers 22, modulators 23, and light receivers 5 are provided.

  In this case, continuous light of four different wavelengths is generated using four lasers 22 mounted on one Si optical element integrated substrate 21. The continuous light of four different wavelengths passes through the Si waveguides and is converted into signal light by the ring modulator 23 joined to each Si waveguide. Thereafter, wavelength multiplexing (WDM) is performed on one waveguide by a multiplexer 24 such as an array waveguide (AWG). The multiplexed 4-wavelength signal light is guided through the optical fiber 27 and is coupled to the waveguide of another Si optical device integrated substrate 25. Thereafter, signal lights of different four wavelengths are again demultiplexed into four different waveguides by a demultiplexer 26 such as an AWG. The signal light that has traveled through each waveguide is converted into an electrical signal by the PIN light receiver 5 of the above-described embodiment.

Therefore, according to the semiconductor device, the manufacturing method thereof, and the optical interconnect system according to the present embodiment, for example, even when the height of the mesa structure 10 is lowered, a sufficient response characteristic can be obtained, and the dark current can be reduced. The effect of being able to be obtained.
In addition, this invention is not limited to the structure described in embodiment mentioned above, A various deformation | transformation is possible in the range which does not deviate from the meaning of this invention.

Hereinafter, additional notes will be disclosed regarding the above-described embodiment.
(Appendix 1)
An n-type and a p-type Si layer provided above the substrate;
The i-type Ge or SiGe layer provided on one of the n-type and p-type Si layers, and the other n-type and p-type Ge or SiGe layer covering the entire surface of the i-type Ge or SiGe layer A mesa structure consisting of
A semiconductor device comprising: one of the n-type and p-type Si layers and an i-type Si layer provided between the other n-type and p-type Ge or SiGe layer.

(Appendix 2)
An insulating film covering one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer;
A first metal electrode penetrating the insulating film and contacting one of the n-type and p-type Si layers;
Supplementary note 1 further comprising: a second metal electrode provided above the mesa structure so as to penetrate the insulating film and contact the other n-type and p-type Ge or SiGe layer. The semiconductor device described.

(Appendix 3)
The semiconductor device according to appendix 2, wherein the second metal electrode includes an opening.
(Appendix 4)
Addendum 2 or 3, wherein the insulating film is also provided between one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer. The semiconductor device described.

(Appendix 5)
The semiconductor device according to any one of appendices 1 to 4, further comprising a Si waveguide core layer optically coupled to one of the n-type and p-type Si layers.
(Appendix 6)
An optical transmitter;
An optical receiver connected to the optical transmitter via an optical transmission line;
6. The optical interconnect system, wherein the optical receiver includes the semiconductor device according to any one of appendices 1 to 5.

(Appendix 7)
A step of ion-implanting one of n-type and p-type dopants into a Si layer provided above the substrate to form one of the n-type and p-type Si layers;
An i-type Si layer is formed by ion-implanting the other n-type and p-type dopants partially in the thickness direction in a region where the outer periphery of the mesa structure of one of the n-type and p-type Si layers is provided. Forming a step;
On one of the n-type and p-type Si layers, an i-type Ge or SiGe layer and the other n-type and p-type Ge or SiGe layer covering the entire surface of the i-type Ge or SiGe layer Forming a mesa structure
In the step of forming the mesa structure, the i-type Si layer is provided between one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer. A method of manufacturing a semiconductor device, comprising forming the other n-type and p-type Ge or SiGe layer by co-doping.

(Appendix 8)
8. The method of claim 7, further comprising a step of forming an insulating film so as to extend between one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer. Semiconductor device manufacturing method.

DESCRIPTION OF SYMBOLS 1 SOI substrate 2 i-type Ge layer 3 n-type Ge layer 4A 1st metal electrode (p side electrode; Al electrode)
4B Second metal electrode (n-side electrode; Al electrode)
5 PIN receiver (PIN PD; PIN Ge receiver)
6 Si substrate 7 BOX layer 8 SOI layer (Si layer)
8A p-type Si layer 8B i-type Si layer 8X Si base part 8Y Si taper part (Si waveguide core layer)
8Z Si wire (Si waveguide core layer)
9, 9A, 9B SiO ₂ film 10 Mesa structure 11 Contact hole 12 Contact hole 20 Optical interconnect system 21 Si optical element integrated substrate (optical transmitter)
22 Laser 23 Ring modulator 24 Multiplexer 25 Si optical device integrated substrate (optical receiver)
26 Demultiplexer 27 Optical fiber

Claims (7)

An n-type and a p-type Si layer provided above the substrate;
The i-type Ge or SiGe layer provided on one of the n-type and p-type Si layers, and the other n-type and p-type Ge or SiGe layer covering the entire surface of the i-type Ge or SiGe layer A mesa structure consisting of
A semiconductor device comprising: one of the n-type and p-type Si layers and an i-type Si layer provided between the other n-type and p-type Ge or SiGe layer. An insulating film covering one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer;
A first metal electrode penetrating the insulating film and contacting one of the n-type and p-type Si layers;
2. A second metal electrode provided above the mesa structure so as to penetrate the insulating film and to contact the other n-type and p-type Ge or SiGe layer. A semiconductor device according to 1.   The semiconductor device according to claim 2, wherein the second metal electrode includes an opening.   The insulating film is also provided between one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer. A semiconductor device according to 1.   5. The semiconductor device according to claim 1, further comprising a Si waveguide core layer optically coupled to one of the n-type and p-type Si layers. 6. An optical transmitter;
An optical receiver connected to the optical transmitter via an optical transmission line;
The optical receiver includes the semiconductor device according to any one of claims 1 to 5. A step of ion-implanting one of n-type and p-type dopants into a Si layer provided above the substrate to form one of the n-type and p-type Si layers;
An i-type Si layer is formed by ion-implanting the other n-type and p-type dopants partially in the thickness direction in a region where the outer periphery of the mesa structure of one of the n-type and p-type Si layers is provided. Forming a step;
On one of the n-type and p-type Si layers, an i-type Ge or SiGe layer and the other n-type and p-type Ge or SiGe layer covering the entire surface of the i-type Ge or SiGe layer Forming a mesa structure
In the step of forming the mesa structure, the i-type Si layer is provided between one of the n-type and p-type Si layers and the other n-type and p-type Ge or SiGe layer. A method of manufacturing a semiconductor device, comprising forming the other n-type and p-type Ge or SiGe layer by co-doping.

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