JP2017212758A - Error correction decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction decoder in which the input speed to a decoder is adjusted not to decrease extremely, without increasing the number of signal wiring for input to the decoder extremely, or an error correction decoder in which the output speed from a decoder is adjusted not to decrease extremely, without increasing the number of signal wiring for output from the decoder extremely.SOLUTION: A decoder 5 decodes N input data in parallel to generate K decoded data. A S/P converter 6 outputs the N input data, inputted in series, to the decoder 5 via first wirings L1-L64, while dividing into multiple times. A P/S converter 7 receives the K decoded data from the decoder 5, while dividing into multiple times, via second wirings R1-R60, and outputs the K decoded data in series to the outside.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an error correction decoding apparatus, and more particularly to an error correction decoding apparatus for decoding a low density parity check code.

  When constructing a signal communication system, high-speed communication, low power consumption, high communication quality (low bit error rate), and the like are required. An error correction technique for detecting and correcting an error in a received code is widely used in wireless, wired and recording systems as one technique that satisfies these requirements.

  In recent years, low density parity check (LDPC) codes and sum-product decoding methods have attracted attention as one of the error correction techniques. The decoding operation using the LDPC code is discussed in Non-Patent Document 1 such as Chung et al. This Non-Patent Document 1 shows that a decoding characteristic of 0.04 dB can be obtained up to the Shannon limit of a white Gaussian channel by using an irregular LDPC code with a coding rate of 1/2. The irregular LDPC code indicates a code in which the row weight (number where 1 stands in a row) and the column weight (number where 1 stands in a column) of the parity check matrix are not constant. An LDPC code whose row weights and column weights are constant in each row and each column is called a regular LDPC code.

  This Non-Patent Document 1 shows a mathematical algorithm for decoding an LDPC code according to a sum-product decoding method, but does not show any circuit configuration that specifically performs enormous calculations.

  Yeo et al., Non-Patent Document 2, discusses the circuit configuration of an LDPC code decoding device. This Non-Patent Document 2 shows a MAP (maximum posterior probability) algorithm based on a trellis, that is, a BCJR algorithm, as an a posteriori probability of an information symbol based on a received sequence. In this trellis, forward and backward repetitions are calculated for each state, and posterior probabilities are obtained based on the forward and backward repetition values. In this calculation formula, calculation is performed using an addition / comparison / selection / addition device. Also for LDPC codes, a circuit is configured to generate a check matrix based on the sum-product decoding method and calculate an estimated value using values from different check nodes.

  Non-Patent Document 3 describes an LDPC code and a sum-product decoding method, and a min-sum decoding method in a logarithmic domain. This Non-Patent Document 3 shows that processing according to Gallager's f-function can be implemented with only four types of basic operations of addition, minimum, positive / negative determination and positive / negative sign multiplication.

  In the above-mentioned Non-Patent Documents 2 and 3, the external value logarithmic ratio α is updated using the Gallager f function according to the sum-product method in order to generate a parity check matrix and calculate a primary estimated word. Then, a process of calculating a prior value logarithmic ratio β of the symbols based on the external value logarithmic ratio is performed. For this reason, it takes a long time to calculate the Gallagher function, and the circuit scale also increases.

  The above-mentioned Non-Patent Document 3 shows that the circuit configuration at the time of mounting can be simplified in a short time by using the min-sum decoding method which is a simplified method of the sum-product decoding method. .

  Further, specific implementation methods of the min-sum decoding method are disclosed in Patent Documents 1 and 2, for example. In these documents, a configuration is disclosed in which a decoder performs parallel processing on input data in units of code length and outputs decoded data.

JP 2007-323515 A JP 2007-335992 A

S. Y. Chung et al., “On the Design of Low-Density Parity-Check Codes within 0.0045dB of the Shannon Limit” IEEE COMUNICATIONS LETTERS, VOL.5, No.2, Feb. 2001, pp.58-60 E. Yeo et al., “VLSI Architectures for Iterative Decoders in Magnetic Recording Channels” IEEE Trans. Magnetics, Vol, 37, No. 2, March 2001, pp.748-755 Wadayama Tadashi, “About Low Density Parity Check Codes and Decoding Methods”, IEICE Technical Report, MR2001-83, December 2001

  By the way, in order to input input data to a decoder that processes input data in parallel in such a code length unit, serial input data is converted into parallel data for the code length, and then the signal for the code length is converted. A configuration of outputting to a decoder through wiring is conceivable. However, in this configuration, when the code length is long, the number of signal wirings is enormous.

  On the other hand, a configuration is also conceivable in which input data for the code length is serially input to the decoder through one signal wiring. However, this configuration increases the time required for input to the decoder.

  Similarly, in order to output decoded data from the decoder to the outside, a configuration in which decoded data for the decoding length is serially output is conceivable. However, with this configuration, it takes time to output from the decoder.

  On the other hand, the decoder outputs the decoded data for the decoding length in parallel, then outputs the decoded data for the decoding length to the outside, and converts the parallel data for the decoding length to serial data externally. It is done. However, in this configuration, when the decoding length is long, the number of signal wirings is enormous.

  Therefore, an object of the present invention is to provide an error correction adjusted so that the number of signal wires for input to the decoder is not extremely increased and the input speed to the decoder is not extremely decreased. To provide an error correction decoding device adjusted so as not to extremely increase the number of signal wirings to be output from a decoding device or a decoder and to prevent the output speed of the decoder from becoming extremely low It is.

  An error correction decoding apparatus according to a first aspect of the present invention is an error correction decoding apparatus that performs decoding in units of code length N, and a decoder that decodes N pieces of input data in parallel. A series-parallel conversion circuit that divides input N pieces of input data into a plurality of times and outputs the decoded data to a decoder, and a series-parallel conversion circuit and a decoder are connected to each other, and B1 transmits one piece of input data. And a first wiring (B1 is a natural number of 2 or more and less than N).

  Preferably, the serial-parallel conversion circuit includes a first storage unit that stores N pieces of input data, and the first storage unit divides the stored N pieces of input data into a plurality of times to perform the first wiring. To the decoder.

  Preferably, the first storage unit includes B1 one-input one-output dual-port memories, and the serial-parallel conversion circuit further converts N input data input in series to B1 dual-port memories. A switch for switching to which one of them is stored is provided, and the B1 dual-port memories and the B1 first wirings are connected one-to-one.

  Preferably, the first storage unit includes B1 one-input one-output dual-port memories, and each dual-port memory stores N input data input in series redundantly, and B1 pieces The dual port memory and the B1 first wirings are connected on a one-to-one basis, and each dual port memory outputs different data among the N input data.

Preferably B1 is a common divisor of N.
An error correction decoding apparatus according to a first aspect of the present invention is an error correction decoding apparatus that performs decoding in units of a decoding length K, and generates K pieces of decoded data by decoding input data in parallel. Decoder, parallel-serial conversion circuit for receiving K pieces of decoded data from decoder in a plurality of times, and outputting K pieces of decoded data serially to the outside, and decoder and parallel-serial converter circuit And B2 (B2 is a natural number of 2 or more and less than K) second wirings.

  Preferably, the parallel-serial conversion circuit includes a second storage unit that stores K pieces of decoded data, and the second storage unit divides the K pieces of decoded data from the decoder into a plurality of times and outputs the second pieces of data. Receive through wiring.

  Preferably, the second storage unit includes B2 one-input one-output dual-port memories, and the parallel-serial conversion circuit further switches a second output from which B2 dual-port memories are output. The B2 dual-port memories and the B2 second wirings are connected on a one-to-one basis.

  Preferably, B2 is a common divisor of K.

  According to an aspect of the present invention, error correction adjusted so that the number of signal wires for input to the decoder is not extremely increased and the input speed to the decoder is not extremely slowed down. A decoding device can be realized.

  Further, according to another aspect of the present invention, an error adjusted so that the number of signal wires for output from the decoder is not extremely increased and the output speed of the decoder is not extremely decreased. A correction decoding apparatus can be realized.

It is a figure which shows an example of a structure of the communication system using the error correction decoding apparatus of embodiment of this invention. It is a figure which lists and shows the correspondence of the output data of a modulator and a demodulator in case a communication path is an optical fiber. It is a figure showing the structure of the decoder of embodiment of this invention. It is a figure which shows the structure of the m-th line (m = 1-6) processing part in FIG. It is a flowchart showing the operation | movement procedure of the error correction decoding apparatus of embodiment of this invention. It is a figure for demonstrating the transfer of the data between the S / P converter and the 1st register | resistor in a decoder in the 1st Embodiment of this invention. It is a figure for demonstrating the transfer of the data between the 2nd register | resistor in a decoder, and a P / S converter in the 1st Embodiment of this invention. It is a figure for demonstrating transfer of the data between the S / P converter and the 1st register | resistor in a decoder in the 2nd Embodiment of this invention. It is a figure for demonstrating transfer of the data between the 2nd register | resistor in a decoder, and a P / S converter in the 2nd Embodiment of this invention. It is a figure for demonstrating transfer of the data between the S / P converter and the 1st register | resistor in a decoder in the 3rd Embodiment of this invention.

[First Embodiment]
FIG. 1 is a diagram illustrating an example of a configuration of a communication system using an error correction decoding apparatus according to an embodiment of the present invention.

  In FIG. 1, in the communication system, on the transmission side, an encoder 1 that adds a redundant bit for error correction to transmission information to generate a transmission code, and (K + M) (= N) from the encoder 1 And a modulator 2 that modulates a bit code according to a predetermined method and outputs the modulated signal to the communication path 3.

  The encoder 1 adds M bits of redundant bits for parity calculation to the K information bits to generate a (K + M) (= N) -bit LDPC code (low density parity check code). In the parity check matrix H, rows correspond to redundant bits and columns correspond to code bits. Here, N corresponds to the code length.

  The modulator 2 performs modulation such as amplitude modulation, phase modulation, code modulation, frequency modulation or direct frequency division multiplexing modulation according to the configuration of the communication path 3. For example, when the communication path 3 is an optical fiber, the modulator 2 performs light intensity modulation (a kind of amplitude modulation) by changing the luminance of the laser diode according to the transmission information bit value. For example, when the transmission data bit is “0”, the emission intensity of the laser diode is increased and transmitted as “+1”, and when the transmission data bit is “1”, the emission intensity of the laser diode is decreased. Then, it is converted to “−1” and transmitted.

  In the receiving unit, the demodulated signal transmitted through the communication path 3 is demodulated to demodulate the (K + M) -bit digital code, and the (K + M) -bit code from the demodulator 4 is converted to the parity. There is provided an error correction decoding apparatus 100 that performs check matrix operation processing to reproduce the original K-bit information.

  The demodulator 4 performs demodulation processing according to the transmission form in the communication path 3. For example, in the case of amplitude modulation, phase modulation, code modulation, frequency modulation, and orthogonal frequency division multiplexing modulation, the demodulator 4 performs processing such as amplitude demodulation, phase demodulation, code demodulation, and frequency demodulation. The demodulator 4 includes a demodulation circuit 4a that demodulates a signal supplied from the communication path 3, and an A / D converter 4b that converts an analog demodulated signal generated by the demodulation circuit 4a into a digital signal. Generally, the output data Xn of the A / D converter 4b is L value (L ≧ 2) data.

  FIG. 2 is a diagram showing a list of correspondence relationships between the output data of the modulator 2 and the demodulator 4 when the communication path 3 is an optical fiber. In FIG. 2, as described above, when the communication path 3 is an optical fiber, when the transmission data is “0”, the modulator 2 increases the emission intensity of the laser diode (light emitting diode) for transmission, When “1” is output and the transmission data bit is “1”, the emission intensity is weakened and bit “−1” is transmitted.

  The light intensity transmitted to the demodulator 4 due to transmission loss in the communication path 3 has an analog intensity distribution from the strongest intensity to the weakest intensity. The demodulator 4 performs a quantization process (analog / digital conversion) on the input optical signal to detect the received light level. FIG. 2 shows the received signal intensity when the light reception level is quantized in eight steps. That is, when the light reception level is data “7”, the light emission intensity is considerably high, and when the light reception level is “0”, the light intensity is considerably low. Each light reception level is associated with signed data and output from the demodulator 4. The output of the demodulator 4 is data “3” when the light reception level is “7”, and data “−4” when the light reception level is “0”. Therefore, the demodulator 4 outputs a signal subjected to multilevel quantization with respect to a 1-bit received signal. In FIG. 2, demodulator 4 generates 3-bit data quantized to 8 levels.

  The error correction decoding apparatus 100 performs decoding in units of a code length N and a decoding length K, and includes an S / P converter 6, a decoder 5, a P / S converter 7, and an S / P. First signal lines L1 to L64 for connecting the converter 6 and the decoder 5 and second signal lines R1 to R60 for connecting the decoder 5 and the P / S converter 7 are provided.

  The S / P converter 6 converts N pieces of received information (each of which is 3-bit data) Xn serially output from the A / D converter 4b into parallel data in a plurality of times, The data is output to the decoder 5 through the first signal lines L1 to L64.

  Each of the first signal wirings L1 to L64 transmits one piece of reception information (each of which is 3-bit data).

  The decoder 5 receives the N pieces of received information Xn sent from the S / P converter 6, applies the LDPC parity check matrix according to the min-sum decoding method, and restores the original K-bit information. The decoder 5 performs a decoding process on the N pieces of received information Xn in parallel to generate a decoded word composed of K bits.

Each of the second signal wirings R1 to R60 transmits one bit of the decoded word.
The P / S converter 7 divides the K-bit decoded word from the decoder 5 into a plurality of times, receives it in parallel through the second signal wirings R1 to R60, and outputs the K-bit of the decoded word serially.

  FIG. 3 is a diagram showing the configuration of the decoder according to the embodiment of the present invention. FIG. 3 shows a configuration in which a parity check matrix having a code length N of 1024, an information bit length K of 960, and a column weight of 3, which is a number where “1” stands in each column of the parity check matrix H, is used. ing.

  Referring to FIG. 3, decoder 5 stores a first register 8 that stores data output from S / P converter 6, and a log likelihood ratio of N data in first register 8. Likelihood calculators 10-1 to 10-N, a row processing unit 34 that performs processing on a parity check matrix row, a column processing unit 35 that performs processing on a parity check matrix column, and a likelihood A decoded word generation unit 14 that generates a decoded word according to the log likelihood ratio λn from the calculators 10-1 to 10-N and the output bit (external value logarithmic ratio) αmn of the row processing unit 34, and the generated decoded word And a second register 9 for storing.

(First register)
The first register 8 is connected to the S / P converter 6 via the first signal wirings L1 to L64. The first register 8 receives the N pieces of reception information Xn from the S / P converter 6 in a plurality of times, receives the first pieces of reception information Xn through the first signal lines L1 to L64, and stores the N pieces of reception information Xn.

(Likelihood calculator)
The likelihood calculators 10-1 to 10-N generate the log likelihood ratio λn independently of the received signal noise information. Normally, when noise information is taken into consideration, this log likelihood ratio λn is given by Xn / (2 × σ ² ). Here, σ represents noise variance. However, in the embodiment of the present invention, the likelihood calculators 10-1 to 10-N are formed by a buffer circuit or a constant multiplier circuit, and the log likelihood ratio λn is given by Xn × f. Here, f is a non-zero positive number. By calculating the log likelihood ratio without using this noise information, the circuit configuration is simplified and the calculation process is also simplified. In the min-sum decoding method, since the calculation is performed using the minimum value in the check matrix processing, linearity is maintained in the signal processing. For this reason, processing such as normalization of output data according to noise information is unnecessary.

(Row processing unit and column processing unit)
The row processing unit 34 performs row processing for each element of the row of the parity check matrix H according to the equation (1), and updates the external value log ratio αmn.

  The column processing unit 35 performs column processing on each element of the column of the parity check matrix H according to the equation (2), and updates the prior value log ratio βmn.

  Here, in each of the above formulas (1) and (2), n′εA (m) \ n and m′εB (n) \ m mean elements other than themselves. For the external value log ratio αmn, n ′ ≠ n, and for the prior value log ratio βmn, m ′ ≠ m. Further, the subscript “mn” indicating the position in the matrix of α and β is usually indicated by a subscript, but in this specification, it is indicated by “horizontal characters” for the sake of readability.

  The function sign (x) is defined by the following equation (3).

  In addition, the sets A (m) and B (n) have a set [1, N] = {1, 2, when the binary M · N matrix H = [Hmn] is a parity check matrix of the LDPC code to be decoded. .., N}.

A (m) = {n: Hmn = 1}
B (n) = {m: Hmn = 1}
Next, specific configurations of the row processing unit 34 and the column processing unit 35 will be described.

  The row processing unit 34 includes a first block row processing unit 18, a second block row processing unit 19, a third block row processing unit 20, and a first block arranged corresponding to the first block row processing unit 18. An adder (β + λ) 15, a second adder (β + λ) 16 arranged corresponding to the second block row processor 19, and a third block arranged corresponding to the third block row processor 20 And an adder (β + λ) 17.

  The first block row processing unit 18 includes a first block (β + λ) storage unit 27 that stores the latest values of (β + λ) for N columns corresponding to the first block of the parity check matrix H, and a first row processing unit 28. -1 and the second row processing unit 28-2.

  The second block row processing unit 19 includes a second block (β + λ) storage unit 30 that stores the latest values of (β + λ) for N columns corresponding to the second block of the parity check matrix H, and a third row processing unit 28. -3 and a fourth row processing unit 28-4.

  The third block row processing unit 19 includes a third block (β + λ) storage unit 33 that stores the latest values of (β + λ) for N columns corresponding to the third block of the parity check matrix H, and a fifth row processing unit 28. -5 and a sixth line processing unit 28-6.

  The column processing unit 35 includes a first block (β) storage unit 24 that stores the latest values of (β) for N columns corresponding to the first block of the parity check matrix H, and a second block of the parity check matrix H. A second block (β) storage unit 25 that stores the latest value of (β) corresponding to N columns, and a latest value of (β) corresponding to N columns corresponding to the third block of the parity check matrix H are stored. Corresponding to the third block (β) storage unit 26, the first addition unit (β) 21 arranged corresponding to the first block (β) storage unit 24, and the second block (β) storage unit 25 The second addition unit (β) 22 arranged in the above manner and the third addition unit (β) 23 arranged corresponding to the third block (β) storage unit 26 are provided.

  A first adder (β + λ) 15, a second adder (β + λ) 16, a third adder (β + λ) 17, a first adder (β) 21, a second adder (β) 22, The third adder (β) 23 has N adders corresponding to the N columns, and each adder performs addition for the corresponding column.

  The operation of each element of the row processing unit 34 and the column processing unit 35 is described in detail in, for example, Japanese Unexamined Patent Application Publication No. 2007-325011.

(Mth row processing section)
FIG. 4 is a diagram illustrating a configuration of the m-th row (m = 1 to 6) processing unit in FIG. 3.

  Referring to FIG. 4, the m-th row processing unit 28-m includes a bit separation unit 36, a code calculation unit 37, an absolute value calculation unit 38, and a code multiplication unit 39.

  The bit separation unit 36 receives S signals {(λn ′ + βmn ′): n ′ is S different numbers satisfying Hmn ′ = 1}, receives a plurality of bits representing the absolute value, a sign Are separated from the bits (that is, the most significant bit), the absolute value consisting of the absolute value bits is output to the absolute value absolute value calculating unit 38, and the code consisting of the sign bits is output to the code calculating unit 37. Here, S is a row weight.

  Based on the S signals {sgn (λn ′ + βmn ′): n ′ is S different numbers satisfying Hmn ′ = 1}, the sign calculation unit 37 determines the sign part (this) Is calculated as Smn).

  Based on the S signals {| λn ′ + βmn ′ |: n ′ is S different numbers satisfying Hmn ′ = 1}, the absolute value calculation unit 38 calculates the absolute value portion ( This is calculated as Rmn).

  The sign multiplier 39 outputs an external value logarithmic ratio αmn with Smn output from the sign calculator 37 as a sign bit and Rmn output from the absolute value calculator 38 as an absolute value bit.

(Decoded word generator)
The decoded word generation unit 14 includes an adder 29, an MSB extraction unit 31, and a decoded word determination unit 32.

  The adder 29 adds the log likelihood ratio λn and the external value log ratio αmn according to the equation (4) to calculate the estimated received signal Qn.

  The MSB extraction unit 31 extracts the most significant bit of the estimated reception signal Qn as the primary estimation code Cn according to the following equation (5).

The decoded word determining unit 32 includes a multiplier and an adder, and according to the equation (6), whether the primary estimated codeword (C ₁ , C ₂ ,..., C _N ) constitutes a codeword, that is, a decoded word As appropriate. When the expression (6) is satisfied, that is, when the syndrome becomes “0”, the decoded word determination unit 32 ends the iterative calculation for the row processing unit 34 and the column processing unit 35, and the codeword (C ₁ , C ₂ ,..., C _k ) are output as decoded words. Also, the decoded word determination unit 32 causes the row processing unit 34 and the column processing unit 35 to end the iterative calculation even when the number of repetitions of the row processing and the column processing exceeds a predetermined value, and the codeword ( C ₁ , C ₂ ,..., C _k ) are output to the second register 9 as decoded words. Here, K corresponds to the decoding length.

(C ₁ , C ₂ ,..., C _N ) · H ^t = 0 (6)
(Second register)
The second register 9 stores the K-bit decoded word generated by the decoded word generation unit 14.

  The second register 9 is connected to the P / S converter 7 via the second signal wirings R1 to R60. The second register 9 outputs the K-bit decoded word to the P / S converter 7 through the second signal wirings R1 to R60 in a plurality of times.

(Operation of error correction decoding device)
FIG. 5 is a flowchart showing an operation procedure of the error correction decoding apparatus according to the embodiment of the present invention.

  Referring to FIG. 5, first, S / P converter 6 outputs N pieces of received information (each of which is 3-bit data) Xn serially output from A / D converter 4b a plurality of times. The data is divided and converted into parallel data, which is output to the decoder 5 through the first signal lines L1 to L64 (step S0).

  Next, as an initial operation, decoder 5 initializes the number of loops and the prior value logarithm ratio βmn. The number of loops indicates the number of repetitions of column processing and row processing. A maximum value is predetermined for the number of loops. The prior value logarithmic ratio βmn is initially set to “0” (step S1).

  Next, the likelihood calculator 10-n (n = 1 to N) calculates the log likelihood ratio λn of the received information Xn (step S2).

Next, the row processing unit 34 performs row processing for each element of the row of the parity check matrix H according to the equation (1), and updates the external value log ratio αmn (step S3).

  Next, the column processing unit 35 performs column processing for each element of the column of the parity check matrix H according to the equation (2), and updates the prior value logarithmic ratio βmn (step S4).

Next, the decoded word generation unit 14 uses the log likelihood ratio λn and the external value log ratio αmn to calculate the estimated received signal Q _n according to the equation (4) (step S5).

Next, the decoded word generation unit 14 calculates a temporary estimated code C _n from the estimated received signal Q _n according to Expression (5) (step S6).

Next, the decoded word generation unit 14 determines whether the primary estimated codewords (C ₁ , C ₂ ,..., C _N ) form a code word according to the equation (6), that is, is appropriate as a decoded word. Parity check.

When the expression (6) is satisfied, that is, when the syndrome becomes “0” (YES in step S7), the decoded word generation unit 14 ends the iterative calculation for the row processing unit 34 and the column processing 35. , Code words (C ₁ , C ₂ ,..., C _k ) are output as decoded words C (= (C ₁ , C ₂ ,..., C _k )) (step S10).

In addition, when the expression (6) is not satisfied (NO in step S7), the decoded word generation unit 14 determines that the row processing unit 34 and the column processing unit 35 have the loop count reaches the maximum value (YES in step S8). On the other hand, the iterative operation is terminated, and the code word (C ₁ , C ₂ ,..., C _k ) is output as a decoded word C (= (C ₁ , C ₂ ,..., C _k )) (step S10).

  Next, the P / S converter 7 divides the K-bit decoded word from the decoder 5 into a plurality of times, receives it in parallel through the second signal wirings R1 to R60, and serially receives the K bits of the decoded word. Output (step S11).

  On the other hand, when the expression (6) is not satisfied (NO in step S7) and the number of loops does not reach the maximum value (NO in step S8), the decoded word generation unit 14 increments the number of loops by 1. (Step S9), returning to Step S3, the process is repeated.

(S / P converter)
FIG. 6 is a diagram for explaining data transfer between the S / P converter 6 and the first register 8 in the decoder 5 in the first embodiment of the present invention.

  Referring to FIG. 6, S / P converter 6 includes a first switch SWA and a first storage unit 110. The first storage unit 110 includes 64 dual port memories DPA1 to DPA64.

  Each of the dual port memories DPA1 to DPA64 has a capacity of 3 × 16 bits and stores 64 pieces of 3-bit data. Each of the dual port memories DPA1 to DPA64 is connected to the first signal wirings L1 to L64 on a one-to-one basis.

  First, data transfer from the A / D converter 4b to the dual port memories DPA1 to DPA64 will be described.

  The first switch SW1 switches the storage destination in units of 64 pieces of 3-bit serial data output from the A / D converter 4b. That is, the first switch SWA sequentially outputs the first to sixteenth data output from the A / D converter 4b to the dual port memory DPA1. Next, the first switch SWA sequentially outputs the 17th to 32nd data output from the A / D converter 4b to the dual port memory DPA2. Similarly, the first switch SWA sequentially outputs the 1009th to 1024th data finally output from the A / D converter 4b to the dual port memory DPA64.

  As a result, the first to sixteenth data are stored in the dual port memory DPA1 in order from the top. The dual port memory DPA2 stores the 17th to 32nd data in order from the top. Similarly, the dual port memory DPA 64 stores the 1009th to 1024th data in order from the top.

  Next, data transfer from the dual port memories DPA1 to DPA64 to the first register 8 will be described.

  64 data is transferred from the dual port memories DPA1 to DPA64 to the first register 8 through the first signal lines L1 to L64 at a time.

  In the first time, data stored at the head position of each of the dual port memories DPA1 to DPA64 is output in parallel to the first register 8 through the first signal lines L1 to L64. Specifically, the first data stored in the head position of the dual port memory DPA1 is sent to the first storage position of the first register 8 through the first signal line L1. The 17th data stored at the head position of the dual port memory DPA2 is sent to the 17th storage position of the first register 8 through the first signal line L2. Thereafter, similarly, the 1009th data stored at the head position of the dual port memory DPA 64 is sent to the 1009th storage position of the first register 8 through the first signal line L64.

  In the second time, data stored in the second position from the top of each of the dual port memories DPA1 to DPA64 is output in parallel to the first register 8 through the first signal lines L1 to L64. Specifically, the second data stored in the second position from the beginning of the dual port memory DPA1 is sent to the second storage position of the first register 8 through the first signal line L1. It is done. The eighteenth data stored in the second position from the beginning of the dual port memory DPA2 is sent to the eighteenth storage position of the first register 8 through the first signal line L2. Similarly, the 1010th data stored in the second position from the top of the dual port memory DPA 64 is transferred to the 1010th storage position of the first register 8 through the first signal line L64. Sent.

  In the same manner, 1024 data stored in the dual port memories DPA1 to DPA64 are divided into 16 times 64 times and sent to the first register 8.

(P / S converter)
FIG. 7 is a diagram for explaining data transfer between the second register 9 in the decoder 5 and the P / S converter 7 in the first embodiment of the present invention.

  Referring to FIG. 7, P / S converter 7 includes a second storage unit 120 and a second switch SWB. The second storage unit 120 includes 60 dual port memories DPB1 to DPB60.

  Each of the dual port memories DPB1 to DPB60 has a capacity of 1 × 16 bits and stores 16 pieces of 1-bit data. The dual port memories DPB1 to DPB60 are connected to the second signal wirings R1 to R60 on a one-to-one basis.

  First, data transfer from the second register 9 to the dual port memories DPB1 to DPB60 will be described.

  From the second register 9 to the dual port memories DPB1 to DPB60, 60 pieces of data are transferred at a time through the second signal lines R1 to R60.

  In the first time, the first data stored in the second register 9 is output to the first storage position of the dual port memory DPB1 through the second signal wiring R1. At the same time, the 17th data stored in the second register 9 is output to the top storage position of the dual port memory DPB2 through the second signal wiring R2. Thereafter, in the same manner, the 945th data stored in the second register 9 is simultaneously output to the top storage position of the dual port memory DPB60 through the second signal wiring R60.

  In the second time, the second data stored in the second register 9 is output from the head of the dual port memory DPB1 to the second storage position through the second signal wiring R1. At the same time, the 18th data stored in the second register 9 is output from the top of the dual port memory DPB2 to the second storage position through the second signal line R2. Thereafter, in the same manner, the 946th data stored in the second register 9 is simultaneously output from the head of the dual port memory DPB60 to the second storage position through the second signal line R60.

  Thereafter, in the same manner, 960 data stored in the second register 9 are divided into 16 times each 60 times and sent to the dual port memories DPB1 to DPB60.

  Next, data transfer from the dual port memories DPB1 to DPB60 to the outside will be described.

  The second switch SWB switches which of the dual port memories DPB1 to DPB60 is output every 16 pieces. That is, first, the second switch SWB switches the input source to the dual port memory DPB1, and sequentially outputs the first to sixteenth data stored in the dual port memory DPB1. Next, the second switch SWB switches the input source to the dual port memory DPB2, and sequentially outputs the 17th to 32nd data stored in the dual port memory DPB2. Hereinafter, similarly, finally, the second switch SWB switches the input source to the dual port memory DPB60, and sequentially outputs the 945th to 960th data stored in the dual port memory DPB60.

  As described above, according to the error correction decoding apparatus of the embodiment of the present invention, the number of signal wires from the S / P converter to the decoder is 64 for the code length 1024, and the S / P conversion is performed. Since the data is transferred in parallel from the transmitter to the decoder in 64 times, 64 data are transferred in parallel each time, the number of signal wirings can be increased at a higher speed than when all 1024 data are transferred serially. The transfer speed is slower than transferring all the pieces of data in parallel, but the number of signal lines can be reduced.

  Similarly, according to the error correction decoding apparatus of the embodiment of the present invention, with respect to the decoding length 960, the number of signal wirings from the decoder to the P / S converter is set to 60, and from the decoder Since 60 data are transferred in parallel to the P / S converter in 16 times, the number of signal wirings is increased compared to serial transfer of all 960 data, but the data can be transferred at high speed. The transfer speed is slower than transferring all the pieces of data in parallel, but the number of signal lines can be reduced.

  With the configuration as described above, it is possible to realize a reasonable configuration in which the request for reducing the number of signal wires and the request for increasing the transfer speed are harmonized.

[Second Embodiment]
(S / P converter)
FIG. 8 is a diagram for explaining data transfer between the S / P converter 6a and the first register 8 in the decoder 5 in the second embodiment of the present invention.

  Referring to FIG. 8, S / P converter 6 a includes a first switch SWA and a first storage unit 110. The first storage unit 110 includes 64 dual port memories DPA1 to DPA64.

  Each of the dual port memories DPA1 to DPA64 has a capacity of 3 × 16 bits and stores 64 pieces of 3-bit data. Each of the dual port memories DPA1 to DPA64 is connected to the first signal wirings L1 to L64 on a one-to-one basis.

  First, data transfer from the A / D converter 4b to the dual port memories DPA1 to DPA64 will be described.

  The first switch SW1 switches the storage destination of each 3-bit serial data output from the A / D converter 4b one by one. That is, the first switch SWA outputs the first data output from the A / D converter 4b to the head position of the dual port memory DPA1. Next, the first switch SWA outputs the second data output from the A / D converter 4b to the head position of the dual port memory DPA2. Similarly, the first switch SWA outputs the 64th data output from the A / D converter 4b to the head position of the dual port memory DPA64.

  Further, the first switch SWA outputs the 65th data output from the A / D converter 4b to the second position from the top of the dual port memory DPA1. Next, the first switch SWA outputs the 66th data output from the A / D converter 4b to the second position from the top of the dual port memory DPA2. Similarly, the first switch SWA outputs the 128th data output from the A / D converter 4b to the second position from the top of the dual port memory DPA64.

  By repeating the above processing, the dual port memory DPA1 stores the first, 65th,..., 961st data in order from the top. The dual port memory DPA2 stores second, 66th,..., 962nd data in order from the top. Similarly, the dual port memory DPA 64 stores the 64th, 128th,..., 1024th data in order from the top.

  Next, data transfer from the dual port memories DPA1 to DPA64 to the first register 8 will be described.

64 data is transferred from the dual port memories DPA1 to DPA64 to the first register 8 through the first signal lines L1 to L64 at a time.
Data transfer will be described.

  In the first time, data stored at the head position of each of the dual port memories DPA1 to DPA64 is output in parallel to the first register 8 through the first signal lines L1 to L64. Specifically, the first data stored in the head position of the dual port memory DPA1 is sent to the first storage position of the first register 8 through the first signal line L1. At the same time, the second data stored at the head position of the dual port memory DPA2 is sent to the second storage position of the first register 8 through the first signal line L2. Thereafter, similarly, the 64th data stored at the head position of the dual port memory DPA 64 is simultaneously sent to the 64th storage position of the first register 8 through the first signal line L64.

  In the second time, data stored in the second position from the top of each of the dual port memories DPA1 to DPA64 is output in parallel to the first register 8 through the first signal lines L1 to L64. Specifically, the 65th data stored in the second position from the beginning of the dual port memory DPA1 is sent to the 65th storage position of the first register 8 through the first signal line L1. It is done. At the same time, the 66th data stored in the second position from the top of the dual port memory DPA2 is sent to the 66th storage position of the first register 8 through the first signal line L2. In the same manner, the 128th data stored in the second position from the top of the dual port memory DPA 64 at the same time passes through the first signal line L64 and the 128th storage position of the first register 8 at the same time. Sent to.

  In the same manner, 1024 data stored in the dual port memories DPA1 to DPA64 are divided into 16 times 64 times and sent to the first register 8.

(P / S converter)
FIG. 9 is a diagram for explaining data transfer between the second register 9 in the decoder 5 and the P / S converter 7a in the second embodiment of the present invention.

  Referring to FIG. 7, P / S converter 7a includes a second storage unit 120 and a second switch SWB. The second storage unit 120 includes 60 dual port memories DPB1 to DPB60.

  Each of the dual port memories DPB1 to DPB60 has a capacity of 1 × 16 bits and stores 16 pieces of 1-bit data. Each of the dual port memories DPB1 to DPB60 is connected to the second signal wirings R1 to R60 on a one-to-one basis.

  First, data transfer from the second register 9 to the dual port memories DPB1 to DPB60 will be described.

  From the second register 9 to the dual port memories DPB1 to DPB60, 60 pieces of data are transferred at a time through the second signal lines R1 to R60.

  In the first time, the first data stored in the second register 9 is output to the first storage position of the dual port memory DPB1 through the second signal wiring R1. At the same time, the second data stored in the second register 9 is output to the top storage position of the dual port memory DPB2 through the second signal wiring R2. Thereafter, similarly, the 60th data stored in the second register 9 is simultaneously output to the top storage position of the dual port memory DPB60 through the second signal line R60.

  In the second time, the 61st data stored in the second register 9 is output from the head of the dual port memory DPB1 to the second storage position through the second signal wiring R1. At the same time, the 62nd data stored in the second register 9 is output from the beginning of the dual port memory DPB2 to the second storage position through the second signal line R2. Thereafter, similarly, the 120th data stored in the second register 9 is simultaneously output from the top of the dual port memory DPB60 to the second storage position through the second signal line R60.

  Thereafter, in the same manner, 960 data stored in the second register 9 are divided into 16 times each 60 times and sent to the dual port memories DPB1 to DPB60.

  Next, data transfer from the dual port memories DPB1 to DPB60 to the outside will be described.

  The second switch SWB switches one of the dual port memories DPB1 to DPB60 to be output one by one. That is, first, the second switch SWB switches the input source to the dual port memory DPB1, and outputs the first data stored at the head position of the dual port memory DPB1. Next, the second switch SWB switches the input source to the dual port memory DPB2, and outputs the second data stored at the head position of the dual port memory DPB2. Similarly, the second switch SWB switches the input source to the dual port memory DPB60 and outputs the 60th data stored at the head position of the dual port memory DPB60.

Further, the second switch SWB switches the input source to the dual port memory DPB1, and outputs the 61st data stored in the second position from the top of the dual port memory DPB1. Next, the second switch SWB switches the input source to the dual port memory DPB2, and outputs the 62nd data stored in the second position from the top of the dual port memory DPB2. Similarly, the second switch SWB switches the input source to the dual port memory DPB60 and outputs the 120th data stored in the second position from the top of the dual port memory DPB60.
By repeating the above processing, the first to 1024th data stored in the dual port memories DPB1 to DPB60 are sequentially output serially.

  As described above, in the embodiment of the present invention, as in the first embodiment, it is possible to realize a reasonable configuration in which the request for reducing the number of signal wirings and the request for increasing the transfer speed are harmonized.

[Third Embodiment]
(S / P converter)
FIG. 10 is a diagram for explaining data transfer between the S / P converter 6b and the first register 8 in the decoder 5 in the third embodiment of the present invention.

  Referring to FIG. 10, S / P converter 6 b includes a first storage unit 130. The first storage unit 130 includes 64 dual port memories DPC1 to DPC64.

  Each of the dual port memories DPC1 to DPC64 has a capacity of 3 × 1024 bits and stores 1024 pieces of 3-bit data. In each of the dual port memories DPC1 to DPC64, data is read from a designated address. Each of the dual port memories DPC1 to DPC64 is connected to the first signal wirings L1 to L64 on a one-to-one basis.

  First, data transfer from the A / D converter 4b to the dual port memories DPC1 to DPC64 will be described.

  First, the first data output from the A / D converter 4b is output to the top positions of the dual port memories DPC1 to DPC64. Next, the second data output from the A / D converter 4b is output to the second position from the top of the dual port memories DPC1 to DPC64. Similarly, the 1024th data finally output from the A / D converter 4b is output to the 1024th position from the top of the dual port memories DPC1 to DPC64.

  As a result, the first to 1024th data are sequentially stored in the dual port memories DPC1 to DPC64 in order from the top.

  Next, data transfer from the dual port memories DPC1 to DPC64 to the first register 8 will be described.

  From the dual port memories DPC1 to DPC64 to the first register 8, 64 different data at a time are transferred in parallel through the first signal lines L1 to L64.

  In the first time, the head position of the dual port memory DPC1 is addressed, and the first data stored therein is stored in the first register 8 through the first signal line L1. Sent to location. At the same time, the second position from the top of the dual port memory DPC2 is addressed, and the second data stored in the second position is transmitted through the first signal line L2 to the second position of the first register 8. Sent to the storage location. In the same manner, the 64th position from the top of the dual port memory DPC 64 is addressed at the same time, and the 64th data stored therein is transferred to the first register through the first signal line L64. 8 is sent to the 64th storage position.

  In the second time, the 65th position from the top of the dual port memory DPC1 is addressed, and the 65th data stored therein is transferred to the first register 8 through the first signal line L1. Sent to the 65th storage position. At the same time, the 66th position from the beginning of the dual port memory DPC2 is addressed, and the 66th data stored therein is transferred to the 66th position of the first register 8 through the first signal line L2. Sent to the storage location. In the same manner, the 128th position stored at the 128th position from the top of the dual port memory DPC 64 is addressed in the same manner, and the 128th data stored therein is the first. Is sent to the 128th storage position of the first register 8 through the signal wiring L64.

  In the same manner, 1024 different data stored in the dual port memories DPC1 to DPC64 are divided into 64 pieces each 16 times and sent to the first register 8.

  As described above, in the embodiment of the present invention, as in the first embodiment, it is possible to realize a reasonable configuration in which the request for reducing the number of signal wirings and the request for increasing the transfer speed are harmonized. Further, by eliminating the need for the first switch SWA, it is possible to avoid technical requirements regarding the high-speed operation of the first switch SWA.

(Modification)
The present invention is not limited to the above embodiment, and includes, for example, the following modifications.

(1) Number of signal wirings and number of transfers In the embodiment of the present invention, the S / P converter and the decoder are connected by 64 first signal wirings. Then, from the S / P converter to the decoder, 1024 data corresponding to the code length 1024 are divided into 16 times and 64 parallel data are transferred each time. However, the present invention is not limited to this. Absent. For example, when the code length is N, the number of first signal wirings may be the common divisor B1 of N, and data may be transferred divided into N / B1 (times). Here, B1 is a natural number of 2 or more and less than N. The number of such first signal wires is the common divisor of the code length, the processing contents of each time are shared, and the processing algorithm is simplified.

  Alternatively, the number of first signal wirings may be a number that is not a common divisor of N, and the last data transfer may be performed using only a part of the first signal wirings.

  Similarly, in the embodiment of the present invention, the decoder and the P / S converter are connected by 60 second signal wires. And, from the decoder to the P / S converter, 960 pieces of data corresponding to the decoding length 960 were divided into 16 times and 60 pieces of parallel data were transferred each time. However, the present invention is not limited to this. Absent. For example, when the decoding length is K, the number of second signal wirings may be a common divisor B2 of K, and data may be transferred divided into K / B2 (times). Here, B2 is a natural number of 2 or more and less than K. The number of such second signal wires is the common divisor of the decoding length, the processing contents of each time are made common, and the processing algorithm is simplified.

  Alternatively, the number of second signal wirings may be a number that is not a common divisor of K, and the last data transfer may be performed using only a part of the second signal wirings.

(2) 1st memory | storage part, 2nd memory | storage part In 1st and 2nd embodiment of this invention, the 1st memory | storage part is 1st switch SWA which switches 64 output destinations, and 64 pieces. Although the 1-input 1-output dual port memories DPA1 to DPA64 are provided, the present invention is not limited to this. For example, a third switch SWC that switches 32 output destinations and 32 2-input 2-output memories DPD1 to DPD32 may be provided.

  In the first and second embodiments of the present invention, the second storage unit includes the second switch SWB that switches 60 output destinations and 60 one-input one-output dual port memories DPB1 to DPB60. Although provided, it is not limited to this. For example, a fourth switch SWD for switching 30 input destinations and 30 2-input 2-output memories DPE1 to DPE30 may be provided.

(3) Likelihood Calculator In the embodiment of the present invention, N likelihood calculators are provided after the S / P converter. However, the present invention is not limited to this. One likelihood calculator may be provided in the preceding stage of the S / P converter.

(4) Number of bits of each input data and each output data to the decoder In the embodiment of the present invention, each decoder inputs 3 bits of data (multi-value data), and from the decoder Each outputs 1-bit data (binary data), but is not limited to this.

  For example, when 1-bit data (binary data) is input to the decoder, each of the first signal wirings may transfer 1-bit data. Similarly, when 3-bit data (multi-level data) is output from the decoder, each of the second signal wirings may transfer 3-bit data.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 Encoder, 2 Modulator, 3 Communication Channel, 4 Demodulator, 4a Demodulator, 4b A / D Converter, 5 Decoder, 6, 6a, 6b S / P Converter, 7, 7a P / S Converter, 15, 16, 17, 21, 22, 23, 29 adder, 10-1 to 10-N likelihood calculator, 14 decoded word generation unit, 24 first block (β) storage unit, 25 second Block (β) storage unit, 26 third block (β) storage unit, 27 first block (β + λ) storage unit, 30 second block (β + λ) storage unit, 33 third block (β + λ) storage unit, 28-1 1st line processing part, 28-2 2nd line processing part, 28-3 3rd line processing part, 28-4 4th line processing part, 28-5 5th line processing part, 28-6 6th line processing part 28-m m-th row processing unit, 31 MSB extraction unit, 32 decoded word determination unit, 34 row processing unit, 35 columns Processing unit, 36-bit separation unit, 37 code calculation unit, 38 absolute value calculation unit, 39 code multiplication unit, 100 error correction decoding device, 110, 130 first storage unit, 120 second storage unit, DPA1 to DPA64, DPB1 to DPB60, DPC1 to DPC64 Dual port memory, SWA first switch, SWB second switch, L1 to L64 first signal wiring, R1 to R60 second signal wiring.

Claims (1)

An error correction decoding apparatus that performs decoding in units of code length N,
A decoder for decoding N input data in parallel;
A serial-to-parallel converter circuit that outputs N pieces of input data input in series to the decoder in a plurality of times;
An error comprising: B1 (B1 is a natural number of 2 or more and N), each of which connects the serial-parallel conversion circuit and the decoder and each transmits one input data. Correction decoding device.