JP2017208400A - Semiconductor light-emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device capable of improving withstand voltage. A semiconductor light emitting device 1 includes a substrate 2. On the substrate 2, an epitaxial layer 6 including an n-type first semiconductor layer 7, a light emitting layer, and a p-type second semiconductor layer 9 laminated in this order from the substrate 2 side is formed. The first pad electrode 17 is arranged on the first semiconductor layer 7, and the second pad electrode 18 is arranged on the second semiconductor layer 9. In the region between the second pad electrode 18 and the second semiconductor layer 9, a high resistance layer 31 having a resistance value higher than the resistance value of the second semiconductor layer 9 is selectively provided. The high resistance layer 31 includes a permissible portion 33 that allows the facing portion 32 facing the second pad electrode 18 in the second semiconductor layer 9 and the first current path P1 passing through the second pad electrode 18 to be formed. ing. [Selection diagram] Fig. 2

Description

  The present invention relates to a semiconductor light emitting device.

  Patent Document 1 discloses a substrate, a first layer (first semiconductor layer) stacked on the substrate, an active layer (light emitting layer) stacked on the first layer, and a first layer stacked on the active layer. LED comprising two layers (second semiconductor layer), a first electrode (first pad electrode) disposed on the first layer, and a second electrode (second pad electrode) disposed on the second layer (Semiconductor light emitting device) is disclosed. In this LED, an insulating island is provided between the second layer and the second electrode to prevent current from being supplied to the facing portion of the second layer facing the second electrode.

JP 2011-517100 A

  In Patent Document 1, in order to prevent light from being generated in the light emitting layer below the second pad electrode, a current blocking layer (current blocking layer) called an insulation island is formed on the second pad in the second semiconductor layer. It is provided so as to cover the entire area of the facing portion facing the electrode. Therefore, when the current flows between the facing portion of the second semiconductor layer and the second pad electrode, the current blocking layer is largely bypassed. Therefore, the current is locally concentrated between the second pad electrode and the second semiconductor layer, particularly around the current blocking layer, and the electric field distribution is dense between the second pad electrode and the second semiconductor layer. There is a possibility that a region, that is, a region where the electric field is concentrated may be generated. When electric field concentration occurs between the second pad electrode and the second semiconductor layer, there is a problem in that the breakdown voltage of the semiconductor light emitting element is reduced.

By removing the current blocking layer from between the second pad electrode and the second semiconductor layer, the above problem can be solved. However, in this case, since the current flows through the region between the second pad electrode and the second semiconductor layer without being shielded, the electric field concentrates on the second pad electrode, and the breakdown voltage of the semiconductor light emitting device is reduced. There is a risk.
Therefore, an object of the present invention is to provide a semiconductor light emitting device capable of improving the breakdown voltage.

  The semiconductor light-emitting device of the present invention includes a substrate, and a semiconductor layer including a first conductive type first semiconductor layer, a light emitting layer, and a second conductive type second semiconductor layer stacked on the substrate in this order from the substrate side. A first pad electrode disposed on the first semiconductor layer, a second pad electrode disposed on the second semiconductor layer, and a region between the second pad electrode and the second semiconductor layer And a high resistance layer having a resistance value higher than the resistance value of the second semiconductor layer, the high resistance layer being opposed to the second pad electrode in the second semiconductor layer And a current path that passes through the second pad electrode and an allowance portion that allows the current path to be formed between the second pad electrode and the facing portion of the second semiconductor layer.

  According to the semiconductor light emitting device of the present invention, the current flowing between the second pad electrode and the second semiconductor layer can be dispersed inside and outside the opposing portion of the second semiconductor layer by the high resistance layer. Therefore, a current can flow between the opposing portion of the second semiconductor layer and the second pad electrode without greatly bypassing the high-resistance layer, so that the region between the second pad electrode and the second semiconductor layer It is possible to suppress the local concentration of current. As a result, it is possible to suppress the formation of a region where the electric field distribution is dense between the second pad electrode and the second semiconductor layer. The occurrence of electric field concentration on the two-pad electrode can be suppressed. As a result, it is possible to provide a semiconductor light emitting device capable of improving the breakdown voltage.

FIG. 1 is a plan view showing a semiconductor light emitting device according to the first embodiment of the present invention. 2 is a longitudinal sectional view taken along line II-II in FIG. FIG. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4 is a longitudinal sectional view showing a semiconductor light emitting device according to a reference example. 5A to 5C are microscopic images showing one aspect of electrostatic breakdown of the semiconductor light emitting device according to the reference example of FIG. FIG. 6A is a longitudinal sectional view showing a step in the method for manufacturing the semiconductor light emitting device of FIG. FIG. 6B is a longitudinal sectional view showing a step subsequent to FIG. 6A. FIG. 6C is a longitudinal sectional view showing a step subsequent to FIG. 6B. FIG. 6D is a longitudinal sectional view showing a step subsequent to FIG. 6C. FIG. 6E is a longitudinal sectional view showing a step subsequent to FIG. 6D. FIG. 6F is a longitudinal sectional view showing a step subsequent to FIG. 6E. FIG. 7 is a plan view showing a semiconductor light emitting device according to the second embodiment of the present invention. 8 is a longitudinal sectional view taken along line VIII-VIII in FIG. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. FIG. 10 is a plan view showing a semiconductor light emitting device according to the third embodiment of the present invention. FIG. 11A is a plan view showing a semiconductor light emitting element according to the fourth embodiment of the present invention. FIG. 11B is an enlarged plan view of a region surrounded by an alternate long and short dash line XIB in FIG. 11A. 12 is a longitudinal sectional view taken along line XII-XII in FIG. 11A. FIG. 13 is a microscopic image showing one aspect of electrostatic breakdown of the semiconductor light emitting device according to the reference example of FIG. FIG. 14 is a longitudinal sectional view showing a semiconductor light emitting device according to the fifth embodiment of the present invention. FIG. 15 is a longitudinal sectional view showing a semiconductor light emitting element according to the sixth embodiment of the present invention. FIG. 16 is a longitudinal sectional view showing a semiconductor light emitting element according to the seventh embodiment of the present invention. FIG. 17 is a cross-sectional view showing a first modification of the semiconductor light emitting device of FIG. FIG. 18 is a cross-sectional view illustrating a second modification of the semiconductor light emitting device of FIG. FIG. 19 is a plan view showing a third modification of the semiconductor light emitting device of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a plan view showing a semiconductor light emitting device 1 according to the first embodiment of the present invention. 2 is a longitudinal sectional view taken along line II-II in FIG. FIG. 3 is a cross-sectional view taken along line III-III in FIG.
As shown in FIGS. 1 and 2, the semiconductor light emitting device 1 according to the present embodiment includes a rectangular parallelepiped substrate 2. The substrate 2 may be a sapphire substrate. The board | substrate 2 has the one surface 3, the other surface 4 on the other side, and the four side surfaces 5 which connect them. On one surface 3 of the substrate 2, an epitaxial layer 6 as an example of the semiconductor layer of the present invention is formed.

  The epitaxial layer 6 covers the entire area of the one surface 3 of the substrate 2. The epitaxial layer 6 includes an n-type first semiconductor layer 7, a light emitting layer 8, and a p-type second semiconductor layer 9 that are stacked in this order from the one surface 3 side of the substrate 2. The first semiconductor layer 7, the light emitting layer 8, and the second semiconductor layer 9 all include a group III nitride semiconductor. The first semiconductor layer 7, the light emitting layer 8, and the second semiconductor layer 9 may include gallium nitride (GaN).

  The epitaxial layer 6 includes a mesa structure 10 formed by selectively notching a part of the first semiconductor layer 7, the light emitting layer 8, and the second semiconductor layer 9 so as to expose the first semiconductor layer 7. It is a region outside the mesa structure 10 and has an outer peripheral region 11 where the first semiconductor layer 7 is exposed. The outer peripheral region 11 has a single layer structure composed of the first semiconductor layer 7 and is formed in a fan shape at one corner of the one surface 3 of the substrate 2 in plan view.

  The mesa structure 10 is formed in an L shape so as to surround the outer peripheral region 11 in plan view. In the present embodiment, the mesa structure 10 has a flat portion 12 positioned above the outer peripheral region 11, a peripheral edge 13 positioned outside the flat portion 12, and an inclination inclined downward from the flat portion 12 toward the peripheral edge 13. Part 14. A part of the first semiconductor layer 7, the light emitting layer 8, and the second semiconductor layer 9 are exposed at the inclined portion 14 of the mesa structure 10.

A first transparent electrode layer 15 electrically connected to the first semiconductor layer 7 and a second transparent electrode layer 16 electrically connected to the second semiconductor layer 9 are disposed on the epitaxial layer 6. Yes. The first transparent electrode layer 15 and the second transparent electrode layer 16 include, for example, indium tin oxide (ITO).
The first transparent electrode layer 15 is joined to the outer peripheral region 11 at a distance from the mesa structure 10 and the side surface 5 of the substrate 2. In the present embodiment, the first transparent electrode layer 15 is formed in a fan shape substantially similar to the outer peripheral region 11 in plan view. On the other hand, the second transparent electrode layer 16 is disposed on the flat portion 12 of the mesa structure 10 so as to be joined to the second semiconductor layer 9. In the present embodiment, the second transparent electrode layer 16 is formed in an L shape that is substantially similar to the mesa structure 10 in plan view.

  A first pad electrode 17 that is electrically connected to the first semiconductor layer 7 is disposed on the first transparent electrode layer 15, and the second semiconductor layer 9 is electrically connected to the second transparent electrode layer 16. A second pad electrode 18 to be connected is disposed. The first pad electrode 17 also serves as a first external terminal that is externally connected, and the second pad electrode 18 also serves as a second external terminal that is externally connected. In the present embodiment, the first pad electrode 17 and the second pad electrode 18 are arranged at a distance from each other along one diagonal line of the substrate 2 in plan view.

  In the present embodiment, the first pad electrode 17 is formed in a fan-shaped column shape substantially similar to the first transparent electrode layer 15 in plan view. The first pad electrode 17 may have a laminated structure in which a plurality of metal films are laminated, or may have a single layer structure made of one metal film. In the present embodiment, the first pad electrode 17 has a two-layer structure including a first electrode layer 19 and a second electrode layer 20 stacked in this order from the first transparent electrode layer 15 side.

  The first electrode layer 19 includes Cr (chromium), and the second electrode layer 20 includes Au (gold). The first electrode layer 19 has a thickness smaller than that of the second electrode layer 20. The thickness of the first electrode layer 19 is, for example, 100 mm or more and 1000 mm or less (300 mm in this embodiment), and the thickness of the second electrode layer 20 is, for example, 15000 mm or more and 25000 mm or less (20,000 mm in this embodiment).

  In the present embodiment, the second pad electrode 18 is formed in a columnar shape having a circular shape in plan view. The second pad electrode 18 has a facing surface 18a that faces the first pad electrode 17 in plan view. The second pad electrode 18 may have a laminated structure in which a plurality of metal films are laminated, or may have a single layer structure made of one metal film. In the present embodiment, the second pad electrode 18 has a two-layer structure including the first electrode layer 21 and the second electrode layer 22 laminated in this order from the second transparent electrode layer 16 side. The first electrode layer 21 and the second electrode layer 22 of the second pad electrode 18 are both formed of the same material and the same thickness as the first electrode layer 19 and the second electrode layer 20 of the first pad electrode 17. .

  The first pad electrode 17 may be formed in a columnar shape having a circular shape in plan view, or may be formed in a columnar shape having a polygonal shape in plan view, such as a triangular shape in plan view, a quadrangular shape in plan view, or a hexagonal shape in plan view. May be. Further, the second pad electrode 18 may be formed in a columnar shape having a polygonal shape in a plan view such as a triangular shape in plan view, a quadrangular shape in plan view, a hexagonal shape in plan view, or a circular arc surface in the plan view. You may form in the fan-shaped column shape facing 17 side.

A passivation film 23 is formed on the epitaxial layer 6 so as to cover the surface of the epitaxial layer 6. More specifically, the passivation film 23 covers the inclined portion 14 of the mesa structure 10 so that a part of the passivation film 23 overlaps the flat portion 12 and the outer peripheral region 11 of the mesa structure 10. The passivation film 23 includes, for example, silicon oxide (SiO ₂ ).

  In order to reflect the light generated in the epitaxial layer 6 (light emitting layer 8) toward the epitaxial layer 6 side so as to cover the entire area of the other surface 4 of the substrate 2 on the other surface 4 side of the substrate 2. The light reflecting layer 24 is formed. The light reflecting layer 24 may have a single layer structure made of one metal film, or may have a stacked structure in which a plurality of metal films are stacked. The light reflecting layer 24 may be formed of one or more metal films selected from the group including aluminum (Al), gold (Au), and silver (Ag).

The light reflecting layer 24 may be an insulating layer having a stacked structure in which a plurality of insulating films having different refractive indexes are stacked. The light reflecting layer 24 may be a DBR (Distributed Bragg Reflector) layer having a laminated structure in which insulating films having different refractive indexes are alternately laminated with an optical length of ¼ wavelength. The DBR layer is formed of two or more insulating films selected from the group including ZrO ₂ , Al ₂ O ₃ , SiO ₂ , TiO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , AlN, SiN, AlON and SiON. May be.

The light reflecting layer 24 may have a laminated structure including both a metal film and an insulating film (DBR layer). In this case, the light reflecting layer 24 may have a laminated structure including a metal film and an insulating film (DBR layer) from the other surface 4 side of the substrate 2 or an insulating film (from the other surface 4 side of the substrate 2). (DBR layer) and a laminated structure including a metal film.
As shown in FIGS. 2 and 3, the semiconductor light emitting device 1 includes the second semiconductor layer 9 in a region between the second pad electrode 18 and the second semiconductor layer 9 (the flat portion 12 of the mesa structure 10). The high resistance layer 31 having a resistance value higher than the resistance value and the resistance value of the second pad electrode 18 is selectively provided. The high resistance layer 31 has a first current path P ₁ passing through the second pad electrode 18 and the facing portion 32 facing the second pad electrode 18 in the second semiconductor layer 9, and the second pad electrode 18 and the second semiconductor layer 9. Is provided with an allowance portion 33 that is allowed to be formed between. In other words, the permitting portion 33 allows the current to pass through the first current path P ₁ and the opposing portion 32 of the second semiconductor layer 9 and the second pad electrode 18.

In the present embodiment, an example in which the high resistance layer 31 includes an insulating layer 34 disposed on the second semiconductor layer 9 in a region between the second pad electrode 18 and the second semiconductor layer 9 will be described. When including an insulating layer 34, the high-resistance layer 31 _is selected from the group comprising _{ZrO 2, Al 2 O 3,} SiO 2, TiO 2, Ta 2 O 5, Nb 2 O 5, AlN, SiN, the AlON and SiON It may be formed of one or more kinds of insulating films. The thickness of the high resistance layer 31 is, for example, not less than 100 mm and not more than 1000 mm (in this embodiment, about 500 mm).

  The high resistance layer 31 extends in a strip shape along the periphery of the second pad electrode 18 so as to selectively expose the facing portion 32 of the second semiconductor layer 9 in plan view. The allowable portion 33 of the high resistance layer 31 is formed by a portion that selectively exposes the facing portion 32 of the second semiconductor layer 9 in the high resistance layer 31. In the present embodiment, the high resistance layer 31 is formed in an annular shape (annular shape) along the periphery of the second pad electrode 18 so as to surround the central region 35 of the facing portion 32 in plan view. The allowable portion 33 of the high resistance layer 31 is formed by the side wall 36 on the inner peripheral side of the high resistance layer 31 surrounding the central region 35 of the facing portion 32.

Therefore, the allowable portion 33 of the high resistance layer 31 is formed on the central region 35 of the facing portion 32 of the second semiconductor layer 9. The central region 35 of the facing portion 32 is a region located at a predetermined distance from the periphery of the second pad electrode 18 toward the inside in a plan view. The central region 35 of the facing portion 32 is also a region facing the central portion of the second pad electrode 18.
The entire region of the high resistance layer 31 is covered with the second transparent electrode layer 16 described above. Therefore, the second transparent electrode layer 16 is interposed between the high resistance layer 31 and the second pad electrode 18. The high resistance layer 31 is disposed across the periphery of the second pad electrode 18 in plan view, and includes an overlapping portion 37 that overlaps the second pad electrode 18 and an exposed portion 38 that is exposed from the second pad electrode 18. Have. Note that the high resistance layer 31 does not necessarily cross the periphery of the second pad electrode 18 in a plan view, and is entirely disposed in a region surrounded by the periphery of the second pad electrode 18 in a plan view. It may be.

This high resistance layer 31, the region between the second pad electrode 18 and the second semiconductor layer 9, in addition to the first current path P _1, part of the outer facing portion 32 of the second semiconductor layer 9 and the second the second current path P ₂ through a pad electrode 18 is formed. Therefore, the current flowing between the second pad electrode 18 and the second semiconductor layer 9 is dispersed by the high resistance layer 31 inside and outside the facing portion 32 of the second semiconductor layer 9.

FIG. 4 is a longitudinal sectional view showing a semiconductor light emitting device 41 according to a reference example. FIG. 4 is also a longitudinal sectional view of a portion corresponding to FIG. In FIG. 4, the same components as those shown in FIGS. 1 to 3 are designated by the same reference numerals and the description thereof is omitted.
The semiconductor light emitting device 41 according to the reference example is different from the semiconductor light emitting device 1 according to this embodiment in that an insulating current blocking layer 42 is provided instead of the high resistance layer 31. The current blocking layer 42 is provided to prevent light from being generated in the light emitting layer 8 below the second pad electrode 18, and has a larger outer shape than the second pad electrode 18 in plan view. 2 The entire region of the facing portion 32 of the semiconductor layer 9 is covered.

In the semiconductor light-emitting element 41 according to the reference example, when the facing portion 32 of the second semiconductor layer 9 flows current I _B toward the second pad electrode 18, and thus to increase bypass current blocking layer 42. Therefore, a region where current is locally concentrated is formed between the second pad electrode 18 and the second semiconductor layer 9, and the electric field distribution is dense between the second pad electrode 18 and the second semiconductor layer 9. There is a risk that a region where the electric field is concentrated, that is, a region where the electric field is concentrated. Therefore, there is a problem that ESD (Electro Static Discharge) resistance, which is one of the breakdown voltages of the semiconductor light emitting device 1, is reduced due to electrostatic breakdown.

On the other hand, in the semiconductor light emitting device 1 according to the present embodiment, the allowable portion that allows the first current path P ₁ passing through the opposing portion 32 of the second pad electrode 18 and the second semiconductor layer 9 to be formed. A high resistance layer 31 including 33 is disposed. Thereby, the current flowing between the second pad electrode 18 and the second semiconductor layer 9 can be dispersed inside and outside the facing portion 32 of the second semiconductor layer 9 by the high resistance layer 31.

  Therefore, current can flow between the opposing portion 32 of the second semiconductor layer 9 and the second pad electrode 18 without greatly bypassing the high resistance layer 31, so that the second pad electrode 18 and the second semiconductor layer It is possible to suppress the local concentration of current in the region between 9 and 9. As a result, it is possible to suppress the formation of a region in which the electric field distribution is dense between the second pad electrode 18 and the second semiconductor layer 9. Generation and generation of electric field concentration on the second pad electrode 18 can be suppressed. As a result, it is possible to provide the semiconductor light emitting device 1 capable of improving the breakdown voltage.

That is, in the present embodiment, the high resistance layer 31 is not used as the current blocking layer 42 but functions as an electric field relaxation layer for relaxing the electric field strength between the second pad electrode 18 and the second semiconductor layer 9. It can be said that.
The result of investigating the mode of electrostatic breakdown of the semiconductor light emitting device 41 according to the reference example is shown in FIGS. 5 (a), 5 (b) and 5 (c). FIGS. 5A to 5C are microscopic images showing one aspect of electrostatic breakdown of the semiconductor light emitting device 41 according to the reference example of FIG.

In FIGS. 5A to 5C, the locations where electrostatic breakdown has occurred are indicated by broken lines D _a , broken lines D _b and broken lines D _c . 5A to 5C, in the semiconductor light emitting element 41 according to the reference example, electrostatic breakdown occurs along the periphery of the second pad electrode 18, and therefore, along the periphery of the second pad electrode 18. It is understood that electric field concentration occurs. Therefore, it is understood that the withstand voltage can be effectively improved by relaxing the electric field strength at the portion along the periphery of the second pad electrode 18 and suppressing the electric field concentration on the second pad electrode 18.

  Therefore, in the semiconductor light emitting device 1 according to the present embodiment, the high resistance layer 31 is disposed along the periphery of the second pad electrode 18 in a plan view, and the high resistance layer 31 is formed on the central region 35 of the facing portion 32 of the second semiconductor layer 9. An allowable portion 33 of the resistance layer 31 is formed. Thereby, the high resistance layer 31 can function well as an electric field relaxation layer that relaxes the electric field strength between the second pad electrode 18 and the second semiconductor layer 9. Such a high resistance layer 31 can satisfactorily relieve the electric field strength at the periphery of the second pad electrode 18, which is likely to cause electrostatic breakdown due to electric field concentration. it can. As a result, it is possible to provide the semiconductor light emitting device 1 that can improve the breakdown voltage satisfactorily.

  5A to 5C, in the semiconductor light emitting device 41 according to the reference example, among the peripheral edges of the second pad electrode 18, in particular, the second pad electrode 18 in the second pad electrode 18 in plan view. It is understood that electrostatic breakdown occurs on the side of the facing surface 18a facing the 1-pad electrode 17. Therefore, in the present embodiment, the high resistance layer 31 is disposed below the facing surface 18a of the second pad electrode 18 (directly in the present embodiment) so as to extend along at least the facing surface 18a of the second pad electrode 18. . Thereby, the electric field strength on the facing surface 18a side of the second pad electrode 18 that is particularly likely to cause electrostatic breakdown due to electric field concentration can be effectively reduced, so that the occurrence of electric field concentration on the second pad electrode 18 can be effectively suppressed. . As a result, it is possible to provide the semiconductor light emitting device 1 that can effectively improve the breakdown voltage.

  Next, an example of a method for manufacturing the semiconductor light emitting device 1 according to this embodiment will be described with reference to FIGS. 6A to 6F. 6A to 6F are longitudinal sectional views showing one process of the method for manufacturing the semiconductor light emitting device 1 of FIG. In the manufacturing process of the semiconductor light emitting device 1, a plurality of semiconductor light emitting devices 1 are simultaneously manufactured. In FIGS. 6A to 6F, only a region where one semiconductor light emitting device 1 is formed is shown. Yes.

  With reference to FIG. 6A, in manufacturing the semiconductor light emitting device 1, first, a wafer 52 as a base of the substrate 2 is prepared. Wafer 52 is a single crystal sapphire wafer, and has one surface 53 and the other surface 54 corresponding to one surface 3 and other surface 4 of substrate 2. Next, the n-type first semiconductor layer 7, the light emitting layer 8, and the p-type second semiconductor layer 9 are sequentially formed on the one surface 53 side of the wafer 52 by an epitaxial growth method. As a result, the epitaxial layer 6 covering the entire area of the one surface 53 of the wafer 52 is formed on the one surface 53 side of the wafer 52.

Next, referring to FIG. 6B, unnecessary portions of first semiconductor layer 7, light emitting layer 8 and second semiconductor layer 9 are selectively removed by etching through a mask, for example. Thereby, the epitaxial layer 6 including the mesa structure 10 in which a part of the first semiconductor layer 7, the light emitting layer 8 and the second semiconductor layer 9 are selectively cut out, and the outer peripheral region 11 outside thereof is formed.
Next, referring to FIG. 6C, a high resistance material (insulating material in this embodiment) having a resistance value higher than the resistance value of the second semiconductor layer 9 is formed by, for example, a CVD (Chemical Vapor Deposition) method. ) Is deposited to form the high resistance layer 31 (insulating layer 34). Next, the high resistance layer 31 is selectively patterned by etching through a mask, for example. The high resistance layer 31 is formed in a predetermined manner immediately below the second pad electrode 18 formed in a later step. The high resistance layer 31 (insulating layer 34) may be formed in a predetermined pattern by sputtering or lift-off.

More specifically, the high resistance layer 31 is formed along the periphery of the second pad electrode 18 so as to selectively expose the facing portion 32 facing the second pad electrode 18 in the second semiconductor layer 9. . As a result, the high resistance layer 31 including the allowing portion 33 that allows the first current path P ₁ passing through the facing portion 32 of the second semiconductor layer 9 and the second pad electrode 18 to be formed is formed.
Next, referring to FIG. 6D, a transparent conductive material that is the basis of first transparent electrode layer 15 and second transparent electrode layer 16 is deposited by, for example, sputtering, and a transparent conductive material layer is formed on epitaxial layer 6. It is formed. Next, the transparent conductive material layer is selectively patterned by etching through a mask, for example, so that the first transparent electrode layer 15 is formed on the outer peripheral region 11 and the second transparent electrode layer 16 is formed on the mesa structure 10. Is done.

  Next, referring to FIG. 6E, first pad electrode 17 is formed on first transparent electrode layer 15 and second pad electrode 18 is formed on second transparent electrode layer 16 by, for example, a lift-off method. More specifically, a mask having an opening for selectively exposing the first transparent electrode layer 15 and an opening for selectively exposing the second transparent electrode layer 16 is formed on the epitaxial layer 6. Next, a conductive material (Cr and Au in this embodiment) to be the first pad electrode 17 and the second pad electrode 18 is deposited so as to fill the opening by, for example, sputtering. Thereafter, the mask is removed, and the first pad electrode 17 including the first electrode layer 19 and the second electrode layer 20 and the second pad electrode 18 including the first electrode layer 21 and the second electrode layer 22 are simultaneously formed. Is done.

Next, referring to FIG. 6F, silicon oxide (SiO ₂ ) is deposited on the epitaxial layer so as to cover first pad electrode 17 and second pad electrode 18 by, eg, CVD, and passivation film 23 is formed. It is formed. Next, the passivation film 23 is selectively removed by etching through a mask, for example. As a result, a passivation film 23 that covers the inclined portion 14 of the mesa structure 10 is formed. The passivation film 23 may be formed in a predetermined pattern by a sputtering method or a lift-off method. Thereafter, the wafer 52 is selectively cut, and individual pieces of the semiconductor light emitting element 1 are cut out. In this way, the semiconductor light emitting element 1 is manufactured.

Second Embodiment
FIG. 7 is a plan view showing a semiconductor light emitting device 60 according to the second embodiment of the present invention. 8 is a longitudinal sectional view taken along line VIII-VIII in FIG. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 7 to 9, the same reference numerals are given to the same components as those described in the first embodiment, and the description thereof will be omitted.

As shown in FIGS. 7 to 9, in the present embodiment, instead of the annular high resistance layer 61, an arc-shaped high resistance layer 61 extending in a strip shape so as to expose the central region 35 of the facing portion 32 is formed. Has been. The high resistance layer 61 according to the present embodiment is disposed below the facing surface 18a of the second pad electrode 18 (directly below in the present embodiment) along the facing surface 18a of the second pad electrode 18. The allowable portion 33 of the high resistance layer 61 is formed by a side wall 36 located on the central region 35 side in the high resistance layer 61. The high resistance layer 61 forms the first current path P ₁ and the second current path P ₂ described above.

  In the present embodiment, the high resistance layer 61 is disposed so as to cross the periphery of the second pad electrode 18 in plan view, and is exposed from the overlapping portion 37 that overlaps the second pad electrode 18 and the second pad electrode 18. The example which has the exposed part 38 is shown. However, the high resistance layer 61 does not necessarily need to cross the periphery of the second pad electrode 18 in a plan view, and is disposed entirely in a region surrounded by the periphery of the second pad electrode 18 in a plan view. It may be.

  With reference to FIG. 5A to FIG. 5C described above, in the semiconductor light emitting device 41 according to the reference example, electrostatic breakdown occurs on the facing surface 18a side of the second pad electrode 18 in plan view. Therefore, in the present embodiment, a configuration is adopted in which the high resistance layer 61 is disposed only below the facing surface 18a of the second pad electrode 18 (directly below in the present embodiment) where electrostatic breakdown due to electric field concentration is particularly likely to occur. . Even with such a configuration, since the electric field strength on the facing surface 18a side of the second pad electrode 18 can be satisfactorily reduced, the semiconductor light emitting device 60 capable of improving the breakdown voltage can be provided.

<Third Embodiment>
FIG. 10 is a plan view showing a semiconductor light emitting device 62 according to the third embodiment of the present invention. In FIG. 10, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
As shown in FIG. 10, the second pad electrode 18 according to this embodiment includes a main body portion 63 and an extending portion 64 extending from the main body portion 63 around the first pad electrode 17. In the present embodiment, the main body 63 is formed in a columnar shape having a circular shape in plan view. The extending portion 64 is formed with the same thickness as the main body portion 63, and has an arc shape centering on the first pad electrode 17 along the peripheral edge of the first pad electrode 17 from the main body portion 63 in plan view. It extends in a strip shape so as to extend.

  In the present embodiment, the extended portion 64 includes a first extended portion 65 and a second extended portion 66 that are extended in different directions and different lengths. The first extending portion 65 is extended to extend in a first length in one of the arc directions (a clockwise direction from the main body portion 63). The second extending portion 66 is extended so as to extend in the other arc direction (counterclockwise direction from the main body portion 63) with a second length smaller than the first length.

  The high resistance layer 31 according to the present embodiment includes the main body portion 63 and the extension of the second pad electrode 18 so as to selectively expose the facing portion 32 of the second semiconductor layer 9 as indicated by a broken line in FIG. It is formed along each peripheral edge of the installation portion 64. In the present embodiment, the facing portion 32 of the second semiconductor layer 9 is formed by a portion where the second semiconductor layer 9 faces the main body portion 63 and the extending portion 64 of the second pad electrode 18.

  With reference to FIG. 5A to FIG. 5C described above, in the semiconductor light emitting device 41 according to the reference example, electrostatic breakdown occurs on the facing surface 18a side of the second pad electrode 18 in plan view. Accordingly, by adjusting the arrangement, shape, and number of the extending portions 64 of the second pad electrode 18 to change the shape of the facing surface 18a of the second pad electrode 18, the breakdown voltage is controlled by providing the high resistance layer 31. Can be adjusted. Thereby, it is possible to provide the semiconductor light emitting device 60 capable of further improving the breakdown voltage.

  In the present embodiment, the example in which the main body 63 of the second pad electrode 18 is formed in a columnar shape having a circular shape in plan view has been described. However, the main body portion 63 of the second pad electrode 18 may be formed in a columnar shape having a polygonal shape in plan view such as a triangular shape in plan view, a quadrangular shape in plan view, or a hexagonal shape in plan view. It may be formed in a fan-shaped column shape facing the first pad electrode 17 side.

  In the present embodiment, the example in which the second pad electrode 18 includes two extending portions 64 including the first extending portion 65 and the second extending portion 66 has been described. However, the second pad electrode 18 may include one extending portion 64 or may include a plurality (two or more) extending portions 64. Further, in the present embodiment, the example in which the second pad electrode 18 includes the extending portion 64 that extends in an arc shape centering on the first pad electrode 17 has been described. However, the second pad electrode 18 may include an extending portion 64 that extends so as to extend linearly from the main body portion 63 toward the first pad electrode 17.

<Fourth embodiment>
FIG. 11A is a plan view showing a semiconductor light emitting device 71 according to a fourth embodiment of the present invention. FIG. 11B is an enlarged plan view of a region surrounded by an alternate long and short dash line XIB in FIG. 11A. 12 is a longitudinal sectional view taken along line XII-XII in FIG. 11A. In FIG. 11A, FIG. 11B, and FIG. 12, about the structure similar to the structure demonstrated in the above-mentioned 1st Embodiment, the same referential mark is attached | subjected and description is abbreviate | omitted.

  With reference to FIGS. 11A, 11B, and 12, the semiconductor light emitting device 71 according to the present embodiment includes, on the second semiconductor layer 9, in addition to the high resistance layer 31 on the second pad electrode 18 side. A second high resistance layer 72 having a resistance value higher than the resistance value of the second semiconductor layer 9 is further included along the periphery of the two transparent electrode layers 16 and so as to be covered with the second transparent electrode layer 16. The second high resistance layer 72 is formed of the same thickness and the same material as the high resistance layer 31 described above.

  The second high resistance layer 72 is formed in a strip shape along the periphery of the second transparent electrode layer 16. The second transparent electrode layer 16 has a facing surface 16 a that faces the first pad electrode 17 in plan view, and the second high resistance layer 72 is at least along the facing surface 16 a of the second transparent electrode layer 16. In addition, the second transparent electrode layer 16 is disposed below the facing surface 16a (directly below in the present embodiment). In the present embodiment, the second high resistance layer 72 includes a covering portion 73 covered with the second transparent electrode layer 16 and an exposed portion 74 exposed from the second transparent electrode layer 16. The entire area of the second high resistance layer 72 may be covered with the second transparent electrode layer 16.

FIG. 13 is a microscopic image showing one aspect of electrostatic breakdown of the semiconductor light emitting device 41 according to the reference example shown in FIG. In Figure 13, portions of the electrostatic breakdown occurs is indicated by the dashed line D ₁ and the broken line D _2.
Referring to FIG. 13, in the semiconductor light emitting device 41 according to the reference example, in addition to the electrostatic breakdown occurring along the facing surface 18 a of the second pad electrode 18, the facing surface of the second transparent electrode layer 16. It is understood that electrostatic breakdown occurs along 16a. Therefore, in addition to the portion along the peripheral edge (opposing surface 18a) of the second pad electrode 18, the electric field strength of the portion along the peripheral edge (opposing surface 16a) of the second transparent electrode layer 16 is reduced, and the second pad electrode 18 and It is understood that the withstand voltage can be effectively improved by suppressing the electric field concentration on the second transparent electrode layer 16.

  Therefore, in the semiconductor light emitting device 71 according to the present embodiment, the second high resistance is formed on the second semiconductor layer 9 along the periphery of the second transparent electrode layer 16 and so as to be covered with the second transparent electrode layer 16. Layer 72 is disposed. Thereby, since the current density in the periphery of the 2nd transparent electrode layer 16 can be reduced, the electric field strength in the periphery of the 2nd transparent electrode layer 16 can be reduced.

  That is, the second high resistance layer 72 is also an electric field relaxation layer for relaxing the electric field strength in a portion along the periphery (opposing surface 16a) of the second transparent electrode layer 16. Thereby, the electric field concentration in the portion along the peripheral edge (opposing surface 18a) of the second pad electrode 18 can be suppressed, and the electric field concentration in the portion along the peripheral edge (opposing surface 16a) of the second transparent electrode layer 16 can also be suppressed. As a result, it is possible to provide the semiconductor light emitting device 71 capable of effectively improving the breakdown voltage.

  The effect of suppressing the electric field concentration on the second transparent electrode layer 16 can be achieved only by the second high resistance layer 72. Therefore, it is preferable to adopt a configuration in which the high resistance layer 31 is disposed on the second pad electrode 18 side. However, focusing on suppression of electric field concentration on the second transparent electrode layer 16, only the second high resistance layer 72 is used. May be employed on the second semiconductor layer 9. In the present embodiment, the example in which the high resistance layer 31 according to the first embodiment is employed has been described, but the high resistance layer 61 according to the second embodiment may be employed. Further, a configuration in which the second high resistance layer 72 and the high resistance layer 31 are integrally formed or a configuration in which the second high resistance layer 72 and the high resistance layer 61 are integrally formed may be employed. .

<Fifth Embodiment>
FIG. 14 is a longitudinal sectional view showing a semiconductor light emitting device 81 according to the fifth embodiment of the present invention. In FIG. 14, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
The semiconductor light emitting element 81 according to this embodiment is an element in which the other surface 4 of the substrate 2 is a light extraction surface. The semiconductor light emitting element 81 includes an insulating light reflecting film 82 formed on the epitaxial layer 6 so as to cover the first transparent electrode layer 15 and the second transparent electrode layer 16. The light reflecting film 82 may be an insulating layer having a stacked structure in which a plurality of insulating films having different refractive indexes are stacked. The light reflecting film 82 may be a DBR layer having a laminated structure in which insulating films having different refractive indexes are alternately laminated with an optical length of ¼ wavelength. The DBR layer is formed of two or more insulating films selected from the group including ZrO ₂ , Al ₂ O ₃ , SiO ₂ , TiO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , AlN, SiN, AlON and SiON. May be.

  In the light reflecting film 82, the first pad opening 84 that selectively exposes the upper surface of the first transparent electrode layer 15 as the first pad region 83 and the upper surface of the second transparent electrode layer 16 are selected as the second pad region 85. A second pad opening 86 is formed to be exposed. On the light reflecting film 82, a first pad electrode 87 electrically connected to the first semiconductor layer 7 through the first transparent electrode layer 15 and a second semiconductor layer through the second transparent electrode layer 16 are provided. A second pad electrode 88 that is electrically connected to 9 is disposed. Each of the first pad electrode 87 and the second pad electrode 88 also serves as a reflective film that reflects the light generated in the epitaxial layer 6 (light emitting layer 8) toward the other surface 4 side of the substrate 2.

  The first pad electrode 87 enters the first pad opening 84 from above the light reflecting film 82, and is electrically connected to the first transparent electrode layer 15 in the first pad opening 84. The first pad electrode 87 may have a laminated structure in which a plurality of metal films are laminated, or may have a single layer structure made of one metal film. In the present embodiment, the first pad electrode 87 has a two-layer structure including a first electrode layer 89 and a second electrode layer 90 that are stacked in this order from the first transparent electrode layer 15 side.

The first electrode layer 89 includes, for example, aluminum (Al), silver (Ag), or gold (Au). The first electrode layer 89 enters the first pad opening 84 from above the light reflection film 82 and is first transparent in the first pad opening 84. It is electrically connected to the electrode layer 15. The second electrode layer 90 includes, for example, gold (Au) and is bonded to the upper surface of the first electrode layer 89.
On the other hand, the second pad electrode 88 enters the second pad opening 86 from above the light reflecting film 82 and is electrically connected to the second transparent electrode layer 16 in the second pad opening 86. The second pad electrode 88 may have a laminated structure in which a plurality of metal films are laminated, or may have a single layer structure made of one metal film. In the present embodiment, the second pad electrode 88 has a two-layer structure including a first electrode layer 91 and a second electrode layer 92 that are stacked in this order from the second transparent electrode layer 16 side.

  The first electrode layer 91 enters the second pad opening 86 from above the light reflecting film 82, and is electrically connected to the second transparent electrode layer 16 in the second pad opening 86. The second electrode layer 92 is bonded to the upper surface of the first electrode layer 91. The first electrode layer 91 and the second electrode layer 92 of the second pad electrode 88 are both formed of the same material and the same thickness as the first electrode layer 89 and the second electrode layer 90 of the first pad electrode 87. .

  The high resistance layer 31 described above is disposed in a region between the second pad electrode 88 and the second semiconductor layer 9 in the same manner as in the first embodiment. Even with such a configuration, the same effects as described in the first embodiment can be obtained. Instead of the high resistance layer 31, the high resistance layer 61 according to the second embodiment described above may be employed. Further, the second high resistance layer 72 according to the third embodiment may be formed along the periphery (opposing surface 16a) of the second transparent electrode layer 16. In this case, the high resistance layer 31 and the second high resistance layer 72 may be integrally formed. Further, the second pad electrode 88 according to the present embodiment may have a main body portion 63 and an extending portion 64 as in the second pad electrode 18 according to the third embodiment described above.

<Sixth Embodiment>
FIG. 15 is a longitudinal sectional view showing a semiconductor light emitting device 101 according to the sixth embodiment of the present invention. In FIG. 15, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
The semiconductor light emitting element 101 according to this embodiment is an element in which the other surface 4 of the substrate 2 is a light extraction surface. The semiconductor light emitting element 101 includes a first mirror metal 102 that covers the first transparent electrode layer 15 and a second mirror metal 103 that covers the second transparent electrode layer 16. The first mirror metal 102 and the second mirror metal 103 are conductive reflection films that reflect the light generated in the epitaxial layer 6 (the light emitting layer 8) toward the other surface 4 side of the substrate 2.

  The first mirror metal 102 includes, for example, aluminum (Al), silver (Ag), or gold (Au), and covers the entire area of the first transparent electrode layer 15 in a planar shape that matches the planar shape of the first transparent electrode layer 15. It is covered. The second mirror metal 103 is formed of the same material and the same thickness as the first mirror metal 102, and has a planar shape that matches the planar shape of the second transparent electrode layer 16, and covers the entire area of the second transparent electrode layer 16. It is covered.

The semiconductor light emitting device 101 further includes an insulating light reflecting film 104 formed on the epitaxial layer 6 so as to cover the first mirror metal 102 and the second mirror metal 103. The light reflecting film 104 may be an insulating layer having a stacked structure in which a plurality of insulating films having different refractive indexes are stacked. The light reflecting film 104 may be a DBR layer having a stacked structure in which insulating films having different refractive indexes are alternately stacked with an optical length of ¼ wavelength. The DBR layer is formed of two or more insulating films selected from the group including ZrO ₂ , Al ₂ O ₃ , SiO ₂ , TiO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , AlN, SiN, AlON and SiON. May be.

  In the light reflecting film 104, the first pad opening 106 that selectively exposes the upper surface of the first mirror metal 102 as the first pad region 105 and the upper surface of the second mirror metal 103 are selectively used as the second pad region 107. A second pad opening 108 to be exposed is formed. On the light reflecting film 104, a first pad electrode 109 electrically connected to the first semiconductor layer 7 via the first mirror metal 102 and the first transparent electrode layer 15, the second mirror metal 103 and the first mirror electrode A second pad electrode 110 that is electrically connected to the second semiconductor layer 9 through the two transparent electrode layers 16 is disposed. Each of the first pad electrode 109 and the second pad electrode 110 also serves as a reflective film that reflects the light generated in the epitaxial layer 6 (light emitting layer 8) toward the other surface 4 side of the substrate 2.

  The first pad electrode 109 enters the first pad opening 106 from above the light reflecting film 104, and is electrically connected to the first mirror metal 102 in the first pad opening 106. The first pad electrode 109 may have a laminated structure in which a plurality of metal films are laminated, or may have a single layer structure made of one metal film. In the present embodiment, the first pad electrode 109 has a two-layer structure including a first electrode layer 111 and a second electrode layer 112 stacked in this order from the first mirror metal 102 side.

The first electrode layer 111 includes, for example, aluminum (Al), silver (Ag), or gold (Au). The first electrode layer 111 enters the first pad opening 106 from above the light reflecting film 104, and the first mirror is formed in the first pad opening 106. It is electrically connected to the metal 102. The second electrode layer 112 includes, for example, gold (Au) and is bonded to the upper surface of the first electrode layer 111.
On the other hand, the second pad electrode 110 enters the second pad opening 108 from above the light reflecting film 104 and is electrically connected to the second mirror metal 103 in the second pad opening 108. The second pad electrode 110 may have a laminated structure in which a plurality of metal films are laminated, or may have a single layer structure made of one metal film. In the present embodiment, the second pad electrode 110 has a two-layer structure including a first electrode layer 113 and a second electrode layer 114 stacked in this order from the second mirror metal 103 side.

  The first electrode layer 113 enters the second pad opening 108 from above the light reflecting film 104 and is electrically connected to the second mirror metal 103 in the second pad opening 108. The second electrode layer 114 is bonded to the upper surface of the first electrode layer 113. The first electrode layer 113 and the second electrode layer 114 of the second pad electrode 110 are both formed with the same material and the same thickness as the first electrode layer 111 and the second electrode layer 112 of the first pad electrode 109. .

  The above-described high resistance layer 31 is arranged in a region between the second pad electrode 110 and the second semiconductor layer 9 in the same manner as in the first embodiment. Even with such a configuration, the same effects as described in the first embodiment can be obtained. Instead of the high resistance layer 31, the high resistance layer 61 according to the second embodiment described above may be employed. Further, the second high resistance layer 72 according to the third embodiment may be formed along the periphery (opposing surface 16a) of the second transparent electrode layer 16. In this case, the high resistance layer 31 and the second high resistance layer 72 may be integrally formed. In addition, the second pad electrode 110 according to the present embodiment may have a main body portion 63 and an extending portion 64, similarly to the second pad electrode 18 according to the third embodiment described above.

<Seventh embodiment>
FIG. 16 is a longitudinal sectional view showing a semiconductor light emitting device 121 according to the seventh embodiment of the present invention. In FIG. 16, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
Referring to FIG. 16, the one surface 3 of the substrate 2 according to the present embodiment has an unevenness 122 formed over the entire region, thereby making the substrate 2 a PSS (Patterned Sapphire Substrate). The unevenness 122 includes a plurality of convex portions 123 regularly arranged. The plurality of convex portions 123 may be arranged in a matrix or in a staggered manner. Of course, the plurality of convex portions 123 may be arranged discretely without regularity. According to the substrate 2 made of PSS, the light generated in the epitaxial layer 6 (light emitting layer 8) can be reflected to the epitaxial layer 6 side by the unevenness 122 in addition to the light reflecting layer 24. It becomes possible to improve.

The substrate 2 having such a PSS is formed on one surface 53 of the wafer 52 by, for example, etching through a mask prior to the epitaxial layer 6 formation step after the wafer 52 preparation step described with reference to FIG. 6A. It can be formed by selectively removing the portion.
Even with such a configuration, the same effects as described in the first embodiment can be obtained. Further, according to the semiconductor light emitting device 121 according to the present embodiment, the entire area of the other surface 4 of the substrate 2 is covered with the light reflecting layer 24, and the unevenness 122 is formed on the one surface 3 of the substrate 2. , The luminance can be effectively improved.

In this embodiment, the example in which the unevenness 122 is formed on the one surface 3 of the substrate 2 using the substrate 2 has been described. However, the unevenness 122 may be formed of a material different from that of the substrate 2. . For example, the unevenness 122 may be formed by forming an insulating film on the one surface 3 of the substrate 2 and then selectively patterning the insulating film in an uneven shape. The concave portion included in the irregularities 122 may be formed so as to expose the one surface 3 of the substrate 2. The insulating film forming the unevenness 122 is, for example, one selected from the group including ZrO ₂ , Al ₂ O ₃ , SiO ₂ , TiO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , AlN, SiN, AlON and SiON. The above insulating material species may be included.

The configuration in which the unevenness 122 (convex portion 123) is formed on the one surface 3 of the substrate 2 is not limited to the configuration of the first embodiment, and can also be applied to the above-described second to sixth embodiments.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the first embodiment described above, the example in which the high resistance layer 31 (insulating layer 34) having a predetermined thickness is formed on the second semiconductor layer 9 has been described. However, the form shown in FIG. 17 may be adopted. FIG. 17 is a cross-sectional view showing a first modification of the semiconductor light emitting device 1 of FIG. FIG. 17 is an enlarged view of a portion corresponding to the enlarged sectional view shown in FIG. In FIG. 17, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 17, the semiconductor light emitting device 1 according to the first modification includes a high resistance layer 31 including a buried insulating layer 131 embedded in the surface portion of the second semiconductor layer 9. More specifically, the buried insulating layer 131 (high resistance layer 31) has a configuration in which an insulator 133 is buried in a groove 132 formed by selectively dug the surface portion of the second semiconductor layer 9. ing. The surface of the buried insulating layer 131 is connected to the surface of the second semiconductor layer 9 without a step. The allowable portion 33 of the high resistance layer 31 is formed by the inner wall portion 134 of the groove 132 on the central region 35 side.

  The high resistance layer 31 including the buried insulating layer 131 can be formed by executing the following process after the process of forming the mesa structure 10 (see FIG. 6B). First, the surface 132 of the second semiconductor layer 9 is selectively dug down by, for example, etching through a mask to form the trench 132. Next, an insulating material is deposited so as to fill the groove 132 by, for example, a CVD method to form an insulating layer. Next, the insulating layer is etched back so that a part of the insulating layer remains in the trench 132. As a result, the high resistance layer 31 including the buried insulating layer 131 is formed.

  Thus, even when the high resistance layer 31 including the buried insulating layer 131 is formed, the same effects as those described in the first embodiment can be obtained. In addition, since the high resistance layer 31 including the buried insulating layer 131 can improve the flatness of the second transparent electrode layer 16 covering the buried insulating layer 131, the second pad electrode 18 and the second semiconductor can be improved. Generation of undesired electric field concentration between the layers 9 can be suppressed. Of course, the high resistance layers 31 and 61 according to the second to seventh embodiments described above may include the buried insulating layer 131. Further, the second high resistance layer 72 according to the fourth embodiment may include the embedded insulating layer 131.

  Further, instead of the high-resistance layer 31 (insulating layer 34) according to the first embodiment described above, the form shown in FIG. 13 may be adopted. FIG. 18 is a plan view showing a second modification of the semiconductor light emitting device 1 of FIG. FIG. 18 is also an enlarged view of a portion corresponding to the enlarged cross-sectional view shown in FIG. 2 described above. In FIG. 18, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 18, the semiconductor light emitting device 1 according to the second modification includes a high resistance layer 31 including a defect layer 135 formed on the surface portion of the second semiconductor layer 9. The defect layer 135 is a layer in which the surface portion of the second semiconductor layer 9 is increased in resistance by irradiating the surface portion of the second semiconductor layer 9 with plasma of an impurity gas (in this case, argon gas). . Therefore, the high resistance layer 31 including the defect layer 135 is selectively doped with an impurity gas (in this case, argon gas) to the surface portion of the second semiconductor layer 9 after the step of forming the mesa structure 10 (see FIG. 6B). It can be formed by plasma irradiation. The allowable portion 33 of the high resistance layer 31 is formed by the side portion 136 of the defect layer 135 on the central region 35 side.

  Thus, even when the high resistance layer 31 including the defect layer 135 is formed, the same effects as those described in the first embodiment can be obtained. Further, since the high resistance layer 31 including the defect layer 135 can improve the flatness of the second transparent electrode layer 16 covering the defect layer 135, the second pad electrode 18 and the second semiconductor layer 9. The occurrence of undesired electric field concentration between the two can be suppressed. Of course, the high resistance layers 31 and 61 according to the second to seventh embodiments may include the defect layer 135. The second high resistance layer 72 according to the fourth embodiment may include the defect layer 135.

  Further, in the first embodiment described above, the example in which the first pad electrode 17 and the second pad electrode 18 are arranged at a distance from each other along one diagonal line of the substrate 2 in plan view has been described. However, instead of this, the form shown in FIG. 19 may be adopted. FIG. 19 is a plan view showing a third modification of the semiconductor light emitting device 1 of FIG. In FIG. 19, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 19, the semiconductor light emitting device 1 according to the third modified example surrounds the outer peripheral region 11 formed in the region on the central portion in the longitudinal direction of one side surface 5 of the substrate 2 and the outer peripheral region 11. The epitaxial layer 6 including the mesa structure 10 having a concave shape in plan view is formed. The first pad electrode 17 and the second pad electrode 18 are spaced apart from each other along the direction in which one side of the substrate 2 extends in plan view.

  In this modification, an example in which the first pad electrode 17 is a columnar shape having a semicircular shape in plan view is shown. However, the first pad electrode 17 may be formed in a columnar shape having a circular shape in plan view, or may be formed in a columnar shape having a polygonal shape in plan view such as a triangular shape in plan view, a quadrangular shape in plan view, or a hexagonal shape in plan view. May be. Further, in this modification, an example in which the second pad electrode 18 is a columnar shape having a circular shape in plan view is shown. However, the second pad electrode 18 may be formed in a columnar shape having a polygonal shape in a plan view, such as a triangular shape in plan view, a quadrangular shape in plan view, or a hexagonal shape in plan view. You may form in the fan-shaped column shape facing 17 side.

Even with such a configuration, the same effects as those described in the first embodiment can be obtained. The configuration in which the first pad electrode 17 and the second pad electrode 18 are arranged at a distance from each other along the direction in which one side of the substrate 2 extends in a plan view is the same as in the second to seventh embodiments described above. Is also applicable.
In each of the above-described embodiments, a configuration in which the conductivity type of each semiconductor portion is reversed may be employed. That is, the p-type portion may be n-type and the n-type portion may be p-type. Therefore, the epitaxial layer 6 including the p-type first semiconductor layer 7, the light emitting layer 8 and the n-type second semiconductor layer 9 stacked in this order may be formed on the one surface 3 of the substrate 2.

In addition, various design changes can be made within the scope of matters described in the claims. Features extracted from this specification and drawings are shown below.
A1: a substrate, a semiconductor layer including a first conductive type first semiconductor layer, a light emitting layer, and a second conductive type second semiconductor layer stacked in this order from the substrate side on the substrate, and the second semiconductor A transparent electrode layer disposed on the layer, and on the second semiconductor layer, along the periphery of the transparent electrode layer and so as to be covered with the transparent electrode layer. A semiconductor light emitting device in which a high resistance layer having a resistance value higher than the resistance value is disposed.

  There is a tendency that the electric field tends to concentrate on the periphery of the transparent electrode layer disposed on the second semiconductor layer. Therefore, there is a problem that electrostatic breakdown is likely to occur at the periphery of the transparent electrode layer, and the breakdown voltage of the semiconductor light emitting element is reduced. Therefore, in the semiconductor light emitting device according to A1, a resistance value higher than the resistance value of the second semiconductor layer is formed on the second semiconductor layer along the periphery of the transparent electrode layer and so as to be covered with the transparent electrode layer. The high resistance layer having

  Thereby, since the current density in the periphery of a transparent electrode layer can be reduced, the electric field strength in the periphery of a transparent electrode layer can be reduced (relaxed). That is, this high resistance layer is also an electric field relaxation layer for relaxing the electric field strength at the periphery of the transparent electrode layer. Thereby, since electric field concentration can be suppressed from occurring at the periphery of the transparent electrode layer, it is possible to provide a semiconductor light emitting device capable of improving the breakdown voltage.

  A2: further including a first pad electrode disposed on the first semiconductor layer and a second pad electrode disposed on the transparent electrode layer, wherein the transparent electrode layer is the first pad electrode in a plan view. The high resistance layer is formed below the facing surface of the transparent electrode layer so as to be along at least the facing surface of the transparent electrode layer. Semiconductor light emitting device.

A3: The semiconductor light emitting element according to A1 or A2, wherein the high resistance layer is formed in a band shape along a periphery of the transparent electrode layer in a plan view.
A4: The semiconductor light emitting element according to any one of A1 to A3, wherein the high resistance layer includes a covering portion covered with the transparent electrode layer in a plan view and an exposed portion exposed from the transparent electrode layer. .

A5: The semiconductor light emitting element according to any one of A1 to A4, wherein the high resistance layer is entirely covered with the transparent electrode layer.
A6: In a region between the first pad electrode disposed on the first semiconductor layer, the second pad electrode disposed on the transparent electrode layer, and the second pad electrode and the second semiconductor layer. A pad-side high-resistance layer that is selectively provided and has a resistance value higher than a resistance value of the second semiconductor layer, and the pad-side high-resistance layer is formed on the second pad electrode in the second semiconductor layer; A1 having an allowance portion that allows a current path passing through the opposite facing portion and the second pad electrode to be formed between the second pad electrode and the facing portion of the second semiconductor layer. The semiconductor light-emitting device described in 1.

A7: The semiconductor light emitting element according to A6, wherein the pad-side high resistance layer is formed of the same resistance material as the high resistance layer.
B1: a substrate, a semiconductor layer including a first conductivity type first semiconductor layer, a light emitting layer, and a second conductivity type second semiconductor layer stacked in this order on the substrate from the substrate side; and the first semiconductor A first pad electrode disposed on the layer; a second pad electrode disposed on the second semiconductor layer; and a region between the second pad electrode and the second semiconductor layer. And an electric field relaxation layer that relaxes an electric field strength between the second pad electrode and the second semiconductor layer, and the electric field relaxation layer is a facing portion facing the second pad electrode in the second semiconductor layer. And a light-emitting element including a permissible portion that allows a current path passing through the second pad electrode to be formed between the second pad electrode and the facing portion of the second semiconductor layer.

  According to the semiconductor light emitting device described in B1, the current flowing between the second pad electrode and the second semiconductor layer can be dispersed inside and outside the opposing portion of the second semiconductor layer by the electric field relaxation layer. Therefore, a current can flow between the opposing portion of the second semiconductor layer and the second pad electrode without greatly bypassing the electric field relaxation layer, so that a current flows between the second pad electrode and the second semiconductor layer. It is possible to suppress the formation of a region where the local concentration is locally concentrated. As a result, it is possible to suppress the formation of a region where the electric field distribution is dense between the second pad electrode and the second semiconductor layer. The occurrence of electric field concentration on the two-pad electrode can be suppressed. As a result, it is possible to provide a semiconductor light emitting device capable of improving the breakdown voltage.

B2: The semiconductor light emitting element according to B1, wherein the allowable portion of the electric field relaxation layer is formed in a central region of the facing portion of the second semiconductor layer.
B3: The semiconductor light emitting element according to B1 or B2, wherein the allowable portion of the electric field relaxation layer is formed by a portion that selectively exposes the facing portion of the second semiconductor layer in the electric field relaxation layer.

B4: Any one of B1 to B3, wherein the electric field relaxation layer is disposed along a peripheral edge of the second pad electrode so as to selectively expose the facing portion of the second semiconductor layer in a plan view. The semiconductor light emitting element as described in one.
B5: The second pad electrode has a facing surface facing the first pad electrode in plan view, and the electric field relaxation layer selectively selects the facing portion of the second semiconductor layer in plan view. The semiconductor light emitting element according to any one of B1 to B4, which is exposed and disposed below the facing surface of the second pad electrode so as to extend along at least the facing surface of the second pad electrode.

B6: The semiconductor light emitting element according to any one of B1 to B5, wherein the electric field relaxation layer is formed in an annular shape along a periphery of the second pad electrode in a plan view.
B7: The electric field relaxation layer is disposed so as to cross the periphery of the second pad electrode in plan view, and an overlapping portion that overlaps the second semiconductor layer, and an exposed portion that is exposed from the second semiconductor layer, The semiconductor light-emitting device according to any one of B1 to B6, having:

B8: The semiconductor light emitting element according to any one of B1 to B7, wherein the electric field relaxation layer includes an insulating layer disposed between the second pad electrode and the second semiconductor layer.
B9: The semiconductor light emitting element according to any one of B1 to B7, wherein the electric field relaxation layer includes a buried insulating layer buried in a surface portion of the second semiconductor layer.
B10: The semiconductor light emitting element according to any one of B1 to B7, wherein the electric field relaxation layer includes a defect layer formed on a surface portion of the second semiconductor layer.

B11: Any one of B1 to B10 further including a transparent electrode layer disposed between the second pad electrode and the second semiconductor layer, wherein the electric field relaxation layer is covered with the transparent electrode layer. The semiconductor light-emitting device described in 1.
B12: The semiconductor layer is a mesa structure formed by selectively cutting out a part of the first semiconductor layer, the light emitting layer, and the second semiconductor layer so as to expose the first semiconductor layer; And an outer peripheral region that is an outer region of the mesa structure and from which the first semiconductor layer is exposed, the first pad electrode is disposed on the outer peripheral region, and the second pad electrode is The semiconductor according to any one of B1 to B11, which is disposed on a mesa structure, and wherein the electric field relaxation layer is selectively provided in a region between the second pad electrode and the mesa structure. Light emitting element.

B13: Any one of B1 to B12, wherein the first pad electrode also serves as a first external terminal for external connection, and the second pad electrode also serves as a second external terminal for external connection. The semiconductor light-emitting device described in 1.
B14: The substrate is formed in a rectangular shape in plan view, and the first pad electrode and the second pad electrode are spaced apart from each other along one diagonal line of the substrate in plan view. , B1 to B13.

B15: The substrate is formed in a rectangular shape in plan view, and the first pad electrode and the second pad electrode are spaced from each other along a direction in which one side of the substrate extends in plan view. The semiconductor light-emitting device according to any one of B1 to B14.
B16: The second pad electrode includes a main body portion and an extending portion extending from the main body portion to the periphery of the first pad electrode, and the electric field relaxation layer is opposite to the second semiconductor layer. The semiconductor light emitting element according to any one of B1 to B15, which is formed along each peripheral edge of the main body portion and the extension portion of the second pad electrode so as to selectively expose the portion.

  B17: The semiconductor light emitting element according to B16, wherein the second pad electrode includes a plurality of the extending portions.

DESCRIPTION OF SYMBOLS 1,60,62,71,81,101,121 ... Semiconductor light emitting element, 2 ... Substrate, 6 ... Epitaxial layer (semiconductor layer), 7 ... 1st semiconductor layer, 8 ... Light emitting layer, 9 ... 2nd semiconductor layer, DESCRIPTION OF SYMBOLS 10 ... Mesa structure, 11 ... Outer peripheral area, 16 ... 2nd transparent electrode layer (transparent electrode), 17 ... 1st pad electrode, 18 ... 2nd pad electrode, 18a ... Opposite surface of 2nd pad electrode, 31, 61 ... High resistance layer, 32 ... opposing part of the second semiconductor layer, 33 ... allowable part of the high resistance layer, 34 ... insulating layer (high resistance layer), 35 ... central region of the opposing part, 37 ... overlapping part of the high resistance layer, 38 ... exposed portion of high resistance layer, 63 ... main body portion of second pad electrode, 64 ... extended portion of second pad electrode, 131 ... embedded insulating layer (high resistance layer), 134 ... defect layer (high resistance layer) , P ₁ ... First current path (current path)

Claims (17)

A substrate,
A semiconductor layer including a first conductive type first semiconductor layer, a light emitting layer, and a second conductive type second semiconductor layer stacked in this order from the substrate side on the substrate;
A first pad electrode disposed on the first semiconductor layer;
A second pad electrode disposed on the second semiconductor layer;
A high resistance layer selectively provided in a region between the second pad electrode and the second semiconductor layer and having a resistance value higher than a resistance value of the second semiconductor layer;
The high resistance layer includes a facing portion facing the second pad electrode in the second semiconductor layer and a current path passing through the second pad electrode, wherein the second pad electrode and the facing portion of the second semiconductor layer A semiconductor light emitting device comprising an allowance portion that allows formation between the two.   2. The semiconductor light emitting element according to claim 1, wherein the allowance portion of the high resistance layer is formed on a central region of the facing portion of the second semiconductor layer.   3. The semiconductor light emitting element according to claim 1, wherein the allowable portion of the high resistance layer is formed by a portion of the high resistance layer that selectively exposes the facing portion of the second semiconductor layer.   The high resistance layer is disposed along a peripheral edge of the second pad electrode so as to selectively expose the facing portion of the second semiconductor layer in a plan view. The semiconductor light emitting device according to one item. The second pad electrode has a facing surface facing the first pad electrode in plan view,
The high resistance layer selectively exposes the facing portion of the second semiconductor layer in plan view, and at least the facing surface of the second pad electrode along the facing surface of the second pad electrode. The semiconductor light-emitting device according to claim 1, which is disposed below the semiconductor device.   The semiconductor light emitting element according to claim 1, wherein the high resistance layer is formed in an annular shape along a periphery of the second pad electrode in a plan view.   The high resistance layer is disposed so as to cross the periphery of the second pad electrode in plan view, and has an overlapping portion overlapping the second pad electrode and an exposed portion exposed from the second pad electrode. The semiconductor light-emitting device according to claim 1.   The semiconductor light emitting element according to claim 1, wherein the high resistance layer includes an insulating layer disposed between the second pad electrode and the second semiconductor layer.   The semiconductor light emitting element according to claim 1, wherein the high resistance layer includes a buried insulating layer embedded in a surface portion of the second semiconductor layer.   The semiconductor light emitting element according to claim 1, wherein the high resistance layer includes a defect layer formed on a surface portion of the second semiconductor layer. A transparent electrode layer disposed between the second pad electrode and the second semiconductor layer;
The semiconductor light emitting element according to claim 1, wherein the high resistance layer is covered with the transparent electrode layer. The semiconductor layer includes a mesa structure formed by selectively notching a part of the first semiconductor layer, the light emitting layer, and the second semiconductor layer so as to expose the first semiconductor layer, and the mesa structure. And an outer peripheral region where the first semiconductor layer is exposed.
The first pad electrode is disposed on the outer peripheral region,
The second pad electrode is disposed on the mesa structure;
The semiconductor light emitting element according to claim 1, wherein the high resistance layer is selectively provided in a region between the second pad electrode and the mesa structure. The first pad electrode also serves as a first external terminal for external connection,
The semiconductor light-emitting element according to claim 1, wherein the second pad electrode also serves as a second external terminal for external connection. The substrate is formed in a rectangular shape in plan view,
14. The semiconductor light emitting device according to claim 1, wherein the first pad electrode and the second pad electrode are spaced apart from each other along one diagonal line of the substrate in a plan view. element. The substrate is formed in a rectangular shape in plan view,
The said 1st pad electrode and the said 2nd pad electrode are arrange | positioned mutually spaced apart along the direction where one side of the said board | substrate is extended in planar view. Semiconductor light emitting device. The second pad electrode includes a main body portion and an extending portion extending from the main body portion around the first pad electrode,
The high resistance layer is formed along each peripheral edge of the main body portion and the extension portion of the second pad electrode so as to selectively expose the facing portion of the second semiconductor layer. Item 16. The semiconductor light emitting device according to any one of Items 1 to 15.   The semiconductor light emitting device according to claim 16, wherein the second pad electrode includes a plurality of the extending portions.