JP2017129951A - Information processor, control method of information processor, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically select the most appropriate FPGA reconstruction data from a plurality of types of FPGA reconstruction data capable of realizing the same processing function according to the amount of available resources of the FPGA. SOLUTION: In an information processing apparatus that writes predetermined reconstruction data in a partial reconstruction area divided into a predetermined number and executes a specific functional process, a new specification specified by a usage state of the managed partial reconstruction area. It is characterized in that one reconstruction data to be written is selected from a plurality of types of reconstruction data having the same specific functional processing according to the number of partially reconstructed areas writable in. [Selection diagram] Fig. 5

Description

  The present invention relates to an information processing apparatus, a control method for the information processing apparatus, and a program.

  In recent years, in a semiconductor integrated circuit device, a reconfigurable circuit device such as an FPGA (Field Programmable Gate Array) has been applied in order to flexibly cope with the demand for frequently expanding functions and improving performance.

  A user configures (writes) FPGA reconfiguration data capable of realizing a desired processing function in the FPGA, thereby realizing desired data processing. Further, it is possible to freely change the function of the FPGA by reconfiguration (rewriting of FPGA reconfiguration data) with another FPGA reconfiguration data.

  Then, a plurality of FPGA reconfiguration data can be configured in one FPGA, and a plurality of processing functions can be realized. At that time, only a partial area of the FPGA is changed, It is possible to change any of them.

  The partial reconfiguration technology is known in that it changes only a desired part without affecting other processing functions that are currently in use or processing functions that should not be changed. Yes.

  Therefore, when newly writing the FPGA reconfiguration data into the FPGA, it is necessary to identify an area where the FPGA can be changed, select configurable FPGA reconfiguration data in the changeable area, and configure the FPGA.

  On the other hand, there may be multiple versions of FPGA reconfiguration data that can realize the same processing function. Generally, these FPGA reconfiguration data are designed in accordance with different required specifications, and have different attributes such as circuit scale, power consumption, and performance, and should be selected according to the actual situation.

  For example, in Patent Document 1, there are a plurality of FPGA reconfiguration data capable of realizing the same processing function, the performance and power consumption are different from each other, and the power consumption of the entire FPGA falls within a predetermined total power consumption value. A method is described in which appropriate FPGA reconstruction data is automatically selected.

JP 2009-271649 A

It can be easily imagined that the following situation occurs when actually using the FPGA.
For example, a part of the area (resource) is occupied by a certain processing function (processing function A), the remaining resource amount is insufficient, and FPGA reconfiguration data that realizes another processing function (processing function B) cannot be written There is sex.
At that time, in the conventional method, there are two methods of giving up the configuration of the processing function B or waiting for the processing function A to stop operating and the resources occupied by it to be released.
However, if the processing function A always occupies FPGA resources, the configuration of the processing function B will continue to wait and eventually the configuration will fail.

  In that case, if the desired processing function B can be realized, the circuit scale is small, and there is another FPGA reconfiguration data that can be configured in the remaining FPGA resources, that FPGA reconfiguration data should be selected. There is no way to detect and automatically select FPGA reconstruction data.

  Patent Document 1 describes a method for selecting an appropriate data from among FPGA reconfiguration data that realizes the same function, but it is only a method for selecting an appropriate data from the viewpoint of the total power consumption value. is there. As described above, there is a problem in that the limitation of the FPGA resource amount is not taken into consideration, and appropriate FPGA reconfiguration data cannot be automatically selected from the viewpoint of whether or not the available resources are sufficient.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to match the amount of resources available to the FPGA from among a plurality of types of FPGA reconfiguration data capable of realizing the same processing function. It is to provide a mechanism that can automatically select the most appropriate FPGA reconstruction data.

The information processing apparatus of the present invention that achieves the above object has the following configuration.
An information processing apparatus that executes predetermined function processing by writing predetermined reconfiguration data in a partial reconfiguration area divided into a predetermined number, and includes a plurality of types of reconfiguration data in which the specific function processing is the same, and Management means for managing the usage state of the reconfiguration data written in the partial reconfiguration area, and specifying according to the number of newly writable partial reconfiguration areas specified by the use state of the partial reconfiguration area Selecting means for selecting one piece of reconstruction data to be written from a plurality of types of reconstruction data having the same function processing.

  According to the present invention, the most appropriate FPGA reconfiguration data can be automatically selected from a plurality of types of FPGA reconfiguration data capable of realizing the same processing function according to the amount of resources available for the FPGA.

It is a block diagram which shows the structure of information processing apparatus. It is a figure which shows the table which manages the information of the processing function of information processing apparatus. It is a figure which shows the example of the method of determining the content described in the item of priority. It is a figure which shows an example of the table | surface which manages the resource of FPGA. It is a flowchart which shows the control method of information processing apparatus. It is a flowchart which shows the control method of information processing apparatus. It is a flowchart which shows the control method of information processing apparatus.

Next, the best mode for carrying out the present invention will be described with reference to the drawings.
<Description of system configuration>
[First Embodiment]
FIG. 1 is a block diagram illustrating the configuration of the information processing apparatus according to the present embodiment. This example is an example of an information processing apparatus to which an FPGA device is applied. The information processing apparatus includes an image forming apparatus, a facsimile apparatus, an MFP, a printer apparatus, an image processing apparatus, and the like.
In FIG. 1, a system 100 includes a control device 101, a server 102, a reconfigurable device (FPGA) 103, a network 104, and a PCI Express 105. Note that the information processing apparatus shown in the present embodiment is configured to execute predetermined function processing by writing predetermined reconstruction data in a partial reconstruction area divided into a predetermined number. Further, the control unit 1011 manages predetermined reconstruction data in a table as will be described later.
The control device 101 includes a control unit 1011, a first IF unit 1012, a storage unit 1013, a second IF unit 1014, and a display unit 1015.

  The control unit 1011 includes a device such as a CPU (Central Processing Unit) and a RAM (Random Access Memory), and controls the first IF unit 1012, the storage unit 1013, and the second IF unit 1014.

  The control unit 1011 can also transmit a control command to the server 102 via the first IF unit 1012. In FIG. 1, transmission is performed via the network 104, but any transmission means in the present invention may be used.

  The control unit 1011 can also store the configuration data of the FPGA 103 transmitted from the server 102 in the storage unit 1013 via the first IF unit 1012. Of course, the configuration data may be transmitted as it is to the FPGA 103 without being stored. The control unit 1011 can also automatically select appropriate configuration data based on information stored in the storage unit 1013.

The control unit 1011 can also transmit configuration data and a control command to the FPGA 103 via the second IF unit 1014. In FIG. 1, transmission is performed via the PCI Express 105, but any transmission means in the present invention may be used. The control unit 1011 can also present characters, images, and the like to the user via the display unit 1015. The first IF unit 1012 is an interface circuit device that can communicate with the server 102 such as a TCP / IP interface.
The storage unit 1013 includes a large-capacity storage device such as a RAM or an HDD (Hard Disk Drive), and can store configuration data of the FPGA 103. The storage unit 1013 can also store configuration state information of the FPGA 103 and attribute information of configuration data transmitted from the server 102.
The second IF unit 1014 is an interface circuit device that can communicate with the FPGA 103 such as PCI Express. The display unit 1015 includes display means including a liquid crystal display and display control means for controlling the display means, and displays characters, images, and the like under the control of the control unit 1011. The server 102 includes a storage unit 1021 and an IF unit 1022.

  The storage unit 1021 includes a large-capacity storage device such as an HDD or a ROM (Read Only Memory). The storage unit 1021 can store configuration data of the FPGA 103 and transmit the configuration data to the control device 101 via the IF unit 1022. The IF unit 1022 is an interface circuit that can communicate with the control device 101 such as a TCP / IP interface. A control command can be received from the control device 101 and desired configuration data can be transmitted. The FPGA 103 includes a reconfiguration control unit 1031, an IF unit 1032, and a function execution unit 1033.

  The reconfiguration control unit 1031 includes a hardware circuit, can receive configuration data of the FPGA 103 via the IF unit 1032, and can rewrite the function execution unit 1033. Further, the entire function execution unit 1033 may be reconfigured, or only a part thereof may be reconfigured.

The IF unit 1032 is an interface circuit that can communicate with the control device 101 such as PCI Express. A control command and configuration data can be received from the control device 101, and a notification such as completion of function execution can be transmitted to the control device 101. The function execution unit 1033 includes an FPGA, a CPLD (Complex Programmable Logic Device), and a RAM. The function execution unit 1033 is controlled by the reconfiguration control unit 1031, and when the received configuration data is written via the IF unit 1032, a predetermined processing function It is a circuit that can realize. For convenience of explanation, the reconfiguration device 103 is hereinafter referred to as an FPGA 103.
The configuration data is referred to as configuration data. The network 104 is an example of a communication unit between the control apparatus 101 and the server 102 in the present embodiment, and other units do not affect the present invention. The PCI Express 105 is an example of communication means between the control apparatus 101 and the FPGA 103 in the present embodiment, and other means do not affect the present invention.

FIG. 2 is a diagram illustrating a table for managing information on processing functions of the information processing apparatus according to the present embodiment. The control unit 1011 registers and manages the processing function name, the reconfiguration data name, the number of partial reconfiguration areas to be used, the performance information, the priority, and the acquisition source in the storage unit 1013. The control unit 1011 reconstructs the partial reconfiguration area, which will be described later with reference to FIG. 4, by associating the reconfiguration data name, the use state, and information for specifying which of the partial reconfiguration areas is rewritable. Manage data.
2, the configuration data management table 200 includes items such as a processing function 201, configuration data 202, required resource amount 203, performance 204, priority 205, path 206, and the like. The configuration data management table 200 manages all configuration data stored in the server 102.
In the item of the processing function 201, all types of processing functions are described. For example, a security function A, an image processing function B, an image processing function C, and the like are described. Here, the image processing function B is controlled to include a plurality of types (three types) of reconstruction data and write any one of the reconstruction data according to the number of faces to be deleted from the FPGA.

In the item of the configuration data 202, all configuration data capable of realizing the processing function described in the processing function 201 is described. For example, there is one piece of configuration data (A_HIGH) that can implement the security function A, and three pieces of configuration data that can implement the image processing function B (B_HIGH, B_MID, B_LOW).
Further, as described above, there are a plurality of configuration data that can realize the image processing function B and the image processing function C, each of which can provide different performance, and the required resource amount is also different.

  The item of the required resource amount 203 describes a minimum resource amount necessary for configuring the configuration data. For example, assuming that the total amount of available resources of the FPGA is four, the configuration data B_HIGH requires three of them, and the configuration data B_MID requires two of them.

The item of performance 204 describes the expected performance when the processing function is executed after the configuration data 202 is configured. For example, in the case of a copying machine, the performance of the configuration data A_HIGH is evaluated by the number of image pages that can be processed in one minute, and is described as 80 ppm (Page Per Minute).
In this embodiment, the performance is evaluated with the processing speed, but this is only an example, and the performance may be evaluated based on other criteria.

In general, the higher the performance, the higher the required resource amount. Therefore, the configuration data for HIGH, MID, and LOW of processing function B requires three, two, and one resource amounts, respectively. And
The priority 205 item describes the priority of each processing function. For example, since A is a security function, priority is high. On the other hand, since B and C are normal image processing, the priority is low. The priority is determined in advance by the designer, and any method may be used for determining the priority.

  The item of the path 206 describes the location where each configuration data is stored. When the control device 101 transmits configuration data to the FPGA 103, the control device 101 refers to the path and acquires configuration data. The control unit 1011 of the control device 101 stores the configuration data management table 200 in the storage unit 1013, refers to it when selecting the FPGA 103, and selects appropriate configuration data.

FIG. 3 is a diagram showing a method for determining the contents described in the item of priority 205 shown in FIG. Hereinafter, the priority order determination table 300 in FIG. 3A will be described in detail.
In FIG. 3A, each processing function name A, B, C is described in the processing function 301 item. In the item of processing function type 302, the type of each processing function is described. For example, A is a security processing function that prohibits copying when a specific image pattern is detected, and B is an image correction process that removes show-through.
In addition, the criteria determined in advance by the designer are high in the priority of security processing functions and low in general image processing. In this case, in the priority 303 item, the priority of A is HIGH and the priority of B and C is LOW.

Next, (B) in FIG. 3 and (C) in FIG. 3 will be described. Since the configuration of the table is basically the same, only the difference from FIG. 3A will be described.
In the item of the usage frequency 304 in FIG. 3B, an estimate of the frequency with which each processing function is used is described. For example, the function A is expected to be used for most jobs, and the usage frequency 304 is 90%. On the other hand, the function C is expected not to be used so much, and the usage frequency 304 is 20%.
Further, according to the criteria determined in advance by the designer, frequently used functions (expected usage frequency of 85% or more) have high priority, and other processes have low priority. In this case, in the priority 303 item, the priority of A is HIGH and the priority of B and C is LOW.

In the item of reconfiguration required time (reconfiguration time) 305 in FIG. 3C, the time required to configure each processing function in the FPGA is described. For example, the circuit scale of function A and the overhead of configuration are large, and it takes 5 seconds to reconfigure. On the other hand, the configuration of functions B and C requires only 1 second.
Further, according to the criteria set in advance by the designer, a function with a long reconfiguration time 305 (3 seconds or more) has a high priority and a low priority for other processing in order to save the configuration time. In this case, in the priority 303 item, the priority of A is HIGH and the priority of B and C is LOW. The contents described in the item of priority 303 are reflected in the item of priority 205 in FIG. The priority may be determined by a method other than the above.

FIG. 4 is a diagram illustrating an example of a table for managing resources of the FPGA 103 illustrated in FIG. Hereinafter, the FPGA resource management table 400 in FIG. 4A will be described in detail. The control unit 1011 stores in the storage unit 1013 information specifying the partial reconfiguration area constituting the FPGA resource management table 400, the reconfiguration data name, the usage state, and which of the partial reconfiguration areas is rewritable. Register and manage.
In (A) of FIG. 4, in the item of the partially reconfigurable area 401, an area number having a partial reconfiguration function is described in the FPGA 103. For example, the FPGA has a four-sided partial reconstruction region, which is divided into a region I, a region II, a region III, and a region IV.

  In the item of the configuration status 402, configuration data configured in each area is described. For example, the area I and the area II are occupied by the configuration data A_HIGH, and the area III and the area IV are occupied by the configuration data B_MID. According to the configuration data management table 200, A_HIGH and B_MID each require two resources.

  The item of use state 403 describes the state of whether or not each configured processing function is actually operating. For example, in the case of FIG. 4A, the processing function A is not operating and the processing function B is actually operating.

In the item of rewriteability 404 indicating whether data can be written, the state of whether or not the original configuration data can be rewritten by writing new configuration data in each partially reconfigurable area 401 of the FPGA 103 is described. For example, in the case of FIG. 4A, all the areas are not rewritable.
For (B) in FIG. 4, only the difference in FIG. 4 (A) will be described.
The item of use state 403 describes that neither function A nor function B is operating. In the item of rewriteability 404, areas I and II are in a state in which rewriting is impossible, and areas III and IV are in a state in which rewriting is possible.
Further, whether or not rewriting is possible is automatically determined based on the contents described in the configuration data management table 200 and the FPGA resource management table 400. A detailed determination method will be described with reference to a flowchart shown in FIG.

  Hereinafter, the operation of the system for automatically selecting appropriate configuration data based on the determination method of whether or not rewriting and the determination result will be described with reference to FIGS.

  FIG. 5 is a flowchart illustrating a method for controlling the information processing apparatus according to the present embodiment. In steps S501 to S515, the control unit 1011 of the control apparatus 101 acquires information from the FPGA resource management table 400 and the configuration data management table 200, and the performance is automatically matched according to the number of rewritable FPGA areas. This is an operation flow for selecting the best configuration data. Each step is stored in the storage unit 1013 of the control apparatus 101 and executed by the control unit 1011. Hereinafter, an example will be described in which the FPGA 103 is in the state shown in FIG. 4B (the processing function A and the processing function B are configured and both are unused), and the processing function C is further implemented. As a result, the state shown in FIG. 4B changes to the state shown in FIG.

The control unit 1011 transmits an instruction to the FPGA 103 via the second IF unit 1014, acquires the resource management table 400 of the FPGA 103 via the second IF unit 1014, and stores it in the storage unit 1013. (S501).
The control unit 1011 refers to the FPGA resource management table 400 to determine whether each area can be rewritten (S502). The determination of whether or not rewriting is possible will be described in detail with reference to FIG. 6 (S516 to S527).
Next, the control unit 1011 acquires the total number of rewritable areas. In the present embodiment, the number of rewritable areas is two (see FIG. 4) (S503). The control unit 1011 refers to the configuration data management table 200 stored in the storage unit 1013 (S504). The control unit 1011 searches for and specifies the processing function C from the item of the processing function 201 in the configuration data management table 200 (S505).

  The control unit 1011 identifies all configuration data that can realize the processing function C from the items of the configuration data 202 of the configuration data management table 200. In the case of the present embodiment, three configuration data of C_HIGH, C_MID, and C_LOW are specified (S506).

  The control unit 1011 acquires the required resource amount of each configuration data from the item of the required resource amount 203 of the configuration data management table 200 (S507). In the present embodiment, C_HIGH requires three surfaces, C_MID requires two surfaces, and C_LOW requires one surface.

  Next, the control unit 1011 refers to the information of the item of the performance 204 of the configuration data management table 200, and compares the configuration data identified in S506 from the one with the highest performance. In the case of the present embodiment, comparison is made from C_HIGH configuration data (S508). The control unit 1011 compares the required resource amount (3 planes) of the C_HIGH configuration data acquired in S507 with the number of rewritable areas (2 planes) acquired in S503 (S509). Specifically, the control unit 1011 determines whether or not the C_HIGH required resource amount 203 exceeds the number of rewritable areas.

  When the control unit 1011 sees the comparison result in S509 and determines that “required resource of C_HIGH”> “number of rewrite areas” is not satisfied, C_HIGH is selected as the most appropriate configuration data, Configuration data is acquired (S510), and the process ends.

  On the other hand, when the control unit 1011 determines that “the required resource of C_HIGH”> “the number of rewrite areas” by looking at the comparison result of S509, the process proceeds to S511. Then, the required resource amount (2 sides) of the configuration data of C_MID is compared with the number of rewritable areas (2 sides) acquired in S503 (S511). Specifically, the control unit 1011 determines whether or not the required resource 203 of C_MID exceeds the number of rewritable areas.

  When the control unit 1011 determines that “the required resource of C_MID”> “the number of rewrite areas” is not satisfied by looking at the comparison result of S511, the control unit 1011 selects C_MID as the most appropriate configuration data, Configuration data is acquired (S512), and this process is terminated.

  On the other hand, when the control unit 1011 determines that “the required resource of C_MID”> “the number of rewrite areas” by looking at the comparison result of S511, the process proceeds to S513. Then, the required resource amount (one side) of the configuration data of C_LOW is compared with the number of rewritable areas (two sides) acquired in S503 (S513). Specifically, the control unit 1011 determines whether or not the C_LOW required resource 203 exceeds the number of rewritable areas.

  Here, when the control unit 1011 determines that “the required resource of C_LOW”> “the number of rewrite areas” is not satisfied by looking at the comparison result of S513, C_LOW is selected as the most appropriate configuration data, Actual configuration data is acquired (S514), and this process ends.

On the other hand, if the control unit 1011 determines that “required resources for C_LOW”> “number of rewrite areas” by looking at the comparison result in S513, all the configuration data that can realize the processing function C is configured in the FPGA. It is determined that it cannot be performed, and it is presented to the user via the display unit 1015 (S515), and this process ends.
In the present embodiment, since the number of rewritable areas is two, C_MID is automatically selected as appropriate configuration data by the above method.

FIG. 4C shows the state of the FPGA resource management table 400 after configuration data is selected and configured by the above method.
The configuration data of the processing function B configured in the rewritable area (area III, area IV) has been rewritten to the configuration data of the processing function C. The configuration data of the processing function A configured in the non-rewritable areas (area I and area II) is not affected.

FIG. 6 is a flowchart illustrating a method for controlling the information processing apparatus according to the present exemplary embodiment. This example is a processing example in which the control unit 1011 of the control apparatus 101 uses the FPGA resource management table 400 stored in the storage unit 1013 to specify a rewritable area. 101 is stored in the storage unit 1013 and executed by the control unit 1011. The detailed procedure of S502 shown in FIG. 5 will be described below.
The control unit 1011 sets each area of the FPGA resource management table 400 to a non-rewritable state (S516). The control unit 1011 refers to the FPGA resource management table 400 stored in the storage unit 1013 (S517).
The control unit 1011 refers to information corresponding to all the regions of the FPGA 103 (regions I, II, III, and IV in this embodiment) in order. In the present embodiment, reference is made from region I (S518).
The control unit 1011 determines whether or not the corresponding area is configured based on the contents described in the item of the configuration state 402 of the FPGA resource management table 400 (S519).

If the control unit 1011 sees the determination result in S519 and determines that it is not configured, the control unit 1011 makes the corresponding area rewritable (S520), and proceeds to S526.
On the other hand, when the control unit 1011 determines that it is configured, the use state 403 of the corresponding area is referred to (S521). Next, the control unit 1011 determines whether or not the processing function configured in the corresponding area (processing function B in this embodiment) is operating (S522).
Note that when the control unit 1011 determines that the processing function B is operating by looking at the determination result in S522, the process proceeds to the determination in S526.
When the control unit 1011 sees the determination result of S522 and determines that the processing function B is not operating, the control unit 1011 refers to the configuration data management table 200 stored in the storage unit 1013 (S523).

The control unit 1011 refers to the priority of the function B from the priority 205 item of the configuration data management table 200, and determines whether the priority is “LOW” or “HIGH” (S524). If the control unit 1011 sees the determination result of S524 and determines that the priority 205 is “LOW”, the corresponding area is made rewritable (S525), and the process proceeds to S526.
In addition, when the control unit 1011 looks at the determination result of S524 and the priority 205 is “HIGH”, whether or not the search has been completed for all the regions without changing the rewriteability attribute of the corresponding region. Is determined (S526).

Here, the control unit 1011 looks at the determination result of S526, and if the determination has not been completed for all the regions, the control unit 1011 proceeds to S518 and determines the next region.
On the other hand, the control unit 1011 obtains the total number of rewritable areas in the case where the determination is completed for all areas by looking at the determination result in S526 (S527).
With the above method, when the processing function C is to be configured in the FPGA 103, the rewritable resource amount can be calculated.

[Second Embodiment]
In the first embodiment, the operation at the time of configuring the configuration data of the processing function of “LOW” as the priority 205 has been described. Hereinafter, the configuration data of the processing function having the priority of “HIGH” in the second embodiment. The operation when configuring is described. The description of the second embodiment will focus on differences from the first embodiment.

FIG. 4D shows an example of the usage status of FPGA resources. As for the resources of the FPGA 103, three of the four surfaces are occupied by the configuration data B_HIGH. However, as is apparent from the use state 403 in FIG. 4D, B_HIGH is not operating.
The second embodiment is an example for explaining the operation of the system when trying to configure the FPGA 103 with the processing function A whose priority 205 is “HIGH” in the state shown in FIG. is there.

  FIG. 7 is a flowchart illustrating a method for controlling the information processing apparatus according to the present embodiment. In this example, the control unit 1011 of the control apparatus 101 preferentially configures the processing function A in the FPGA 103, and then considers the remaining resource amount of the FPGA 103, and selects the appropriate configuration data from among the configuration data that can realize the processing function B. In this example, each step is stored in the storage unit 1013 of the control apparatus 101 and executed by the control unit 1011.

  The control unit 1011 acquires the configuration data management table 200 from the storage unit 1013, and determines the priority 205 of the processing function to be configured from now on (S601). Here, when the control unit 1011 looks at the determination result of S601 and the priority 205 of the processing function B is “LOW”, the configuration data that can realize the corresponding processing function by the method described in S501 to S515. Is automatically selected and the FPGA 103 is configured (S602).

  When the control unit 1011 looks at the determination result of S601 and the priority 205 is “HIGH”, the FPGA resource management table 400 is acquired from the storage unit 1013, and is described in the item of the configuration state 402 in the table. Is stored in the storage unit 1013. In the present embodiment, information “B_HIGH is configured” is stored in the storage unit 1013 (S603).

  The control unit 1011 issues a command to the FPGA 103 via the second IF unit 1014 and deletes all configured data (S604). The control unit 1011 automatically selects configuration data by the method described in S501 to S515, and writes the processing function to be configured in the FPGA 103. In this embodiment, A_HIGH is configured (S605).

  The control unit 1011 refers to the information stored in S603 and tries to reconfigure the processing function that was originally configured and deleted in S604. In the present embodiment, the control unit 1011 finds that the processing function B has been deleted, and tries to reconfigure the processing function B (S606).

  The control unit 1011 also selects appropriate configuration data by the method described in S501 to S515, and reconfigures the function deleted in S604. In the present embodiment, considering the remaining amount of FPGA resources at that time, “B_MID” is selected instead of the original B_HIGH, and the FPGA is configured (S607). Thus, FIG. 4B shows the FPGA resource management table after configuration.

Further, when the configuration data is changed in S607, if there is B_MID configuration data in the storage unit 1013 of the control apparatus 101, the FPGA 103 is configured as it is, but if it is determined that there is no B_MID configuration data, the first B_MID configuration data may be received from the server 102 via the IF unit 1012.
Next, the control unit 1011 extracts the configuration data information of the processing function B from the post-configuration FPGA resource management table 400 and compares it with the original configuration data information stored in S603 (S608). The control unit 1011 looks at the comparison result of S608, and if there is a difference, presents it to the user via the display unit 1015 (S609).

In the above method, when a processing function having a higher priority 205 is configured later, a function having a higher priority 205 is configured first, and a function lower than the originally configured priority according to the remaining resource remaining amount. Can be restored. At that time, if there is a performance difference, it can be presented to the user.
In addition, although this embodiment demonstrated the information processing apparatus which rewrites reconstruction data by FPGA, it is applicable also to information processing apparatus provided with CPLD (Complex Programmable Logic Device).

  The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

101 control device 103 reconfigurable device

Claims (12)

An information processing apparatus that executes predetermined function processing by writing predetermined reconstruction data in a partial reconstruction area divided into a predetermined number,
Management means for managing a plurality of types of reconfiguration data in which specific function processing is the same, and a use state of the reconfiguration data written in the partial reconfiguration area;
One reconfiguration data to be written from a plurality of types of reconfiguration data in which specific function processing is the same according to the number of newly writable partial reconfiguration regions specified in the usage state of the partial reconfiguration region A selection means for selecting
An information processing apparatus comprising: Obtaining means for obtaining the selected predetermined reconstruction data;
Control means for controlling the deletion of any reconstruction data written in the partial reconstruction area and the writing of the partial reconstruction area of the predetermined reconstruction data acquired by the acquisition means;
The information processing apparatus according to claim 1, further comprising:   The control means executes a specific function process based on the reconfiguration data written in the partial reconfiguration area, deletes the reconfiguration data corresponding to the specific function process, and then deletes the reconfiguration previously deleted. The information processing apparatus according to claim 2, wherein data is written in the partial reconstruction area.   The control means does not delete reconfigured data that is higher in priority than specific function processing to be newly written and is not used among reconstructed data written in the partial reconfiguration area. The information processing apparatus according to claim 1.   The information processing apparatus according to claim 1, wherein the management unit manages reconfiguration data having a different number of the partial reconfiguration areas to be used for one specific function process.   The information processing apparatus according to claim 1, wherein the management unit manages a processing function name, a reconfiguration data name, the number of partial reconfiguration areas to be used, performance information, a priority, and an acquisition destination.   The information processing apparatus according to claim 6, wherein the priority is specified by a use frequency of predetermined reconstruction data.   The information processing apparatus according to claim 6, wherein the priority is specified by a reconstruction time of predetermined reconstruction data.   The information processing apparatus according to claim 6, wherein the priority is specified by a priority set in predetermined reconstruction data.   The management unit associates and manages the partial reconfiguration area and reconfiguration data name, use state, and information specifying whether any of the partial reconfiguration areas is rewritable. Item 4. The information processing apparatus according to Item 1. A control method for an information processing apparatus that writes predetermined reconstruction data in a partial reconstruction area divided into a predetermined number and executes specific function processing,
A management step of registering and managing a plurality of types of reconfiguration data in which specific function processing is the same and a use state of the reconfiguration data written in the partial reconfiguration area in a registration unit;
One reconfiguration data to be written from a plurality of types of reconfiguration data in which specific function processing is the same according to the number of newly writable partial reconfiguration regions specified in the usage state of the partial reconfiguration region A selection process for selecting
An acquisition step of acquiring the selected predetermined reconstruction data from the acquisition destination;
A control step for controlling the deletion of any of the reconstruction data written in the partial reconstruction area and the writing of the partial reconstruction area of the predetermined reconstruction data acquired by the acquisition step;
An information processing apparatus control method comprising:   A program for causing a computer to execute the control method of the information processing apparatus according to claim 11.

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