JP2017112458A - Spread spectrum clock generating circuit and method for generating spread spectrum clock - Google Patents

Abstract

A spread spectrum clock generation circuit capable of accurately testing a modulation width in a short time while suppressing a test cost.
A spread spectrum clock generation circuit generates an output clock signal vco_ck modulated within a predetermined modulation frequency range. When the output clock signal vco_ck reaches a predetermined test frequency within the modulation frequency range, the spread spectrum clock generation circuit 100 stops the modulation of the output clock signal vco_ck and fixes the frequency of the output clock signal vco_ck to the test frequency. To do.
[Selection] Figure 14

Description

  The present invention relates to a spread spectrum clock generator (SSCG) circuit and a spread spectrum clock generation method.

  In recent years, spread spectrum clock generation (SSCG) circuits have been used as a solution for suppressing EMI noise emitted from electronic devices. The SSCG circuit distributes the frequency at which EMI noise occurs by applying frequency modulation to the clock signal, and reduces EMI. As examples of the SSCG circuit, there are inventions of Patent Documents 1 and 2.

  As one of the test items of the SSCG circuit, for example, there is a modulation width of the SSCG circuit. In order to accurately test the modulation width of a conventional SSCG circuit, it is possible to provide a filter, an amplifier, a power meter, and the like after the SSCG circuit to measure the power of the modulated clock signal in a plurality of frequency bands. I need it. For this reason, there is a problem that a circuit for testing is complicated and the test cost increases.

  In general, the modulation frequency of the SSCG circuit is very slow (for example, several tens of kHz) compared to the frequency of the clock signal. Therefore, when attempting to count the clock signal output from the SSCG circuit over a period corresponding to a plurality of modulation periods, there is a problem that the test time becomes long and the test cost increases.

  An object of the present invention is to provide a spread spectrum clock generation circuit capable of accurately testing a modulation width in a short time while suppressing a test cost.

According to the spread spectrum clock generation circuit of one aspect of the present invention,
In a spread spectrum clock generation circuit that generates an output clock signal modulated within a predetermined modulation frequency range,
When the frequency of the output clock signal reaches a predetermined test frequency within the modulation frequency range, the modulation of the output clock signal is stopped and the frequency of the output clock signal is fixed to the test frequency. And

  According to the present invention, it is possible to provide a spread spectrum clock generation circuit capable of accurately testing a modulation width in a short time while suppressing a test cost.

1 is a block diagram showing a configuration of a spread spectrum clock generation circuit 100 according to an embodiment of the present invention. It is a figure for demonstrating the phase of the output clock signal vco_ck selected by the phase selection circuit 6 of FIG. It is a figure for demonstrating the phase of the output clock signal vco_ck selected by the phase selection circuit 6 of FIG. 3 is a timing chart showing the phase shift when the phase shift amount Δph is positive, which is a phase shift by the phase selection circuit 6 of FIG. 1. It is a graph which shows the phase selected by the phase selection circuit 6 when performing the phase shift of FIG. 2 is a timing chart showing the phase shift by the phase selection circuit 6 of FIG. 1 when the phase shift by the phase selection circuit 6 of FIG. 1 and the phase shift amount Δph is negative. It is a graph which shows the phase selected by the phase selection circuit 6 when performing the phase shift of FIG. It is a timing chart which shows the phase shift by the phase shift by the phase selection circuit 6 of the spread spectrum clock generation circuit 100 according to the modification of the embodiment of the present invention and the phase shift amount Δph is positive. It is a graph which shows the phase selected by the phase selection circuit 6 when performing the phase shift of FIG. It is a timing chart which shows the phase shift by the phase shift by phase selection circuit 6 of spread spectrum clock generation circuit 100 concerning the modification of the embodiment of the present invention, and when phase shift amount Δph is negative. It is a graph which shows the phase selected by the phase selection circuit 6 when performing the phase shift of FIG. It is a figure for demonstrating the spread spectrum modulation by the phase selection circuit 6 of FIG. FIG. 13 is a diagram showing a change in frequency of an output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. It is a block diagram which shows the structure of the phase controller 5 of FIG. It is a figure for demonstrating the 1st operation | movement of the phase selection circuit 6 of FIG. 1 for testing the maximum value of a modulation frequency range. FIG. 16 is a diagram showing a change in frequency of an output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. 15. It is a figure for demonstrating operation | movement of the phase selection circuit 6 of FIG. 1 for testing the minimum value of a modulation frequency range. It is a figure which shows the change of the frequency of the output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operate | moves according to FIG. It is a figure for demonstrating the 1st operation | movement of the phase selection circuit 6 of FIG. 1 for testing the median value of a modulation frequency range. FIG. 20 is a diagram showing a change in frequency of an output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. It is a figure for demonstrating the 2nd operation | movement of the phase selection circuit 6 of FIG. 1 for testing the median value of a modulation frequency range. FIG. 22 is a diagram showing a change in frequency of an output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. 21. It is a figure for demonstrating the 2nd operation | movement of the phase selection circuit 6 of FIG. 1 for testing the maximum value of a modulation frequency range. FIG. 24 is a diagram showing a change in frequency of an output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. FIG. 2 is a block diagram showing a configuration for testing the spread spectrum clock generation circuit 100 of FIG. 1.

  A spread spectrum clock generation circuit according to an embodiment of the present invention will be described below with reference to the drawings.

  First, spread spectrum modulation of a clock signal by a spread spectrum clock generation circuit according to an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of a spread spectrum clock generation (SSCG) circuit 100 according to an embodiment of the present invention. The SSCG circuit 100 includes a phase frequency comparator 1, a charge pump 2, a loop filter 3, a voltage controlled oscillator 4, a phase controller 5, a phase selection circuit 6, a frequency divider 7, an input frequency divider 11, and an output frequency divider 12. It has.

  The SSCG circuit 100 is configured as a fractional PLL circuit.

  The reference clock signal ref_ck generated by the reference clock generator outside the SSCG circuit 100 is divided by the input frequency divider 11, and the divided input clock signal comp_ck is input to the phase frequency comparator 1.

  The phase frequency comparator 1 detects a phase difference between the input clock signal comp_ck and a feedback signal fb_ck described later, and outputs it to the charge pump 2.

  The charge pump 2 outputs the charge pump voltage increased or decreased according to the phase difference to the loop filter 3, and the loop filter 3 outputs the control voltage corresponding to the charge pump voltage to the voltage controlled oscillator (VCO) 4.

  The voltage controlled oscillator 4 generates and outputs an output clock signal vco_ck having a frequency and phase corresponding to the control voltage.

  The output divider 12 divides the output clock signal vco_ck for use by other circuits and outputs it as a pixel clock signal pix_ck. The feedback circuit from the voltage controlled oscillator 4 to the phase frequency comparator 1 is provided with a phase selection circuit 6 that operates under the control of the phase controller 5 and a frequency divider 7 having a fixed integer frequency division ratio. .

  The phase selection circuit 6 generates and outputs a phase-shifted clock signal pi_out having a period changed from the period of the output clock signal vco_ck by changing the phase of the rising edge of the output clock signal vco_ck. Specifically, the phase selection circuit 6 selects one of the phases obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into a predetermined number, and selects the phase-shifted clock signal pi_out having a rising edge in the selected phase. Generate and output. The phase controller 5 determines the phase of the rising edge of the phase shift clock signal pi_out selected by the phase selection circuit 6 and sends the phase selection signal ph_sel indicating the determined phase to the phase selection circuit 6, thereby 6 is controlled. Specifically, the phase controller 5 controls the phase selection circuit 6 so that the period of the phase shift clock signal pi_out is changed by a predetermined phase shift amount Δph from the period of the output clock signal vco_ck. Here, the predetermined phase shift amount Δph is an integer multiple of the phase equally divided by the phase selection circuit 6.

  The frequency divider 7 divides the phase-shifted clock signal pi_out and inputs it to the phase frequency comparator 1 as a feedback signal fb_ck.

  The fractional PLL circuit included in the SSCG circuit 100 of the present embodiment performs negative feedback control so that the frequency and phase of the feedback signal fb_ck coincide with the frequency and phase of the input clock signal comp_ck. Furthermore, the fractional PLL circuit operates only the change in the frequency division ratio of the frequency divider 7 by generating the phase shift clock signal pi_out having a period changed from the period of the output clock signal vco_ck by the phase selection circuit 6. The rational division ratio can be realized without using the principle. When the phase shift amount Δph is positive, the frequency of the feedback signal fb_ck is higher than the frequency of the input clock signal comp_ck. When the phase shift amount Δph is negative, the frequency of the feedback signal fb_ck is higher than the frequency of the input clock signal comp_ck. Also lower. Furthermore, the SSCG circuit 100 according to the present embodiment can SS modulate the frequency of the output clock signal vco_ck by changing the period of the phase-shifted clock signal pi_out by the phase selection circuit 6.

  The phase selection circuit 6 can further divide the output clock signal vco_ck when generating the phase shift clock signal pi_out having a period changed from the period of the output clock signal vco_ck. In this specification, the set value of the division ratio of the phase selection circuit 6 is represented by div_puck = 0, 1, 2,..., And when div_puck = n, the division ratio is n + 1. When the output divider 12 has a division ratio of 2 or more, the phase selection circuit 6 further divides the output clock signal vco_ck in consideration of this division ratio. In this specification, the setting value of the frequency division ratio of the output frequency divider 12 is represented by div_pll = 0, 1, 2,..., And when div_pll = n, the frequency division ratio is n + 1. Further, in this specification, the setting value of the frequency division ratio of the frequency divider 7 is represented by div_fb = 0, 1, 2,..., And when div_fb = n, the frequency division ratio is n + 1. Therefore, the division ratio of the feedback signal fb_ck to the output clock signal vco_ck is obtained by multiplying the division ratio of the phase selection circuit 6, the division ratio of the output divider 12, and the division ratio of the divider 7. become.

  The output divider 12 divides the output clock signal vco_ck having a frequency of, for example, 60 to 120 MHz into a pixel clock signal pix_ck having a frequency of 5 to 40 MHz.

  A control signal Mode for switching the operation mode of the SSCG circuit 100 is input to the phase controller 5 from outside the SSCG circuit 100. The operation modes of the SSCG circuit 100 include a normal mode for generating a spread spectrum output clock signal and a test mode for testing the SSCG circuit 100. Hereinafter, the operation in the normal mode of the SSCG circuit 100 will be described first, and then the operation in the test mode of the SSCG circuit 100 will be described with reference to FIGS.

  2 and 3 are diagrams for explaining the phase of the output clock signal vco_ck selected by the phase selection circuit 6. In this specification, the phase selection circuit 6 selects any one of the phases (indicated as “0” to “511” in FIGS. 2 and 3) obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into 512 pieces. It will be explained as a thing. The phase selection circuit 6 functions as a phase interpolator that inserts a rising edge into an arbitrary phase.

  First, the operation of the SSCG circuit 100 as a fractional PLL circuit will be described in detail with reference to FIGS. For simplification of explanation, it is assumed that the division ratios of the phase selection circuit 6, the output divider 12, and the divider 7 are all 1, that is, div_puck = 0, div_fb = 0, and div_pll = 0. .

  FIG. 4 is a timing chart showing the phase shift by the phase selection circuit 6 of FIG. 1 and the phase shift when the phase shift amount Δph is positive. The horizontal axis of FIG. 4 has a unit obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into 512 units (the phase is expressed in the same unit throughout the following FIGS. 5 to 11). In the case of FIG. 4, the cycle of the phase shift clock signal pi_out is increased by the phase shift amount Δph from the cycle of the output clock signal vco_ck (that is, 512 + Δph). Accordingly, the rising edge of each clock of the phase shift clock signal pi_out is delayed by an increment of the phase shift amount Δph from the rising edge of each corresponding clock of the output clock signal vco_ck each time the clock advances. Assume that the rising edges of the first clock vco_ck (0) of the output clock signal and the first clock pi_out (0) of the phase-shifted clock signal match. The rising edge of the second clock pi_out (1) of the phase-shifted clock signal is delayed by the phase shift amount Δph from the rising edge of the second clock vco_ck (1) of the output clock signal. The rising edge of the third clock pi_out (2) of the phase shift clock signal is delayed by twice the phase shift amount Δph from the rising edge of the third clock vco_ck (2) of the output clock signal. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal is n−1 times the phase shift amount Δph from the rising edge of the nth clock vco_ck (n−1) of the output clock signal. Delayed.

  FIG. 5 is a graph showing the phase selected by the phase selection circuit 6 when the phase shift of FIG. 4 is performed. The phase selection circuit 6 selects one of the phases “0” to “511” obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into 512 as the current phase. As shown in FIG. 5, every time the clock of the output clock signal vco_ck advances, the phase selection circuit 6 selects the phase incremented by the phase shift amount Δph as a new current phase. The phase selection circuit 6 determines whether or not the sum of the current phase and the phase shift amount Δph is less than one cycle of the clock of the output clock signal vco_ck even if it is incremented by the phase shift amount Δph, that is, the phase after the increment is Depending on whether it is “511” or less, it operates as follows. When the phase after the increment is “511” or less, the rising edge of the next clock of the phase-shifted clock signal pi_out is in the corresponding phase within the period of the next clock of the output clock signal vco_ck. When the phase after the increment is “512” or more, the rising edge of the next clock of the phase-shifted clock signal pi_out is not the next clock of the output clock signal vco_ck, but after the increment within the period of the next clock. The phase is obtained by subtracting “512” from the phase of. In the latter case, for example, as shown in FIG. 4, the rising edge of the fifth clock pi_out (4) of the phase-shifted clock signal is not the fifth clock vco_ck (4) of the output clock signal but the sixth clock vco_ck (5). Is within the period. Further, this rising edge is delayed from the rising edge of the sixth clock vco_ck (5) of the output clock signal by mod (4 × Δph, 512), that is, the remainder when 4 × Δph is divided by 512. This is indicated by a white arrow in FIG. 5, and instead of selecting the phase indicated by the dotted circle in the clocks vco_ck (4), vco_ck (8), and vco_ck (12) of the output clock signal, The solid white circle on the clock is selected.

  By selecting the phase as shown in FIG. 4 and FIG. 5, the period of each clock pi_out (0),. The length increased by Δph (512 + Δph).

  FIG. 6 is a timing chart showing the phase shift by the phase selection circuit 6 of FIG. 1 and the phase shift by the phase selection circuit 6 of FIG. 1 when the phase shift amount Δph is negative. In the case of FIG. 6, the cycle of the phase shift clock signal pi_out is decreased from the cycle of the output clock signal vco_ck by a phase shift amount | Δph | (that is, 512− | Δph |). Therefore, the rising edge of each clock of the phase-shifted clock signal pi_out is increased by a phase shift amount | Δph | from the rising edge of each corresponding clock of the output clock signal vco_ck each time the clock advances. Assume that the rising edges of the first clock vco_ck (0) of the output clock signal and the first clock pi_out (0) of the phase-shifted clock signal match. The rising edge of the second clock pi_out (1) of the phase shift clock signal is advanced by a phase shift amount | Δph | from the rising edge of the second clock vco_ck (1) of the output clock signal. The rising edge of the third clock pi_out (2) of the phase shift clock signal is advanced by twice the phase shift amount | Δph | from the rising edge of the third clock vco_ck (2) of the output clock signal. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal is n−1 of the phase shift amount | Δph | from the rising edge of the nth clock vco_ck (n−1) of the output clock signal. Doubled and made faster.

  FIG. 7 is a graph showing the phase selected by the phase selection circuit 6 when the phase shift of FIG. 6 is performed. As shown in FIG. 7, the phase selection circuit 6 selects a phase that is decreased by a phase shift amount | Δph | every time the clock of the output clock signal vco_ck advances. If the phase after the decrease does not become negative even if the phase shift amount | Δph | is decreased, the rising edge of the next clock of the phase shift clock signal pi_out corresponds to the period of the clock next to the output clock signal vco_ck. In phase. When the phase after the decrease becomes negative when the phase shift amount | Δph | is decreased, the rising edge of the next clock of the phase shift clock signal pi_out is not within the period of the current clock, but the next clock of the output clock signal vco_ck. The phase is obtained by adding “512” to the phase after the decrease. In the latter case, for example, as shown in FIG. 6, the rising edge of the fifth clock pi_out (4) of the phase-shifted clock signal is not the fourth clock vco_ck (3) of the output clock signal but the third clock vco_ck (2). Is within the period. Further, this rising edge is the remainder when mod (4 × | Δph |, 512), that is, 4 × | Δph | is divided by 512 from the rising edge of the fourth clock vco_ck (3) of the output clock signal. Be done early. This is indicated by a white arrow in FIG. 7, and instead of selecting the phase indicated by the dotted circle in the clocks vco_ck (1), vco_ck (3),. The white circle is selected.

  By selecting the phase as shown in FIGS. 6 and 7, the period of each clock pi_out (0),..., Pi_out (n) of the phase-shifted clock signal is always the amount of phase shift from the period of the clock of the output clock signal vco_ck. The length is reduced by | Δph | (512− | Δph |).

  The phase controller 5 determines the phase of the rising edge of the phase shift clock signal pi_out as described with reference to FIGS. 4 to 7, and controls the operation of the phase selection circuit 6 according to the determined phase.

  When the frequency of the phase-shifted clock signal pi_out is fpi_out and the frequency of the output clock signal vco_ck is fvco_ck, the following equation holds.

[Equation 7]
fpi_out = fvco_ck × 512 / (512 + Δph)

  At this time, as described above, the fractional PLL circuit of the present embodiment performs negative feedback control so that the frequency and phase of the feedback signal fb_ck coincide with the frequency and phase of the input clock signal comp_ck. Therefore, when the frequency of the input clock signal comp_ck is fcomp_ck and the frequency of the feedback signal fb_ck is ffb_ck, the following equation holds between the frequencies of the signals.

[Equation 8]
ffb_ck = fpi_out = fcomp_ck
[Equation 9]
fcomp_ck = fvco_ck × 512 / (512 + Δph)
[Equation 10]
fvco_ck = fcomp_ck × (1 + Δph / 512)

  According to the SSCG circuit 100 including the fractional PLL circuit of the present embodiment, a very small multiplication factor (for example, a multiplication factor of 1% or less) can be realized by improving the resolution of the phase selection circuit 6. In the described embodiment, the minimum multiplication ratio is 1 / 512≈0.002 = 0.2%.

  Next, referring to FIGS. 8 to 11, the operation of the SSCG circuit 100 as a fractional PLL circuit when the frequency division ratios of the phase selection circuit 6, the output frequency divider 12, and the frequency divider 7 are taken into consideration. Will be described. In other words, in this case, any of div_puck, div_fb, and div_pll is 1 or more. 8 to 11 show a case where the setting value div_puck = 2 of the frequency division ratio of the phase selection circuit 6, that is, the frequency division ratio of the phase selection circuit 6 is 3. FIG.

  FIG. 8 is a timing chart showing the phase shift by the phase selection circuit 6 of the spread spectrum clock generation circuit 100 according to the modification of the embodiment of the present invention and the phase shift when the phase shift amount Δph is positive. . Every three clocks of the output clock signal vco_ck is called a clock signal div_ck obtained by dividing the phase selection circuit 6. For example, the tenth to twelfth clocks vco_ck (9), vco_ck (10), and vco_ck (11) of the output clock signal become the fourth clock div_ck (3) of the divided clock signal. In each of the clocks of the divided clock signal div_ck, the three clocks of the output clock signal vco_ck are referred to as first to third sub clocks vco_ck (0) ′, vco_ck (1) ′, and vco_ck (2) ′. In the case of FIG. 8, the period of the phase-shifted clock signal pi_out is increased by a phase shift amount Δph from the period of three clocks of the output clock signal vco_ck (that is, the period of the divided clock signal div_ck) (that is, 512 × 3 + Δph). Accordingly, the rising edge of each clock of the phase shift clock signal pi_out is delayed by an increment of the phase shift amount Δph from the rising edge after 3 clocks of the output clock signal vco_ck each time the clock advances. In other words, the rising edge is delayed by an increment of the phase shift amount Δph from the head of the clock of the divided clock signal div_ck. Assume that the rising edges of the first clock vco_ck (0) of the output clock signal and the first clock pi_out (0) of the phase-shifted clock signal match. The rising edge of the second clock pi_out (1) of the phase-shifted clock signal is delayed by the phase shift amount Δph from the rising edge of the fourth clock vco_ck (3) of the output clock signal. The rising edge of the third clock pi_out (2) of the phase shift clock signal is delayed by twice the phase shift amount Δph from the rising edge of the seventh clock vco_ck (6) of the output clock signal. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal is n−1 of the phase shift amount Δph from the rising edge of the third n−2 clock vco_ck (3n−3) of the output clock signal. Delayed by a factor of two.

  FIG. 9 is a graph showing a phase selected by the phase selection circuit 6 when the phase shift of FIG. 8 is performed. The phase selection circuit 6 selects one of the phases “0” to “1535” obtained by equally dividing the period of the divided clock signal div_ck into 1536 as the current phase. However, in the same manner as in FIGS. 2 and 3, the phase selection circuit 6 substantially outputs one of the phases “0” to “511” obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into 512 pieces. select. As shown in FIG. 9, each time the clock of the divided clock signal div_ck advances, the phase selection circuit 6 selects the phase incremented by the phase shift amount Δph as a new current phase. The phase selection circuit 6 determines whether or not the sum of the current phase and the phase shift amount Δph is less than the period of the divided clock signal div_ck even if it is incremented by the phase shift amount Δph, that is, the phase after the increment is Depending on whether it is “1535” or less, it operates as follows. When the phase after the increment is “1535” or less, the rising edge of the next clock of the phase-shifted clock signal pi_out is in the corresponding phase within the period of the next clock of the divided clock signal div_ck. When the phase after the increment is “1536” or more, the rising edge of the next clock of the phase-shifted clock signal pi_out is “1536” from the phase after the increment in the period after two clocks of the divided clock signal div_ck. ”Is subtracted. In the latter case, for example, as shown in FIG. 8, the rising edge of the eighth clock pi_out (7) of the phase-shifted clock signal is within the period of the seventh clock div_ck (6) of the divided clock signal. Furthermore, this rising edge is delayed from the beginning of the seventh clock div_ck (6) of the divided clock signal by mod (5 × Δph, 1536), that is, the remainder when 5 × Δph is divided by 1536. The

  By selecting the phase as shown in FIGS. 8 and 9, the period of each clock pi_out (0),..., Pi_out (n) of the phase-shifted clock signal is always shifted from the period of three clocks of the output clock signal vco_ck. The length is increased by the phase amount Δph (512 × 3 + Δph).

  FIG. 10 is a timing chart showing the phase shift by the phase selection circuit 6 of the spread spectrum clock generation circuit 100 according to the modification of the embodiment of the present invention and the phase shift when the phase shift amount Δph is negative. . In the case of FIG. 10, the period of the phase-shifted clock signal pi_out is decreased by a phase shift amount Δph from the period of three clocks of the output clock signal vco_ck (that is, the period of the divided clock signal div_ck) (that is, 512 × 3- | Δph |). Therefore, the rising edge of each clock of the phase-shifted clock signal pi_out is increased by a phase shift amount | Δph | from the rising edge after 3 clocks of the output clock signal vco_ck each time the clock advances. In other words, this rising edge is accelerated by incrementing the phase shift amount | Δph | from the head of the clock of the divided clock signal div_ck. Assume that the rising edges of the first clock vco_ck (0) of the output clock signal and the first clock pi_out (0) of the phase-shifted clock signal match. The rising edge of the second clock pi_out (1) of the phase shift clock signal is advanced by a phase shift amount | Δph | from the rising edge of the fourth clock vco_ck (3) of the output clock signal. The rising edge of the third clock pi_out (2) of the phase shift clock signal is advanced by twice the phase shift amount | Δph | from the rising edge of the seventh clock vco_ck (6) of the output clock signal. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal is n of the phase shift amount | Δph | from the rising edge of the third n−2 clock vco_ck (3n−3) of the output clock signal. -1 times faster.

  FIG. 11 is a graph showing the phase selected by the phase selection circuit 6 when the phase shift of FIG. 10 is performed. As shown in FIG. 9, the phase selection circuit 6 selects a phase that is decreased by a phase shift amount | Δph | every time the clock of the divided clock signal div_ck advances. If the phase after the decrease does not become negative even if the phase shift amount | Δph | is decreased, the rising edge of the next clock of the phase shift clock signal pi_out is the period of the next clock of the divided clock signal div_ck. In the corresponding phase. On the other hand, when the phase after the decrease becomes negative when the phase shift amount | Δph | is decreased, the rising edge of the next clock of the phase shift clock signal pi_out is within the period of the current clock of the divided clock signal div_ck. The phase is obtained by adding “1536” to the phase after the decrease. In the latter case, for example, as shown in FIG. 10, the rising edge of the sixth clock pi_out (5) of the phase-shifted clock signal is within the period of the fourth clock div_ck (3) of the divided clock signal. Further, this rising edge is obtained by dividing mod (5 × | Δph |, 1536), that is, 5 × | Δph | by 1536 from the rising edge of the fifth clock div_ck (4) of the divided clock signal. Will be done early in the remainder.

  By selecting the phase as shown in FIGS. 10 and 11, the period of each clock pi_out (0),..., Pi_out (n) of the phase-shifted clock signal is always shifted from the period of three clocks of the output clock signal vco_ck. The length decreased by the phase amount | Δph | (512 × 3- | Δph |).

  The phase controller 5 determines the phase of the rising edge of the phase-shifted clock signal pi_out as described with reference to FIGS. 8 to 11, and controls the operation of the phase selection circuit 6 according to the determined phase.

  In the case of FIGS. 8 to 11 (that is, when any of div_puck, div_fb, div_pll is 1 or more), Equation 7 is transformed as the following equation.

[Equation 11]
fpi_out = fvco_ck × 512 / {512 × (div_pll + 1) × (div_puck + 1) + Δph}
[Equation 12]
fcomp_ck
= Ffb_ck
= Fpi_out / ([div_fb] +1)
= Fvco_ck × 512 / [{512 × (div_pll + 1) × (div_puck + 1) + Δph} × ([div_fb] +1)]
[Equation 13]
fvco_ck
= Fcomp_ck × (div_fb + 1) × {512 × (div_pll + 1) × (div_puck + 1) + Δph} / 512
= Fcomp_ck × (div_fb + 1) × {(div_pll + 1) × (div_puck + 1) + Δph / 512}
= Fcomp_ck × {(div_fb + 1) × (div_pll + 1) × (div_puck + 1) + (div_fb + 1) × Δph / 512}

  According to the SSCG circuit 100 including the fractional PLL circuit of the present embodiment, a smaller multiplication factor can be realized by the phase selection circuit 6 performing frequency division. In the models of Equations 11 to 13, the minimum multiplication rate (%) is expressed by the following equation.

[Formula 14]
([Div_fb] +1) × Δph / 512
≈ 0.002 × ([div_fb] +1)
= 0.2 × ([div_fb] +1) [%]

  The minimum unit of change rate of the frequency fvco_ck of the output clock signal vco_ck is expressed by the following equation.

[Equation 15]
Δfvco_ck / fvco_ck
= {(Div_pll + 1) × (div_puck + 1) + Δph / 512}
/ {(Div_pll + 1) × (div_puck + 1) +0/512}
= 1 + Δph / {512 × (div_pll + 1) × (div_puck + 1)}
≈ 1 + 0.002 / {(div_pll + 1) × (div_puck + 1)}

  FIG. 12 is a diagram for explaining spread spectrum modulation by the phase selection circuit 6 of FIG. As described with reference to FIGS. 4 to 11, the SSCG circuit 100 including the fractional PLL circuit of the present embodiment operates as follows. The SSCG circuit 100 changes the cycle of the phase shift clock signal pi_out from the cycle of the output clock signal vco_ck by the phase shift amount Δph. At this time, the SSCG circuit 100 further changes the output clock signal by changing the phase shift amount pll_frac (hereinafter referred to as the first phase shift amount pll_frac) that is the center of the phase shift amount Δph by the second phase shift amount pi_ssd. SS modulation of vco_ck is performed. The frequency of the output clock signal vco_ck depends on the setting values div_puck, div_fb, div_pll, the modulation degree ss_amp, and the modulation period ssint of the respective division ratios of the phase selection circuit 6, the output divider 12, and the divider 7. Similar to FIG. 13, it changes to a triangular wave shape.

  First, the minimum time units for changing the phase shift amount Δph for performing SS modulation are SS modulation clocks puck (0), puck (1),..., Puck (n). The SS modulation clock puck (n) is obtained by dividing the clock of the output clock signal vco_ck by the frequency division ratio of the output frequency divider 12 and the frequency division ratio of the phase selection circuit 6. Therefore, the frequency fpuck of the SS modulation clock puck (n) is expressed by the following equation.

[Equation 16]
fpuck = fpix_ck / (div_puck + 1)
[Equation 17]
fpix_ck = fvco_ck / (div_pll + 1)

  As shown in FIG. 12, the phase shift amount Δph is changed stepwise with a step size Δθ for each time interval including a predetermined number of packs (n) (hereinafter referred to as a step time interval step_p). The phase shift amount Δph is changed to a triangular wave shape. The number of SS modulation clocks puck (n) in the step time interval step_p varies depending on the setting.

  Next, the maximum value pi_ssd_max and the minimum value pi_ssd_min of the second phase shift amount pi_ssd are calculated by the following equations.

[Equation 18]
pi_ssd_max = int ([ss_amp] / 1024 / Δf_step)
[Equation 19]
pi_ssd_min = −int ([ss_amp] / 1024 / Δf_step)
[Equation 20]
Δf_step
= Δfvco_ck / fvco_ck-1
= 1/512 / {(div_pll + 1) × (div_puck + 1)}

  The modulation degree ss_amp takes an integer value of 0 to 31, and the maximum change rate of the frequency of the output clock signal vco_ck is represented by ss_amp / 1024 (%). For example, when ss_amp = 31, the frequency of the output clock signal vco_ck increases about 3.1% with respect to the center frequency fc at the maximum value fmax, and about 3.1% with respect to the center frequency fc at the minimum value fmin. Decrease.

  Next, in order to calculate the second phase shift amount pi_ssd, a count value count (n) that is incremented every modulation clock puck (n) is introduced. The count value count (n) and its step size Δcount are represented by decimal numbers including, for example, a 9-bit integer part and a 16-bit decimal part. The step size Δcount of the count value, the initial value count (0) of the count value, and the count value count (n) are expressed by the following equations.

[Equation 21]
Δcount = 2 × (pi_ssd_max−pi_ssd_min) / ssint
[Equation 22]
count (0) = 0
[Equation 23]
count (n) = count (n−1) + Δcount, 1 ≦ n ≦ ssint−1

  The count value count (n) is incremented by a step size Δcount over the modulation period ssint. In accordance with the count value count (n), the second phase shift amount pi_ssd is calculated by the following equation.

[Equation 24]
If 0 ≦ int (count (n)) <pi_ssd_max + 1:
pi_ssd = int (count (n))
[Equation 25]
When pi_ssd_max + 1 ≦ int (count (n)) <pi_ssd_max + 1 + (pi_ssd_max−pi_ssd_min):
pi_ssd = pi_ssd_max- {int (count (n))-pi_ssd_max}
[Equation 26]
When pi_ssd_max + 1 + (pi_ssd_max−pi_ssd_min) ≦ int (count (n)) <2 × (pi_ssd_max−pi_ssd_min):
pi_ssd = pi_ssd_min + {int (count (n)) − (2 × pi_ssd_max−pi_ssd_min)}

  By adding the second phase shift amount pi_ssd calculated as described above to the first phase shift amount pll_frac, the phase shift amount Δph of the phase selection circuit 6 is obtained as shown in FIG. That is, the phase shift amount Δph when performing SS modulation is expressed by the following equation.

[Equation 27]
Δph = pll_frac + pi_ssd

  According to the spread spectrum clock generation circuit of this embodiment, the frequency of the output clock signal vco_ck can be changed as shown in FIG. 13 by changing the phase shift amount Δph in this way. When the phase shift amount Δph increases, the frequency fvco_ck of the output clock signal vco_ck also increases. When the phase shift amount Δph decreases, the frequency fvco_ck of the output clock signal vco_ck also decreases.

  FIG. 13 is a diagram showing a change in the frequency of the output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. FIG. 13 is a diagram for explaining spread spectrum (SS) modulation. By performing SS modulation, the frequency of the output clock signal vco_ck periodically changes in the modulation cycle ssint over a frequency between the maximum value fmax and the minimum value fmin, centering on a predetermined frequency fc.

  The modulation degree ss_amp takes an integer value of 0 to 31, and the maximum change rate of the frequency of the output clock signal vco_ck is represented by ss_amp / 1024 (%). For example, when ss_amp = 31, the frequency of the output clock signal vco_ck increases about 3.1% with respect to the center frequency fc at the maximum value fmax, and about 3.1% with respect to the center frequency fc at the minimum value fmin. Decrease.

  As described above, the SSCG circuit 100 of FIG. 1 generates the output clock signal vco_ck modulated within a predetermined modulation frequency range corresponding to the above-described modulation degree ss_amp. The phase controller 5 determines the phase of the rising edge of the phase-shifted clock signal pi_out as described with reference to FIGS. 8 to 11, and controls the operation of the phase selection circuit 6 according to the determined phase. The phase controller 5 has a phase selection circuit so that the period of the phase shift clock signal pi_out is changed by a phase shift amount pll_frac + pi_ss that varies within a predetermined phase shift amount range from the cycle of the output clock signal vco_ck. 6 is controlled. Here, the phase shift amount range is expressed as follows.

[Equation 28]
pi_ssd_min ≦ pll_frac + pi_ssd ≦ pi_ssd_max

  Next, the modulation width test of the SSCG circuit 100 of FIG. 1 will be described with reference to FIGS.

  FIG. 14 is a block diagram showing the configuration of the phase controller 5 of FIG. The phase controller 5 includes a count value generation circuit 21, a triangular wave generation circuit 22, an adder 23, and a control circuit 24. Inside the phase controller 5, a step size Δcount and a first phase shift amount pll_frac are stored in advance. The count value generation circuit 21 generates a count value count (n) based on the step size Δcount and outputs the integer part int (count (n)). The triangular wave generation circuit 22 operates as follows depending on whether the control signal Mode is the normal mode or the test mode. When the control signal Mode is in the normal mode, the triangular wave generation circuit 22 calculates and outputs the second phase shift amount pi_ssd that changes based on the integer part int (count (n)) of the count value. When the control signal Mode is in the test mode, the triangular wave generation circuit 22 determines whether or not the second phase shift amount pi_ssd has reached a predetermined phase shift amount within the phase shift amount range. The second phase shift amount pi_ssd is fixed to the phase shift amount at that time. The adder 23 adds the first phase shift amount pll_frac and the second phase shift amount pi_ssd to generate the phase shift amount Δph of the phase selection circuit 6. The control circuit 24 outputs the phase selection signal ph_sel to the subsequent phase selection circuit 6.

  When the control signal Mode is in the normal mode, the spread spectrum modulation waveform of FIG. 13 can be obtained.

  On the other hand, when the control signal Mode is in the test mode, the triangular wave generation circuit 22 determines whether the output clock signal vco_ck has reached a predetermined test frequency within the modulation frequency range based on the second phase shift amount pi_ssd. Determine whether. When the frequency of the output clock signal vco_ck reaches a predetermined test frequency within the modulation frequency range, the modulation of the output clock signal vco_ck is stopped. Thereafter, the frequency of the output clock signal vco_ck is fixed to the test frequency.

  The test modes include a maximum value test mode for testing the maximum value of the modulation frequency range, a minimum value test mode for testing the minimum value, and a median value test mode for testing the median value.

  FIG. 15 is a diagram for explaining a first operation of the phase selection circuit 6 of FIG. 1 for testing the maximum value of the modulation frequency range. FIG. 16 is a diagram showing a change in the frequency of the output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. When the control signal Mode is in the maximum value test mode, the triangular wave generation circuit 22 changes the second phase shift amount pi_ssd as shown in FIG. The triangular wave generation circuit 22 fixes the second phase shift amount pi_ssd when the second phase shift amount pi_ssd reaches the maximum value pi_ssd_max of the phase shift amount range. The triangular wave generation circuit 22 continues this state until the maximum value test mode is canceled. The second phase shift amount pi_ssd is added to the first phase shift amount pll_frac to obtain the phase shift amount Δph of the phase selection circuit 6. At this time, the frequency of the output clock signal vco_ck changes as shown in FIG. The modulation operation starts from, for example, the center frequency fc. When the frequency of the output clock signal vco_ck reaches the test frequency that is the maximum value fmax of the modulation frequency range, the modulation of the output clock signal vco_ck is stopped. Thereafter, the frequency of the output clock signal vco_ck is fixed to the test frequency. With the output clock signal vco_ck having the fixed test frequency being output, the frequency can be measured.

  FIG. 17 is a diagram for explaining the operation of the phase selection circuit 6 of FIG. 1 for testing the minimum value of the modulation frequency range. FIG. 18 is a diagram showing a change in frequency of the output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. When the control signal Mode is in the minimum value test mode, the triangular wave generation circuit 22 changes the second phase shift amount pi_ssd as shown in FIG. The triangular wave generation circuit 22 fixes the second phase shift amount pi_ssd when the second phase shift amount pi_ssd reaches the minimum value pi_ssd_min of the phase shift amount range. The triangular wave generation circuit 22 continues this state until the minimum value test mode is canceled. The second phase shift amount pi_ssd is added to the first phase shift amount pll_frac to obtain the phase shift amount Δph of the phase selection circuit 6. At this time, the frequency of the output clock signal vco_ck changes as shown in FIG. The modulation operation starts from, for example, the center frequency fc. When the frequency of the output clock signal vco_ck reaches the test frequency that is the minimum value fmin of the modulation frequency range, the modulation of the output clock signal vco_ck is stopped. Thereafter, the frequency of the output clock signal vco_ck is fixed to the test frequency. With the output clock signal vco_ck having the fixed test frequency being output, the frequency can be measured.

  FIG. 19 is a diagram for explaining a first operation of the phase selection circuit 6 of FIG. 1 for testing the median value of the modulation frequency range. 20 is a diagram showing a change in the frequency of the output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. When the control signal Mode is in the median test mode, the triangular wave generation circuit 22 changes the second phase shift amount pi_ssd as shown in FIG. When the second phase shift amount pi_ssd reaches the maximum value pi_ssd_max of the phase shift amount range once and decreases to reach the median value 0 of the phase shift amount range, the triangular wave generating circuit 22 Fix pi_ssd. The triangular wave generation circuit 22 continues this state until the median test mode is canceled. The second phase shift amount pi_ssd is added to the first phase shift amount pll_frac to obtain the phase shift amount Δph of the phase selection circuit 6. At this time, the frequency of the output clock signal vco_ck changes as shown in FIG. The modulation operation starts from, for example, the center frequency fc. When the frequency of the output clock signal vco_ck once reaches the maximum frequency fmax of the modulation frequency range and then reaches the test frequency that is the center frequency fc, the modulation of the output clock signal vco_ck is stopped. Thereafter, the frequency of the output clock signal vco_ck is fixed to the test frequency. With the output clock signal vco_ck having the fixed test frequency being output, the frequency can be measured.

  FIG. 21 is a diagram for explaining a second operation of the phase selection circuit 6 of FIG. 1 for testing the median value of the modulation frequency range. FIG. 22 is a diagram showing a change in the frequency of the output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. When the control signal Mode is in the median value test mode, the triangular wave generation circuit 22 changes the second phase shift amount pi_ssd as shown in FIG. When the second phase shift amount pi_ssd reaches the minimum value pi_ssd_min of the phase shift amount range once and reaches the median value 0 of the phase shift amount range, the triangular wave generation circuit 22 Fix pi_ssd. The triangular wave generation circuit 22 continues this state until the median test mode is canceled. The second phase shift amount pi_ssd is added to the first phase shift amount pll_frac to obtain the phase shift amount Δph of the phase selection circuit 6. At this time, the frequency of the output clock signal vco_ck changes as shown in FIG. The modulation operation starts from, for example, the center frequency fc. When the frequency of the output clock signal vco_ck once reaches the test frequency that is the center frequency fc after reaching the minimum value fmin of the modulation frequency range, the modulation of the output clock signal vco_ck is stopped. Thereafter, the frequency of the output clock signal vco_ck is fixed to the test frequency. With the output clock signal vco_ck having the fixed test frequency being output, the frequency can be measured.

  The output clock signal vco_ck may be modulated so as to change at a predetermined modulation period within the modulation frequency range. At this time, when the frequency of the output clock signal vco_ck reaches the test frequency after a plurality of modulation periods have elapsed since the start of the modulation of the output clock signal vco_ck, the modulation of the output clock signal vco_ck is stopped and the frequency May be fixed at the test frequency.

  FIG. 23 is a diagram for explaining a second operation of the phase selection circuit 6 of FIG. 1 for testing the maximum value of the modulation frequency range. FIG. 24 is a diagram showing a change in frequency of the output clock signal vco_ck when the phase selection circuit 6 of FIG. 1 operates according to FIG. When the control signal Mode is in the maximum value test mode, the triangular wave generation circuit 22 changes the second phase shift amount pi_ssd as shown in FIG. When the second phase shift amount pi_ssd reaches the maximum value pi_ssd_max of the phase shift amount range, for example, in the second modulation period after the modulation of the output clock signal vco_ck is started, the triangular wave generation circuit 22 The phase shift amount pi_ssd is fixed. The triangular wave generation circuit 22 continues this state until the maximum value test mode is canceled. The second phase shift amount pi_ssd is added to the first phase shift amount pll_frac to obtain the phase shift amount Δph of the phase selection circuit 6. At this time, the frequency of the output clock signal vco_ck changes as shown in FIG. The modulation operation starts from, for example, the center frequency fc. When the frequency of the output clock signal vco_ck reaches the test frequency that is the maximum value fmax of the modulation frequency range in the second modulation period after the modulation of the output clock signal vco_ck is started, the modulation of the output clock signal vco_ck is stopped. Is done. Thereafter, the frequency of the output clock signal vco_ck is fixed to the test frequency. With the output clock signal vco_ck having the fixed test frequency being output, the frequency can be measured.

  When the maximum value fmax of the modulation frequency range in a certain modulation period and the next modulation period are different, by outputting the output clock signal vco_ck according to both FIG. 15 and FIG. 23, the maximum value fmax of the modulation frequency range in each modulation period Can be tested.

  In FIG. 23, the frequency of the output clock signal vco_ck is fixed to the test frequency that is the maximum value fmax of the modulation frequency range, but is fixed to the minimum value fmin or the center frequency fc of the modulation frequency range as described above. May be. Further, the frequency of the output clock signal vco_ck may be fixed to an arbitrary frequency in the third and subsequent modulation periods after the modulation of the output clock signal vco_ck is started.

  Thereby, in the output clock signal vco_ck having a waveform whose modulation width is not constant, it is possible to accurately test the variation of the maximum value, the variation of the minimum value, and the variation of the center value of the modulation waveform.

  FIG. 25 is a block diagram showing a configuration for testing the spread spectrum clock generation circuit 100 of FIG. The SSCG circuit 100 is connected to the test apparatus 200. The test apparatus 200 generates a reference clock signal ref_ck and inputs the reference clock signal ref_ck to the SSCG circuit 100, and acquires the output clock signal vco_ck from the SSCG circuit 100. Further, the test apparatus 200 generates a control signal Mode and inputs it to the SSCG circuit 100. Accordingly, the test apparatus 200 can test the output clock signal vco_ck of the SSCG circuit 100, and can test the modulation width thereof, for example.

  The SSCG circuit 100 according to the embodiment described above has the following advantageous effects.

  When the frequency of the output clock signal vco_ck reaches a test frequency within the modulation frequency range, the frequency of the output clock signal can be accurately fixed to the test frequency by stopping the modulation operation and fixing the frequency. Thereby, the frequency of the output clock signal vco_ck can be accurately measured. This is advantageous, for example, in an SSCG circuit using a digitally controlled modulation system, or in an SSCG circuit that performs a modulation operation by shifting the phase of a multi-phase clock that constitutes a VCO by digital control.

  Also, the time taken from the start of the modulation operation at the center frequency in the modulation frequency range to the arrival of the test frequency is within one modulation period since the modulation operation is stopped in the middle of the modulation. Therefore, the frequency of the output clock signal vco_ck can be tested in a short time.

  Further, stopping the modulation operation and fixing the frequency can be realized by the triangular wave generation circuit 22 of the phase controller 5, so that a small-scale addition to the circuit of the conventional SSCG circuit is sufficient.

  A spread spectrum clock generation circuit according to an aspect of the present invention has the following configuration.

The spread spectrum clock generation circuit according to the first aspect includes:
In a spread spectrum clock generation circuit that generates an output clock signal modulated within a predetermined modulation frequency range,
When the frequency of the output clock signal reaches a predetermined test frequency within the modulation frequency range, the modulation of the output clock signal is stopped and the frequency of the output clock signal is fixed to the test frequency. And

The spread spectrum clock generation circuit according to the second aspect is the spread spectrum clock generation circuit according to the first aspect,
The test frequency is a maximum value in the modulation frequency range.

A spread spectrum clock generation circuit according to a third aspect is the spread spectrum clock generation circuit according to the first aspect,
The test frequency is a minimum value of the modulation frequency range.

A spread spectrum clock generation circuit according to a fourth aspect is the spread spectrum clock generation circuit according to the first aspect,
The test frequency is a median value of the modulation frequency range.

A spread spectrum clock generation circuit according to a fifth aspect is the spread spectrum clock generation circuit according to the second aspect,
The spread spectrum clock generation circuit includes:
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage in accordance with the phase difference;
Voltage-controlled oscillation means for generating and outputting the output clock signal having a frequency according to the control voltage;
A phase shift clock signal having a rising edge in the selected phase is generated by selecting one of the phases obtained by equally dividing one cycle of the clock of the output clock signal into a predetermined number, and the phase shift clock signal is Phase selection means for sending to the phase comparison means as a feedback signal;
The phase selection means selects the phase shift clock signal to have a length changed by a phase shift amount that fluctuates within a predetermined phase shift amount range from the cycle of the output clock signal. Phase control means for determining the phase of the rising edge of the phase-shifted clock signal and controlling the phase selection means to select the determined phase;
The phase control means fixes the phase shift amount when the phase shift amount reaches a maximum value in the phase shift amount range.

A spread spectrum clock generation circuit according to a sixth aspect is the spread spectrum clock generation circuit according to the third aspect,
The spread spectrum clock generation circuit includes:
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage in accordance with the phase difference;
Voltage-controlled oscillation means for generating and outputting the output clock signal having a frequency according to the control voltage;
A phase shift clock signal having a rising edge in the selected phase is generated by selecting one of the phases obtained by equally dividing one cycle of the clock of the output clock signal into a predetermined number, and the phase shift clock signal is Phase selection means for sending to the phase comparison means as a feedback signal;
The phase selection means selects the phase shift clock signal to have a length changed by a phase shift amount that fluctuates within a predetermined phase shift amount range from the cycle of the output clock signal. Phase control means for determining the phase of the rising edge of the phase-shifted clock signal and controlling the phase selection means to select the determined phase;
The phase control unit fixes the phase shift amount when the phase shift amount reaches a minimum value in the phase shift amount range.

A spread spectrum clock generation circuit according to a seventh aspect is the spread spectrum clock generation circuit according to the fourth aspect,
The spread spectrum clock generation circuit includes:
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage in accordance with the phase difference;
Voltage-controlled oscillation means for generating and outputting the output clock signal having a frequency according to the control voltage;
A phase shift clock signal having a rising edge in the selected phase is generated by selecting one of the phases obtained by equally dividing one cycle of the clock of the output clock signal into a predetermined number, and the phase shift clock signal is Phase selection means for sending to the phase comparison means as a feedback signal;
The phase selection means selects the phase shift clock signal to have a length changed by a phase shift amount that fluctuates within a predetermined phase shift amount range from the cycle of the output clock signal. Phase control means for determining the phase of the rising edge of the phase-shifted clock signal and controlling the phase selection means to select the determined phase;
The phase control means fixes the phase shift amount when the phase shift amount reaches a median value of the phase shift amount range.

A spread spectrum clock generation circuit according to an eighth aspect is the spread spectrum clock generation circuit according to one of the first to seventh aspects,
The output clock signal is modulated to change at a predetermined modulation period within the modulation frequency range;
When the output clock signal reaches the test frequency after a plurality of modulation periods have elapsed since the modulation of the output clock signal has started, the modulation of the output clock signal is stopped and the output clock signal The frequency is fixed to the test frequency.

The spread spectrum clock generation circuit according to the ninth aspect includes
In a spread spectrum clock generation method for generating an output clock signal modulated within a predetermined modulation frequency range by a spread spectrum clock generation circuit,
When the frequency of the output clock signal reaches a predetermined test frequency within the modulation frequency range, the modulation of the output clock signal is stopped and the frequency of the output clock signal is fixed to the test frequency. And

  According to the spread spectrum clock generation circuit according to the first aspect, it is possible to accurately test the modulation width in a short time while suppressing the test cost.

  With the spread spectrum clock generation circuit according to the second aspect, the maximum value of the modulation frequency range can be accurately tested.

  According to the spread spectrum clock generation circuit according to the third aspect, the minimum value of the modulation frequency range can be accurately tested.

  According to the spread spectrum clock generation circuit according to the fourth aspect, the median value of the modulation frequency range can be accurately tested.

  According to the spread spectrum clock generation circuit according to the fifth aspect, since the phase shift amount is fixed at the maximum value of the phase shift amount range, the maximum value of the modulation frequency range can be accurately tested.

  According to the spread spectrum clock generation circuit of the sixth aspect, the phase shift amount is fixed at the minimum value of the phase shift amount range, so that the minimum value of the modulation frequency range can be accurately tested.

  According to the spread spectrum clock generation circuit according to the seventh aspect, since the phase shift amount is fixed by the median value of the phase shift amount range, the median value of the modulation frequency range can be accurately tested.

  According to the spread spectrum clock generation circuit according to the eighth aspect, the output clock signal having a waveform with a non-constant modulation width can accurately test the variation of the maximum value, the variation of the minimum value, and the variation of the center value of the modulation waveform. can do.

  According to the spread spectrum clock generation method of the ninth aspect, it is possible to accurately test the modulation width in a short time while suppressing the test cost.

1 ... Phase frequency comparator,
2 ... Charge pump
3 ... Loop filter,
4 ... Voltage controlled oscillator,
5 ... Phase controller,
6 ... Phase selection circuit,
7 ... frequency divider,
11 ... Input divider,
12 ... Output divider,
21 ... Count value generation circuit,
22 ... Triangular wave generation circuit,
23 ... adder,
24 ... control circuit,
100: Spread spectrum clock generation (SSCG) circuit,
200: Test device.

Japanese Patent No. 4816781 Japanese Patent No. 4819400

Claims (9)

In a spread spectrum clock generation circuit that generates an output clock signal modulated within a predetermined modulation frequency range,
When the frequency of the output clock signal reaches a predetermined test frequency within the modulation frequency range, the modulation of the output clock signal is stopped and the frequency of the output clock signal is fixed to the test frequency. Spread spectrum clock generation circuit.   2. The spread spectrum clock generation circuit according to claim 1, wherein the test frequency is a maximum value in the modulation frequency range.   2. The spread spectrum clock generation circuit according to claim 1, wherein the test frequency is a minimum value of the modulation frequency range.   2. The spread spectrum clock generation circuit according to claim 1, wherein the test frequency is a median value of the modulation frequency range. The spread spectrum clock generation circuit includes:
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage in accordance with the phase difference;
Voltage-controlled oscillation means for generating and outputting the output clock signal having a frequency according to the control voltage;
A phase shift clock signal having a rising edge in the selected phase is generated by selecting one of the phases obtained by equally dividing one cycle of the clock of the output clock signal into a predetermined number, and the phase shift clock signal is Phase selection means for sending to the phase comparison means as a feedback signal;
The phase selection means selects the phase shift clock signal to have a length changed by a phase shift amount that fluctuates within a predetermined phase shift amount range from the cycle of the output clock signal. Phase control means for determining the phase of the rising edge of the phase-shifted clock signal and controlling the phase selection means to select the determined phase;
3. The spread spectrum clock generation circuit according to claim 2, wherein the phase control unit fixes the phase shift amount when the phase shift amount reaches a maximum value in the phase shift amount range. The spread spectrum clock generation circuit includes:
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage in accordance with the phase difference;
Voltage-controlled oscillation means for generating and outputting the output clock signal having a frequency according to the control voltage;
A phase shift clock signal having a rising edge in the selected phase is generated by selecting one of the phases obtained by equally dividing one cycle of the clock of the output clock signal into a predetermined number, and the phase shift clock signal is Phase selection means for sending to the phase comparison means as a feedback signal;
The phase selection means selects the phase shift clock signal to have a length changed by a phase shift amount that fluctuates within a predetermined phase shift amount range from the cycle of the output clock signal. Phase control means for determining the phase of the rising edge of the phase-shifted clock signal and controlling the phase selection means to select the determined phase;
4. The spread spectrum clock generation circuit according to claim 3, wherein the phase control unit fixes the phase shift amount when the phase shift amount reaches a minimum value in the phase shift amount range. The spread spectrum clock generation circuit includes:
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage in accordance with the phase difference;
Voltage-controlled oscillation means for generating and outputting the output clock signal having a frequency according to the control voltage;
A phase shift clock signal having a rising edge in the selected phase is generated by selecting one of the phases obtained by equally dividing one cycle of the clock of the output clock signal into a predetermined number, and the phase shift clock signal is Phase selection means for sending to the phase comparison means as a feedback signal;
The phase selection means selects the phase shift clock signal to have a length changed by a phase shift amount that fluctuates within a predetermined phase shift amount range from the cycle of the output clock signal. Phase control means for determining the phase of the rising edge of the phase-shifted clock signal and controlling the phase selection means to select the determined phase;
5. The spread spectrum clock generation circuit according to claim 4, wherein the phase control means fixes the phase shift amount when the phase shift amount reaches a median value of the phase shift amount range. The output clock signal is modulated to change at a predetermined modulation period within the modulation frequency range;
When the output clock signal reaches the test frequency after a plurality of modulation periods have elapsed since the modulation of the output clock signal has started, the modulation of the output clock signal is stopped and the output clock signal 8. The spread spectrum clock generation circuit according to claim 1, wherein a frequency is fixed to the test frequency. In a spread spectrum clock generation method for generating an output clock signal modulated within a predetermined modulation frequency range by a spread spectrum clock generation circuit,
When the frequency of the output clock signal reaches a predetermined test frequency within the modulation frequency range, the modulation of the output clock signal is stopped and the frequency of the output clock signal is fixed to the test frequency. Spread spectrum clock generation method.

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