JP2017112335A - Semiconductor element manufacturing method - Google Patents

Abstract

[Problem] To provide a method for manufacturing a high-voltage semiconductor element using a thin semiconductor substrate. [Solution] This method for manufacturing a semiconductor element is characterized in that one unit process is composed of a bonding step (a) for bonding a first substrate 1, at least the surface layer of which is made of a single crystal of a first semiconductor material, to a second substrate 2 for suppressing warping of the first substrate 1, a first step (b) for processing the surface of the bonded first substrate 1, a separation step (c) for separating the bonded first substrate 1 and second substrate 2, and a second step (d) for processing the separated first substrate 1, and the unit process is performed multiple times to form a semiconductor element on the first substrate 1. [Selected Figure] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor element. Specifically, the present invention relates to a method for manufacturing a high voltage semiconductor element using a thin semiconductor substrate.

A silicon carbide (hereinafter also referred to as “SiC”) semiconductor substrate having a large band gap is attracting attention as a substrate for a semiconductor element for high voltage applications. FIG. 11 shows a cross-sectional structure of a general vertical structure MOSFET (200) made of SiC. An active layer 220 is formed on the support substrate 210 by epitaxial growth, and a source 201, a drain 202, and a gate 203 are formed in the region of the active layer 220. The gate 203 controls the conduction and interruption of the current between the source 201 and the drain 202. The drain current i during conduction flows between the drain 202 and the drain electrode 204 formed on the bottom surface of the support substrate 210.
The support substrate 210 is a region where current flows in the vertical direction (vertical direction in the figure), and has a low resistivity of 20 mΩ · cm or less. On the other hand, the active layer 220 requires a high voltage withstand voltage, and therefore has a resistivity that is two to three orders of magnitude higher than that of the support substrate 210. Since the semiconductor element using SiC has a large band gap width, the thickness of the active layer 220 can be reduced to about 5 to 10 μm. Since the active layer 220 is formed on the support substrate 210 by epitaxial growth, the crystallinity of the active layer 220 depends on the support substrate 210 as a base. For this reason, the SiC crystal quality of the support substrate 210 is important. The thickness of the support substrate 210 is required to be about 300 μm in the case of a 6-inch substrate in order to prevent cracking when handling the single crystal substrate. Then, after the element is formed on the front surface side of the substrate, the back surface is ground to reduce the thickness to 100 μm or less.

Since SiC is a compound composed of carbon and silicon having different lattice constants, many crystal defects are generated in the element substrate. In particular, since crystal defects are fatal in power device applications, various attempts have been made to reduce crystal defects, but the cost of the device substrate is therefore high. For this reason, it is an issue to achieve both reduction of crystal defects and cost reduction of the support substrate 210 which is the base of the active layer 220 to be epitaxially grown. Further, in the case of the vertical structure as shown in FIG. 11, the support substrate 210 needs to have a low resistivity in order to pass a current in the vertical direction. Therefore, a high concentration of nitrogen is added to the N-type semiconductor. It is said that. In addition, after the element is formed, the resistance of the support substrate layer is further reduced by thinly processing the support substrate 210.
Thus, an expensive single crystal substrate is used as a substrate for a semiconductor element, and the thickness of the single crystal substrate is not increased for the active layer, but is increased for handling the substrate in the element formation process. Has been. Further, after the element is formed, the substrate is processed thinly, and a large part of the single crystal substrate is currently removed by grinding.

  Moreover, as a substrate of a semiconductor element made of SiC, only the surface active layer may be a single crystal. The supporting substrate layer may be monocrystalline, polycrystalline, or amorphous regardless of crystallinity. Conventionally, there is a substrate manufacturing method in which a single crystal active layer and a non-single crystal support substrate layer are bonded. For example, there is a substrate manufacturing method in which amorphous silicon is deposited on a polycrystalline SiC support, the polycrystalline SiC support and a single crystal SiC substrate are joined, and integrated by direct bonding (see Patent Document 1). ). An example in which substrates are bonded by a surface activation method is also disclosed (see Non-Patent Documents 1 and 2).

Special table 2004-503942 Japanese Patent Application Laid-Open No. 2002-280531

S. Essig et al., Fast atom beam-activated n-Si / n-GaAs wafer bonding with high interfacial transparency and electrical conductivity, JOURNAL OF APPLIED PHYSICS 113, 203512 (2013) J.Suda et al., Characterization of 4H-SiC Homoepitaxial Layers Grown on 100-mm-Diameter 4H-SiC / Poly-SiC Bonded Substrates, ICSCRM 2013 by Suda Kyoto University, Author corrected paper: Th-P-62

  As described above, conventionally, in a substrate of a semiconductor device for high voltage use, a thin film layer made of a single crystal is formed as an active layer on a support substrate (support layer) having a certain thickness. The active layer is manufactured by epitaxial growth. Since this support substrate may be a single crystal or a polycrystal, a method of bonding a thin single crystal layer and an inexpensive polycrystalline semiconductor substrate by a bonding technique has been proposed. Any of the methods described in Patent Documents 1 and 2 and Non-Patent Document 1 are methods for reducing the cost of the support substrate. However, a further problem is that it is possible to significantly reduce the cost of the semiconductor substrate by making it possible to form elements in the active layer on the surface layer even if the supporting substrate is thin.

  Conventionally, a thick single crystal SiC substrate is used for handling during processing, and the thickness of the support layer is reduced in order to finally obtain good device characteristics. However, this has a problem that an expensive single crystal substrate is not fully utilized. Considering that the support layer is thinned by grinding after element formation, it is possible to eliminate the waste part of the expensive single crystal substrate by making it possible to use a thin substrate as an element substrate. For example, in the case of a substrate for an SiC element, since the material has a large band gap width, the thickness of the substrate is sufficient for the thickness of the epitaxial layer portion of the surface layer even for a high voltage element. It should be noted. However, there is a problem that a thin substrate is easy to bend and warpage increases. Conventionally, there have been no reports of practical use of elements by using such a thin substrate that is easily bent or a substrate having a large warp.

  The present invention has been made in view of the above situation, and an object of the present invention is to provide a method for manufacturing a semiconductor device having a high withstand voltage using a thin semiconductor substrate.

The present invention is as follows.
1. A bonding step of bonding a first substrate having at least a surface layer made of a single crystal of a first semiconductor material and a second substrate for suppressing warpage of the first substrate; and a surface of the bonded first substrate One unit process from a first process for processing the first substrate, a separation process for separating the bonded first substrate and the second substrate, and a second process for processing the separated first substrate. Is formed, and the semiconductor element is formed on the first substrate by performing the unit process a plurality of times.
2. In the first unit process, in the first process, a semiconductor impurity material is ion-implanted into a predetermined region of the first substrate, and in the second process, the first substrate is heat-treated at a first temperature, In the second unit process, in the first process, a predetermined pattern of an insulating film is formed on the surface of the first substrate, and in the second process, the first substrate is moved to a second temperature lower than the first temperature. In the third unit process, a predetermined pattern is formed on the surface of the first substrate with a metal in the third unit process. The manufacturing method of the semiconductor element of description.
3. In the third unit step, an electrode is formed from a metal on the surface of the first substrate in the first step, the electrode portion is annealed in the second step, and in the fourth unit step, the electrode is annealed. In the first step, element wiring is formed of metal on the surface of the first substrate. The manufacturing method of the semiconductor element of description.
4). In the third unit step, an electrode is formed on the surface of the first substrate with a metal in the first step, and silicidation processing of the electrode portion is performed. In the second step, annealing treatment of the electrode portion is performed. In the fourth unit process, in the first process, element wiring is formed of metal on the surface of the first substrate. The manufacturing method of the semiconductor element of description.
5). In the first unit process, in the first process, a semiconductor impurity material is ion-implanted into a predetermined region of the first substrate, and in the second process, the first substrate is heat-treated at a first temperature, In the unit process of 2, in the first process, an electrode is formed with a metal after a predetermined pattern of an insulating film is formed on the surface of the first substrate, and in the second process, the first substrate is replaced with the first substrate. Heat treatment at a second temperature equal to or lower than the temperature, and in the fourth unit process, in the first process, an element wiring is formed on the surface of the first substrate with a metal. The manufacturing method of the semiconductor element of description.
6). After each of the unit processes, in the fifth unit process, the upper surface on which the element wiring of the first substrate is formed and the second substrate are bonded in the bonding process, and the first substrate is bonded in the first process. An electrode thin film made of a first metal is formed on the bottom surface opposite to the upper surface of the substrate, and the electrode thin film portion is silicided in the second step. To 5. The manufacturing method of the semiconductor element in any one of.
7). Further, in the sixth unit process, the upper surface on which the element wiring of the first substrate is formed and the second substrate are bonded in the bonding process, and the upper surface of the first substrate is bonded in the first process. 5. An electrode thick film made of a second metal is formed on the bottom surface on the opposite side, and the electrode thick film is annealed in the second step. The manufacturing method of the semiconductor element of description.
8). The first semiconductor material is one of SiC, GaN, and gallium oxide. To 7. The manufacturing method of the semiconductor element in any one of.

According to the method for manufacturing a semiconductor element of the present invention, even if at least the surface layer of the first substrate made of a single crystal of the first semiconductor material is thin and warps or bends, By being joined, warping and bending are suppressed and flattened. Thereby, in the first step, the surface processing of the first substrate can be performed using a general-purpose photolithography apparatus or the like. That is, the bonded substrate obtained by bonding the second substrate and the first substrate can be processed by a semiconductor manufacturing process similar to that of a semiconductor substrate having no warping or bending.
In particular, since semiconductors such as SiC suitable for high power applications have a small impurity diffusion coefficient, doping by thermal diffusion is difficult for both N-type impurities and P-type impurities. Further, self-alignment processing by thermal diffusion as in the Si semiconductor manufacturing process is impossible. Therefore, in order to determine the addition position of the N-type impurity and the P-type impurity, a high-precision exposure machine such as a stepper is required, and it is required to suppress the warp or bend of the semiconductor substrate to about 20 μm or less. In the present invention, since the warping and bending can be reduced by the bonded substrate, the thickness of the first substrate is not limited by the size of the warping or bending itself, and may be the minimum necessary. This makes it possible to reduce the cost of the high voltage semiconductor element by thinning the first substrate made of expensive single crystal or including the single crystal layer.

  Moreover, the 1st board | substrate should just be a board | substrate which the surface layer consists of a single crystal of the 1st semiconductor material. Therefore, not only a thin single crystal substrate but also a substrate in which a single crystal thin layer is mounted on a polycrystalline substrate or an amorphous substrate can be used as the first substrate. By using such a polycrystalline substrate or an amorphous substrate as a thin substrate, a low-cost support substrate can be obtained. For example, a SiC substrate having a thickness of about 350 μm is conventionally used as a semiconductor substrate for high power applications, and after forming a semiconductor element, it is polished to a thickness of about 100 μm, and then an electrode is processed on the back surface of the substrate. . According to the present invention, a semiconductor element can be formed on a thin first substrate having a thickness of about 100 μm, so that not only the cost of the semiconductor substrate can be reduced, but also a thinning process after the formation of the semiconductor element is unnecessary. It becomes.

  Bonding and separation of the first substrate and the second substrate can be easily performed by a known method. For example, if a substrate that transmits light, such as a sapphire substrate, is used as the second substrate, it can be easily bonded and separated by ultraviolet rays, heat, etc., using an ultraviolet curable resin or an ultraviolet peelable adhesive as the bonding material. Thus, the sapphire substrate can be used repeatedly.

  Since the second step is performed after the first substrate 1 and the second substrate 2 are separated, the first substrate 1 is warped or bent, and processing such as photolithography that requires flatness of the substrate is performed. It is difficult. However, in the second step, heat treatment or chemical treatment at a high temperature that is not restricted by the bonding material can be performed, and impurity activation treatment, oxide film or metal annealing treatment, and the like are possible.

  As described above, since bonding and separation between the thin first substrate including the single crystal layer and the second substrate are established in a simple process, optimum processing is performed on the first substrate in the bonded state and the separated state, respectively. It can be performed. Therefore, despite the additional steps of bonding and separation of the substrates, it is possible to manufacture a high breakdown voltage semiconductor element using a thin semiconductor substrate at a significantly lower cost than before.

Schematic side view and top view showing examples of first substrate and second substrate Schematic sectional view showing a configuration example of the first substrate Schematic cross-sectional view for explaining one unit process Schematic sectional view for explaining the first and second unit steps Schematic sectional view for explaining the third unit process Schematic sectional view for explaining the fourth unit process Schematic sectional view for explaining the fifth unit process Schematic sectional view for explaining the sixth unit process Schematic sectional view for explaining a modification of the fifth unit process Typical sectional drawing for demonstrating the modification of a 4th unit process Schematic sectional view showing a vertical semiconductor device (MOSFET)

In the method for manufacturing a semiconductor device of the present invention, a single unit process composed of a plurality of small processes is performed a plurality of times, so that a semiconductor element ( (See FIG. 11). The plurality of small steps include a bonding step of bonding the first substrate and the second substrate for suppressing warpage of the first substrate, a first step of processing a surface of the bonded first substrate, and a bonded first step. It comprises a separation step for separating the first substrate and the second substrate, and a second step for processing the separated first substrate.
In one unit process, the joining process, the first process, the separation process, and the second process are performed in this order. Depending on the purpose of each unit process, the content of the processing performed in the first process and the second process is arbitrary, and includes the case where any small process (for example, the second process) is omitted.

Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic side view and top view showing examples of the first substrate 1 and the second substrate 2. FIG. 2 is a cross-sectional view for explaining the configuration of the first substrate 1 in an unprocessed state.
The first substrate 1 may be a substrate whose surface layer is made of a single crystal of the first semiconductor material. As the first substrate 1, a thin single crystal substrate made of the first semiconductor material can be used. Further, as the first substrate 1, a substrate in which a single crystal thin layer made of the first semiconductor material is mounted on a polycrystalline substrate or an amorphous substrate can be used. For example, as shown in FIG. 2, in the first substrate 1, a single crystal thin film layer 120 serving as an active layer is formed on a support layer 110 regardless of crystallinity. The support layer 110 may be a single crystal substrate, or may be a polycrystalline or amorphous substrate. The polycrystalline substrate or the amorphous substrate used as the support layer 110 can be used as a low-cost support substrate by making the substrate as thin as necessary.
The first semiconductor material is not particularly limited, and examples thereof include SiC, GaN, and gallium oxide.

  The first substrate 1 is preferably a disk-shaped or columnar substrate as shown in FIG. The size is not limited, and for example, a substrate having an outer diameter of 6 inches (about 150 mm) can be used. In the first substrate 1, the single crystal layer 120 having a thin surface layer only needs to have a thickness (about 5 to 10 μm in the case of SiC) necessary for at least an active layer of a semiconductor element. The thickness of the entire first substrate 1 is not limited and may be a thickness necessary for the final semiconductor element (for example, about 100 μm). Such a thin substrate has a problem that it is easy to bend and warpage is increased. However, since the processing of the surface of the first substrate 1 can be performed in a state of being bonded to the second substrate 2 by the manufacturing method of the present invention, the bending and warping of the first substrate 1 itself does not cause a problem.

The second substrate 2 is a substrate for suppressing bending and warping of the thin first substrate 1 by bonding to the first substrate 1. The material of the second substrate 2 is not particularly limited. It is preferable to use a sapphire substrate or the like that transmits light as the second substrate 2 because it can be easily joined to and separated from the first substrate 1 and can be used repeatedly.
The second substrate 2 is also preferably disk-shaped or cylindrical as shown in FIG. Further, it is preferable that the outer diameter of the second substrate 2 is slightly larger than the outer diameter of the first substrate 1 in order to facilitate handling during bonding and separation with the first substrate 1. If the second substrate 2 is in the state of a bonded substrate bonded to the first substrate 1, it can suppress bending and warping to the extent that the surface processing of the first substrate 1 can be performed using a general-purpose photolithography apparatus. Good (for example, it is sufficient if the warpage can be suppressed to 20 μm or less).

In the method for manufacturing a semiconductor element, a semiconductor element is formed on the first substrate 1 by performing one unit process including the plurality of small processes (hereinafter simply referred to as “process”) a plurality of times.
FIG. 3 is a cross-sectional view for explaining one unit process. In the present embodiment, the case where the first substrate 1 is made of SiC and a thin single crystal layer 120 is formed on a support layer 110 made of SiC polycrystal will be described as an example (see FIG. 2). The case where a sapphire substrate is used as the second substrate 2 will be described as an example. The first substrate 1 and the second substrate 2 are both disk-shaped or cylindrical, and the outer diameter of the second substrate 2 is slightly larger than that of the first substrate 1. For example, the first substrate 1 can have an outer diameter of 6 inches (about 150 mm) and a thickness of about 100 μm, and the second substrate 2 can have an outer diameter of about 180 mm and a thickness of about 500 μm.

(Joining process)
In the bonding step, the first substrate 1 and the second substrate 2 are bonded using a bonding material.
FIG. 3A shows a substrate (bonded substrate) bonded by the bonding process. The first substrate 1 and the second substrate 2 can be bonded by a known method. When the 2nd board | substrate 2 is a sapphire board | substrate, it is possible to join by using an ultraviolet curable resin as a joining material and irradiating a joining surface with an ultraviolet-ray. It is also possible to use an adhesive that can be peeled off by ultraviolet rays as the bonding material, and to perform bonding by heating. Since the bonded substrates are supported by the cypher substrate, there is no bending and little warping.
Specifically, in the bonding step, an ultraviolet curable resin film is formed on the sapphire substrate 2 with a uniform thickness, and the first substrate 1 is bonded in a semi-dry state. Thereafter, by irradiating ultraviolet rays from the cypher substrate 2 side, curing proceeds and both substrates can be joined. Moreover, it can be hardened by using the adhesive agent which can be peeled with an ultraviolet-ray, heating the sapphire substrate 2 whole to 100 degreeC, after bonding the 1st board | substrate 1 together. Since an adhesive is used, the process which becomes 400 degreeC or more in the following 1st process cannot be performed.

(First step)
Next, in the first step, surface processing of the first substrate 1 bonded to the second substrate 2 is performed. As long as the surface processing performed here can maintain the bonding between the first substrate 1 and the second substrate 2, the type and number of times are not limited. The surface processing in the first step needs to be performed in a temperature range that does not affect the bonding of the substrates. For this reason, in the first step, processing that can be performed at a relatively low temperature (for example, 400 ° C. or lower) can be appropriately performed according to the purpose of the unit step. Examples of processing that can be performed at a relatively low temperature include generation of a metal film and an oxide film, photolithography, etching, impurity ion implantation, and trench formation. In the first step, a plurality of types of processing may be performed, or one type of processing may be performed a plurality of times.
FIG. 3B illustrates an example of the bonded substrate that has undergone the first step. In this example, in the first step, one or more kinds of semiconductor impurity materials are ion-implanted in order to form a P-type layer in the surface layer of the N-type first substrate 1, and the source region 31 and the drain region 32 of the MOSFET element are formed. Is formed. In an element having a wide band gap such as SiC, it is difficult to form an impurity profile by thermal diffusion. For this reason, it is necessary to create an impurity profile by ion implantation as in this example. In the case of forming an isolation structure element using a trench, the trench can be processed before and after the ion implantation.

(Separation process)
In the separation step, the bonded first substrate 1 and second substrate 2 are separated. Both substrates can be separated by a known method. When the second substrate 2 is a sapphire substrate and an ultraviolet curable resin is used as a bonding material, the two substrates can be separated by heating to about 400 ° C. In addition, when an adhesive that can be peeled off by ultraviolet rays is used as a bonding material, it can be separated by irradiating the bonding surfaces with ultraviolet rays. In either case, the separated sapphire substrate 2 can be repeatedly used after being washed.
FIG. 3C shows the first substrate 1 and the second substrate 2 separated in the separation step.

(Second step)
In the second step, the separated first substrate 1 is processed. Since the first substrate 1 is separated from the second substrate 2, warping and bending occur, and it is difficult to perform processing using photolithography or the like that requires flatness of the substrate. On the other hand, in the second step, heat treatment or chemical treatment at a high temperature that is not limited by the bonding material can be performed. Examples of such processing include an impurity activation process performed at about 1700 ° C., a CVD oxide film annealing process, a gate oxide film thermal oxidation process, and a metal film annealing process.
FIG. 3D shows an example of the first substrate 1 that has undergone the second step. In this example, in the second step, heat treatment at 1700 ° C. is performed to activate the impurities. In the second step, the first substrate 1 is subjected to high-temperature heat treatment in a state where it is mounted on a jig or the like, and thus warpage or bending of the first substrate 1 is allowed.

The manufacturing method of the semiconductor device according to the present embodiment includes the bonding process, the first process, the separation process, and the second process described above as one unit (unit process), and the unit process is repeatedly performed. A semiconductor element is formed on one substrate. The contents of the processing (first process, second process) performed in each unit process are selected according to the purpose of the unit process.
Each unit process is referred to as a first unit process, a second unit process, a third unit process, or the like. In the following, the small steps are (a) joining step, (b) first step, (c) separation step, and (d) second step, and in the drawings, each step is denoted by the unit step number and the small step number. Represents. For example, FIG. 2B shows the first process of the second unit process, and FIG. 3D shows the second process of the third unit process.

(First unit process)
FIG. 4 illustrates an example of a first unit process for forming the source region 31 and the drain region 32 on the surface layer of the first substrate 1 shown in FIG. 2, and a second unit process for forming an oxide film thereafter. FIG. The first unit process is the same as the process illustrated in FIG. 3, and the joining process and the separation process are omitted.
In the first step shown in FIG. 1B, a semiconductor impurity material is ion-implanted into a predetermined region of the first substrate 1 to form a P well, an N-type layer, a P-type layer, and the like. First, a P-well pattern is formed by photolithography (that is, application of a photoresist, drying, and exposure using a mask). Then, a P well layer is formed by ion implantation of impurities. Similarly, ion implantation is performed for the N-type layer and the P-type layer. In the case of forming a trench type element, a trench etching pattern can be formed and processed before or during the formation of these impurity layers. In this example, the source region 31 and the drain region 32 of the MOSFET element are formed on the surface layer of the first substrate 1.
In the second step shown in FIG. 1D, the implanted impurity layer is activated by performing heat treatment at a high temperature (first temperature). Since the impurity layer can be activated in a lump, heat treatment is not required for each ion implantation, and the process can be simplified. For example, in the second step, the first substrate separated from the second substrate is horizontally arranged in a vertical furnace using a jig and tool and annealed at a high temperature of 1700 ° C. for 30 minutes. As a result, activation of the P-well, the P-type layer, the N-type layer, etc. can be performed simultaneously. The first substrate processed in the first unit process is referred to as the first substrate 11.

(Second unit process)
FIG. 4 (2a) shows the joining process in the second unit process, and the first substrate 11 and the second substrate 2 that have undergone the first unit process are joined again. The second substrate 2 does not have to be the same as the second substrate 2 used in the first unit process (the same applies to the following).
FIG. 2B shows the first step in the second unit step. First, an oxide film (silicon oxide film) having a required thickness is formed on the surface of the first substrate 11 by chemical vapor deposition (CVD) performed at a low temperature. Then, after processing the shape by photolithography and etching, the photoresist is removed. As a result, the oxide film in the gate 33 portion between the drain and the source is removed, and the field oxide film 41 is formed. Further, the gate oxide film portion 42 is formed. Thereafter, the first substrate 11 is separated from the second substrate 2 in the separation step.
FIG. 2D shows the second step in the second unit step. In this step, the oxide film on the first substrate 11 is heat-treated at a high temperature (second temperature that is equal to or lower than the first temperature). In this example, the field oxide film 41 is annealed by heating, and a thermal oxide film is grown on the portion where the gate oxide film portion 42 is formed by CVD under high temperature, and the gate oxide film 43 is formed on the gate 33 portion. Is formed. The heat treatment is performed at 1000 ° C. for 30 minutes to double the annealing of the field oxide film 41 and the generation of the gate oxide film 43. Thereby, the gate oxide film 43 having a thickness of 50 nm can be formed. In semiconductor devices, the quality of the gate oxide film is extremely important, and it is necessary to form a dense film at a high temperature. The first substrate processed by the above second unit process is referred to as a first substrate 12.

(Third unit process)
FIG. 5 is a cross-sectional view for explaining an example of a third unit process for forming a predetermined pattern with metal on the surface of the first substrate 12 after the second unit process.
FIG. 3A shows a joining process in the third unit process, and the first substrate 12 and the second substrate 2 that have undergone the second unit process are joined together.
FIG. 3B shows the first step in the third unit step. The element control portion on the surface of the first substrate 12 is opened by photolithography and etching, and a first metal (for example, nickel) serving as a barrier metal is deposited on the entire surface. Then, the electrode 51 can be formed only in the element electrode portion by processing into a predetermined pattern by photolithography and etching. In this state, it is also possible to perform the silicidation process of the contract part by heating in such a short time that the temperature of the substrate bonding part does not rise. Thereafter, the first substrate 12 is separated from the second substrate 2 in the separation step.
FIG. 3D shows the second step in the third unit step. In this example, the electrode 51 is metalized by raising the temperature in a lamp annealing furnace for a short time (third temperature which is equal to or lower than the second temperature). The nickel metallization process is performed at a high temperature of 1000 ° C. for several seconds. The first substrate processed by the above third unit process is referred to as a first substrate 13.

  In the second step of the third unit step, the electrode 51 was heat-treated by short-time lamp annealing or the like as the heat treatment of the first substrate 12. If this heat treatment temperature is approximately the same as the temperature of the heat treatment in the second step (see FIG. 4 (2d)) in the second unit step, the series of contents of the third unit step is changed in the second unit step. Is possible. That is, in the first step of the second unit step, the field oxide film 41 is formed, and further, a first metal (for example, nickel) serving as a barrier metal is vapor-deposited in a state where the element control portion is opened. The electrode 51 can be formed only on the element electrode portion by photoetching. In the second step, the electrode 51 can be metalized. If it does in this way, the objective of the 3rd unit process will be achieved by the 2nd unit process. Therefore, when the heat treatment in the second unit process and the heat treatment in the third unit process are performed at the same temperature (the second temperature), the contents of the third unit process are merged with the second unit process. The third unit process can be omitted.

(4th unit process)
FIG. 6 is a cross-sectional view for explaining an example of a fourth unit process for forming an element wiring having a predetermined pattern after the third unit process. In the joining step in the fourth unit step, the first substrate 13 and the second substrate 2 that have undergone the third unit step are joined.
FIG. 4B shows the first step in the fourth unit step. In this step, first, the natural oxide film is removed by etching to ensure the opening of the electrode portion. Then, a second metal (for example, aluminum) film is vapor-deposited on the surface of the first substrate 13, and the element wiring 52 is formed by performing shape processing. A protective film such as PIQ is formed thereon, and a bonding portion that becomes a metal surface for bonding is opened by photolithography. Thereafter, the first substrate 13 is separated from the second substrate 2 in the separation step.
FIG. 4D shows the second step in the fourth unit step. In this step, annealing of the second metal for forming the element wiring 52 (fourth temperature that is equal to or lower than the second temperature) can be performed. When the process is not required, the process may be shifted to the next unit process without performing any particular processing in the second process. The first substrate processed by the fourth unit process as described above is referred to as a first substrate 14.

Up to the fourth unit process, the processing of the active layer side surface (upper surface) of the target semiconductor element is completed. In the following fifth and sixth unit processes, surface processing on the bottom surface (opposite surface to the active layer) side of the semiconductor element is performed.
(5th unit process)
FIG. 7 is a cross-sectional view for explaining an example of a fifth unit process for forming an electrode thin film on the bottom surface side of the semiconductor element.
FIG. 7 (5 a) shows a bonding process in the fifth unit process. The active layer side surface (upper surface) of the first substrate 14 and the second substrate 2 that have undergone the fourth unit process are bonded to each other.
FIG. 5B shows the first step in the fifth unit step. In this step, the electrode thin film 61 is formed by polishing the bottom surface side of the first substrate 14 by about 5 μm and then depositing a metal (for example, the first metal). Thereafter, the first substrate 14 is separated from the second substrate 2 in the separation step.
FIG. 5D shows the second step in the fifth unit step. Since the active layer side is completed, the temperature is limited. For this reason, the electrode thin film 61 is annealed at a relatively low temperature (fifth temperature lower than the fourth temperature, eg, about 400 ° C.). The first substrate processed by the above fifth unit process is referred to as a first substrate 15.

(Sixth unit process)
FIG. 8 is a cross-sectional view for explaining a sixth unit process for further forming an electrode thick film on the bottom surface side of the semiconductor element.
FIG. 8 (6 a) shows a bonding process in the sixth unit process. The active layer side surface of the first substrate 15 and the second substrate 2 that have undergone the fifth unit process are bonded to each other.
FIG. 6B shows the first step in the sixth unit step. In this step, an electrode thick film 62 such as nickel or copper is formed on the electrode thin film 61 on the bottom surface side of the first substrate 15. The electrode thick film 62 can be about 30 μm thick by electroless plating. Thereafter, the first substrate 15 is separated from the second substrate 2 in the separation step. Bending and warping of the separated first substrate 15 are reduced by the electrode thick film 62.
FIG. 6D shows the second step in the sixth unit step. In this step, the electrode thick film 62 can be annealed at a temperature of about 400 ° C. The target semiconductor element 16 is completed by the first to sixth unit processes described above.

  In the step of processing the bottom surface side of the first substrate 1, it is preferable to perform annealing at a higher temperature in order to further reduce the resistance of the electrode thin film 61 part. Further, if the contents of the unit process are rearranged, silicidation of the electrode thin film 61 part on the bottom surface side can be performed simultaneously with silicidation of the electrode 51 part on the upper surface side of the first substrate 1 (FIG. 5 (3d)). It is. An example of this will be described below.

FIG. 9 shows the formation of the electrode thin film 61 on the bottom surface side in the fifth unit process shown in FIG. 7 immediately after the formation of the electrode 51 on the upper surface side in the third unit process. It is a figure explaining the case where silicidation of the electrode part of is performed simultaneously. The unit process number is 5 ′.
The first substrate 12 ′ shown in FIG. 5 (a) is a substrate separated from the second substrate 2 in the separation step after the upper electrode 51 is formed in the first step in the third unit step. . That is, the first substrate 12 ′ is not yet silicided by heat treatment. As shown in the figure, the upper surface side of the first substrate 12 ′ in that state and the second substrate 2 are bonded.
FIG. 5 (b) shows the first step in the unit step 5 ′. In this step, the electrode thin film 61 is formed of the first metal on the bottom surface of the first substrate 12 ′. Thereafter, the first substrate 12 ′ is separated from the second substrate 2 in the separation step.
FIG. 5 (d) shows the second step in the unit step 5 ′. In this step, for example, the electrode 51 and the electrode thin film 61 on the bottom side are annealed at the third temperature (about 1000 ° C.). This heat treatment is performed in a short time by lamp annealing or the like. The first substrate processed by the above unit process 5 ′ is represented as a first substrate 15 ′.

Subsequently, a wiring metal is formed on the upper surface of the first substrate 15 ′. The unit process number is 4 ′. For this reason, in the joining step of this unit step, the bottom surface of the first substrate 15 ′ and the second substrate 2 are joined.
FIG. 10 (4′b) represents the first step in the unit step 4 ′. In this step, the element wiring 52 is formed by forming a metal film on the surface of the first substrate 15 ′ and performing shape processing. Thereafter, the first substrate 15 ′ is separated from the second substrate 2 in the separation step.
FIG. 4 (d) shows the second step in the unit step 4 ′. In this step, for example, a metal annealing process for forming the element wiring 52 is performed at the fourth temperature. The first substrate processed by the above unit process 4 ′ is referred to as a first substrate 15 ″.
Thereafter, a thick metal film 62 can be formed on the bottom surface side of the first substrate 15 ''. The process is the same as the sixth unit process (see FIGS. 8 (6a)-(6d)). Thus, the target semiconductor element 16 is completed.

  Although the case where the first semiconductor material is SiC has been described in the above embodiment, the same applies to the case where the first semiconductor material is GaN, gallium oxide, gallium oxide, or the like.

  The present invention is not limited to the embodiments described in detail above, and various modifications or changes can be made within the scope of the claims of the present invention.

  Power-based compound semiconductor elements using SiC and the like are becoming increasingly important in vehicles with the spread of hybrid cars and electric cars. In addition, the role of power-based compound semiconductor devices becomes important for home appliance control and energy management with the spread of smart grids at home. According to the present invention, the amount of SiC single crystal, which is an expensive material, can be greatly reduced, and an inexpensive SiC semiconductor element can be manufactured.

1, 11, 12, 12 ′, 13, 14, 15, 15 ′, 16; first substrate (SiC substrate), 2; second substrate (sapphire substrate), 31; source, 32; drain, 33; gate, 41; Field oxide film, 42; Gate oxide film portion, 43; Gate oxide film, 51; Electrode, 52; Element wiring, 61; Electrode thin film on the bottom surface side, 62; Electrode thick film on the bottom surface side, 110, 210; Layers, 120, 220; active layers (single crystal layers).

Claims (8)

A bonding step of bonding a first substrate having at least a surface layer made of a single crystal of a first semiconductor material and a second substrate for suppressing warpage of the first substrate;
A first step of processing a surface of the bonded first substrate;
A separation step of separating the bonded first substrate and the second substrate;
A second step of processing the separated first substrate;
One unit process consists of
A method of manufacturing a semiconductor element, wherein a semiconductor element is formed on the first substrate by performing the unit process a plurality of times. In the first unit process,
In the first step, a semiconductor impurity material is ion-implanted into a predetermined region of the first substrate,
In the second step, the first substrate is heat-treated at a first temperature,
In the second unit process,
In the first step, a predetermined pattern of an insulating film is formed on the surface of the first substrate,
In the second step, the first substrate is heat-treated at a second temperature lower than the first temperature,
In the third unit process,
In the first step, a predetermined pattern is formed of metal on the surface of the first substrate.
A method for manufacturing a semiconductor device according to claim 1. The third unit process includes
Forming an electrode with a metal on the surface of the first substrate in the first step;
In the second step, the electrode part is annealed,
In the fourth unit process,
In the first step, element wiring is formed of metal on the surface of the first substrate.
A method for manufacturing a semiconductor device according to claim 2. The third unit process includes
In the first step, an electrode is formed from a metal on the surface of the first substrate and silicidation of the electrode portion is performed.
In the second step, the electrode part is annealed,
In the fourth unit process,
In the first step, element wiring is formed of metal on the surface of the first substrate.
A method for manufacturing a semiconductor device according to claim 2. In the first unit process,
In the first step, a semiconductor impurity material is ion-implanted into a predetermined region of the first substrate,
In the second step, the first substrate is heat-treated at a first temperature,
In the second unit process,
In the first step, an electrode is formed of metal after a predetermined pattern of an insulating film is formed on the surface of the first substrate,
In the second step, the first substrate is heat-treated at a second temperature lower than the first temperature,
In the fourth unit process,
In the first step, element wiring is formed of metal on the surface of the first substrate.
A method for manufacturing a semiconductor device according to claim 1. After each unit process, in the fifth unit process,
In the bonding step, the upper surface on which the element wiring of the first substrate is formed and the second substrate are bonded,
In the first step, an electrode thin film made of a first metal is formed on the bottom surface of the first substrate opposite to the top surface;
In the second step, silicidation of the electrode thin film portion is performed.
A method for manufacturing a semiconductor device according to claim 3. Furthermore, in the sixth unit process,
In the bonding step, the upper surface on which the element wiring of the first substrate is formed and the second substrate are bonded,
In the first step, an electrode thick film made of a second metal is formed on the bottom surface of the first substrate opposite to the top surface;
In the second step, the electrode thick film is annealed.
A method for manufacturing a semiconductor device according to claim 6.   The method of manufacturing a semiconductor element according to claim 1, wherein the first semiconductor material is one of SiC, GaN, and gallium oxide.

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