JP2017108321A - Solid-state imaging device - Google Patents

Abstract

A solid-state imaging device that reduces the phase shift of a clock signal is provided. Pixels 1 arranged in N rows×M columns (N is an integer of 1 or more and M is an integer of 2 or more), and pixel signals provided corresponding to the columns of pixels and output from the pixels. , a reference voltage and a comparator 6 for outputting a comparison signal; a clock signal generator 8 connected to a plurality of clock signal lines for outputting a clock signal; a first clock signal; A first latch circuit 10a to which a first detection signal based on a clock signal generator is input and a first clock signal line having a first length is connected from a clock signal generator; A second latch circuit 10b connected to the first clock signal line having a second length longer than the first length from the device, and the first clock signal between the first latch circuit and the second latch circuit. and an adjustment circuit 11 connected to the signal line. [Selection drawing] Fig. 1

Description

  This embodiment relates to a solid-state imaging device.

In general, a solid-state imaging device converts an analog pixel signal output from a pixel into a digital pixel signal and transfers it to a signal processing circuit. In the solid-state imaging device, the analog pixel signal is read out for each row of pixels. The output analog pixel signal is supplied to a comparator arranged for each pixel column. The analog pixel signal is converted into a digital signal by measuring the comparison time with the reference voltage by the clock signal output from the counter. However, even in the same row of pixels, a phase shift of the clock signal occurs in a column far from the counter.

JP 2009-130827 A

  The present embodiment provides a solid-state imaging device that can reduce the phase shift of a clock signal.

The solid-state imaging device according to the embodiment is provided corresponding to pixels arranged in N rows × M columns (N is an integer of 1 or more and M is an integer of 2 or more) and the columns of pixels, and is output from the pixels A comparator that compares a pixel signal with a reference voltage and outputs a comparison signal; a clock signal generator that outputs a clock signal connected to a plurality of clock signal lines; a first clock signal; and a first comparison signal The first detection signal based on the first latch circuit is input, the first clock signal line from the clock signal generator is connected with the first length, and the first latch circuit is connected to the first latch circuit to generate the clock signal. A second latch circuit connected to the first clock signal line having a second length longer than the first length from the device;
And an adjustment circuit connected to the first clock signal line between the first latch circuit and the second latch circuit.

FIG. 2 is a schematic circuit diagram illustrating a part of the configuration of the solid-state imaging device according to the first embodiment. 6 is a timing chart showing the operation of the solid-state imaging device according to the first embodiment. (A) is a timing chart which shows operation | movement in the position close | similar to a counter among the solid-state imaging devices which concern on 1st Embodiment. (B) is a timing chart showing an operation at a position far from the counter in the solid-state imaging device according to the first embodiment. (C) is a timing chart showing an operation via a delay circuit at a position far from the counter in the solid-state imaging device according to the first embodiment. FIG. 6 is a schematic circuit diagram showing a part of a configuration of a solid-state imaging apparatus according to a second embodiment.

Hereinafter, a first embodiment will be described with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected about the same component, and detailed description is abbreviate | omitted suitably.

(First embodiment)
A solid-state imaging device according to the first embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a schematic circuit diagram illustrating a part of the configuration of the solid-state imaging device according to the first embodiment. FIG. 2 is a timing chart showing the operation of the solid-state imaging device according to the first embodiment. FIG. 3A is a timing chart illustrating an operation at a position near the counter in the solid-state imaging device according to the first embodiment.
(B) is a timing chart showing an operation at a position far from the counter in the solid-state imaging device according to the first embodiment. (C) is a timing chart showing an operation via a delay circuit at a position far from the counter in the solid-state imaging device according to the first embodiment.

The solid-state imaging device according to the first embodiment outputs a pixel region 2 in which pixels 1 including photoelectric conversion elements are arranged in a matrix, a vertical scanning circuit 3 that scans the pixel 1 in the vertical direction, and the pixel 1. Vertical signal line 4 for reading out a pixel signal, reference voltage supply unit 5, comparator 6, edge detection circuit 7, clock signal generator 8, latch unit 9, and latch circuit 10 included in latch unit 9, adjustment A circuit 11 and a timing generator 12 are included.

In the pixel area 2, the pixels 1 are arranged in a matrix. In the first embodiment, description will be made assuming that the pixels 1 are arranged in N rows × M columns (N is an integer of 1 or more and M is an integer of 2 or more) in the pixel region 2. In the first embodiment, a description will be given using the first pixel 1a and the second pixel 1b provided in the same row as the first pixel 1a. For example, the first pixel 1a is arranged in the m-th column, and the second pixel 1b is arranged in the m + 1-th column. The pixel 1 includes a photodiode as a photoelectric conversion element and a transistor. The photodiode photoelectrically converts incident light and accumulates electric charges according to the amount of light. Transistors and photodiodes are not shown.

The transistor includes a transfer transistor that accumulates charge in the photodiode and transfers the charge to the floating diffusion, a reset transistor that resets the floating diffusion to a predetermined voltage, an amplification transistor that outputs a potential according to the voltage of the floating diffusion, and a selection signal And a selection transistor that outputs the signal transmitted by the amplification transistor to the vertical signal line 4. Here, the description has been given on the assumption that the selection transistor is included, but the present invention can be implemented even if the pixel signal is output from the amplification transistor to the vertical signal line 4 without including the selection transistor. Note that a detailed description of the transistor is omitted.

The first pixel 1a is connected to the first vertical signal line 4a. One end of the first vertical signal line 4a is connected to a first comparator 6a arranged for each pixel column. As a result, the analog pixel signal output from the first pixel 1a is input to the first comparator 6a via the first vertical signal line 4a.

The second pixel 1b is connected to the second vertical signal line 4b. One end of the second vertical signal line 4b is connected to a second comparator 6b arranged for each pixel column. As a result, the analog pixel signal output from the second pixel 1b is input to the second comparator 6b via the second vertical signal line 4b.

The vertical scanning circuit 3 is connected to the pixel 1 in the pixel region 2. The vertical scanning circuit 3 outputs a transfer signal to the transfer transistor included in the pixel 1, outputs a reset signal to the reset transistor, and outputs a selection signal to the selection transistor. By outputting each signal to the pixel 1, the transistor included in the pixel 1 operates, and an analog pixel signal is output from the pixel 1. Here, the analog pixel signal means the reset potential output from the pixel 1 when the vertical scanning circuit 3 outputs a reset signal, and the charge accumulated in the photodiode when the vertical scanning circuit 3 outputs a transfer signal. This is the pixel potential output from the pixel 1 according to the amount of. Hereinafter, the analog pixel signal is indicated as Vsig. Details of the operation will be described later.

There are M vertical signal lines 4 corresponding to each column of pixels, and the vertical signal lines 4 are connected to each of N pixels arranged in each column. In the first embodiment, the first vertical signal line 4a is connected to the first pixel 1a, and the second vertical signal line 4b is connected to the second pixel 1b. In the present embodiment, a vertical signal line 4 including a signal line for propagating the edge detection signal Eout from the comparator 6 described later to the latch circuit 10 will be described.

One end of the reference voltage supply unit 5 is connected to the timing generator 12, and the other end is connected to the comparator 6. The reference voltage supply unit 5 generates a reference voltage Vref based on a signal supplied from the timing generator 12. The reference voltage Vref is, for example, a ramp waveform in which the voltage waveform shown in FIG. The reference voltage supply unit 5 supplies the reference voltage Vref to the comparator 6.
In the present embodiment, the reference voltage Vref adopts a waveform that decreases linearly as time passes after the transfer transistor operates, but is not limited to this, and adopts a waveform that increases linearly as time passes. May be.

The comparator 6 is arranged for each column of pixels. In the first embodiment, the comparator 6 will be described using a first comparator 6a and a second comparator 6b.

The first vertical signal line 4a and the reference voltage supply unit 5 are connected to the input terminal of the first comparator 6a, and the first edge detection circuit 7a is connected to the output terminal. The first comparator 6a compares the analog pixel signal Vsig output from the first pixel 1a via the first vertical signal line 4a with the reference voltage Vref output from the reference voltage supply unit 5. When the voltage level of the reference voltage Vref reaches the voltage level of the analog pixel signal Vsig, the signal output according to the pulse signal CLK is changed from high level to low level or from low level to high level. The output first comparison signal will be described as Cout.

A second vertical signal line 4b and a reference voltage supply unit 5 are connected to the input terminal of the second comparator 6b, and a second edge detection circuit 7b is connected to the output terminal. The second comparator 6b is connected to the second comparator 6b via the second vertical signal line 4b.
The analog pixel signal Vsig output from the two pixels 1b is compared with the reference voltage Vref output from the reference voltage supply unit 5. When the voltage level of the reference voltage Vref reaches the voltage level of the analog pixel signal Vsig, the signal output according to the pulse signal CLK is changed from high level to low level or from low level to high level. The output second comparison signal will be described as Cout.

M edge detection circuits 7 are arranged with respect to the pixel column. In the first embodiment, the edge detection circuit 7 will be described as a first edge detection circuit 7a and a second edge detection circuit 7b.

The first edge detection circuit 7 a detects the edge of the first comparison signal Cout output from the first comparator 6 a and outputs a pulsed first edge detection signal Eout to the latch unit 9.

The second edge detection circuit 7 b detects the edge of the second comparison signal Cout output from the second comparator 6 b and outputs a pulsed second edge detection signal Eout to the latch unit 9.

The clock signal generator is composed of a 4-bit counter, for example, and performs a counting operation according to the pulse signal CLK. Here, the clock signal generator 8 is connected to the latch unit 9 via four clock signal lines CL1 to CL4 corresponding to 4 bits from the least significant bit to the most significant bit. For example, a count signal G1 having the same cycle as the pulse signal CLK is output to the clock signal line CL1. For example, a count signal G2 obtained by dividing the pulse signal CLK by two is output to the clock signal line CL2. For example, a clock signal G3 obtained by dividing the pulse signal line CLK by 4 is output to the clock signal line CL3. For example, a clock signal G4 obtained by dividing the pulse signal line CLK by 8 is output to the clock signal line CL4. In the first embodiment, the clock signal generator is 4 bits.
The present invention is not limited to this, and any number of clock signal generators of 2 bits or more can be implemented. For example, if the clock signal generator 8 is a 12-bit counter, the number of latch circuits 10 per column is 12. If the clock signal generator 8 is an 8-bit counter, the number of latch circuits 10 per column is 8. Depending on the number of bits of the clock signal generator 8,
The number of latch circuits 10 in each column is changed.

The latch unit 9 includes an adjustment circuit 11 and a latch circuit 10 arranged in a matrix of 4 rows × M columns corresponding to each of the four clock signal lines CL1 to CL4 and the M vertical signal lines 4.

In the present embodiment, the latch circuit 10 included in the latch unit 9 is described as a first latch circuit 10a connected to the first vertical signal line 4a and a second latch circuit 10b connected to the second vertical signal line 4b. To do. The first latch circuit 10a and the second latch circuit 10b are connected to, for example, the first clock signal line CL1.

For example, the first latch circuit 10a is disposed at a position having a first distance 16 from the clock signal generator 8, and the second latch circuit 10b is a second longer than the first distance 16 from the clock signal generator 8. Are disposed at positions having a distance 17 of. In the first clock signal line CL1, the length of the portion connecting the clock signal generator 8 and the first latch circuit 10a is the first length.
Have a length of Further, in the first clock signal line CL1, the clock signal generator 8 and the second clock signal line CL1 are connected.
The length of the portion connecting the latch circuit 10b has a second length that is longer than the first length.

The third latch circuit 10c and the fourth latch circuit 10d are connected to the second clock signal line CL2.

The third latch circuit 10 c is connected to the first vertical signal line 4 a and is disposed at a position having a first distance 16 from the clock signal generator 8.

The fourth latch circuit 10 d is connected to the second vertical signal line 4 b and is disposed at a position having a second distance 17 longer than the first distance 16 from the clock signal generator 8. Further, the first clock signal line CL2 has a first length which is the length of the portion connecting the clock signal generator 8 and the third latch circuit 10c. In the second clock signal line CL2, the length of the portion connecting the clock signal generator 8 and the fourth latch circuit 10d has a second length that is longer than the first length.
The adjustment circuit 11 is provided according to the number of the latch circuits 10 arranged in the row direction. In the present embodiment, the adjustment circuit 11 is connected between the first latch circuit 10a and the second latch circuit 10b via the first clock signal line CL1. The adjustment circuit 11 has a role of delaying the clock signals G1 to G4 output from the clock signal generator 8 and adjusting the cycle of the clock signal. By delaying the clock signals G1 to G4, the phases of the clock signals G1 to G4 input to the latch circuit 10 arranged at a position away from the clock signal generator 8 can be adjusted. In the first embodiment, the adjustment circuit 11 is arranged between the first adjustment circuit 11a arranged between the first latch circuit 10a and the second latch circuit 10b, and between the third latch circuit 10c and the fourth latch circuit 10d. The description will be made assuming that the number of second adjustment circuits 11b is larger than the number of first adjustment circuits 11a. However, the present invention is not limited to this.

The timing generator 12 as a frequency generator is connected to the vertical scanning circuit 3, the reference voltage supply unit 5, the edge detection circuit 7, and the clock signal generator 8. The timing generator 12 generates a pulse signal CLK, a control signal, and the like serving as an operation reference, and the vertical scanning circuit 3,
A pulse signal CLK is supplied to the reference voltage supply unit 5, the clock signal generator 8, and the like.

The horizontal scanning circuit 13 is composed of a shift register, for example. The horizontal scanning circuit 13 sequentially selects the M vertical signal lines 4 in the column direction in synchronization with the pulse signal CLK, and outputs a digital signal from the latch circuit 10.

  Next, the operation of the solid-state imaging device according to the first embodiment will be described.

As shown in FIG. 2, at time t1, the vertical scanning circuit 3 outputs a reset signal reset to the reset transistor. As a result, a reset potential that is a reference potential of the pixels 1 in the first row is output. The reset potential output from the pixel 1 is input via the vertical signal line 4 to the comparator 6 corresponding to the pixel column. In this embodiment, the transfer transistor operates, and the analog pixel signal Vsig output from the pixel 1 according to the amount of charge accumulated in the photodiode and the reference voltage
Only the comparison with Vref will be described.

At time t2, the vertical scanning circuit 3 outputs a transfer signal read. As a result, a pixel potential corresponding to the charge accumulated in the photodiode is output from the pixel 1. The analog pixel signal Vsig output from the pixel 1 is input to the comparator 6 via the vertical signal line 4.

At time t3, the reference voltage supply unit 5 outputs the reference voltage Vref to the comparator 6. Reference voltage Vref
Is supplied to the comparator 6 and the timing generator 12
The pulse signal CLK is supplied to. When the clock signal generator 8 is supplied with the pulse signal CLK, the clock signal generator 8 counts the comparison time until the reference voltage Vref in the comparator 6 matches the analog pixel signal Vsig.

When the reference voltage Vref matches the analog pixel signal Vsig at time t4, the comparison signal Cout output from the comparator 6 rises from low level to high level. When the comparison signal Cout output from the comparator 6 rises, the edge detection circuit 7 outputs the edge detection signal Eout. When the edge detection signal Eout is output from the edge detection circuit 7, the latch circuit 10 outputs “1” when the clock signals G1 to G4 output from the clock signal generator 8 are at a high level.
The signal “0” is latched, and when it is at the low level, the signal “0” is latched. 4 in 1 row of pixels
Analog pixel signals output from one pixel 1 in the corresponding column by one latch circuit 10
Vsig is latched into a 4-bit digital value. That is, the analog pixel signal Vsig output from each pixel 1 is A / D converted into a 4-bit digital pixel signal by the clock signal generator 8 and the latch unit 9. Accordingly, as shown in FIG. 2, the four latch circuits 10 corresponding to the columns to which the detection signal Eout is output receive the clock signals G1 to G4 of “0110” from the counter when the edge detection signal Eout is input. Since it is output, the signal “0110” is latched.

As shown in FIG. 3A, the clock signals G1 to G4 input from the clock signal generator 8 to the first latch circuit 10a connected to the clock signal lines CL1 to CL4 having the first length are used as a reference. Then, the clock signals G1 ′ to G4 ′ input from the clock signal generator 8 to the second latch circuit 10b connected to the clock signal lines CL1 to CL4 having the second length are shown in FIG. Delay occurs. This is because the clock signal lines CL1 to CL4 have a wiring load composed of a parasitic resistance and a parasitic capacitance. For this reason, even if the amount of light incident on the photodiode is the same, the phase of the clock value is shifted as it is arranged in a row farther from the clock signal generator 8, so that an accurate digital value cannot be obtained.

In the first embodiment, an inverter as the adjustment circuit 11 is provided between the first latch circuits 10a and the second latch circuit 10b of the latch unit 9. As a result, the clock signals G1 to G4 output from the clock signal generator 8 at the above-described time t4 are supplied to the second n + 1-th column via the adjustment circuit 11.
It is input to the latch circuit 10b. As the clock signals G1 to G4 pass through the adjustment circuit 11, the clock signals G1 ′ to G4 ′ are further delayed. By increasing the delay time, the phase shift between the delayed clock signals G1 ″ to G4 ″ via the inverter and the count signals G1 to G4 output from the clock signal generator 8 can be reduced. it can. Note that the number of adjustment circuits 11 may be changed according to clock signals CL1 to CL4 having different frequency division ratios. For example, the adjustment circuit 11 connected to the first clock signal line CL1 between the first latch circuit 10a and the second latch circuit 10b.
May be smaller than the number of adjustment circuits 11 connected to the second clock signal line CL2 between the third latch circuit 10c and the fourth latch circuit 10d.

In the present embodiment, the adjustment circuit 11 is provided for every two columns to adjust the delay times of the clock signals G1 to G4. However, the present invention is not limited to this.

From the above, by increasing the delay time via the inverter as the adjustment circuit 11, the phase shift between the clock signals G1 to G4 and the clock signals G1 '' to G4 '' can be reduced. That is, an error in the digital signal output depending on the location where the latch circuit 10 is disposed can be suppressed.

(Second Embodiment)
A solid-state imaging device according to the second embodiment will be described with reference to FIG. FIG. 4 is a schematic circuit diagram illustrating a part of the configuration of the solid-state imaging device according to the second embodiment.

The difference between the solid-state imaging device according to the second embodiment and the first embodiment is that a memory 14 as a storage device and a determination circuit 15 are provided. Since the solid-state imaging device according to the second embodiment is the same as the structure of the solid-state imaging device according to the first embodiment except for the above points, the same parts are denoted by the same reference numerals and detailed description thereof is omitted. . The horizontal scanning circuit 13 described in the first embodiment.
Is omitted in order to avoid complication of the drawing.

  The structure of the solid-state imaging device according to the second embodiment will be described.

The memory 14 is connected to a determination circuit 15 connected to the latch circuit 10. Memory 1
4 stores the digital signal output from the latch circuit 10. The memory 14 stores in advance AD-converted values as a reference.

The determination circuit 15 is connected to the memory 14. The determination circuit 15 compares the value stored in the memory 14 with the digital signal output from the latch circuit 10. At this time, when there is a deviation from the stored value, the determination circuit 15 outputs a phase adjustment signal corresponding to the deviation amount to the adjustment circuit 11. The determination circuit 15 includes an adjustment circuit 11 provided for each of the clock signal lines CL1 to CL4.
In order to avoid complication of the drawing, the determination circuit 15 and the clock signal lines CL1 to CL4 are connected.
These are described as being connected with a single adjustment circuit 11.

In the second embodiment, the determination circuit 15 connected to the adjustment circuit 11 is provided. The determination circuit 15
Since a signal is output to each of the adjustment circuits 11 provided for each of the clock signal lines CL1 to CL4 according to the delay amount, the signal is output to the adjustment circuit 11 corresponding to the clock signal line having a large deviation amount among the clock signals G1 to G4. do it. Therefore, a delay error is suppressed as compared with the case where the clock signal lines CL1 to CL4 are delayed at the same time. Further, since there are clock signal lines CL1 to CL4 that do not require the adjustment circuit 11 to operate, power consumption can be suppressed.

Although the embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Pixel 1a ... 1st pixel 1b ... 2nd pixel 1c ... 3rd pixel 2 ... Pixel area 3 ... Vertical scanning circuit 4 ... Vertical signal line 4a ... First vertical signal line 4b ... second vertical signal line 5 ... reference voltage supply 6 ... comparator 6a ... first comparator 6b ... second comparator 7 ... edge detection Circuit 7a ... First edge detection circuit 7b ... Second edge detection circuit 8 ... Clock signal generator 9 ... Latch unit 10 ... Latch circuit 10a ... First latch circuit 10b ... Second latch circuit 10c ... third latch circuit 10d ... fourth latch circuit 11a ... first adjustment circuit 11b ... second adjustment circuit 12 ... timing generator 13 ... horizontal scanning circuit 14 ... Memory 15 ... Determination circuit 16 ... First distance 17 ... Second distance

Claims (8)

Pixels arranged in N rows × M columns (N is an integer of 1 or more, M is an integer of 2 or more);
A vertical signal line connected to the pixel and provided for each column;
Comparing a pixel signal read from the pixel via the vertical signal line with a reference voltage;
A comparator that outputs a comparison signal;
A clock signal generator connected to a clock signal line that propagates the clock signal;
A first latch circuit connected to the vertical signal line for inputting the comparison signal and having a first length from the clock signal generator and connected to the clock signal line;
A second latch circuit connected to the vertical signal line, for inputting the comparison signal, and having a second length longer than the first length from the clock signal generator and connected to the clock signal line When,
An adjustment circuit connected to the clock signal line between the first latch circuit and the second latch circuit;
A solid-state imaging device. The first latch circuit receives the clock signal and a first detection signal based on the first comparison signal,
The solid-state imaging device according to claim 1, wherein the clock signal and a second detection signal based on the second comparison signal are input to the second latch circuit. The vertical signal lines include a first vertical signal line connected to the pixel located in the mth column (m is an integer), and a second vertical signal line connected to the pixel located in the m + 1th column. The first latch circuit is connected to the first vertical signal line;
The solid-state imaging device according to claim 1, wherein the second latch circuit is connected to the second vertical signal line. The clock signal line includes a first clock signal line and a second clock signal line,
The clock signal generator outputs a second clock signal having a frequency division ratio different from that of the first clock signal to a second clock signal line;
A third latch circuit connected to the first vertical signal line and a second adjustment circuit connected to the second clock signal line between the fourth latch circuit connected to the second vertical signal line; Have
The solid-state imaging device according to claim 3, wherein the number of the first adjustment circuits connected to the first clock signal line is different from the number of the second adjustment circuits connected to the second clock signal line. 5. The adjustment circuit according to claim 1, wherein the adjustment circuit includes a resistance element or an inverter.
The solid-state imaging device described in 1. The solid-state imaging device according to claim 4, wherein the number of the first adjustment circuits is smaller than the number of the second adjustment circuits. A first pixel column including a first pixel;
A first vertical signal line connected to the first pixel column;
A first comparator that compares a pixel signal output from the first pixel via the first vertical signal line with a reference voltage and outputs a first comparison signal;
A second pixel column including a second pixel disposed at a predetermined interval from the first pixel;
A second vertical signal line connected to the second pixel column;
A second comparator that compares a pixel signal output from the second pixel via the second vertical signal line with a reference voltage and outputs a second comparison signal;
A first clock signal line for propagating the first clock signal and a second clock signal for propagating the second clock signal.
A clock signal generator connected to the clock signal line;
A first latch circuit that receives a first clock signal and a first detection signal based on the first comparison signal and is connected to the first clock signal line and the first comparator;
A second latch circuit that receives the first clock signal and a second detection signal based on the second comparison signal and is connected to a second clock signal line and the second comparator;
An adjustment circuit connected to the first clock signal line between the first latch circuit and the second latch circuit;
A solid-state imaging device. The solid-state imaging device further includes a storage device and a determination circuit,
The determination circuit is connected to the storage device and the adjustment circuit, and the phase of the clock signal output from the clock signal generator is shifted from the phase of the clock signal stored in the storage device in advance. The solid-state imaging device according to claim 1, wherein an adjustment signal is output to the adjustment circuit.

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