JP2017103758A - Wireless power receiving apparatus, electronic device, and demodulation method of power signal subjected to FSK - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deterioration of communication quality in a situation where ringing occurs. A rectifier circuit 304 includes an H-bridge circuit 330 to rectify an alternating current flowing through a receiving antenna 301. The smoothing capacitor 306 smoothes the output of the rectifier circuit 304. The demodulator 350 demodulates the FSK-applied power signal. The first comparator CMP1 compares the voltage VAC1 of the first AC input terminal AC1 with the first threshold voltage VTH1 and generates the first detection signal S11. The second comparator CMP2 compares the voltage VAC2 of the second AC input terminal AC2 with the second threshold voltage VTH2, and generates the second detection signal S12. The clock generation circuit 352 generates a frequency detection clock CLK_OUT that transitions according to one edge of the first detection signal S11 and one edge of the second detection signal S12. The frequency detection circuit 354 detects the frequency of the frequency detection clock CLK_OUT. [Selection diagram] Fig. 5

Description

  The present invention relates to a wireless power feeding technique.

  In recent years, contactless power transmission (also referred to as non-contact power feeding or wireless power feeding) has begun to spread in order to supply power to electronic devices. In order to promote mutual use between products of different manufacturers, the WPC (Wireless Power Consortium) was organized, and the international standard Qi (Qi) standard was formulated by WPC.

  FIG. 1 is a diagram illustrating a configuration of a wireless power feeding system 100 compliant with the Qi standard. The power supply system 100 includes a power transmission device 200 (TX, Power Transmitter) and a power reception device 300r (RX, Power Receiver). The power receiving device 300r is mounted on an electronic device such as a mobile phone terminal, a smart phone, an audio player, a game device, or a tablet terminal.

  The power transmission device 200 includes a transmission antenna 201, an inverter 204, a controller 206, and a demodulator 208. The transmission antenna 201 includes a transmission coil (primary coil) 202 and a resonance capacitor 203. The inverter 204 includes an H-bridge circuit (full-bridge circuit) or a half-bridge circuit, and applies a drive signal S 1, specifically a pulse signal, to the transmission coil 202. An electromagnetic field power signal S2 is generated. The controller 206 controls the power transmission apparatus 200 as a whole. Specifically, the controller 206 changes the transmission power by controlling the switching frequency, the switching duty ratio, or the phase of the inverter 204.

  In the Qi standard, a communication protocol is defined between the power transmission device 200 and the power reception device 300r, and control data S3 can be transmitted from the power reception device 300r to the power transmission device 200. The control data S3 is transmitted from the reception coil 302 (secondary coil) to the transmission coil 202 in the form of AM (Amplitude Modulation) modulation using backscatter modulation. The control data S3 includes, for example, power control data (also referred to as a packet) for instructing the amount of power supplied to the power receiving apparatus 300r, data indicating unique information of the power receiving apparatus 300r, and the like. The demodulator 208 demodulates the control data S3 included in the current or voltage of the transmission coil 202. The controller 206 controls the inverter 204 based on the power control data included in the demodulated control data S3.

  The power receiving device 300r includes a receiving coil 302, a rectifier circuit 304, a capacitor 306, a modulator 308, a controller 312, a charging circuit 314, and a demodulator 320. The reception coil 302 receives the power signal S <b> 2 from the transmission coil 202 and transmits control data S <b> 3 to the transmission coil 202. The rectifier circuit 304 and the capacitor 306 rectify and smooth the current S4 induced in the receiving coil 302 in accordance with the power signal S2, and convert it into a DC voltage. The charging circuit 314 charges the secondary battery 102 using the power supplied from the power transmission device 200.

  The controller 312 monitors the power supply amount received by the power receiving apparatus 300r, and generates power control data (control error value) instructing the power supply amount accordingly. The modulator 308 modulates the control current S3 including the power control data and modulates the coil current of the reception coil 302, thereby modulating the coil current and the coil voltage of the transmission coil 202.

  In the Qi standard, the control data S5 can be transmitted from the power transmission device 200 to the power reception device 300r. The control data S5 is superimposed on the power signal S2 by FSK (Frequency Shift Keying) and transmitted from the transmission coil 202 to the reception coil 302. The control data S5 may include an acknowledge (ACK) signal notifying receipt of the control data S3, a non-acknowledge (NACK) signal notifying that the control data S3 could not be received, and the like.

  The FSK modulator 220 is built in the controller 206 and changes the switching frequency of the inverter 204 in accordance with data to be transmitted. The demodulator 320 on the power receiving device 300r side demodulates the FSK control data S5.

  FIG. 2 is a circuit diagram of the rectifier circuit 304 and the demodulator 320 examined by the present inventors. The rectifier circuit 304 is a so-called synchronous rectifier circuit (also referred to as a synchronous detection circuit), and includes an H bridge circuit 330, a driver 332, a first comparator 334, a second comparator 336, and a logic circuit 338. H bridge circuit 330 includes transistors M1 to M4 and rectifier diodes D1 to D4.

The receiving antenna 301 is connected to the input terminals AC1 and AC2 of the synchronous rectifier circuit 304, and an alternating current I _AC (S4 in FIG. 1) induced by the power signal S2 flows. The rectifier circuit 304 switches the state φ of the H bridge circuit 330 at the timing when the alternating current I _AC is zero, that is, the polarity is inverted. This is called zero current switching. The H bridge circuit 330 can take the following four states φ1 to φ4.
・ First state φ1
1st transistor M1 = ON
Second transistor M2 = OFF
Third transistor M3 = OFF
4th transistor M4 = ON
・ Second state φ2
1st transistor M1 = OFF
Second transistor M2 = OFF
Third transistor M3 = OFF
Fourth transistor M4 = OFF
・ Third state φ3
1st transistor M1 = OFF
Second transistor M2 = ON
Third transistor M3 = ON
Fourth transistor M4 = OFF
・ Fourth state φ4
1st transistor M1 = OFF
Second transistor M2 = OFF
Third transistor M3 = OFF
Fourth transistor M4 = OFF
In the second state φ2 and the fourth state φ4, the rectifier circuit 304 functions as a diode rectifier circuit.

The first comparator 334, second comparator 336, AC1 terminal, the voltage _{V AC1, V AC2} of AC2 terminals respectively, compared to the threshold voltage _{V ZC1, V ZC2} for zero current detection. These comparators 334 and 336 are hysteresis comparators, and the threshold voltage changes in two values: a negative voltage (for example, −0.2 V) and a voltage in the vicinity of 0 (for example, −2 mV).

  The logic circuit 338 controls the state of the H bridge circuit 330 based on the combination of the outputs AC1_DET and AC2_DET of the first comparator 334 and the second comparator 336. The driver 332 drives the transistors M1 to M4 in accordance with a control signal from the logic circuit 338. It should be noted that all of the configuration and operation of the rectifier circuit 304 shown in FIG.

  FIG. 3 is an operation waveform diagram of the rectifier circuit 304. The vertical axis and horizontal axis of the waveform diagrams and time charts in this specification are appropriately expanded and reduced for easy understanding, and each waveform shown is also simplified for easy understanding. Or it is exaggerated or emphasized.

AC1_DET signal voltage _{V AC1} in AC1 terminal to a high level exceeding -2 mV, changes to the low level becomes lower than -0.2V. Similarly, AC2_DET signal voltage _{V AC2} of AC2 terminal to a high level exceeding -2 mV, changes to the low level becomes lower than -0.2V. The logic circuit 338 switches between the first state φ1 to the fourth state φ4 based on the AC1_DET signal and the AC2_DET signal. There may be a delay between the level change of the AC1_DET signal and the AC2_DET signal and the state transition.

Returning to FIG. 2, the demodulator 320 will be described. The frequency of the AC2_DET signal is equal to the frequency of the alternating current I _AC , in other words, the power signal S2. Therefore, the demodulator 320 detects the frequency by counting the period of the AC2_DET signal, and performs FSK demodulation. Since the AC1 terminal and the AC2 terminal are symmetrical, the demodulator 320 may perform FSK demodulation based on the AC1_DET signal.

JP 2011-111780 A

  However, the demodulator 320 in FIG. 2 has the following problems. 4A and 4B are operation waveform diagrams of the rectifier circuit 304 and the demodulator 320. FIG. The FSK_CLK_ID signal is a signal obtained by retiming the AC1_DET signal using an internal clock and masking short chattering, but they may be regarded as substantially the same.

In wireless power feeding, apart from FSK for communication, in order to change transmission power, a transmission frequency, a switching duty ratio, a switching phase, or the like is changed. As a result, large ringing sometimes occurs in the voltages V _AC1 and V _AC2 of the AC1 terminal and the AC2 terminal during the second state φ2 and the fourth state φ4 in which the H bridge circuit becomes a diode rectifier circuit. As shown in FIG. 4B, when the ringing amplitude increases, the voltage V _AC1 (V _AC2 ) crosses the threshold voltage V _ZC regardless of the zero crossing point of the _AC current I _AC . The level of the AC1_DET signal (or AC2_DET signal) changes. As a result, the frequency of the power signal S2 and the frequency of the AC1_DET1 signal (FSK_CLK_ID signal) become inconsistent, communication quality and stability are lowered, and the bit error rate is deteriorated.

  The present invention has been made in view of such a problem, and one of exemplary purposes of an aspect thereof is a wireless reception device capable of suppressing deterioration in communication quality and bit error rate in a situation where ringing occurs. On offer.

1. One embodiment of the present invention relates to a wireless power receiving apparatus that receives a power signal from a wireless power transmitting apparatus. The wireless power receiving apparatus includes a receiving antenna including a receiving coil that receives a power signal, a rectifying circuit that rectifies an alternating current flowing through the receiving antenna, a smoothing capacitor that smoothes the output of the rectifying circuit, and FSK (Frequency Shift Keying). And a demodulator for demodulating the generated power signal. The rectifier circuit includes an H bridge circuit having a first AC input terminal and a second AC input terminal connected to the receiving antenna, and a synchronous rectifier controller that controls the H bridge circuit. The demodulator compares the voltage at the first AC input terminal with the first threshold voltage, generates a first detection signal, and converts the voltage at the second AC input terminal into the second threshold voltage. A second comparator that generates a second detection signal, a clock generation circuit that generates a frequency detection clock that transitions according to one edge of the first detection signal and one edge of the second detection signal; And a frequency detection circuit for detecting the frequency of the frequency detection clock.

  By generating the frequency detection clock using the two detection signals corresponding to the voltages of the two AC input terminals, it is possible to prevent a change in the detection signal due to the influence of ringing from being transmitted to the frequency detection clock. According to this aspect, even in a situation where ringing occurs at the AC input terminal, FSK demodulation can be correctly performed, and deterioration in communication quality can be suppressed.

  The clock generation circuit may generate a frequency detection clock according to a positive edge of the second detection signal and a negative edge of the first detection signal that follows the positive edge.

  The clock generation circuit may include an inverter that inverts the first detection signal, and a logic circuit that generates a frequency detection clock according to the second detection signal and the first detection signal inverted by the inverter.

  The clock generation circuit may retime the inverted first detection signal and second detection signal using an internal clock.

  The clock generation circuit includes a first chattering removal circuit that makes the transition valid when the first detection signal takes the same level over M cycles of the internal clock (M is an integer of 2 or more), and the second detection signal A second chattering elimination circuit that makes the transition valid when the same level is taken over N cycles (N is an integer of 2 or more) of the internal clock may be further included.

  The clock generation circuit may further include a first one-shot circuit provided on the inverted path of the first detection signal and a second one-shot circuit provided on the path of the second detection signal. By generating a pulse signal having a predetermined pulse width using a one-shot circuit, it is possible to perform reliable processing according to the edge of the detection signal.

  The frequency detection circuit may measure the frequency of the frequency detection clock using an internal clock.

  The clock generation circuit may generate a frequency detection clock according to the negative edge of the second detection signal and the subsequent negative edge of the first detection signal.

The synchronous rectification controller may control the bridge circuit based on the first detection signal and the second detection signal.
By sharing the comparator of the demodulator and the comparator of the rectifier circuit, the circuit area can be reduced.

  The wireless power receiving apparatus may conform to the Qi standard.

2. Another aspect of the present invention also relates to a wireless power receiving apparatus that receives a power signal from the wireless power transmitting apparatus. The wireless power receiving apparatus includes a receiving antenna including a receiving coil that receives a power signal, a rectifying circuit that rectifies an alternating current flowing through the receiving antenna, a smoothing capacitor that smoothes the output of the rectifying circuit, and FSK (Frequency Shift Keying). A demodulator that demodulates the received power signal, and an auxiliary circuit that shifts the parallel resonant frequency of the receiving antenna during reception of the FSK signal.

  By changing the parallel resonant frequency of the receiving antenna, it is possible to suppress the occurrence of ringing, thereby suppressing the deterioration of the bit error rate.

  The auxiliary circuit includes a first capacitor and a first switch provided in series between one end of the receiving antenna and the ground, a second capacitor and a second switch provided in series between the other end of the receiving antenna and the ground, And a control circuit that controls the first switch and the second switch.

  The auxiliary circuit may further include a resistor provided between the connection node of the first switch and the second switch and the ground. The shift amount of the parallel resonance frequency can be determined according to the resistance value of the resistor.

  In one aspect, the wireless power receiving apparatus may further include an AM modulator that is connected to the reception antenna and changes a parallel resonance frequency of the reception antenna in accordance with the AM modulation signal. The auxiliary circuit may act on the AM modulator. Thereby, an increase in circuit area can be suppressed.

  The AM modulator includes a first capacitor and a first switch provided in series between one end of the receiving antenna and the ground, a second capacitor and a second switch provided in series between the other end of the receiving antenna and the ground, May be included. The auxiliary circuit includes a logic gate that performs a logical operation on the AM modulation signal and a reception period signal indicating a reception period of the FSK signal, and controls the first switch and the second switch based on the output signal of the logic gate. Good.

The rectifier circuit may include an H bridge circuit having a first AC input terminal and a second AC input terminal connected to the receiving antenna, and a synchronous rectifier controller that controls the H bridge circuit. The demodulator compares the voltage at the first AC input terminal with the first threshold voltage, generates a first detection signal, and converts the voltage at the second AC input terminal into the second threshold voltage. A second comparator that generates a second detection signal, a clock generation circuit that generates a frequency detection clock that transitions according to one edge of the first detection signal and one edge of the second detection signal; And a frequency detection circuit for detecting a frequency of the frequency detection clock.
By generating the frequency detection clock using the two detection signals corresponding to the voltages of the two AC input terminals, it is possible to prevent a change in the detection signal due to the influence of ringing from being transmitted to the frequency detection clock. According to this aspect, even in a situation where ringing occurs at the AC input terminal, FSK demodulation can be performed correctly, and deterioration of the bit error rate can be suppressed.

  The clock generation circuit may generate a frequency detection clock according to a positive edge of the second detection signal and a negative edge of the first detection signal that follows the positive edge.

  The clock generation circuit may include an inverter that inverts the first detection signal, and a logic circuit that generates a frequency detection clock according to the second detection signal and the first detection signal inverted by the inverter.

  The clock generation circuit may retime the inverted first detection signal and second detection signal using an internal clock.

  The clock generation circuit includes a first chattering removal circuit that makes the transition valid when the first detection signal takes the same level over M cycles of the internal clock (M is an integer of 2 or more), and the second detection signal A second chattering elimination circuit that makes the transition valid when the same level is taken over N cycles (N is an integer of 2 or more) of the internal clock may be further included.

  The clock generation circuit may further include a first one-shot circuit provided on the inverted path of the first detection signal and a second one-shot circuit provided on the path of the second detection signal. By generating a pulse signal having a predetermined pulse width using a one-shot circuit, it is possible to perform reliable processing according to the edge of the detection signal.

  The frequency detection circuit may measure the frequency of the frequency detection clock using an internal clock.

  The clock generation circuit may generate a frequency detection clock according to the negative edge of the second detection signal and the subsequent negative edge of the first detection signal.

The synchronous rectification controller may control the bridge circuit based on the first detection signal and the second detection signal.
By sharing the comparator of the demodulator and the comparator of the rectifier circuit, the circuit area can be reduced.

  The wireless power receiving apparatus may conform to the Qi standard.

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to suppress deterioration in communication quality in a situation where ringing occurs. According to a certain aspect, ringing that occurs in the receiving antenna during reception of the FSK signal can be suppressed, and deterioration of the bit error rate can be suppressed.

It is a figure which shows the structure of the wireless electric power feeding system based on Qi specification. It is a circuit diagram of the rectifier circuit and demodulator which the present inventors examined. It is an operation | movement waveform diagram of a rectifier circuit. 4A and 4B are operation waveform diagrams of the rectifier circuit and the demodulator. It is a circuit diagram of a power receiving apparatus provided with a demodulator according to an embodiment. FIG. 6 is an operation waveform diagram of a demodulator of the power receiving device in FIG. 5. It is a circuit diagram which shows the specific structural example of a power receiving apparatus. FIGS. 8A and 8B are circuit diagrams showing specific configuration examples of the demodulator. It is an operation | movement waveform diagram of the demodulator which concerns on a 1st modification. It is a circuit diagram of the demodulator which concerns on a 1st modification. It is a circuit diagram of the power receiving apparatus which concerns on 2nd Embodiment. 12A to 12D are circuit diagrams illustrating configuration examples of the ringing suppressor. FIGS. 13A and 13B are circuit diagrams of the modulator and the ringing suppressor. FIG. 14A is an operation waveform diagram of the power receiving apparatus including the modulator and the ringing suppressor of FIG. 13A, and FIG. 14B is a waveform diagram for comparison. It is a perspective view of an electronic device provided with a power receiving apparatus.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

(First embodiment)
FIG. 5 is a circuit diagram of a power receiving device 300 including the demodulator 350 according to the first embodiment. The basic configuration of the power receiving device 300 is as described with reference to FIG.

The reception antenna 301 includes a reception coil 302 that receives the power signal S2 and a resonance capacitor 303. Rectifier circuit 304 rectifies an alternating current _{I AC} flowing into the reception antenna 301. The rectifier circuit 304 includes an H bridge circuit 330 including a first transistor M1 to a fourth transistor M4 and rectifier diodes D1 to D4, and a synchronous rectifier controller 331 that controls the H bridge circuit 330. The smoothing capacitor 306 smoothes the output of the rectifier circuit 304.

  The power signal S <b> 2 is subjected to FSK (Frequency Shift Keying) by the modulator of the power transmission device 200. The demodulator 350 demodulates the FSK signal.

The demodulator 350 includes a first comparator CMP1, a second comparator CMP2, a clock generation circuit 352, and a frequency detection circuit 354. The first comparator CMP1 compares the voltage V _AC1 at the first AC input terminal (AC1 terminal) with the first threshold voltage V _TH1 and generates the first detection signal S11. Similarly, the second comparator CMP2 is a voltage _{V AC2} of the second AC input terminal (AC2 terminal), compared with the second threshold voltage _{V TH2,} generates a second detection signal S12. The first threshold voltage V _TH1 and the second threshold voltage V _TH2 are preferably negative voltages near zero volts, and they can be the same voltage. The first comparator CMP1 and the second comparator CMP2 may be configured by a hysteresis comparator, and the threshold voltage V _TH1 (V _TH2 ) varies depending on two values of the two threshold voltages V _THH and V _THL. Also good. As an example, V _THH = −2 mV and V _THL = −0.2 V may be used.

  The clock generation circuit 352 is a frequency detection clock CLK_OUT that transitions according to one edge (that is, positive edge or negative edge) of the first detection signal S11 and one edge (that is, positive edge or negative edge) of the second detection signal. Is generated.

  In the present embodiment, the clock generation circuit 352 transits to a first level (for example, a high level) according to the positive edge of the second detection signal S12, and then changes to the second level according to the negative edge of the first detection signal S11. A frequency detection clock CLK_OUT that changes to a level (for example, a low level) is generated.

  The frequency detection circuit 354 detects the frequency of the frequency detection clock CLK_OUT and generates data FREQ indicating the frequency. The frequency data FREQ is supplied to a digital demodulator (not shown).

The above is the basic configuration of the power receiving device 300 according to the embodiment. Next, the operation will be described. 6 is an operation waveform diagram of the demodulator 350 of the power receiving device 300 of FIG. The voltage V _{AC1 at the} AC1 terminal is compared with the first threshold voltage V _TH1 to generate the first detection signal S11. Similarly, the voltage V _AC2 at the AC2 terminal is compared with the second threshold voltage V _TH2 to generate the second detection signal S12.

  The clock generation circuit 352 sets the frequency detection clock CLK_OUT to the high level in response to the positive edge of the second detection signal S12, and sets the frequency detection clock CLK_OUT to the low level in response to the negative edge of the first detection signal S11. To do. The frequency detection circuit 354 measures the frequency (that is, the cycle) of the frequency detection clock CLK_OUT.

The above is the basic operation of the power receiving apparatus 300.
Here, in the period _{T A} immediately after the positive edge of the second detection signal S12, and the voltage _{V AC2} was significantly ringing. In this case, the level of the second detection signal S12 is changed, the clock generation circuit 352 in the period T _A is insensitive to positive edge of the second detection signal S12, also for the negative edge of the second detection signal S12 Since it is always insensitive, the frequency detection clock CLK_OUT does not change.

Also in the period _{T B} of the immediately following positive edge of the first detection signal S11, and the voltage _{V AC1} was increased ringing. In this case, the level of the first detection signal S11 is changed, the clock generation circuit 352 in the period T _B is insensitive to the negative edge of the first detection signal S11, also with respect to the positive edge of the first detection signal S11 Therefore, the frequency detection clock CLK_OUT does not change.

Thus, the demodulator 350 can correctly detect the frequency of the alternating current I _AC even if ringing occurs in the voltages V _AC1 and V _AC2 .

  Certain aspects of the present invention are understood as the block diagram and circuit diagram of FIG. 5 or extend to various devices and circuits derived from the above description, and are not limited to a specific configuration. Hereinafter, more specific configuration examples will be described in order not to narrow the scope of the present invention but to help understanding and clarify the essence and circuit operation of the present invention.

  FIG. 7 is a circuit diagram illustrating a specific configuration example of the power receiving device. In the power receiving device 300a of FIG. 7, the synchronous rectification controller 331 performs zero current switching. Specifically, the synchronous rectification controller 331 includes a driver 332, a first comparator 334, a second comparator 336, and a logic circuit 338. These configurations and operations are as described with reference to FIG.

  In the power receiving apparatus 300a of FIG. 7, the first comparator 334 and the second comparator 336 for detecting zero current (zero cross) are used as the first comparator CMP1 and the second comparator CMP2 of the demodulator 350. That is, the AC1_DET signal is used as the first detection signal S11, and the AC2_DET signal is used as the second detection signal S12.

  According to this configuration example, the synchronous rectification controller 331 and the demodulator 350 share two comparators, thereby reducing the circuit area.

  FIGS. 8A and 8B are circuit diagrams showing specific configuration examples of the demodulator. The clock generation circuit 352 in FIG. 8A includes an inverter 360, a first chattering removal circuit 362, a second chattering removal circuit 364, a first one-shot circuit 366, a second one-shot circuit 368, and a logic circuit 370.

  The inverter 360 inverts the first detection signal S11. The logic circuit 370 generates the frequency detection clock CLK_OUT according to the second detection signal S12 and the first detection signal # S11 (# represents logic inversion) inverted by the inverter. The logic circuit 370 may be an SR flip-flop or SR latch that is set by one of the second detection signal S12 and the inverted first detection signal # S11 and reset by the other one.

The clock generation circuit 352 may be designed as a synchronization circuit that operates in synchronization with the internal clock CLK_INT. Internal clock CLK_INT has a sufficiently higher frequency than the frequency of the alternating current _{I AC.} In this case, the clock generation circuit 352 may retime the inverted first detection signal # S11 and second detection signal S12 using the internal clock CLK_INT.

  The first chattering removal circuit 362 validates the transition when the inverted first detection signal # S11 takes the same level over M cycles (M is an integer of 2 or more) of the internal clock CLK_INT. The second chattering removal circuit 364 validates the transition when the second detection signal S12 takes the same level over N cycles (N is an integer of 2 or more) of the internal clock CLK_INT. For example, M = 3 and N = 2 may be set. The chattering removal circuits 362 and 364 synchronize the detection signals S11 and S12 with the internal clock. Chattering removal circuits 362 and 364 can be formed of flip-flops.

  The first one-shot circuit 366 is provided on the path of the inverted first detection signal # S11, and generates a reset signal RST that is asserted (for example, high level) for a predetermined time from the positive edge. The second one-shot circuit 368 is provided on the path of the second detection signal S12, and generates a set signal SET that is asserted (for example, high level) for a predetermined time from the positive edge. The logic circuit 370 is set according to the set signal SET and reset according to the reset signal RST. By using the one-shot circuit, the logic circuit 370 can be reliably set and reset.

  The frequency detection circuit 354 measures the frequency (cycle) of the frequency detection clock CLK_OUT using the internal clock CLK_INT. The frequency detection circuit 354 may be a digital counter 372, and the count value may be output as frequency data FREQ.

  Further, the clock generation circuit 352 may be configured as an asynchronous circuit that directly responds to the edge or level change without retiming the detection signals S11 and S12 by the internal clock. FIG. 8B is a circuit diagram illustrating another configuration example of the clock generation circuit 352. Clock generation circuit 352 includes flip-flop FF1. The second detection signal S12 is input to the clock terminal of the flip-flop FF1, and the first detection signal S11 is input to the negative logic reset terminal.

Next, a modification of the power receiving device 300 in FIG. 5 will be described.
(First modification)
In the first modification, the clock generation circuit 352 generates the frequency detection clock CLK_OUT according to the negative edge of the second detection signal S12 and the subsequent negative edge of the first detection signal S11. FIG. 9 is an operation waveform diagram of the demodulator 350 according to the first modification.

In the period _{T A} immediately after the positive edge of the second detection signal S12, and the voltage _{V AC2} was significantly ringing. In this case, the level of the second detection signal S12 is changed, the clock generation circuit 352 in the period T _A is insensitive to the negative edge of the second detection signal S12, with respect to the positive edge of the second detection signal S12 Is always insensitive, so the frequency detection clock CLK_OUT does not change.

Also in the period _{T B} after the negative edge of the first detection signal S11, and the voltage _{V AC1} was increased ringing. In this case, the level of the first detection signal S11 is changed, the clock generation circuit 352, in the period T _B is insensitive to the negative edge of the first detection signal S11, with respect to the positive edge of the first detection signal S11 Is always insensitive, so the frequency detection clock CLK_OUT does not change.

Thus, the demodulator 350 can correctly detect the frequency of the alternating current I _AC even if ringing occurs in the voltages V _AC1 and V _AC2 .

  FIG. 10 is a circuit diagram of a demodulator 350b according to the first modification. The clock generation circuit 352b further includes an inverter 361 that inverts the second detection signal S12 in addition to the clock generation circuit 352 of FIG. Other configurations are the same as those in FIG. The clock generation circuit 352b may be configured with an asynchronous circuit.

(Second Embodiment)
FIG. 11 is a circuit diagram of a power receiving device 300 according to the second embodiment. The power receiving apparatus 300 further includes a ringing suppressor 380 in addition to the power receiving apparatus 300r of FIG. Alternatively, the second embodiment can be combined with the first embodiment. In this case, the power receiving apparatus 300 includes a ringing suppressor 380 in addition to the power receiving apparatus including the demodulator of FIG. become.

The reception antenna 301 includes a reception coil 302, a series resonance capacitor Cs, and a parallel resonance capacitor Cd. Rectifier circuit 304 rectifies an alternating current _{I AC} flowing into the reception antenna 301. The rectifier circuit 304 is a diode bridge circuit or a synchronous rectifier circuit. The smoothing capacitor 306 smoothes the output of the rectifier circuit 304.

  The demodulator 320 demodulates the power signal S2 on which the FSK signal S5 is superimposed. The ringing suppressor 380 receives a reception period signal S21 that is asserted (for example, high level) during reception of the FSK signal S5 from the controller 312. The ringing suppressor 380 shifts the parallel resonance frequency of the receiving antenna 301 during reception of the FSK signal S5.

The parallel resonance frequency fd ′ after the shift is not limited to a specific value as long as it is determined so that the ringing of the voltage generated in the receiving antenna 301 can be suppressed. The optimum value of the parallel resonance frequency fd ′ can be found experimentally or by simulation. As a result of studies by the present inventors, the parallel resonance frequency fd ′ during reception of the FSK signal is determined closer to the transmission frequency f _TX than the parallel resonance frequency fd during non-reception of FSK signal (during normal power feeding). Is desirable. For example, it is desirable that the following relational expression holds:
f _TX ≦ fd ′ <fd
In the Qi standard, the transmission frequency f _TX is variable between 110 kHz and 205 kHz. As an example, fd may be about 1 MHz, and fd ′ may be set in a range of 100 to 700 kHz. That is, during reception of the FSK signal, the ringing suppressor 380 shifts the parallel resonance frequency to the lower side.

The above is the configuration of the power receiving device 300. Next, the operation will be described.
During the reception period of the FSK signal S5, the reception period signal S21 is asserted, and the parallel resonance frequency fd of the reception antenna 301 is shifted to be close to the frequency of the power signal S2. As a result, ringing due to the back electromotive force of the receiving coil 302 is suppressed, and the demodulator 320 can correctly receive the FSK signal.

  Certain aspects of the present invention are understood as the block diagram and circuit diagram of FIG. 11 or extend to various devices and circuits derived from the above description, and are not limited to a specific configuration. Hereinafter, more specific configuration examples will be described in order not to narrow the scope of the present invention but to help understanding and clarify the essence and circuit operation of the present invention.

  12A to 12D are circuit diagrams illustrating a configuration example of the ringing suppressor 380. FIG. The ringing suppressor 380a of FIG. 12A includes a first capacitor C1, a second capacitor C2, a first switch SW1, a second switch SW2, and a resistor R1. The first capacitor C1 and the first switch SW1 are provided in series between one end E1 of the receiving antenna 301 and the ground. The second capacitor C2 and the second switch SW2 are provided in series between the other end E2 of the receiving antenna 301 and the ground. The resistor R1 is inserted between the connection node of the first switch SW1 and the second switch SW2 and the ground. The arrangement of the resistor R1 is not particularly limited, and a plurality of resistors may be provided. As shown in FIG. 12D, the resistor R1 may be omitted.

  The control circuit 382 receives a reception period signal S21 indicating that the FSK signal is being received from the controller 312. The control circuit 382a turns on the first switch SW1 and the second switch SW2 while the reception period signal S21 is asserted.

  The ringing suppressor 380b of FIG. 12B includes a switch SW3 and a capacitor C3. The switch SW3 and the capacitor C3 are provided in series between both ends E1 and E2 of the receiving antenna 301 and in parallel with the capacitor Cd. The control circuit 382b turns on the switch SW3 while the reception period signal S21 is asserted. A resistor may be inserted in series with the capacitor C3 and the switch SW3.

  A ringing suppressor 380c in FIG. 12C is a modification of the ringing suppressor 380a in FIG. 12A, and the capacitances of the first capacitor C1 and the second capacitor C2 are variable. Between the one end E1 of the receiving antenna 301 and the ground, a plurality (two in the figure) of serial connection circuits of the capacitor C1 and the switch SW1 are provided in parallel. Similarly, a plurality of series connection circuits of a capacitor C2 and a switch SW2 are provided in parallel between the other end E2 of the receiving antenna 301 and the ground. According to this configuration, the parallel resonance frequency can be switched between a plurality of values, and an appropriate parallel resonance frequency can be selected during FSK communication in accordance with the operation status of the power feeding system 100. Therefore, ringing can be further suppressed. Also in FIG. 12C, the resistor R1 can be omitted.

  In the Qi standard, the modulator 308 is connected to the receiving antenna 301 and is configured to change the parallel resonance frequency fd of the receiving antenna 301 in accordance with the AM modulation signal S22. Therefore, the ringing suppressor 380 acts on the AM modulator 308 and can suppress ringing by using the function of the modulator 308.

Specifically, the modulator 308 has the same configuration as the ringing suppressor 380a of FIG. 13A and 13B are circuit diagrams of the modulator 308 and the ringing suppressor 380. FIG. As shown in FIG. 13A, the modulator 308 includes capacitors C _CM1 and C _CM2 and switches SW11 and SW12. The switches SW11 and SW12 are switched according to the AM modulation signal S22. The ringing suppressor 380 turns on the switches SW11 and SW12 during reception of the FSK signal. C _CM1 , C _CM2 , SW11, SW12 of the modulator 308 in FIG. 13A can be associated with C1, C2, SW1, SW2 in FIG. 12A, and the modulator 308 and the ringing suppressor 380 are It is understood that some circuit elements are shared.

  FIG. 13B shows a configuration example of the ringing suppressor 380. The ringing suppressor 380 includes a first logic gate 384 that performs a logical operation on the AM modulation signal S22 and the reception period signal S21. When the assertion of the reception period signal S21 is at a high level, the first logic gate 384 can be configured by an OR gate. The first switch SW1 and the second switch SW2 are controlled according to the output signal S23 of the first logic gate 384.

  During the period in which the reception period signal S21 is asserted (high level), the signal S23 is high level and the switch SW1 (SW2) is turned on. During the period in which the reception period signal S21 is negated (low level), the signal S23 takes a level corresponding to the AM modulation signal S22, and the switch SW1 (SW2) switches according to the AM modulation signal S22.

  The shift of the parallel resonance frequency fd by the ringing suppressor 380 may be switched between valid and invalid. The ringing suppressor 380 further includes a register 386 that stores control data S24 instructing validity / invalidity. For example, the control data S24 becomes 0 (low level) when invalidating the frequency shift by the ringing suppressor 380, and becomes 1 (high level) when validating. The second logic gate 388 performs a logical operation on the control data S24 and the reception period signal S21. For example, the second logic gate 388 is an AND gate. If the control data S24 is 0, the output of the second logic gate 388 is fixed at a low level regardless of the reception period signal S21. When the control data S24 is 1, the output of the second logic gate 388 has the same logic level as the reception period signal S21.

FIG. 14A is an operation waveform diagram of the power receiving apparatus 300 including the modulator 308 and the ringing suppressor 380 of FIG. This waveform diagram shows that in the actual power receiving apparatus 300, the switches SW11 and SW12 of the modulator 308 are turned on during the reception period of the FSK signal, and the voltages V _AC1 and V _AC2 and the AC1_DET signal and the AC2_DET signal of the AC1 terminal and AC2 terminal are shown. Was measured with an oscilloscope. Note that the AC1_DET signal and the AC2_DET signal are outputs of the comparators 334 and 336 in FIG.

For comparison, FIG. 14B shows a waveform when the switches SW11 and SW12 of the modulator 308 are turned off during the reception period of the FSK signal. Thus, by shifting the parallel resonance frequency fd, ringing of the voltages V _AC1 and V _{AC2 at} the AC1 terminal and the AC2 terminal can be suppressed.

(Use)
Applications of the power receiving device 300 according to the various embodiments described above will be described. FIG. 15 is a perspective view of an electronic device 500 including the power receiving device 300. The electronic device 500 is a mobile phone terminal, a smart phone, a tablet PC, a portable audio player, a digital camera, a digital video camera, or the like, and is a battery-driven device. Electronic device 500 includes secondary battery 102 and power receiving device 300. The synchronous rectifier circuit 304, the demodulator 320, the modulator 308, the controller 312, and the charging circuit 314 may be integrated on one or a plurality of semiconductor chips.

  In the embodiment, the wireless power transmission apparatus conforming to the Qi standard has been described. However, the present invention is not limited thereto, and the power receiving apparatus 300 used in a system similar to the Qi standard or a standard that will be established in the future. The present invention can also be applied to a compliant power receiving device 300.

  The assignment of the high level, low level, positive edge, and negative edge of each signal described in the embodiment is merely an example, and can be arbitrarily changed by those skilled in the art.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Power feeding system, 102 ... Secondary battery, 200, TX ... Power transmission device, 201 ... Transmitting antenna, 202 ... Transmitting coil, 203 ... Resonant capacitor, 204 ... Inverter, 206 ... Controller, 208 ... Demodulator, 300, RX ... Power receiving device, 301 ... receiving antenna, 302 ... receiving coil, 304 ... synchronous rectifier circuit, 306 ... smoothing capacitor, 308 ... modulator, 312 ... controller, 314 ... charging circuit, 320 ... demodulator, 330 ... H bridge circuit, 331 Synchronous rectification controller 332 Driver 334 First comparator 336 Second comparator 338 Logic circuit 350 Demodulator CMP1 First comparator CMP2 Second comparator 352 Clock generation circuit 354 ... Frequency detection circuit, 360 ... Inverter, 362 First chattering removal circuit, 364 ... second chattering removal circuit, 366 ... first one-shot circuit, 368 ... second one-shot circuit, 370 ... logic circuit, 372 ... digital counter, 380 ... ringing suppressor, 382 ... control circuit , SW1... First switch, SW2... Second switch, R1... Resistor, S21... Reception period signal, S22... AM modulation signal, S11.

Claims (20)

A wireless power receiver that receives a power signal from a wireless power transmitter,
A receiving antenna including a receiving coil for receiving the power signal;
A rectifying circuit for rectifying an alternating current flowing through the receiving antenna;
A smoothing capacitor for smoothing the output of the rectifier circuit;
A demodulator that demodulates the power signal subjected to FSK (Frequency Shift Keying);
With
The rectifier circuit is
An H-bridge circuit having a first AC input terminal and a second AC input terminal connected to the receiving antenna;
A synchronous rectifier controller for controlling the H-bridge circuit;
Including
The demodulator
A first comparator for comparing the voltage of the first AC input terminal with a first threshold voltage and generating a first detection signal;
A second comparator for comparing the voltage of the second AC input terminal with a second threshold voltage and generating a second detection signal;
A clock generation circuit that generates a frequency detection clock that transitions according to one edge of the first detection signal and one edge of the second detection signal;
A frequency detection circuit for detecting a frequency of the frequency detection clock;
A wireless power receiving apparatus comprising: A method of demodulating a power signal transmitted from a wireless power transmitting apparatus and subjected to FSK (Frequency Shift Keying),
A receiving antenna including a receiving coil receives the power signal;
An H-bridge circuit connected to the receiving antenna rectifies an alternating current flowing through the receiving antenna;
Comparing a voltage of a first AC input terminal, which is one connection point of the H-bridge circuit and the receiving antenna, with a first threshold voltage, and generating a first detection signal;
Comparing the voltage of the second AC input terminal, which is the other connection point of the H-bridge circuit and the receiving antenna, with a second threshold voltage, and generating a second detection signal;
Generating a frequency detection clock that transitions according to one edge of the first detection signal and one edge of the second detection signal;
Detecting the frequency of the frequency detection clock;
A demodulation method comprising: A wireless power receiver that receives a power signal from a wireless power transmitter,
A receiving antenna including a receiving coil for receiving the power signal;
A rectifying circuit for rectifying an alternating current flowing through the receiving antenna;
A smoothing capacitor for smoothing the output of the rectifier circuit;
A demodulator that demodulates the power signal subjected to FSK (Frequency Shift Keying);
A ringing suppressor that shifts a parallel resonant frequency of the receiving antenna during reception of an FSK signal;
A wireless power receiving apparatus comprising: The ringing suppressor is
A first capacitor and a first switch provided in series between one end of the receiving antenna and the ground;
A second capacitor and a second switch provided in series between the other end of the receiving antenna and the ground;
A control circuit for controlling the first switch and the second switch;
The wireless power receiving apparatus according to claim 3, comprising:   The wireless power receiving apparatus according to claim 4, wherein the ringing suppressor further includes a resistor provided between a connection node of the first switch and the second switch and a ground. An AM modulator connected to the receiving antenna and changing a parallel resonant frequency of the receiving antenna according to an AM modulation signal;
The wireless power receiving apparatus according to claim 3, wherein the ringing suppressor acts on the AM modulator. The AM modulator is
A first capacitor and a first switch provided in series between one end of the receiving antenna and the ground;
A second capacitor and a second switch provided in series between the other end of the receiving antenna and the ground;
Including
The ringing suppressor includes a logic gate that performs a logical operation on the AM modulation signal and a reception period signal indicating a reception period of the FSK signal, and based on an output signal of the logic gate, the first switch and the first switch The wireless power receiving apparatus according to claim 6, wherein two switches are controlled. The rectifier circuit is
An H-bridge circuit having a first AC input terminal and a second AC input terminal connected to the receiving antenna;
A synchronous rectifier controller for controlling the H-bridge circuit;
Including
The demodulator
A first comparator for comparing the voltage of the first AC input terminal with a first threshold voltage and generating a first detection signal;
A second comparator for comparing the voltage of the second AC input terminal with a second threshold voltage and generating a second detection signal;
A clock generation circuit that generates a frequency detection clock that transitions according to one edge of the first detection signal and one edge of the second detection signal;
A frequency detection circuit for detecting a frequency of the frequency detection clock;
The wireless power receiving apparatus according to claim 3, further comprising:   9. The wireless device according to claim 1, wherein the clock generation circuit generates the frequency detection clock according to a positive edge of the second detection signal and a negative edge of the subsequent first detection signal. Power receiving device. The clock generation circuit includes:
An inverter for inverting the first detection signal;
A logic circuit for generating the frequency detection clock according to the second detection signal and the first detection signal inverted by the inverter;
The wireless power receiving apparatus according to claim 9, comprising:   The wireless power receiving apparatus according to claim 10, wherein the clock generation circuit retimes the inverted first detection signal and the second detection signal using an internal clock. The clock generation circuit includes:
A first chattering elimination circuit that makes the transition effective when the first detection signal takes the same level over M cycles of the internal clock (M is an integer of 2 or more);
A second chattering elimination circuit that makes the transition effective when the second detection signal takes the same level over N cycles (N is an integer of 2 or more) of the internal clock;
The wireless power receiving apparatus according to claim 11, further comprising: The clock generation circuit includes:
A first one-shot circuit provided on a path of the inverted first detection signal;
A second one-shot circuit provided on the path of the second detection signal;
The wireless power receiving apparatus according to claim 9, further comprising:   The wireless power receiving apparatus according to claim 11, wherein the frequency detection circuit measures the frequency of the frequency detection clock using the internal clock.   The wireless power receiving device according to claim 8, wherein the clock generation circuit generates the frequency detection clock according to a negative edge of the second detection signal and a negative edge of the first detection signal that follows the negative edge of the second detection signal. .   The wireless power receiving device according to any one of claims 8 to 15, wherein the synchronous rectification controller controls the bridge circuit based on the first detection signal and the second detection signal.   17. The wireless power receiving apparatus according to claim 1, wherein the wireless power receiving apparatus conforms to a Qi standard.   An electronic apparatus comprising the wireless power receiving device according to claim 1. A method of demodulating a power signal transmitted from a wireless power transmitting apparatus and subjected to FSK (Frequency Shift Keying),
A receiving antenna including a receiving coil receives the power signal;
An H-bridge circuit connected to the receiving antenna rectifies an alternating current flowing through the receiving antenna;
Demodulating the power signal subjected to FSK (Frequency Shift Keying);
Changing the parallel resonant frequency of the receiving antenna during reception of the FSK signal;
A demodulation method comprising: Comparing a voltage of a first AC input terminal, which is one connection point of the H-bridge circuit and the receiving antenna, with a first threshold voltage, and generating a first detection signal;
Comparing the voltage of the second AC input terminal, which is the other connection point of the H-bridge circuit and the receiving antenna, with a second threshold voltage, and generating a second detection signal;
Generating a frequency detection clock that transitions according to one edge of the first detection signal and one edge of the second detection signal;
Detecting the frequency of the frequency detection clock;
The demodulation method according to claim 19, further comprising:

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