JP2017195280A - Method for manufacturing laminated electronic component and laminated electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a laminated electronic component capable of suppressing peeling of a laminated structure from a substrate and a laminated electronic component.SOLUTION: The method includes steps of: preparing a substrate 1; and forming a laminated structure 20 for a laminated electronic component on the substrate 1. The step of forming the laminated structure 20 is a step of forming a supporting layer 5 of the laminated structure 20 on the substrate 1, and includes: a step in which a part of the support layer 5 is fixed to the substrate 1 and a gap G or a low Young's modulus member 31 is interposed between the other part of the support layer 5 and the substrate 1, and a step of forming a laminated portion 10 other than the supporting layer 5 of the laminated structure 20 on the supporting layer 5 such that at least a part of the laminated portion 10 overlaps the gap G or the low Young's modulus member 31 in plan view .SELECTED DRAWING: Figure 10

Description

  The present invention relates to a method of manufacturing a laminated electronic component and a laminated electronic component.

  As an electronic component that can be made thinner, a laminated electronic component in which a laminated structure including a plurality of layers for the electronic component is formed on a substrate is known. Examples of such multilayer electronic components include thin film capacitors as described in Patent Documents 1 and 2 below. In these thin film capacitors, a laminated structure including a lower electrode layer, an upper electrode layer, and a dielectric layer provided between these electrode layers is formed on a substrate.

JP 2004-281446 A JP 2011-228462 A

  It is known that internal stress occurs in a film formed on a substrate due to a difference in coefficient of thermal expansion between the substrate and the material constituting the film. When this internal stress increases, it causes peeling of the film. Therefore, even in the multilayer electronic component as described above, an internal stress is generated in each layer of the multilayer structure for the multilayer electronic component formed on the substrate. When the internal stress is increased, there is a problem that the laminated structure may be peeled off from the substrate at the time of manufacturing and using the laminated electronic component.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method for manufacturing a multilayer electronic component and a multilayer electronic component capable of suppressing the multilayer structure from peeling from the substrate.

  In order to solve the above-mentioned problems, a method of manufacturing a multilayer electronic component according to the present invention includes a step of preparing a substrate and a step of forming a multilayer structure for the multilayer electronic component on the substrate, the multilayer structure Forming a support layer having a laminated structure on the substrate, wherein a part of the support layer is fixed to the substrate, and the other part of the support layer is interposed between the substrate and the substrate. A step of interposing a low Young's modulus member having a Young's modulus smaller than that of the gap or the substrate, and a laminated portion other than the support layer of the laminated structure, and at least a part of the laminated portion in the plan view, Forming on the support layer so as to overlap with the member.

  According to the method of manufacturing a multilayer electronic component according to the present invention, even if stress is generated in the multilayer structure due to a difference in materials constituting the substrate and each layer of the multilayer structure, at least one of the stresses. The part is absorbed by the gap or the low Young's modulus member. Thereby, compared with the case where the whole support layer is being fixed to the board | substrate, it becomes possible to reduce the stress which remains in a laminated structure. As a result, it is possible to prevent the laminated structure from peeling from the substrate.

  In order to solve the above-described problems, a multilayer electronic component according to the present invention includes a substrate and a multilayer structure for the multilayer electronic component provided on the substrate, and the multilayer structure includes a support layer and the above-described multilayer structure. A part provided on the support layer, a part of the support layer is fixed to the substrate, and a Young's modulus is smaller than the gap or the substrate between the other part of the support layer and the substrate. A low Young's modulus member is interposed, and at least a part of the laminated portion overlaps the gap or the low Young's modulus member in plan view.

  According to the multilayer electronic component according to the present invention, even if stress is generated in the multilayer structure due to a difference in materials constituting the substrate and each layer of the multilayer structure, at least a part of the stress is It is absorbed by the gap or the low Young's modulus member. Thereby, compared with the case where the whole support layer is being fixed to the board | substrate, it becomes possible to reduce the stress which remains in a laminated structure. As a result, it is possible to suppress the peeling of the laminated structure.

  ADVANTAGE OF THE INVENTION According to this invention, the method and laminated electronic component which manufacture the laminated electronic component which can suppress that a laminated structure peels from a board | substrate are provided.

It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is an end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is an end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is an end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 1st Embodiment. It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 2nd Embodiment. It is the top view and end view for demonstrating the method to manufacture the multilayer electronic component of 2nd Embodiment. It is the top view and end view which show the modification of 1st Embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements when possible. In addition, the dimensional ratios in the components in the drawings and between the components are arbitrary for easy viewing of the drawings.

(First embodiment)
A method for manufacturing a multilayer electronic component and a multilayer electronic component according to a first embodiment of the present invention will be described. 1 to 6 and 10 are a plan view (A) and an end view (B) for explaining a method of manufacturing the multilayer electronic component of the first embodiment, and FIGS. It is an end view for demonstrating the method to manufacture the multilayer electronic component of embodiment.

  In the method according to the present embodiment, first, as shown in FIG. 1A and the end view taken along line IB-IB of the plan view, as shown in FIG. Prepare. The substrate 1 has, for example, a plate shape having a substantially flat surface 1S. The substrate 1 is made of, for example, Si, various ceramics, glass, or the like, and a surface layer made of an insulating material such as alumina or silicon oxide may be formed on the surface 1S with a thickness of about 3 μm, for example.

  Subsequently, as shown in FIG. 1, a photoresist layer 3 having a predetermined shape is formed by applying a photoresist mainly composed of novolac, polystyrene, polyimide, epoxy, etc. on the surface 1S of the substrate 1 and then patterning it. Form. The photoresist layer 3 substantially corresponds to the shape of the gap G (see FIG. 5) formed in a later step.

  Specifically, the photoresist layer 3 has, for example, a substantially rectangular shape in plan view (viewed from a direction orthogonal to the surface 1S of the substrate 1, that is, viewed from the stacking direction of each layer), and is 0.01 μm or more And a thickness of 3.00 μm or less. Further, the photoresist layer 3 has two openings 3h at the center. In this embodiment, since the photoresist layer 3 is removed in a later process (see FIGS. 4 and 5), the photoresist layer 3 is not subjected to heat treatment after the formation of the photoresist layer 3 for easy removal. be able to.

  Next, as shown in the plan view of FIG. 2A and the end view along the line IIB-IIB of the plan view, as shown in FIG. 2B, on the surface 1S and the photoresist layer 3 The insulating layer 5a is formed by a sputtering method or the like. The insulating layer 5 a is also formed in the opening 3 h of the photoresist layer 3.

  The insulating layer 5a is preferably made of a material that reduces the internal stress when formed on the surface 1S of the substrate 1, and can be formed of an insulating material such as alumina, silicon oxide, silicon nitride, or the like. The thickness of the insulating layer 5a can be, for example, 1 μm or more and 10 μm or less. In the region where the photoresist layer 3 does not exist, the insulating layer 5a may be fixed directly in contact with the surface 1S of the substrate 1 or may be fixed to the surface 1S of the substrate 1 through another member such as an adhesive layer. It may be.

  Subsequently, as shown in FIG. 3A and an end view taken along the line IIIB-IIIB in FIG. 3B, a novolac, polystyrene is formed on the insulating layer 5a. A photoresist layer 7 having a predetermined shape is formed by applying a photoresist mainly composed of, for example, and then patterning. The shape of the photoresist layer 7 corresponds to a support layer 5 (see FIGS. 4 to 6) described later. The photoresist layer 7 has a portion overlapping with the photoresist layer 3 and a portion not overlapping with the photoresist layer 3 in plan view.

  In the present embodiment, the photoresist layer 7 has a shape substantially corresponding to the photoresist layer 3 in plan view, and a central portion that covers the opening 3h (see FIG. 2) of the photoresist layer 3, and an outer portion from the central portion. A plurality of protrusions 7 </ b> P extending toward the direction. Since the central portion of the photoresist layer 7 is slightly smaller than the photoresist layer 3 in plan view, a part of the outer edge portion of the photoresist layer 3 is not covered with the photoresist layer 7.

  Each of the plurality of protrusions 7P extends from the central portion of the photoresist layer 7 to a region that does not overlap with the photoresist layer 3 in plan view. In the present embodiment, the central portion of the photoresist layer 7 has a rectangular shape in plan view, and two protruding portions 7P extend from each of the pair of sides facing each other, and from each of the other pair of sides facing each other, Three projecting portions 7P extend.

  Next, as shown in FIG. 4A and FIG. 4B, which is an end view taken along the line IVB-IVB of the plan view, using the photoresist layer 7 as a mask. Then, the part of the outer edge portion of the insulating layer 5a and the photoresist layer 3 is etched by ion milling, reactive ion etching, or the like. Thereby, the support layer 5 having a shape corresponding to the photoresist layer 7 is formed. At this time, since the part of the outer edge portion of the photoresist layer 3 is etched, a part of the side surface portion of the photoresist layer 3 is exposed.

  Subsequently, as shown in FIG. 5A, which is a plan view of FIG. 5A, and an end view taken along the line VB-VB of the plan view, as shown in FIG. The lower photoresist layer 3 is removed by dissolution with an organic solvent such as isopropyl alcohol or acetone, ashing, or reactive ion etching. The photoresist layer 7 and the photoresist layer 3 may be removed simultaneously in the same process as described above, or each may be removed in a separate process. As described above, since a part of the side surface portion of the photoresist layer 3 is exposed after the step shown in FIG. 4, the photoresist layer 3 can be removed from the exposed portion.

  By this step, a gap G is formed in a region where the photoresist layer 3 between the surface 1S of the substrate 1 and the support layer 5 was present. The support layer 5 has a central portion and a plurality of protruding portions 5P extending outward from the central portion in plan view. In the present embodiment, the central portion of the support layer 5 has a rectangular shape in plan view, and two protruding portions 5P extend from each of a pair of opposite sides thereof, and from each of the other pair of opposite sides, 3 Two protrusions 5P extend.

  In FIG. 5A, the region of the support layer 5 that is fixed to the surface 1S of the substrate 1 is hatched. Of the support layer 5, most of the plurality of protruding portions 5P and a portion corresponding to the insulating layer 5a formed in the opening 3h of the photoresist layer 3 in the step shown in FIG. 2 are fixed to the surface 1S of the substrate 1. Has been. Other portions of the support layer 5 are not fixed to the surface 1S of the substrate 1.

  That is, in FIG. 5A, a gap G is formed between a region of the support layer 5 that is not hatched and the surface 1S of the substrate 1. The hatched region of the support layer 5 may be fixed directly in contact with the surface 1S of the substrate 1 or may be fixed to the surface 1S of the substrate 1 through another member such as an adhesive layer.

  Next, as shown in FIG. 6A and FIG. 6B, which is an end view taken along the line VIB-VIB of the plan view, the laminated portion 10 is formed on the support layer 5. Form. The support layer 5 supports the stacked portion 10. The support layer 5 and the laminated portion 10 constitute a laminated structure 20 for a laminated electronic component. In the present embodiment, a part of the laminated part 10 overlaps with the gap G in plan view, and the other part of the laminated part 10 is a region fixed to the surface 1S of the substrate 1 in the support layer 5. The stacked portion 10 is formed on the support layer 5 so as to overlap.

  In the present embodiment, the multilayer structure 20 is a multilayer structure for a thin film capacitor. An example of forming the laminated portion 10 in that case will be described with reference to FIGS. 7 to 9 are end views for explaining a process of forming the laminated portion 10. In the step of forming the laminated portion 10, first, as shown in FIG. 7A, the internal electrode layer 11a, the dielectric film 13a, and the upper electrode layer 15a are formed in this order on the support layer 5 by DC sputtering or the like. To do.

  Subsequently, as shown in FIG. 7B, after applying a photoresist to the surface of the upper electrode layer 15a, the upper electrode 15 (see FIG. 9B) included in the completed stacked portion 10 is formed by photolithography. A mask 17a having a pattern corresponding to (see) is formed. After the formation of the mask 17a, as shown in FIG. 7C, the upper electrode layer 15a is etched with an etching solution such as an ammonium persulfate aqueous solution to form the upper electrode 15. After the upper electrode 15 is formed, the mask 17a covering the surface of the upper electrode 15 is removed by peeling or the like.

  Next, as shown in FIG. 8A, after the photoresist is applied to the surfaces of the upper electrode 15 and the dielectric film 13a, the dielectric layer 13 (see FIG. A mask 17b having a pattern corresponding to 9) is formed. After the formation of the mask 17b, as shown in FIG. 8B, the dielectric film 13a is etched with an etchant such as a mixed solution of hydrochloric acid and ammonium fluoride to form the dielectric layer 13. After the dielectric layer 13 is formed, the upper electrode 15 and the mask 17b that covers the surface of the dielectric layer 13 are removed by peeling or the like.

Next, as shown in FIG. 8C, after the photoresist is applied to the surfaces of the upper electrode 15, the dielectric layer 13, and the internal electrode layer 11a, the internal electrode provided with the completed stacked portion 10 by photolithography. A mask 17c having a pattern corresponding to 11 is formed. After the formation of the mask 17c, as shown in FIG. 9A, the internal electrode layer 11a is etched with an etching solution such as an iron chloride (FeCl ₃ ) aqueous solution to form the internal electrode 11. After the internal electrode 11 is formed, the upper electrode 15, the dielectric layer 13, and the mask 17c that covers the surface of the internal electrode 11 are peeled off.

  Subsequently, as shown in FIG. 9B, a cover layer 19 made of an insulating material such as a resin such as polyimide is formed so as to cover the internal electrode 11, the dielectric layer 13, and the upper electrode 15, and the cover layer 19, a through hole 19 a penetrating from the upper surface of the cover layer 19 to the upper surface of the upper electrode 15 and a through hole 19 b penetrating from the upper surface of the cover layer 19 to the internal electrode 11 are formed. Thereby, the lamination | stacking part 10 is completed.

  After the laminated portion 10 is completed, as shown in the plan view of FIG. 10A and the end view along the XB-XB line of the plan view, as shown in FIG. Terminal electrodes 25 and 27 are formed on the substrate. In the present embodiment, the terminal electrodes 25 and 27 are formed on the stacked portion 10 and are not in contact with the support layer 5 and the substrate 1. The terminal electrode 25 is electrically connected to the upper electrode 15 through the through hole 19a, and the terminal electrode 27 is electrically connected to the internal electrode 11 through the through hole 19b (see FIG. 9). . In this way, the multilayer electronic component 100 according to this embodiment is completed.

  According to the method for manufacturing the multilayer electronic component according to the present embodiment as described above and the multilayer electronic component according to the present embodiment, it is caused by the difference in the material constituting the substrate 1 and each layer of the multilayer structure 20. Even if stress occurs in the laminated structure 20, at least a part of the stress is absorbed by the gap G (see FIG. 10). That is, even if such stress occurs, the portion of the support layer 5 of the laminated structure 20 that is in contact with the gap G can be distorted toward the substrate 1 side or toward the opposite side of the substrate 1. Therefore, the stress is relieved.

  Thereby, compared with the case where the whole support layer is being fixed to the board | substrate 1, it becomes possible to reduce the stress which remains in the laminated structure 20. FIG. As a result, it is possible to prevent the laminated structure 20 from peeling from the substrate 1. In addition, since the stress remaining in the stacked structure 20 can be reduced, the range of selection of combinations of materials and formation methods of the layers of the substrate 1 and the stacked structure 20 is expanded.

(Second Embodiment)
Next, a method for manufacturing a multilayer electronic component and a multilayer electronic component according to a second embodiment of the present invention will be described. In the description of the second embodiment, the same elements as those in the first embodiment are denoted by the same reference numerals, and the detailed description thereof may be omitted. 11 and 12 are a plan view (A) and an end view (B) for explaining a method of manufacturing the multilayer electronic component of the second embodiment.

  The method of manufacturing the multilayer electronic component of the present embodiment is different from the method of manufacturing the multilayer electronic component of the first embodiment in the step of forming the support layer 5. FIG. 11 shows a step corresponding to the step shown in FIG. 5 of the first embodiment.

  As shown in the plan view of FIG. 11A and the end view along the XIB-XIB line in the plan view of FIG. 11B, in this embodiment, the gap in the first embodiment is used. The low Young's modulus member 31 is formed in the region where G has been formed. That is, a part of the support layer 5 is fixed to the substrate 1, and the low Young's modulus member 31 is interposed between the other part of the support layer 5 and the substrate 1. Form. The low Young's modulus member 31 is a member having a Young's modulus smaller than that of the substrate 1.

  In the step of forming the laminated portion 10 on the support layer 5, a part of the laminated portion 10 overlaps the low Young's modulus member 31 in plan view, and the other part of the laminated portion 10 is the support layer 5. The stacked portion 10 is formed so as to overlap with the region fixed to the surface 1S of the substrate 1.

  As a material constituting the low Young's modulus member 31, for example, a resin such as novolac, epoxy, polyimide, and acrylic resin is preferably used. However, glass or a metal such as magnesium, lead, gold, or zinc, or these metals An alloy containing at least one of them can also be used.

  Further, the low Young's modulus member 31 may not be fixed to the support layer 5 and / or the substrate 1. The low Young's modulus member 31 may be fixed to the support layer 5 and / or the substrate 1. In this case, the bonding force between the support layer 5 and the substrate 1 through the low Young's modulus member 31 is low Young's modulus. It is preferably weaker than the bonding force between the support layer 5 and the substrate 1 in the region where the member 31 does not exist (corresponding to the hatched region of the support layer 5 in FIG. 5).

  As a method of forming such a low Young's modulus member 31, for example, in the step shown in FIG. 2 of the first embodiment, a low Young's modulus member is formed instead of the photoresist layer 3, and the first embodiment is formed. In the step shown in FIG. 5, a method of removing only the photoresist layer 7 without removing the low Young's modulus layer covered with the support layer 5 can be mentioned. As another method, in the step shown in FIG. 2 of the first embodiment, the photoresist layer 3 is cured by heating after forming the photoresist layer 3, and in the step shown in FIG. 5 of the first embodiment, There may be mentioned a method in which the low Young's modulus member 31 is formed without removing the photoresist layer 3 covered with the support layer 5 and only the photoresist layer 7 is removed.

  After forming the support layer 5 in this manner, the steps shown in FIGS. 6 to 10 of the first embodiment are performed in the same manner, whereby the multilayer electronic component 200 of the second embodiment as shown in FIG. 12 can be obtained. it can. FIG. 12 shows a step corresponding to FIG. 10 of the first embodiment. As shown in FIG. 12B, which is a plan view of FIG. 12A and an end view taken along the line XIIB-XIIB of the plan view, the multilayer electronic component 200 is provided for a multilayer electronic component. It has the laminated structure 40, and the support layer 5, the laminated part 10, and the low Young's modulus member 31 constitute the laminated structure 40.

  According to the method for manufacturing the multilayer electronic component according to the present embodiment as described above and the multilayer electronic component according to the present embodiment, it is caused by the difference in the material constituting the substrate 1 and each layer of the multilayer structure 20. Even if stress occurs in the laminated structure 20, at least a part of the stress is absorbed by the low Young's modulus member 31 (see FIG. 12).

  That is, since the low Young's modulus member 31 is a member having a Young's modulus smaller than that of the substrate 1, the low Young's modulus of the support layer 5 of the laminated structure 20 is lower than that when the entire support layer is fixed to the substrate 1. The portion in contact with the rate member 31 tends to be distorted toward the substrate 1 side or toward the side opposite to the substrate 1. Therefore, the stress generated in the laminated structure 20 is relaxed. As a result, the laminated structure 40 can be prevented from peeling from the substrate 1. In addition, since the stress remaining in the stacked structure 40 can be reduced, the range of selection of combinations of materials and formation methods of the layers of the substrate 1 and the stacked structure 40 is expanded. Further, as compared with the case where the gap G is provided between the support layer 5 and the substrate 1 as in the first embodiment, it is possible to suppress the multilayer structure 20 from being greatly distorted by stress. Is possible.

  The present invention is not limited to the above-described embodiment, and various modifications can be made.

  For example, the shape of the terminal electrodes 25 and 27 in the multilayer electronic component 100 of the first embodiment is not limited to the above. FIG. 13 shows a modification of the first embodiment, and corresponds to FIG. 10 of the first embodiment. As shown in FIG. 13A which is a plan view of FIG. 13A and an end view taken along the line XIIIB-XIIIB of the plan view, the multilayer electronic component 100X of the present modification includes terminal electrodes. This is different from the multilayer electronic component 100 of the first embodiment in the point of the shape. As illustrated in FIG. 13, the terminal electrodes 25X and 27X of the multilayer electronic component 100 according to the present modification extend from the multilayer portion 10 to the surface 1S of the substrate 1 via the support layer 5, respectively. ing. In the multilayer electronic component 200 of the second embodiment, a terminal electrode having a similar configuration can be used.

  In the multilayer electronic components 100 and 200 of the first and second embodiments described above, the multilayer structures 20 and 40 are multilayer structures for thin film capacitors (see FIGS. 10 and 12). A laminated structure for an inductor, a semiconductor element or the like may be used, or a laminated structure for a module device in which a circuit is formed by combining a plurality of these devices.

  In the multilayer electronic components 100 and 200 of the first and second embodiments described above, a part of the center part and a part of the end part of the support layer 5 are fixed to the surface 1S of the substrate 1. (Refer FIG. 5), it is not restricted to such an aspect, For example, only a part of center part of the support layer 5 may be fixed to the surface 1S of the board | substrate 1, or a part of edge part of the support layer 5 Only the surface 1S of the substrate 1 may be fixed. Alternatively, the support layer 5 may be fixed to the surface 1S of the substrate 1 in a so-called cantilever shape by fixing only one end portion of the support layer 5 to the surface 1S of the substrate 1.

  In the multilayer electronic components 100 and 200 of the first and second embodiments described above, the support layer 5 is made of an insulating material (see FIGS. 2 to 5), but the outermost surface is made of an insulating material. A laminated structure of an insulating material and a conductive material such as a metal may be taken.

  Further, in the multilayer electronic components 100 and 200 of the first and second embodiments described above, the multilayer portion 10 is overlapped with the gap G or the low Young's modulus member 31 in a plan view. The other part of the laminated layer 10 is formed on the support layer 5 so as to overlap the region of the support layer 5 fixed to the surface 1S of the substrate 1 (see FIGS. 6 and 12). The laminated portion 10 may be formed on the support layer 5 so that the entire laminated portion 10 overlaps with the gap G or the low Young's modulus member 31 in plan view.

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 5 ... Supporting layer, 10 ... Laminate part, 20 ... Laminated structure for laminated electronic components, 31 ... Low Young's modulus member, 100 ... Laminated electronic component, G ... Gap.

Claims (2)

Preparing a substrate;
Forming a laminated structure for a laminated electronic component on the substrate;
With
The step of forming the laminated structure includes
Forming a support layer of the laminated structure on the substrate, wherein a part of the support layer is fixed to the substrate, and a gap or a gap between the other part of the support layer and the substrate A low Young's modulus member having a Young's modulus smaller than that of the substrate is interposed;
Forming a laminated part other than the support layer of the laminated structure on the support layer so that at least a part of the laminated part overlaps the gap or the low Young's modulus member in plan view;
A method for manufacturing a laminated electronic component, comprising: A substrate,
A laminated structure for a laminated electronic component provided on the substrate;
With
The laminated structure has a support layer and a laminated portion provided on the support layer,
A part of the support layer is fixed to the substrate, a gap or a low Young's modulus member having a Young's modulus smaller than the substrate is interposed between another part of the support layer and the substrate,
At least a part of the laminated portion is a laminated electronic component that overlaps with the gap or the low Young's modulus member in plan view.

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