JP2017191964A - AD converter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AD conversion circuit improved in accuracy, which can keep down a consumed current because of using a conventional comparator slow in response, having an offset.SOLUTION: An AD conversion circuit comprises: a temporary high-order bit voltage select circuit for producing a temporary high-order bit voltage signal based on a result of comparison of an input voltage with a high-order bit reference voltage; a comparator circuit with high accuracy for comparing the input voltage with the temporary high-order bit voltage signal; a high-order bit digital data correction-encoding circuit for producing data by correcting high-order bit digital data based on an output of the comparator circuit with high accuracy; and a low-order bit reference voltage select switch group for selecting a low-order bit reference voltage in connection with the high-order bit digital data. The input voltage is compared with the low-order bit reference voltage to produce low-order bit digital data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an AD conversion circuit that converts an analog signal into a digital signal and outputs the digital signal.

  In recent years, in digital electrical products, for example, image processing has been highly refined, and high resolution, high bit, and high speed of an AD conversion circuit are required. Further, for example, in an AD conversion circuit used in an analog front end of a sensor, further lower power consumption is required. Conventional AD converter circuits are difficult to cope with such demands for high resolution, high bits, and high speed.

  FIG. 4 shows an example of a conventional parallel AD converter circuit. The ladder resistor 101 in which the resistor R is connected in series, the comparator group circuit 102 that compares the reference voltage output from the ladder resistor 101 with the input voltage VIN and outputs a high and low voltage, and the output from the comparator group circuit 102 is converted into a digital quantity. And an encoding circuit 103 for converting and outputting. A reference voltage REF output from the operational amplifier is applied to the ladder resistor 101, and a reference voltage is output between the resistors. The input voltage is an analog signal to be converted.

  All comparators to which a reference voltage lower than the input voltage is connected output a high voltage. A comparator connected to a reference voltage higher than that outputs a low voltage. Such an output of the comparator is encoded by the encoding circuit 103 and a digital signal is output. The parallel AD converter circuit is advantageous for high-speed AD conversion because each bit is output simultaneously with a clock with respect to the input voltage VIN.

JP 2011-193340 A

  However, in order to improve the accuracy of such an AD conversion circuit, the accuracy of the comparator must be improved as in Patent Document 1. In addition, an erroneous determination due to a response speed or an offset is an obstacle. If the area of the comparator is increased in order to suppress the offset and increase the response speed, there is a problem that the entire area increases, current further increases, and power consumption increases. For n-bit code signals, 2n-1 comparators are required.

  An object of the present invention is to provide an AD converter circuit that can suppress current consumption and improve accuracy by using a comparator having a conventional offset and a slow response speed.

In order to solve the above problems, the present invention provides a temporary upper bit voltage selection circuit that creates a temporary upper bit voltage signal based on a result of comparing an input voltage with a reference voltage for an upper bit, and the input voltage and the temporary upper bit. It has a high-precision comparator circuit that compares voltage signals,
An upper bit digital data correction encoding circuit for correcting and creating upper bit digital data based on the output of the high precision comparator circuit;
A lower bit reference voltage selection switch group for selecting a lower bit reference voltage related to the upper bit digital data;
An AD conversion circuit comprising a lower bit digital data creation circuit for creating lower bit digital data by comparing the input voltage with the lower bit reference voltage.

  The present invention thereby uses a low-precision comparator for upper bits having a conventional specification size and a conventional offset, so that the area of the comparator can be reduced and the response speed may be slow, so that the current consumption can be suppressed. An AD converter circuit with improved accuracy can be obtained.

  Further, the present invention is the above-described AD conversion circuit, wherein the input using the low-order comparator group circuit for high-order bits provided with a buffer circuit at the input terminal for the input voltage and the input terminal for the high-order bit reference voltage An AD conversion circuit characterized in that a voltage is compared with the upper bit reference voltage.

  Since the AD conversion circuit of the present invention has the above-described configuration, only one high-precision comparator for high-order bits needs to be used. Further, since the low precision comparator connected to the ladder does not require high precision, a low precision comparator having a small area and a low response speed can be used.

  That is, according to the present invention, it is possible to use a comparator having a conventional specification size and a conventional offset while being an AD converter circuit with high accuracy and a fast response speed, thereby reducing the power consumption of the comparator and reducing the manufacturing cost. There is an effect that an AD conversion circuit that can be reduced is obtained.

1 is a circuit diagram illustrating an AD conversion circuit including a high-precision upper-bit digital data creation circuit according to a first embodiment of the present invention. It is a circuit diagram showing the AD converter circuit provided with the highly accurate high-order bit digital data creation circuit of the 2nd Embodiment of this invention. It is a circuit diagram showing the AD converter circuit provided with the highly accurate high-order bit digital data creation circuit of the 3rd Embodiment of this invention. It is a circuit diagram which shows the conventional parallel type AD converter circuit.

<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing the entire circuit of a high-precision upper-bit digital data creation circuit and a 1-bit lower-bit digital data creation circuit in the first embodiment of the AD conversion circuit of the present invention.

(1-bit lower bit digital data creation circuit)
The 1-bit lower-bit digital data creation circuit includes a lower-bit reference voltage selection switch group 6 and a lower-bit comparator circuit B.

(Lower bit reference voltage selection switch group 6)
The lower bit reference voltage selection switch group 6 is controlled by the output data of the upper bit digital data correction encoding circuit 5, and the lower bit reference voltage selection switch group 6 relates to the output data of the upper bit digital data correction encoding circuit 5. The lower bit reference voltage is selected, and the lower bit reference voltage signal is connected to one input terminal of the lower bit comparator circuit B.

  An input voltage VIN is connected to the other input terminal of the lower bit comparator circuit B, and the input voltage VIN is compared with a given lower bit reference voltage.

(High precision upper bit digital data creation circuit)
The high-precision upper-bit digital data creation circuit includes a ladder resistor 1 that connects a plurality of resistance elements in series to generate a plurality of reference voltages, and a low-precision comparator group circuit 2 for high-order bits by a group of low-precision comparators A for high-order bits. The high-order bit voltage selection circuit 3, the high-precision comparator circuit 4, and the high-order bit digital data correction encoding circuit 5. The high-precision comparator circuit 4 has an offset cancel function for reducing the circuit offset voltage and performing a voltage comparison with high accuracy.

(Low precision comparator group circuit 2 for upper bits)
As shown in FIG. 1, the high-precision high-order bit digital data creation circuit is a group of low-order comparators A for high-order bits that compare a high-order bit reference voltage and an input voltage VIN among a plurality of reference voltages generated by the ladder resistor 1. It has a low-precision comparator group circuit 2 for upper bits consisting of

  The output terminal of the binary data signal of the low-order comparator group circuit 2 for the upper bits is connected to the input terminals of the temporary upper bit voltage selection circuit 3 and the upper bit digital data correction encoding circuit 5.

(Temporary upper bit voltage selection circuit 3)
Each temporary high-order bit voltage selection circuit 3 has one 3-input OR circuit 3a, and three high-order bits adjacent in the low-precision comparator group circuit 2 for high-order bits are connected to each input terminal of the 3-input OR circuit. Connect the output terminal of the low precision comparator A.

  Specifically, the output terminal of the low-order high-order bit low-precision comparator A among the three high-order bit low-precision comparators A connected to the temporary high-order bit voltage selection circuit 3 is used as one input terminal of the 3-input OR circuit 3a. Connect to. Then, the output signal terminals obtained by inverting the output signals of the two higher-order bit low-precision comparators A higher than the upper-bit low-precision comparator A by the inverter are connected to the remaining input terminals of the 3-input OR circuit 3a.

  The 3-input OR circuit 3a takes the OR of the 3 inputs and outputs it from the output terminal. The output terminal outputs to the control terminal of the temporary upper bit voltage signal output switch circuit 3b for each temporary upper bit voltage selection circuit 3.

  Here, the output signals of the three low-order comparators A for high-order bits connected to the three input terminals of a certain three-input OR circuit 3a are (logic '1') and (logic '0') in order from the least significant terminal. , (Logic '0'), the three-input OR circuit 3a controls the control terminal of the temporary upper bit voltage signal output switch circuit 3b, and the temporary upper bit voltage signal output switch circuit 3b A bit voltage signal is output.

  The temporary upper bit voltage signal output switch circuit 3b is located above the lowest reference voltage among the three reference voltages connected to the input terminals of the three low precision comparators A connected to the input terminals of the three-input OR circuit 3a. The reference voltage is output as a temporary upper bit voltage signal, and the output terminal is connected to the input terminal of the high-precision comparator circuit 4.

(High-precision comparator circuit 4)
The high-precision comparator circuit 4 is configured as a high-precision chopper type comparator circuit having an offset cancel function. The high-precision chopper comparator compares the temporary high-order bit voltage signal received from the temporary high-order bit voltage selection circuit 3 with the input voltage VIN, and encodes the 1-bit correction signal of the high-order bit digital data of the comparison result as the high-order bit digital data correction encoding. Output to the circuit 5.

(Upper bit digital data correction encoding circuit 5)
The upper bit digital data correction encoding circuit 5 creates binary data of the output signal of the lower bit comparator group circuit 2 for upper bits. Specifically, accurate high-order bit digital data that is 1-bit corrected based on the 1-bit correction signal of the high-order bit digital data received from the high-precision comparator circuit 4 (high-precision chopper type comparator) is created.

(Operation of high-precision upper-bit digital data creation circuit)
Hereinafter, the operation of the high-precision upper-bit digital data creation circuit will be described.

(Temporary upper bit voltage selection circuit 3)
To the three input terminals of the 3-input OR circuit 3 a of the temporary upper bit voltage selection circuit 3, the output terminals of the three higher-order bit low-precision comparators A adjacent in the upper-bit low-precision comparator group circuit 2 are connected.

  In the temporary upper bit voltage selection circuit 3, the output voltage of the lower-order high-bit low-precision comparator A among the three adjacent high-bit low-precision comparators A is a high voltage (logic “1”). When the outputs of the two low-order comparators A for high-order bits subsequent thereto are at a low voltage (logic “0”), a temporary high-order bit voltage signal is output to the temporary high-order bit voltage signal output switch circuit 3b. Let

  The temporary upper bit voltage signal output switch circuit 3b is located above the lowest reference voltage among the three reference voltages connected to the input terminals of the three low precision comparators A connected to the input terminals of the three-input OR circuit 3a. The reference voltage is output to the input terminal of the high precision comparator circuit 4 as a temporary upper bit voltage signal.

(High-precision comparator circuit 4)
The high-precision comparator circuit 4 is configured by a high-precision chopper type comparator circuit having an offset cancel function. The high-precision chopper comparator compares the temporary upper bit voltage signal received from the temporary upper bit voltage selection circuit 3 with the input voltage VIN, and outputs a 1-bit correction signal of the upper bit digital data.

  The high-precision comparator circuit 4 having a circuit configuration of a high-precision chopper type comparator has an output terminal of the switch SW1 connected to the input side of the inverter D via the capacitor C1, and the first input terminal of the switch SW1 is the input voltage VIN. And the second input terminal is connected to the selected temporary upper bit voltage signal. The switch SW1 switches and connects the input voltage VIN and the selected temporary upper bit voltage signal to the capacitor C1. The input of the inverter D is connected to the output terminal of the inverter D via the switch SW2.

  With such a circuit configuration of the high-precision chopper comparator, the high-precision comparator circuit 4 first connects the switch SW2, connects the switch SW1 to the input voltage VIN side, and connects the capacitor C1 to the input voltage VIN (high-precision comparator). (Reducing the threshold voltage). In this case, the threshold potential and the input voltage VIN are applied in series to the input of the inverter D via the capacitor, and offset cancellation is performed.

  Next, the switch SW2 is turned off, and the switch SW1 is switched to the temporary upper bit voltage signal side. Then, the difference between the input voltage VIN charged in the capacitor C1 and the temporary upper bit voltage signal, Δ = temporary upper bit voltage signal −VIN, is applied to the input of the inverter D.

  The high-precision comparator circuit 4 (high-precision chopper comparator) operates with the offset of the inverter D compensated.

  When Δ is positive, the output of the inverter D becomes a low voltage (logic ‘0’). Upon receiving the output signal, the upper bit digital data correction encoding circuit 5 creates normal upper bit digital data from the binary data of the output signal of the upper bit low precision comparator group circuit 2 and outputs it.

  On the other hand, when Δ is negative, the output of the inverter D becomes a high voltage (logic ‘1’). The high-order bit digital data correction encoding circuit 5 that has received the output signal creates normal high-order bit digital data from the binary data of the output signal of the low-precision comparator group circuit 2 for high-order bits and outputs it. To do.

  In this way, even if the accuracy of the comparator circuit 2 is low, high-order bit digital data that is accurately AD-converted can be obtained by using the high-precision comparator circuit 4 in which the offset is canceled.

  In this high-precision upper-bit digital data creation circuit, in particular, the upper-bit low-precision comparator A includes a maximum error because there is a delay in time. Therefore, first, the low-order comparator group circuit 2 for upper bits selects a temporary upper bit voltage signal including an error from a plurality of reference voltages and makes a temporary determination.

  Next, the temporary high-order bit voltage signal is compared with the input voltage VIN by the high-precision comparator circuit 4 (high-precision chopper type comparator) to accurately determine the reference voltage corresponding to the minimum bit, and based on the result, the high-order bit digital The data correction encoding circuit 5 creates and outputs accurate upper bit digital data corrected by 1 bit. As a result, output data that does not include the error of the comparator can be obtained.

(1-bit lower bit digital data creation circuit)
The operation of the 1-bit lower-bit digital data creation circuit will be described below.

(Reference voltage selection switch)
As shown in the circuit diagram of FIG. 1, the lower-bit reference voltage selection switch group 6 is controlled by the high-precision upper-bit digital data created by the upper-bit digital data correction encoding circuit 5 and connected to the lower-bit comparator circuit B. Select and output the lower bit reference voltage. The output terminal is connected to the input terminal of the lower bit comparator circuit B.

  Specifically, the lower-bit reference voltage selection switch group 6 is controlled by the high-precision upper-bit digital data output from the upper-bit digital data correction encoding circuit 5, selects the lower-bit reference voltage selection switch 6a, and closes the circuit. Thus, the lower bit reference voltage is selected and connected to the input terminal of the lower bit comparator circuit B.

(Lower bit comparator circuit B)
The input voltage VIN is connected to the other input terminal of the lower bit comparator circuit B. Then, the binary data of the output signal of the lower bit comparator circuit B is output as the lower bit digital data of the 1 bit lower bit digital data generating circuit.

Thus, the accurate upper bit digital data output from the upper bit digital data correction encoding circuit 5 and the lower bit digital data output from the lower bit comparator circuit B can be combined to obtain digital data that has been accurately AD converted. it can.

  Since the present embodiment has the above-described configuration and operation, a low-precision comparator having a small area with a low-speed specification and having a low-precision offset can be used as a main element. There is an effect that the area of the integrated circuit can be reduced. Further, since the response speed of the comparator to be used may be slow, there is an effect that a high-precision and high-speed AD converter circuit that can suppress the current consumption of the AD converter circuit is obtained.

<Second Embodiment>
A second embodiment of the present invention will be described below with reference to FIG. The AD conversion circuit of the second embodiment has a 2-bit lower bit digital data creation circuit as shown in FIG. Other circuits have a ladder resistor 1 and a high-precision upper-bit digital data creation circuit, as in the first embodiment.

(High precision upper bit digital data creation circuit)
The high-precision upper-bit digital data creation circuit is configured in the same manner as in the first embodiment and operates in the same manner.

(Lower bit digital data creation circuit)
The 2-bit lower-bit digital data creation circuit according to the second embodiment includes a lower-bit reference voltage selection switch group 6, a lower-bit comparator group circuit 2b including a lower-bit comparator circuit B, and a lower-bit encoding circuit. 5b.

(Lower bit reference voltage selection switch group 6)
The lower bit reference voltage selection switch group 6 is controlled by the output data of the upper bit digital data correction encoding circuit 5. The lower-bit reference voltage selection switch group 6 selects a plurality of lower-bit reference voltages related to the output data of the upper-bit digital data correction encoding circuit 5, and uses the lower-bit reference voltage signals as lower-bit comparators. It is connected to the input terminal of each lower bit comparator circuit B of the group circuit 2b.

  The input voltage VIN is connected to the other input terminal of each low-order bit comparator circuit B so that each low-order bit comparator circuit B compares the input voltage VIN with a given reference voltage.

(Operation of lower bit digital data creation circuit)
Hereinafter, the operation of the lower-order bit digital data creation circuit of the second embodiment will be described with reference to FIG.

(Operation of the lower-bit reference voltage selection switch group 6)
As shown in the circuit diagram of FIG. 2, the lower-bit reference voltage selection switch group 6 is generated by the output signal of the higher-order bit digital data correction encoding circuit 5, that is, the high-order higher-order bit digital data generation circuit shown in FIG. Controlled to high-precision digital data. The lower bit reference voltage selection switch group 6 selects a plurality of lower bit reference voltages related to the output data of the upper bit digital data correction encoding circuit 5, and each lower bit comparator of the lower bit comparator group circuit 2b. Connect to circuit B.

More specifically, the lower-bit reference voltage selection switch group 6 is controlled by the high-precision upper-bit digital data output from the upper-bit digital data correction encoding circuit 5, and selects the lower-bit reference voltage selection switch 6a to select a plurality of lower-order bits. A bit reference voltage is selected and connected to each lower bit comparator circuit B of the lower bit comparator group circuit 2b.

  As shown in FIG. 2, the binary data of the output signal of each lower bit comparator circuit B of the lower bit comparator group circuit 2b is guided to the lower bit encoding circuit 5b. The low-order bit encoding circuit 5b uses the output signal of each low-order bit comparator circuit B to create 2-bit low-order bit digital data as the low-order bits.

  In this way, the accurate upper bit digital data output from the upper bit digital data correction encoding circuit 5 and the lower bit digital data of 2 bits output from the lower bit encoding circuit 5b are combined, and the digital data accurately AD-converted is obtained. Can be obtained.

<Third Embodiment>
Hereinafter, a third embodiment of the present invention will be described with reference to FIG. As in the first embodiment, the configuration of the AD conversion circuit of the present embodiment is configured by a ladder resistor 1, a high-precision upper bit digital data creation circuit, and a lower bit digital data creation circuit as shown in FIG.

(High precision upper bit digital data creation circuit)
In the third embodiment, as shown in FIG. 3, an input terminal for inputting a plurality of reference voltages generated by the ladder resistor 1 of the low-order comparator group circuit 2 for high-order bits of the high-precision high-order bit digital data creation circuit, A buffer circuit 7 composed of a source follower circuit or the like is installed. Further, a buffer circuit 8 composed of a source follower circuit or the like is provided at the input terminal for inputting the input voltage VIN of the low-precision comparator group circuit 2 for upper bits.

  The other circuits are similar to the first embodiment or the second embodiment in that a plurality of provisional upper bit voltage selection circuits 3, one high-precision comparator circuit 4, and an upper bit digital data correction encoding circuit 5 are used. The low-order bit digital data creation circuit is used.

  In the previous embodiment, there is a problem that the input capacitance is increased by connecting a plurality of input terminals of the low precision comparator circuit A to the signal line of the input voltage VIN. The third embodiment has an effect that the input capacitance connected to the signal line of the input voltage VIN can be reduced by using the buffer circuit 8.

  In a normal circuit, when the buffer circuit 7 and the buffer circuit 8 are inserted into the input terminal of the low precision comparator circuit A, a conversion error of the low precision comparator circuit A occurs due to the offset of the buffer circuit. However, in the present embodiment, accurate high-order bit digital data can be obtained by using the high-precision comparator circuit 4 and the high-order bit digital data correction encoding circuit 5, so that the offset error caused by the buffer circuit 7 and the buffer circuit 8 can be obtained. Can be set to 1 LSB or less, a buffer circuit can be inserted without causing a conversion error.

  Therefore, there is an effect that it is possible to install the buffer circuit 7 and the buffer circuit 8 that cannot normally be inserted due to a conversion error at the input terminal of the low precision comparator circuit A. By inserting the buffer circuit 7 and the buffer circuit 8, the input capacitance connected to the signal line of the input voltage VIN and the input capacitance connected to the signal line of the reference voltage generated by the ladder resistor 1 can be greatly reduced. There is an effect that can be done. Thereby, there is an effect that the operation of the low precision comparator circuit A can be speeded up.

DESCRIPTION OF SYMBOLS 1, 101 ... Ladder resistor 2 ... Low-precision comparator group circuit 2b for upper bits ... Comparator group circuit 3 for lower bits ... Temporary upper bit voltage selection circuit 3a ... 3-input OR circuit 3b ... Temporary upper bit voltage signal output switch circuit 4 ... High precision comparator circuit 5 ... Upper bit digital data correction encoding circuit 5b ... Lower bit encoding circuit 6 ... Lower bit reference voltage selection switch Group 6a: Lower bit reference voltage selection switches 7, 8 ... Buffer circuit 102 ... Comparator group circuit 103 ... Encoding circuit A ... (for upper bits) Low precision comparator circuit B ... Comparator circuit C1 (for low-order bits) High-precision comparator circuit capacitor D Inverter OutPut D Tal data REF · · · reference voltage SW1 · · · Precision Comparator circuit input terminal switches SW2 · · · precision comparator circuit of the input and output short-circuiting switch VIN · · · input voltage of the inverter D

Claims (2)

A provisional high-order bit voltage selection circuit that creates a provisional high-order bit voltage signal based on a result of comparing the input voltage with a high-order bit reference voltage; and a high-precision comparator circuit that compares the input voltage and the provisional high-order bit voltage signal ,
An upper bit digital data correction encoding circuit for correcting and creating upper bit digital data based on the output of the high precision comparator circuit;
A lower bit reference voltage selection switch group for selecting a lower bit reference voltage related to the upper bit digital data;
An AD conversion circuit comprising a lower bit digital data creation circuit for creating lower bit digital data by comparing the input voltage with the lower bit reference voltage.   2. The AD conversion circuit according to claim 1, wherein the input voltage is obtained by using an upper bit low-precision comparator group circuit including a buffer circuit at an input terminal of the input voltage and an input terminal of the upper bit reference voltage. An AD conversion circuit characterized by comparing with a reference voltage for upper bits.

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