JP2017188781A - ΔΣ A / D converter, A / D converter integrated circuit - Google Patents

Abstract

An object of the present invention is to improve the reliability of a circuit or system. A ΔΣ A/D converter 200 converts an analog input signal VIN into a digital output signal DOUT. The integrating circuit 204 is composed of a switched capacitor circuit. A leak detection circuit 230 detects leakage in at least one capacitor of the integration circuit 204 . [Selection drawing] Fig. 2

Description

  The present invention relates to a ΔΣ A / D converter.

A ΔΣ A / D converter is used in the measurement of minute signals that require high resolution and audio applications. FIG. 1 is a block diagram showing a basic configuration of a first-order ΔΣ A / D converter. The ΔΣ A / D converter 100r converts the analog input signal V _IN into a digital output signal D _OUT . The ΔΣ A / D converter 100r includes a subtractor 102, an integrator 104, a quantizer 106, and a D / A converter 108. The D / A converter 108 delays the digital output signal D _OUT by one sample and converts it into an analog feedback signal V _FB . The subtractor 102 generates a difference between the analog input signal _VIN and the feedback signal _VFB . The integrator 104 integrates the difference that is the output of the subtractor 102. The quantizer 106 quantizes the output of the integrator 104 and generates a digital output signal _DOUT .

  By using the ΔΣ A / D converter, the noise spectrum due to the quantization error can be moved out of the band of the input signal. This is called noise shaping.

JP 2011-150561 A JP 2014-171035 A

  As a result of examining the ΔΣ A / D converter, the present inventors have recognized the following problems. In a first-order, especially second-order or higher ΔΣ A / D converter, the integrator 104 is often formed of a switched capacitor circuit.

When the ΔΣ A / D converter completely fails and becomes inoperable, the digital output signal D _OUT has no correlation with the analog input signal _VIN . In this case, it is possible to recognize an abnormality in a subsequent processor or circuit using the output signal D _OUT of the ΔΣ A / D converter.

However, an incomplete failure may occur in the ΔΣ A / D converter. An incomplete failure refers to a failure mode in which some abnormality has occurred, but the ΔΣ A / D converter is operating at first glance, and some output signal D _OUT is generated although it is inaccurate. When an incomplete failure occurs, the subsequent processor or circuit operates based on an erroneous output signal D _OUT , which causes a system malfunction.

  The present inventor has been made in view of such a problem, and one of the exemplary purposes of an aspect thereof is to provide a ΣA / D converter with improved reliability.

  One embodiment of the present invention relates to a ΔΣ A / D converter that converts an analog input signal into a digital output signal. The ΔΣ A / D converter includes at least one integration circuit configured by a switched capacitor circuit and a leak detection circuit that detects a leak of at least one capacitor of the integration circuit.

  The inventor has recognized that capacitor leakage in a switched capacitor circuit is one cause of an incomplete failure mode of a ΔΣ A / D converter. According to this aspect, the ΔΣ A / D converter can self-diagnose the leak of the capacitor, thereby detecting an incomplete failure that cannot be detected in the subsequent processor or circuit, and improving the reliability.

The leak detection circuit may open the capacitor after charging the capacitor to be leak detected and measure the voltage of the capacitor.
If there is no leakage or is small enough, the capacitor voltage will continue to maintain its original voltage level after the capacitor is opened. On the other hand, if there is a leak, the capacitor charge is discharged by the leak current, and the voltage relaxes. Therefore, by measuring the voltage of the capacitor, it is possible to measure the presence or absence of leakage or the degree of leakage.

  The leak detection circuit may measure the relaxation time until the voltage of the capacitor crosses a predetermined threshold voltage after the leak detection target capacitor is opened. By measuring the relaxation time, the presence or absence of leak or the degree of leak can be measured.

  Alternatively, the leak detection circuit may measure the voltage of the capacitor after a predetermined time has elapsed after the capacitor for leak detection is opened. The amount of fluctuation in the voltage of the capacitor that occurs during a predetermined time indicates the presence or absence of leak or the degree of leak.

  The at least one capacitor may include a capacitor having a maximum capacitance value among a plurality of capacitors constituting the integrating circuit. The larger the capacitance value, that is, the larger the area, the easier the leak detection.

  The ΔΣ A / D converter may be second order or higher. The at least one capacitor may include a first-stage integrator capacitor. Since the capacitance value of the capacitor of the first-stage integrator is often the largest, leak detection is easy.

  The leak detection circuit includes a first switch provided between one end of a capacitor to be leak detected and a first fixed voltage line, and a second switch provided between the other end of the capacitor and the second fixed voltage line. And a comparator that compares the voltage of the capacitor with a threshold voltage.

  The comparator of the leak detection circuit may be shared with the comparator of the quantizer of the ΔΣ A / D converter. Thereby, an increase in circuit area can be suppressed.

  The ΔΣ A / D converter may be a differential type. The leak detection circuit may detect the leakage of each of the capacitor provided on the differential positive phase side and the capacitor provided on the negative phase side.

  The ΔΣ A / D converter may be integrated on a single semiconductor substrate.

  Another aspect of the present invention is an A / D converter integrated circuit. An A / D converter integrated circuit includes a plurality of input terminals each capable of receiving an analog input signal, a multiplexer that selects one of the plurality of input terminals, an amplifier that amplifies an output signal of the multiplexer, and an output of the amplifier You may provide the filter which filters a signal, and one of above-mentioned (DELTA) (Sigma) A / D converters which convert the output signal of a filter into a digital signal.

  It should be noted that any combination of the above-described constituent elements and a representation obtained by converting the expression of the present invention between methods, apparatuses, and the like are also effective as an aspect of the present invention.

  According to the ΔΣ A / D converter according to the present invention, the reliability can be improved.

It is a block diagram which shows the basic composition of a primary ΔΣ A / D converter. 1 is a circuit diagram of a ΔΣ A / D converter according to an embodiment. FIG. It is a circuit diagram which shows the structural example of a leak detection circuit. 4A and 4B are operation waveform diagrams of the leak detection circuit of FIG. FIG. 5 is a circuit diagram illustrating a specific configuration example of a ΔΣ A / D converter. It is a circuit diagram which shows a part of differential type integration unit. It is a block diagram of A / D converter IC provided with a delta-sigma A / D converter.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 2 is a circuit diagram of the ΔΣ A / D converter 200 according to the embodiment. The ΔΣ A / D converter 200 includes a subtracter 202, an integration circuit (integration filter) 204, a quantizer 206, a D / A converter 208, and a leak detection circuit 230. The ΔΣ A / D converter 200 is integrated on a single semiconductor substrate.

The D / A converter 208 delays the digital output signal D _OUT by one sample and converts it into an analog feedback signal V _FB . The subtractor 202 generates a difference between the analog input signal _VIN and the feedback signal _VFB . The integration circuit 204 integrates the difference that is the output of the subtractor 102. The quantizer 206 quantizes the output of the integrating circuit 204 and generates a digital output signal _DOUT .

  The ΔΣ A / D converter 200 of FIG. 2 is a third-order ΔΣ A / D converter, and the integration circuit 204 includes three-stage integration units 210, 212, and 214. Each integration unit multiplies the signal from the previous stage by a predetermined coefficient and integrates it. In the present invention, the topology of the integration circuit 204 and the value of the coefficient are not limited, and may be designed so as to obtain a desired filter characteristic.

  The configuration of the quantizer 206 is not particularly limited. For example, multipliers 240, 242, and 244 for multiplying outputs of the integration units 210, 212, and 214 by predetermined coefficients a1, a2, and a3, and multipliers 240, 242, and 2402, respectively. An adder 246 that adds the outputs of 244 and a comparator (comparison circuit) 250 that quantizes the outputs of the adder 246 are included.

  The integrating circuit 204 is configured by a switched capacitor circuit. The leak detection circuit 230 detects a leak of at least one capacitor among the plurality of capacitors constituting the integration circuit 204.

  The leak detection method and circuit configuration are not particularly limited, but may be detected as follows. The leak detection circuit 230 opens the capacitor after charging the capacitor to be leak detected, and measures the voltage of the capacitor.

  The above is the configuration of the ΔΣ A / D converter 200. According to the ΔΣ A / D converter 200, the leakage of the capacitor of the switched capacitor circuit can be self-diagnosed, and thereby an incomplete failure that cannot be detected by the subsequent processor or circuit can be detected. Therefore, the reliability and safety of the ΔΣ A / D converter 200 itself or a system using the ΔΣ A / D converter 200 can be improved.

  For example, ΔΣ A / D converter 200 may notify an external circuit when leak detection circuit 230 detects a leak. Alternatively, the ΔΣ A / D converter 200 may transmit a signal indicating the degree of leakage to an external circuit. Alternatively, data indicating the degree of leakage may be accessible from an external circuit.

  The present invention is understood as the block diagram and circuit diagram of FIG. 2 or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. In the following, more specific configuration examples and examples will be described in order not to narrow the scope of the present invention but to help understanding and clarify the essence and circuit operation of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration example of the leak detection circuit 230. The first switch SW11 is provided between one end of the capacitor Cx subject to leak detection and a first fixed voltage line (for example, a power supply line or a reference voltage line) 260. The second switch SW12 is provided between the other end of the capacitor Cx and a second fixed voltage line (for example, a ground line or a common voltage line) 262. The comparator 232 compares the voltage V _{CX of the} capacitor Cx with the threshold voltage V _TH . A third switch SW13 is provided between the comparator 232 and the other end of the capacitor Cx. The threshold voltage V _TH may be generated by resistance voltage division of the resistors R 11 and R 12, and a fourth switch SW 14 is provided between the output of the resistance voltage divider circuit and the comparator 232.

  The comparator 232 may be shared with a part of the comparator 248 of the quantizer 206 of the ΔΣ A / D converter 200. Thereby, an increase in circuit area can be suppressed. Some of the switches of the leak detection circuit 230 may be shared with the switches of the integration circuit 204.

FIGS. 4A and 4B are operation waveform diagrams of the leak detection circuit 230 of FIG. The leak detection circuit 230 turns on the first switch SW11 and the second switch SW12, and charges both ends of the capacitor Cx with the voltage V _DD . Subsequently, the second switch SW12 is turned off, and the third switch SW13 and the fourth switch SW14 are turned on. When the second switch SW12 is turned off, the capacitor Cx is opened. The comparator 232 compares the voltage V _{CX of the} capacitor Cx with the threshold voltage V _TH . If no leakage occurs, the voltage ΔV across the capacitor Cx maintains the initial power supply voltage V _DD as shown by the solid line (i), so the capacitor voltage V _CX is equal to the initial ground voltage 0V. To maintain.

On the other hand, when a leak occurs, as indicated by a broken line (ii), the capacitor Cx is discharged, so that the voltage ΔV between both ends of the capacitor Cx decreases, and the capacitor voltage V _CX becomes the initial grounding voltage. It rises with time from voltage 0V.

As shown in FIG. 4B, the leak detection circuit 230 measures the relaxation time τ until the voltage V _{CX of the} capacitor Cx crosses the predetermined threshold voltage V _TH after the capacitor Cx is opened. Good. If there is no leak, the relaxation time τ is sufficiently long, and if there is a leak, the relaxation time τ is short. Therefore, by measuring the relaxation time τ, it is possible to measure the presence or absence of leak or the degree of leak.

  The leak detection circuit 230 may include a counter (timer) 234 that measures a time τ from when the second switch SW12 is turned off until the output of the comparator 232 transitions. The leak detection circuit 230 may store data indicating the measured relaxation time τ in the register as data indicating the degree of leak. Alternatively, the leak detection circuit 230 may set a flag indicating the occurrence of a leak failure when the measured relaxation time τ is shorter than a predetermined threshold value.

Alternatively, the leak detection circuit 230 may measure the voltage V _CX of the capacitor Cx after a predetermined time has elapsed after the capacitor Cx to be leaked is opened. The fluctuation amount of the voltage V _CX generated during the predetermined time indicates the presence or absence of the leak or the degree of the leak.

In FIG. 2, the leakage is measured with the power supply voltage V _DD as a reference, but it may be measured with the ground voltage as a reference. That is, after charging the capacitor Cx, the first switch SW11 may be turned off and the voltage at one end on the upper side of the capacitor Cx may be monitored.

  FIG. 5 is a circuit diagram illustrating a specific configuration example of the ΔΣ A / D converter 200. Although shown here as a single-ended format, the ΔΣ A / D converter 200 may be a differential format.

  The leak detection circuit 230 desirably monitors a capacitor having the maximum capacitance value among the plurality of capacitors constituting the integration circuit 204. This is because the larger the capacitance value, that is, the larger the area, the easier the leak detection. Also, the larger the capacitance value, the greater the effect on the performance of the ΔΣ A / D converter 200 when a leak occurs.

  In the configuration of FIG. 5, the feedback capacitor 272 of the integrator 270 of the integration unit 210 at the first stage is suitable as a leak detection target. This is because it is effective to increase the feedback capacitor 272 of the first-stage integrator 270 in order to suppress the noise of the ΔΣ A / D converter 200. Further, the voltage applied during operation is also susceptible to leakage because the first-stage feedback capacitor 272 is the largest.

  This is because the capacity of the feedback capacitor 272 is the largest compared to other capacitors. In addition to the feedback capacitor 272, the feedback capacitor 276 of the integrator 274 in the second and subsequent stages may be a leak detection target. Alternatively, the capacitor 280 forming the equivalent resistance (or sample-and-hold circuit) 278 may be a leak detection target.

  FIG. 6 is a circuit diagram showing a part of the differential type integration unit 210. The leak detection circuit 230 preferably detects leaks of the feedback capacitor CP provided on the differential positive phase side and the feedback capacitor CN provided on the negative phase side.

  FIG. 7 is a block diagram of an A / D converter IC (integrated circuit) 300 including the ΔΣ A / D converter 200. Each of the plurality of input terminals IN1 to INM (M is an integer) can receive an analog input signal from the outside. For example, a temperature detection signal from a temperature sensor such as a thermistor or a thermocouple, a current detection signal corresponding to a voltage drop of a sense resistor for current detection, a signal indicating a battery voltage, and the like are input to the input terminal IN.

The multiplexer 302 selects one of the plurality of input terminals. The amplifier 304 is a programmable gain amplifier (PGA) that amplifies the output signal of the multiplexer 302. Filter 306 filters the output signal of amplifier 304. The ΔΣ A / D converter 308 converts the output signal _VIN of the filter 306 into a digital signal D _OUT . The ΔΣ A / D converter 308 is configured using the architecture of the ΔΣ A / D converter 200 described above. The logic circuit 310 performs predetermined signal processing on the digital signal DOUT from the ΔΣ A / D converter 308. The interface circuit 312 is an SPI (Serial Peripheral Interface) or I ² C (Inter IC) interface, and is connected to an external processor or microcontroller. The output signal D _OUT of the ΔΣ A / D converter 308 and a signal obtained as a result of processing the signal can be read from an external circuit via the interface circuit 312. Further, the presence / absence of the leak detected by the leak detection circuit 230 of the ΔΣ A / D converter 308 (200) or the level of the leak can be read from the outside via the interface circuit 312.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible within the range not leaving.

100: ΔΣ A / D converter, 102: Subtractor, 104: Integrator, 106: Quantizer, 108: D / A converter, 200: ΔΣ A / D converter, 202: Subtractor, 204: Integration circuit, 206: Quantum 208 ... D / A converter 210 ... integration unit 230 ... leakage detection circuit 232 ... comparator SW11 ... first switch SW12 ... second switch SW13 ... third switch SW14 ... fourth switch R11 ... first resistor, R12 ... second resistor, 300 ... A / D converter IC, 302 ... multiplexer, 304 ... amplifier, 306 ... filter, 308 ... ΔΣ A / D converter, 310 ... logic circuit, 312 ... interface circuit.

Claims (11)

A ΔΣ A / D converter for converting an analog input signal into a digital output signal,
An integrating circuit composed of a switched capacitor circuit;
A leak detection circuit for detecting a leak of at least one capacitor of the integration circuit;
A ΔΣ A / D converter comprising:   2. The ΔΣ A / D converter according to claim 1, wherein the leak detection circuit opens the capacitor after charging the capacitor to be leak detected, and measures the voltage of the capacitor.   3. The ΔΣA / of claim 2, wherein the leak detection circuit measures a relaxation time until the voltage of the capacitor crosses a predetermined threshold voltage after the leak detection target capacitor is opened. D converter.   The ΔΣ A / D converter according to claim 1, wherein the at least one capacitor includes a capacitor having a maximum capacitance value among a plurality of capacitors constituting the integration circuit. The ΔΣ A / D converter is second order or higher,
The ΔΣ A / D converter according to claim 1, wherein the at least one capacitor includes a capacitor of a first-stage integrator. The leak detection circuit includes:
A first switch provided between one end of the leak detection target capacitor and the first fixed voltage line;
A second switch provided between the other end of the capacitor and the second fixed voltage line;
A comparator for comparing the voltage of the capacitor with the threshold voltage;
The ΔΣ A / D converter according to claim 3, comprising:   The ΔΣ A / D converter according to claim 6, wherein a comparator of the leak detection circuit is shared with a comparator of a quantizer of the ΔΣ A / D converter.   The ΔΣ A / D converter according to claim 1, wherein the ΔΣ A / D converter is a differential type.   8. The ΔΣA according to claim 1, wherein the leak detection circuit detects a leak of each of a capacitor provided on a differential positive phase side and a capacitor provided on a negative phase side. 9. / D converter.   The ΔΣ A / D converter according to claim 1, wherein the ΔΣ A / D converter is integrated on a single semiconductor substrate. A plurality of input terminals each capable of receiving an analog input signal;
A multiplexer for selecting one of the plurality of input terminals;
An amplifier for amplifying the output signal of the multiplexer;
A filter for filtering the output signal of the amplifier;
The ΔΣ A / D converter according to claim 1, which converts an output signal of the filter into a digital signal;
An A / D converter integrated circuit comprising:

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