JP2017184017A - Imaging apparatus, infrared detection apparatus and correction method for dark current of infrared detector - Google Patents

Abstract

Provided is an imaging device that stores a dark current in each pixel in a nonvolatile manner and corrects the dark current by a CDS. An image pickup apparatus includes a pixel array including a light receiving element for detecting infrared rays, which is provided for each pixel, and a bipolar resistance change type memory element provided for each pixel. The current amount of the current can be stored in the resistance change type memory element, and a first signal reflecting the amount of read current flowing in the resistance change type memory and a second signal reflecting the amount of current flowing in the light receiving element at the time of imaging are displayed. It includes a read circuit for outputting and a difference circuit for obtaining a difference between the first signal and the second signal. [Selection diagram] Figure 2

Description

  The present disclosure relates to an imaging apparatus, an infrared detection apparatus, and a dark current correction method for an infrared detector.

  In the quantum infrared detector, the light receiving element generates an amount of current corresponding to the intensity of incident infrared rays, the current is accumulated in a capacitor as a charge by a readout circuit, and the voltage corresponding to the accumulated charge is amplified by an amplifier. Output. Since the upper limit of the detector operating temperature is limited by the ratio of signal to noise (S / N ratio), quantum infrared detectors generally require cooling during operation. Typical noise includes dark current that flows through the light receiving element when the incident infrared ray is zero, shot noise that is a quantum fluctuation of the current, reset noise of the charge storage capacitor, fixed pattern noise of the CMOS that constitutes the readout circuit, There is random telegraph signal noise. By cooling the detector to a low temperature, particularly dark current and reset noise can be significantly reduced.

  In order to cool to a low temperature, a large-sized and high-power-consumption refrigerating machine is required, and the price is also expensive. In order to develop an infrared sensor system that includes a small-sized, low power consumption, and low-cost quantum infrared detector, noise generation should not be reduced by lowering the temperature, but generated noise should be removed by signal processing. Is preferred. As one of such noise removal methods, Correlated Double Sampling (CDS) effective for removing reset noise that increases rapidly at high temperatures is known. In the CDS, first, the charge storage capacitor is reset, and then a read voltage corresponding to the voltage of the charge storage capacitor including reset noise is held in the first capacitor. Thereafter, the charge storage capacitor is discharged by the current of the light receiving element, and then the read voltage corresponding to the voltage of the charge storage capacitor including the reset noise and the voltage change due to the discharge is held in the second capacitor. By taking the difference between the voltage of the first capacitor and the voltage of the second capacitor, it is possible to cancel the reset noise included in both voltages and detect the current of the light receiving element. Further, by taking the difference by CDS, it is possible to reduce the fixed pattern noise specific to each readout circuit.

  When the temperature rises, the dark current of the light receiving element also increases rapidly. In order to correct the dark current, it is necessary to collect data obtained by measuring only the dark current for each pixel. In order to create a state in which only dark current flows to the light receiving element in the absence of infrared incidence, the pixel array of the light receiving element is blocked from the outside by a sufficiently cooled mechanical shutter.

  Conventionally, it is not easy to correct dark current by CDS, and it is general to correct dark current after CDS. This is because it is not easy to store the dark current for each pixel in a non-volatile manner with a simple mechanism in the circuit in the previous stage of the CDS. This is because it is necessary to execute for each video frame. However, if a dark current is acquired every frame, a time equivalent to the integration time of the photocurrent is required for the measurement of the dark current, resulting in a decrease in operating speed. In addition, it is not easy to maintain such a high-speed mechanical shutter opening / closing operation for a long time without any problem, leading to a shortened life of the infrared detector due to a shutter failure.

  For the output signal of the pixel array of the infrared detector, it is necessary to correct the sensitivity and the non-linearity variation for each light receiving element, and when the dark current is corrected after the CDS, In addition to correction, these correction processes are performed. When the pixel array has a high resolution and the number of pixels is large, the correction data and correction calculation amount required for a series of correction processes increase when dark current correction is performed. As a result, the operation speed decreases and the system area decreases. Will lead to an increase.

JP-A-6-86174 JP 2010-278143 A JP-A-6-334165 Japanese Patent Laid-Open No. 11-39858

  In view of the above, an imaging device that stores dark current in a nonvolatile manner for each pixel and performs dark current correction by CDS is desired.

  The imaging apparatus includes a pixel array including a light receiving element for detecting infrared rays provided for each pixel, and a bipolar resistance change memory element provided for each pixel, and a dark current flowing through the light receiving element. A first signal reflecting the amount of read current flowing through the resistance change memory and a second signal reflecting the amount of current flowing through the light receiving element. A readout circuit for outputting, and a difference circuit for obtaining a difference between the first signal and the second signal.

  According to at least one embodiment, the imaging apparatus can store dark current in a nonvolatile manner for each pixel and perform dark current correction by CDS.

It is a figure which shows an example of a structure of an infrared rays detection apparatus. It is a figure which shows an example of the voltage versus current characteristic which a bipolar type resistance change memory element shows. It is a figure which shows the outline | summary of the correction process in the infrared rays detection apparatus shown in FIG. It is a figure which shows an example of a structure of a pixel array and a readout circuit. It is a figure which shows an example of a structure of a read-out circuit. 6 is a flowchart illustrating an example of operations of the infrared detection device illustrated in FIG. 1 and the circuit illustrated in FIG. 5. It is a figure which shows an example of a structure of a resistance change type memory element. It is a figure for demonstrating the circuit structure in the case of producing | generating the electric current of the magnitude | size of an input electric current with a current mirror circuit. It is a figure for demonstrating the circuit structure in the case of producing | generating the electric current of m magnitude | size of input current with a current mirror circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of an infrared detection device. 1 includes an optical system 11, an infrared detector 12, a correction signal processing unit 13, a display recording unit 14, a cooler 15, a control unit 16, and a control unit 17. The infrared detector 12 includes a shutter 21, a pixel array 22, a readout circuit 23, and a temperature sensor 24.

  The optical system 11 images incident light on the imaging surface. The pixel array 22 is provided on the imaging surface and captures an infrared image based on incident light. The shutter 21 is, for example, a mechanical shutter that can be opened and closed. The shutter 21 allows incident light to pass when opened, and blocks incident light when blocked. The pixel array 22 includes a plurality of light receiving elements that detect infrared rays arranged vertically and horizontally on a matrix. The light receiving element has a characteristic that an electric resistance value changes according to the intensity of incident light (incident infrared light). By applying a bias voltage to the light receiving element irradiated with incident light, an amount of current corresponding to the intensity of the incident light flows through the light receiving element. A plurality of light receiving elements are provided corresponding to a plurality of pixels on a one-to-one basis, and imaging data by each light receiving element is pixel data of each pixel.

  The readout circuit 23 includes a plurality of pixel readout circuits provided in a one-to-one correspondence with the plurality of light receiving elements, and a CDS circuit provided for each column of the pixel array 22, for example (see FIG. 5). The pixel readout circuit converts the current flowing through the light receiving element into a voltage, amplifies the voltage, and outputs the amplified voltage to the CDS circuit. The CDS circuit performs correlated double sampling on the output voltage from the readout circuit.

  The readout circuit 23 further includes a bipolar resistance change memory element provided for each pixel. That is, each pixel readout circuit includes one resistance change type memory element. The resistance change memory element includes a resistance change material, an upper metal electrode, and a lower metal electrode, and is arranged so that the resistance change material is sandwiched between the upper metal electrode and the lower metal electrode. In a bipolar resistance change memory element, transition metal oxides such as TaOx, HfOx, TiOx, WOx, CoOx, and MoOx, a laminate of these transition metal oxides, or the oxygen content of these transition metal oxides What was changed in the film is used as the resistance change material.

  FIG. 2 is a diagram illustrating an example of voltage-current characteristics exhibited by the bipolar resistance change memory element. For the sake of explanation, a linear resistance is assumed. In FIG. 2, the horizontal axis indicates the voltage applied to the resistance change memory element, and the vertical axis indicates the current flowing through the resistance change memory element. The resistance change type memory element has a high resistance state SH and a low resistance state SL. The resistance change type memory element in the high resistance state SH exhibits a relatively high constant resistance value. The resistance change type memory element in the low resistance state SL exhibits a relatively low constant resistance value.

  When a voltage equal to or higher than the first predetermined voltage value V1 is applied to the resistance change memory element in the high resistance state SH in the first direction, the resistance change memory element is indicated as a state transition T1. Transition to the low resistance state SL. At this time, the amount of current I1 flowing through the resistance change type memory element when the state transition T1 is caused determines the resistance value of the low resistance state SL after the transition. Specifically, the resistance change memory element is set to a low resistance state SL having a resistance value (= V1 / I1) determined from the applied voltage V1 and the current amount I1 at the time of transition. The current amount I1 is called a compliance current, and can be set to an arbitrary value by adjusting the gate voltage of the selection transistor.

  When a voltage equal to or higher than the second predetermined voltage value V2 is applied to the resistance change type memory element in the low resistance state SL in the second direction opposite to the first direction, the resistance change type memory element becomes low. Transition from the resistance state SL to the high resistance state SH. The resistance change memory element in the high resistance state SH does not transition to the low resistance state SL unless a voltage equal to or higher than the first predetermined voltage value V1 is applied in the first direction. Further, the resistance change memory element in the low resistance state SL does not transition to the high resistance state SH unless a voltage equal to or higher than the second predetermined voltage value V2 is applied in the second direction.

  As a reset state, a current of the amount of current flowing through the light receiving element when the shutter 21 is shut off is supplied to the resistance change memory element in the high resistance state SH in the first direction. At this time, the resistance of SH is set so that the voltage applied to the resistance change memory exceeds the first predetermined voltage V1. Thereby, the resistance change memory element can be changed to the low resistance state SL, and the dark current of the light receiving element can be stored in the resistance change memory element. Thereafter, when the first predetermined voltage V1 in the first direction is applied to the resistance change memory element in the low resistance state SL, the same amount of current as the stored dark current flows through the resistance change memory element. It will be.

  Returning to FIG. 1, the pixel readout circuit of the readout circuit 23 reflects the amount of read current (stored dark current) that flows through the resistance change memory and the amount of current (darkness) that flows through the light receiving element when the shutter 21 is opened. A second signal reflecting the sum of current and photocurrent is output. That is, the pixel readout circuit outputs a first signal including a dark current component and a second signal including a dark current component and a photocurrent component. Further, a difference between the first signal and the second signal is obtained by the CDS circuit of the reading circuit 23. More specifically, the CDS circuit may perform correlated double sampling on the first signal and the second signal. This makes it possible to remove the influence of dark current from the pixel signal.

  A signal of each pixel obtained by the correlated double sampling performed by the CDS circuit is supplied to the correction signal processing unit 13 as an output signal of the infrared detector 12. The correction signal processing unit 13 generates corrected imaging data by performing a process for correcting variations in sensitivity and nonlinearity for each light receiving element on the output signal of the infrared detector 12. The corrected imaging data output from the correction signal processing unit 13 is supplied to the display recording unit 14 and displayed as a captured image on the display unit of the display recording unit 14 or stored in the recording unit of the display recording unit 14. To do.

  The control unit 16 controls the optical system 11, the infrared detector 12, and the cooler 15. The controller 16 opens and closes the shutter 21 at a predetermined timing, thereby enabling dark current measurement and imaging data measurement by the pixel array 22 and the readout circuit 23. The controller 16 may operate to keep the temperature of the infrared detector 12 constant by controlling the operation of the cooler 15 based on the temperature detected by the temperature sensor 24. The control unit 16 controls the shutter 21, the pixel array 22, and the readout circuit 23 based on the temperature detected by the temperature sensor 24 to measure dark current and change to a resistance change type memory element when the temperature changes. May be operated to perform storage. The temperature sensor 24 detects the temperature of the infrared detector 12, more preferably the temperature of the pixel array 22.

  FIG. 3 is a diagram showing an outline of the correction process in the infrared detecting device 10 shown in FIG. The CDS process 30 shown in FIG. 3 is executed by the CDS circuit of the read circuit 23. In order to correct the dark current by the CDS process 30, the amount of current flowing through the light receiving element when the shutter 21 is shut off is added to the bipolar resistance change memory element provided for each pixel of the infrared detector as described above. Is stored.

  The first signal 31 that is an input to the CDS processing 30 is a signal reflecting noise caused by the readout circuit 23 and dark current stored in the resistance change type memory element, that is, noise components and dark current components. It is a signal containing. Here, the noise caused by the readout circuit 23 includes reset noise and fixed pattern noise. The reset noise is noise generated when the voltage of the charge storage capacitor of the pixel readout circuit is reset, and more specifically, noise generated when the CMOS switch biased to the charge storage node is shut off. Charge injection, feedthrough, and switch thermal noise are the main causes of reset noise. The fixed pattern noise is a noise generated due to variations in characteristics of various circuit elements, and is a constant noise that does not change every reading operation by the reading circuit 23.

  After resetting the voltage of the charge storage capacitor, a read current flowing through the resistance change type memory is caused to flow through the charge storage capacitor, whereby the voltage between the terminals of the charge storage capacitor is changed according to the amount of the read current. A voltage corresponding to the inter-terminal voltage after the change is output from the pixel readout circuit of the readout circuit 23 as the first signal 31.

  The second signal 32 for the CDS process 30 is a signal reflecting noise caused by the readout circuit 23 and an imaging current (sum of dark current and photocurrent) flowing through the light receiving element during imaging, that is, a dark current component and light. A signal including a current component. After resetting the voltage of the charge storage capacitor, a current at the time of imaging flowing through the light receiving element (that is, a current flowing through the light receiving element when the shutter 21 is opened) is caused to flow through the charge storage capacitor. Vary the voltage between. A voltage corresponding to the inter-terminal voltage after the change is output from the pixel readout circuit of the readout circuit 23 as the second signal 32.

  By taking the difference between the first signal 31 and the second signal 32 by the CDS process 30, it is possible to generate an output signal from which reset noise, fixed pattern noise, and dark current components are removed. That is, only the photocurrent component is included in this output signal. Thereafter, sensitivity and nonlinearity correction processing 33 is performed on the output signal. This sensitivity and nonlinearity correction processing 33 is executed by the correction signal processing unit 13 shown in FIG.

  FIG. 4 is a diagram illustrating an example of the configuration of the pixel array and the readout circuit. The pixel array circuit 41 includes a plurality of light receiving elements 43 arranged on a matrix vertically and horizontally. One light receiving element 43 corresponds to one pixel. The pixel array circuit 41 corresponds to the pixel array 22 in FIG.

  The pixel readout circuit array 42 and the CDS circuit 46 correspond to the readout circuit 23 in FIG. The pixel readout circuit array 42 includes a plurality of pixel readout circuits 44 arranged on a matrix vertically and horizontally. The plurality of pixel readout circuits 44 are provided in a one-to-one correspondence with the plurality of light receiving elements 43, and the corresponding pixel readout circuit 44 and the light receiving element 43 are electrically connected to each other by a bump 45, which is representative of only one. It is connected to the. The bump 45 is formed of two bumps per pixel in order to draw the upper and lower electrodes of the light receiving element 43 to the pixel readout circuit 44.

  A column of pixel readout circuits 44 arranged in the row direction (horizontal direction in the drawing) can be selected by asserting one of the plurality of row lines 48. The plurality of pixel readout circuits 44 in one selected row are electrically connected to the plurality of CDS circuits 46 on a one-to-one basis through a plurality of column lines 47 extending in the column direction (vertical direction in the drawing).

  The optical system 11 shown in FIG. 1 forms an image of incident infrared light on the surface where the plurality of light receiving elements 43 of the pixel array circuit 41 are arranged. A current corresponding to the intensity of incident light flows through each light receiving element 43, and the current is supplied to the pixel readout circuit 44. The pixel readout circuit 44 converts the current from the light receiving element 43 into a voltage for further amplification, and supplies the amplified voltage to the CDS circuit 46 via the column line 47.

  FIG. 5 is a diagram illustrating an example of a configuration of the reading circuit. As described above, the readout circuit 23 includes a pixel readout circuit and a CDS circuit. The pixel readout circuit 44 corresponding to one pixel shown in FIG. 5 includes MOS transistors 52 to 63, a resistance change memory element 64, a charge storage capacitor 65, and switch circuits SW1 and SW2. Note that the light receiving element 43 connected to the MOS transistor 52 is not a part of the pixel readout circuit 44, but is included in the pixel readout circuit 44 among the plurality of light receiving elements 43 (see FIG. 4) included in the pixel array 22. One corresponding light receiving element. Connected to the pixel readout circuit 44 are PMOS transistors 72 and 73 and switch circuits SW3 and SW4, which are current mirror circuits for performing a write current to the resistance change memory element 64 and a read from the resistance change memory element 64. ing. The pixel readout circuit 44 is further connected with a write driver 71 for resetting the resistance change memory element 64 to a high resistance state.

  The output signal of the pixel readout circuit 44 is supplied to the CDS circuit. In FIG. 5, the CDS circuit includes MOS transistors 82 and 83, capacitors 84 and 85, and a differential amplifier 86. The MOS transistor 81 is a load transistor and forms a source follower circuit for output amplification together with the MOS transistor 55.

  The control unit 16 shown in FIG. 1 controls the conduction and non-conduction states of the transistors and the conduction and non-conduction states of the switch circuits, whereby the dark current storage operation, the dark current read operation, and the imaging current detection in the pixel readout circuit 44. Perform the action. The amount of dark current flowing through the light receiving element 43 is stored in the resistance change memory element 64 by the dark current storing operation. By the dark current read operation, the charge storage capacitor 65 is discharged by causing the amount of read current flowing through the resistance change type memory element 64 to flow from the charge storage capacitor 65. Further, by the imaging current detection operation, a current flowing through the light receiving element 43 is supplied from the charge storage capacitor 65 to discharge the charge storage capacitor 65. Each operation will be described in more detail below.

  In any operation, the charge storage capacitor 65 may be reset to the reset voltage by first turning off the MOS transistors 52 and 53 and turning on the MOS transistor 54. A node between the channel end of the MOS transistor 54 and the channel end of the MOS transistor 55 is set to a reset potential. Thereafter, the MOS transistor 54 is shut off. At this time, the above-described reset noise occurs, and the voltage stored in the charge storage capacitor 65 includes noise.

  In the dark current storing operation, first, the resistance change type memory element 64 is reset to a high resistance state. In order to execute this reset operation, the MOS transistors 59 and 62 are turned off, and the MOS transistors 61 and 63 are turned on. In this state, the write driver 71 side is set to a sufficiently high potential and connected to the ground potential via the MOS transistor 61, thereby resetting the resistance change memory element 64 to the high resistance state. Thereafter, in a state where the shutter 21 (see FIG. 1) is closed, the MOS transistors 52 and 53 are turned on and off, respectively, and a dark current is passed from the charge storage capacitor 65 through the light receiving element 43 and the MOS transistor 58.

  At this time, the switch circuits SW1 and SW2 are set to a non-conductive state and a conductive state, respectively, as illustrated. The switch circuits SW3 and SW4 are set to a non-conductive state and a conductive state, respectively, as shown in the figure. Further, the MOS transistors 59, 60, and 62 are turned on, and the MOS transistors 61 and 63 are turned off. Due to the action of the current mirror circuit, the same amount of current as the dark current flowing through the MOS transistor 58 flows through the MOS transistor 57, and the same amount of current as the current flowing through the MOS transistor 57 flows through the resistance change type memory element 64. At this time, a sufficient voltage is applied to the resistance change memory element 64, and the resistance change memory element 64 is set to a low resistance state that stores the amount of dark current.

  In the dark current read operation, the switch circuits SW1 and SW2 are set to a conductive state and a non-conductive state, respectively, contrary to the illustrated state. The switch circuits SW3 and SW4 are set in a conductive state and a non-conductive state, respectively, contrary to the illustrated state. Further, the MOS transistors 59, 60, and 62 are turned on, and the MOS transistors 61 and 63 are turned off. Further, the MOS transistors 52 and 53 are turned off and on, respectively. In this state, the voltage applied to the resistance change memory element 64 is the same as that at the time of writing, and a read current having the same amount as the amount of dark current stored in the resistance change memory element 64 flows.

  Due to the action of the current mirror circuit, the same amount of current as the read dark current flows through the MOS transistor 57, and the same amount of current as the current flowing through the MOS transistor 57 flows through the MOS transistor 58. As a result, the same amount of current as the dark current flows from the charge storage capacitor 65 through the MOS transistors 53 and 58, and the voltage value of the charge storage capacitor 65 shows a voltage change corresponding to the amount of dark current. By causing the current to flow for the same time as that during imaging, the voltage value of the charge storage capacitor 65 is set to a voltage value indicating the same voltage drop as the voltage drop due to the dark current during imaging.

  Thereafter, the row selection MOS transistor 56 is turned on, and the MOS transistors 81, 82, and 83 are turned on, turned on, and turned off, so that a voltage (amplified voltage) corresponding to the voltage of the charge storage capacitor 65 is obtained. It can be held in the capacitor 84.

  In the imaging current detection operation, the switch circuits SW1 and SW2 are set to a non-conductive state and a conductive state as illustrated. Also, all the MOS transistors 59, 60, 61 and 63 are kept in a non-conductive state. Also, the MOS transistors 52 and 53 are turned on and off, respectively. In this state, when the shutter 21 (see FIG. 1) is open, an imaging current (photocurrent + dark current) flows from the charge storage capacitor 65 via the light receiving element 43 and the MOS transistor 58. Thereby, the voltage value of the charge storage capacitor 65 shows a voltage change corresponding to the amount of the imaging current. By flowing a current for a predetermined time, the voltage value of the charge storage capacitor 65 is set to a voltage value indicating a voltage drop corresponding to the magnitude of the imaging current.

  Thereafter, the row selection MOS transistor 56 is turned on, and the MOS transistors 81, 82, and 83 are turned on, turned off, and turned on, so that a voltage (amplified voltage) corresponding to the voltage of the charge storage capacitor 65 is obtained. It can be held in the capacitor 85. The differential amplifier 86 outputs a voltage corresponding to the voltage difference between the voltage of the capacitor 84 and the voltage of the capacitor 85. The output voltage of the differential amplifier 86 becomes an image pickup pixel voltage from which the influence of the dark current is removed, that is, the dark current is corrected. The output voltage is an imaging pixel voltage from which the influence of fixed pattern noise and reset noise is removed.

  Since the reset noise includes a random component, even if two reset noises generated by two different reset operations are input to the correlated double sampling, the reset noise cannot be completely canceled for this random component. Can not. That is, if different reset operations are executed for the dark current reading operation and the imaging current detection operation, the reset noise cannot be completely cancelled. Considering this, for example, the charge storage capacitor 65 is a pair of capacitors, the same reset operation is executed for these two capacitors, and then the two capacitors are separated from each other, and the dark current is applied to each capacitor. A read operation and an imaging current detection operation may be executed. Thereafter, by taking the difference between the voltages (amplified voltages) corresponding to the voltages of these two capacitors, it is possible to cancel the same reset noise. However, in this case, different circuit elements (same specifications but physically different capacitors) are used, which may cause fixed pattern noise.

  As described above, by storing dark current data in a nonvolatile memory provided in the readout circuit, dark current can be removed by correlated double sampling in addition to reset noise and fixed pattern noise. . With this configuration, it is not necessary to carry out data correction by holding the dark current data outside, so that it is possible to reduce the size and weight of the apparatus and to achieve both high sensitivity and high speed operation.

  By providing a current mirror circuit or the like for dark current storage operation and dark current read operation, the number of transistors mounted on the read circuit 23 increases. However, the pixel area of the infrared detection device is determined by the wavelength of infrared rays, and even when it is small, the pixel area is about 10 μm × 10 μm to 20 μm × 20 μm. Therefore, an increase in the number of transistors hardly increases the area of the light receiving surface of the infrared detector.

  FIG. 6 is a flowchart showing an example of the operation of the infrared detection device shown in FIG. 1 and the circuit shown in FIG. Each step shown in FIG. 6 may be executed by appropriately using the shutter 21, the pixel array 22, the readout circuit 23, and the like by the control unit 16 shown in FIG.

  In step S11, the infrared detector is turned on. In step S12, the control unit 16 uses the infrared detection device for the first time, there is a temperature change greater than a predetermined temperature difference compared to the temperature at the previous dark current storage, or since the last dark current storage. It is determined whether any of the conditions that the predetermined time or more has passed is satisfied. Regarding the temperature change, the control unit 16 stores the temperature detection value indicated by the temperature sensor 24 during dark current storage, and compares the temperature value indicated by the current temperature sensor 24 with the stored temperature detection value. The control unit 16 may make the determination.

  When any condition of step S12 is satisfied, the control unit 16 closes the shutter 21 in step S13. In step S <b> 14, the control unit 16 controls the readout circuit 23 to execute the dark current storage operation described above, and stores the dark current of the light receiving element 43 of each pixel in the resistance change type memory element 64 for each pixel. To do. At this time, since the voltage of the charge storage capacitor 65 is a voltage reflecting the dark current, an amplified voltage corresponding to the voltage of the charge storage capacitor 65 obtained by this dark current storage operation is applied to one of the CDS circuits. It may be held in a capacitor (eg, capacitor 84 in FIG. 5).

  In step S15, the control unit 16 opens the shutter 21. Thereafter, in step S17, the control unit 16 performs the above-described imaging current detection operation, reflects the sum of the photocurrent and the dark current in the voltage of the charge storage capacitor 65, and applies the amplified voltage corresponding to the voltage to the other of the CDS circuit. (For example, the capacitor 85 in FIG. 5). In step S18, the control unit 16 performs correlated double sampling using the CDS circuit.

  When none of the conditions in step S12 is satisfied, in step S16, the control unit 16 performs the dark current reading operation described above. That is, the control unit 16 reflects the dark current read from the resistance change type memory element 64 in the voltage of the charge storage capacitor 65, and applies the amplified voltage corresponding to the voltage to the other capacitor (for example, the capacitor 85 in FIG. 5). ). Thereafter, the imaging current detection operation in step S17 and the correlated double sampling operation in step S18 are executed.

  After performing correlated double sampling in step S18, the control procedure returns to step S12 to capture the next video frame, and the subsequent processing is repeated. In step S19, a series of video data is output. Note that the timing of data output in step S19 may be changed as appropriate. If the memory for storing a series of video data is not provided, video data for each frame or video data for each row is sequentially output. What should I do?

  As described above, the control unit 16 performs the operation of storing the current amount of the dark current flowing in the light receiving element 43 in the resistance change type memory element 64 once in a plurality of video frames, for example, any condition of step S12 is satisfied. Sometimes run intermittently. In the case of a cooled quantum infrared detector, the operating temperature is ideally constant, and dark current data may be acquired at a fixed operating temperature before shipment. However, in actuality, the actual operating environment temperature slightly changes from moment to moment due to changes in the surrounding environment and aging of the refrigerator. In the infrared detection device 10 shown in FIG. 1 having the readout circuit 23 shown in FIG. 5, by using a resistance change type memory element that is a rewritable nonvolatile memory, it is possible to cope with changes in the external environment, changes in the cooler over time, etc. It is possible to respond flexibly.

  FIG. 7 is a diagram showing an example of the configuration of a resistance change memory element. FIG. 7 is a diagram schematically showing a part of the semiconductor device on which the readout circuit 23 is mounted. A part of the semiconductor device illustrated in FIG. 7 includes a semiconductor substrate 101, a source region diffusion layer 102, a drain region diffusion layer 103, a gate electrode 104, and four layers of metal wirings M1 to M4. In the infrared detector 12 disclosed in the present application, the resistance change type memory element 64 is mounted by being mixed with the readout circuit 23. That is, the resistance change type memory element 64 is mounted so as to be embedded between the metal wiring layers of the read circuit 23.

  Specifically, in a part of the read circuit 23 shown in FIG. 7, the resistance change memory element includes a resistance change material layer 105, an upper metal electrode 106, and a lower metal electrode 107. The upper metal electrode 106 is directly connected to the uppermost metal wiring M4, for example, and the lower metal electrode 107 is connected to the metal wiring M3 through the dedicated via 108, for example.

  The element area of the resistance change type memory element 64 is sufficiently smaller than the area of the light receiving element 43. Furthermore, as described above, the resistance change type memory element 64 is embedded in the metal wiring of the semiconductor device of the read circuit 23. be able to. Therefore, the pixel area of the infrared detector 12 is hardly increased by providing the resistance change type memory element 64 for each pixel.

  FIG. 8 is a diagram for explaining a circuit configuration in the case where a current mirror circuit generates a current having a magnitude that is one time the input current. FIG. 8A shows a schematic plan view of a MOS transistor used in a current mirror circuit as viewed from above. The MOS transistor includes a source region diffusion layer 111, a drain region diffusion layer 112, and a gate electrode 110. The transistor width of this MOS transistor is assumed to be Tw.

  FIG. 8B illustrates an example of a configuration of a current mirror circuit that generates a current that is one-fold larger than the input current. The current mirror circuit shown in FIG. 8B includes MOS transistors 113 and 114 and a resistance change memory element 115. Each of MOS transistors 113 and 114 is the same size as the MOS transistor shown in FIG. 8A and has the same transistor width Tw. By passing a current amount stored in the resistance change type memory element 115 through the MOS transistor 113, the same amount of current as that current can be passed through the MOS transistor 114.

  FIG. 9 is a diagram for explaining a circuit configuration in the case where a current having a magnitude m times the input current is generated by a current mirror circuit. FIG. 9A shows a schematic plan view of a MOS transistor used in a current mirror circuit as viewed from above. This MOS transistor includes a plurality of source region diffusion layers 121, a plurality of drain region diffusion layers 122, and a plurality of gate electrodes 120. By connecting the source region diffusion layers to each other and connecting the drain diffusion layers to each other, it is possible to realize a circuit configuration in which a plurality of MOS transistors having the same transistor width are connected in parallel. It is assumed that the transistor width of each of the plurality of MOS transistors connected in parallel is Tw.

  FIG. 9B illustrates an example of a configuration of a current mirror circuit that generates a current that is m times larger than the input current. The current mirror circuit shown in FIG. 9B includes MOS transistors 123 and 124 and a resistance change type memory element 125. The MOS transistor 123 is a transistor having the same size as the MOS transistor shown in FIG. 8A, for example, and has a transistor width Tw. The MOS transistor 124 is the MOS transistor shown in FIG. 9A, and a plurality of m MOS transistors having a transistor width Tw are connected in parallel. Therefore, the MOS transistor 124 effectively has a transistor width of mTw. By causing the current of the amount of current stored in the resistance change type memory element 125 to flow through the MOS transistor 123, a current that is m times the current can be passed through the MOS transistor 124.

  In the readout circuit 23 shown in FIG. 5 described above, for example, the PMOS transistor 73 may be configured as shown in FIG. In the dark current storage operation, for example, by using only the extreme gate electrode of the gate electrode 120 shown in FIG. 9A, the transistor width of the PMOS transistor 73 is the same as the transistor width of the PMOS transistor 72. And On the other hand, in the dark current reading operation, the transistor width of the PMOS transistor 73 can be made m times the transistor width of the PMOS transistor 72 by using all the gate electrodes. As a result, the current mirror circuit generates a current that is a constant multiple of the read current flowing through the resistance change type memory element 64, and a voltage corresponding to the voltage across the terminals of the charge storage capacitor 65 that has been changed by this constant multiple current is generated. It is possible to output from the reading circuit 44. The PMOS transistors 72 and 73 are provided outside the pixel readout circuit 44 corresponding to each pixel of the pixel array 22, and the pixel area increases even if the configuration is switched as described above between storage and readout. There is no.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

DESCRIPTION OF SYMBOLS 10 Infrared detector 11 Optical system 12 Infrared detector 13 Correction signal processing part 14 Display recording part 15 Cooler 16 Control part 17 Control part 21 Shutter 22 Pixel array 23 Reading circuit 24 Temperature sensor

Claims (9)

A pixel array including a light receiving element for detecting infrared rays provided for each pixel;
A bipolar type resistance change memory element provided for each pixel, a current amount of dark current flowing through the light receiving element can be stored in the resistance change memory element, and readout flowing through the resistance change memory element A readout circuit that outputs a first signal reflecting the amount of current and a second signal reflecting the amount of current flowing through the light receiving element during imaging;
A difference circuit for determining a difference between the first signal and the second signal;
An imaging apparatus including:   The readout circuit further includes a charge storage capacitor provided for each pixel, and between the terminals of the charge storage capacitor changed in accordance with a read current flowing through the resistance change type memory element after resetting the voltage of the charge storage capacitor. A voltage corresponding to a voltage is output as the first signal, and a voltage corresponding to a voltage between the terminals of the charge storage capacitor that has changed due to an imaging current flowing through the light receiving element after the voltage of the charge storage capacitor is reset, The imaging apparatus according to claim 1, wherein the imaging apparatus outputs the second signal.   3. The correlated double sampling circuit according to claim 1, wherein the difference circuit is a correlated double sampling circuit that performs correlated double sampling on the first signal and the second signal sequentially output from the read circuit. Imaging device.   The imaging device according to claim 1, wherein the resistance change type memory element is mixedly mounted in a wiring layer of the readout circuit.   The control circuit further includes a control circuit that controls operations of the pixel array and the readout circuit, and the control circuit stores, in a plurality of video frames, an operation of storing the amount of dark current flowing in the light receiving element in the resistance change type memory element. 5. The imaging apparatus according to claim 1, wherein the readout device is intermittently executed once, and the readout circuit outputs the first signal and the second signal in each video frame. 6.   The read circuit applies a voltage in the first direction to the resistance change type memory element to increase the resistance, and then performs a second operation opposite to the first direction for the resistance change type memory element. 6. The imaging device according to claim 1, wherein a voltage is applied in a direction to reduce the resistance, whereby the amount of dark current flowing through the light receiving element is stored in the resistance change type memory element.   The read circuit further includes a current mirror circuit that generates a current that is a constant multiple of a read current that flows through the resistance change type memory element, and a voltage that corresponds to a voltage across the charge storage capacitor that is changed by the constant multiple current. The imaging apparatus according to claim 2, wherein the image signal is output as the first signal. A cooler,
An optical system that images incident light on the imaging surface;
A shutter that blocks the incident light;
A pixel array provided on the imaging surface including a light receiving element for detecting infrared rays provided for each pixel;
A variable resistance memory element of a bipolar type provided for each pixel, the amount of current flowing through the light receiving element when the shutter is shut off can be stored in the variable resistance memory element; A readout circuit that outputs a first signal reflecting the amount of read current flowing and a second signal reflecting the amount of current flowing through the light receiving element when the shutter is opened;
A difference circuit for determining a difference between the first signal and the second signal;
Infrared detector including. In the bipolar resistance change memory element provided for each pixel of the infrared detector capable of blocking incident light by the shutter, the amount of current flowing through the light receiving element when the shutter is blocked is stored,
After resetting the voltage of the charge storage capacitor, a voltage between the terminals of the charge storage capacitor is changed according to a read current flowing through the resistance change type memory element to generate a first voltage,
After resetting the voltage of the charge storage capacitor, a voltage between the terminals of the charge storage capacitor is changed by a current flowing through the light receiving element when the shutter is opened to generate a second voltage,
A method of correcting a dark current of an infrared detector, including each step of obtaining a difference between a voltage according to the first voltage and a voltage according to the second voltage.

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