JP2017174394A - Semiconductor integrated circuit and clock supply method for semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit capable of high-speed operation by suppressing wiring delay and waveform disturbance of a clock signal. A semiconductor integrated circuit formed on a rectangular semiconductor substrate includes a plurality of timing generation circuits having the same function that generate a plurality of control clock signals based on a control reference clock signal to be acquired; A parallel processing circuit section divided into equal circuit blocks; each circuit block receives a plurality of control clock signals from each corresponding timing generation circuit, and each circuit block receives a plurality of control clock signals input thereto. A plurality of clock distribution networks corresponding to each other are formed, and the parallel processing circuit unit can process each clock distribution network in parallel. Each clock distribution network includes an input buffer circuit; and the input buffer circuit in series. A clock buffer circuit connected and arranged near the center with respect to the longitudinal direction of the semiconductor substrate of the circuit block; Comprises; control output clock signals output from the plurality of terminal devices to be supplied is distributed. [Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit and a clock supply method for the semiconductor integrated circuit.

  In recent years, with the miniaturization and high integration of semiconductor integrated circuits, the clock wiring has become thinner and the interval has become narrower. Therefore, the arrival timing shift due to the delay of the clock signal due to the increase in wiring resistance and wiring capacity (clock clock). Cue), signal voltage attenuation, and steepness of rise / fall characteristics have occurred.

  In general, the internal operation of a semiconductor integrated circuit is performed in synchronization with a clock signal, so if the above problem occurs beyond the allowable value, an incorrect signal may be taken in or beard-like noise may be generated at the output. In some cases, the circuit may malfunction.

  Therefore, as a method for reducing the clock skew, a method in which a plurality of buffer circuits are provided from the input terminal of the clock signal to the end element and the clock supply lines are connected in a tree shape, that is, two clock wirings and four clock wirings are provided. , Eight,..., And a technique for constructing a clock signal distribution system so that the load capacity of the buffer circuit is made equal to each stage is already known.

  However, the conventional method of distributing the clock wiring in a tree shape requires that the wiring between the nodes be designed to have the same length and the same capacity, so that the circuit becomes complicated and difficult to design. Particularly in a solid-state imaging device (such as a linear sensor) in which the aspect ratio of a semiconductor chip is generally several tens of times, it is difficult to arrange a multistage buffer circuit due to design restrictions due to area and the like. In addition, it is difficult to design a wiring with the same wiring length and load capacity, and it is difficult to control the wiring delay and waveform disturbance of the clock signal, making it difficult to operate at high speed.

  Therefore, in Patent Document 1, for the purpose of reducing the occurrence of noise, in the horizontally long solid-state imaging device, the first column AD circuit and the second column in which the signal phases of the portions where the horizontal transfer bus lines intersect are mutually inverted. A configuration is disclosed in which the first column AD circuit 51A and the second column AD circuit are alternately arranged for each predetermined number.

  As another example, the configuration of Patent Document 2 is shown in FIGS. 10A and 10B. FIG. 10A is a block diagram illustrating the configuration of the image sensor, and FIG. 10B is a diagram illustrating the relationship between the image capturing unit and the A / D conversion unit. Independent drive signals (sig_1 to sig_2, sig_3 to sig_4) are generated by a drive control unit arranged on the left side in the drawing and supplied to the pixel unit and the A / D converter. Referring to FIG. 10B, the signal wiring from the drive control unit extends in a horizontal straight line, and the wiring is sequentially connected to the pixel unit and the A / D converter.

  In the configuration of Patent Document 1, it is possible to reduce crosstalk between intersecting signal wirings, but the configuration is such that the wiring resistance and wiring capacitance of signal wirings are reduced and wiring delay and waveform disturbance are suppressed. Not.

  In the configuration of Patent Document 2, between a control signal supplied from a drive control unit to a neighboring pixel unit or an A / D converter and a control signal supplied to a remote pixel unit or an A / D converter, The arrival time may be shifted or the signal voltage may be attenuated. If the arrival time shift or the signal voltage attenuation becomes large, there is a possibility that the high-speed operation may cause a problem that processing is not normally performed in the subsequent digital processing unit due to mismatch of processing timing.

  SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit that suppresses wiring delay and waveform disturbance of a clock signal and enables appropriate high-speed operation.

In order to solve the above problems, according to one embodiment of the present invention, a semiconductor integrated circuit formed over a rectangular semiconductor substrate having a pair of long sides and a pair of short sides can obtain a control reference clock signal. A plurality of timing generation circuits having the same function that generate a plurality of control clock signals based on the same, and a parallel processing circuit section that is divided into circuit blocks having substantially the same area as the plurality of timing generation circuits. And
Each circuit block receives a plurality of control clock signals from each corresponding timing generation circuit, and each circuit block has the same number as the plurality of control clock signals respectively corresponding to the plurality of input control clock signals. A plurality of clock distribution networks are formed, and the parallel processing circuit unit can process in parallel for each clock distribution network,
Each of the clock distribution networks is connected in series with the input buffer circuit to which each control clock signal is input, and the clock that is arranged near the center with respect to the longitudinal direction of the semiconductor substrate of the circuit block. A buffer circuit and a plurality of terminal elements connected to the clock buffer circuit by branching clock wiring and supplied with a control output clock signal output from the clock buffer circuit. Features.

  According to one embodiment, in a semiconductor integrated circuit, wiring delay and waveform disturbance of a clock signal are suppressed, and high-speed operation is enabled.

5 is a configuration example when two timing generation circuits are arranged on the left and right in the semiconductor integrated circuit of one embodiment of the present invention. 6 is a configuration example when four timing generation circuits are arranged in the lower part in a semiconductor integrated circuit according to another embodiment of the present invention. The example which made the clock buffer circuit contained in the parallel processing circuit part of this invention the 2 step | paragraph structure of an inverter. An example in which the clock buffer circuit included in the parallel processing circuit unit of the present invention has a two-output configuration. An example in which a clock buffer circuit included in a parallel processing circuit unit of the present invention is configured to transmit a non-inverted signal and an inverted signal. FIG. 3B is a circuit diagram showing a connection configuration of an inverter, which is a part of the clock buffer circuit of FIG. 3A. The figure which shows the positional relationship of the layout which comprises the inverter of FIG. 5A with a transistor, and load. The figure which shows the example which arrange | positions a phase adjustment circuit in the input stage and output stage of a timing generation circuit. 7 is a configuration example of a phase adjustment circuit provided in the input stage of the timing generation circuit of FIG. 7 is a configuration example of a phase adjustment circuit provided at the output stage of the timing generation circuit of FIG. The figure which shows the example which arrange | positions the phase adjustment circuit for 180 degree | times phase adjustment in the input stage of a timing generation circuit. 8B is a configuration example of a phase adjustment circuit provided at the input stage of the timing generation circuit of FIG. 8A. The figure which shows the example which arrange | positions the phase adjustment circuit for 180 degree | times phase adjustment in the output stage of a timing generation circuit. 9B is a configuration example of a phase adjustment circuit provided at the output stage of the timing generation circuit of FIG. 9A. The semiconductor integrated circuit in a prior art example. FIG. 10B is an enlarged view of the semiconductor integrated circuit of FIG. 10A.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. Note that, in the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

<Configuration example of semiconductor integrated circuit>
FIG. 1 shows a configuration example when two timing generation circuits are arranged on the left and right in a semiconductor integrated circuit according to an embodiment of the present invention. The semiconductor integrated circuit 1 of the present invention is formed on a rectangular semiconductor substrate having a pair of long sides and a pair of short sides. The semiconductor substrate on which the semiconductor integrated circuit of the present invention is formed is applied to a solid-state imaging device such as a linear sensor (also referred to as a linear image sensor or a line image sensor) that is a one-dimensional image sensor.

  The semiconductor integrated circuit 1 includes a parallel processing circuit unit 10 and timing generation circuits 31 and 32. A clock generation circuit 20 is connected to the semiconductor integrated circuit 1 via a buffer 40. Although FIG. 1 shows an example in which one buffer 40 is provided, a plurality of buffers 40 may be arranged in series.

  The clock generation circuit 20 generates a control reference clock signal RCK having a predetermined frequency with reference to an externally input clock, for example, a clock generated by a crystal oscillation circuit using a crystal oscillator. The clock generation circuit 20 can acquire the control reference clock signal RCK and arbitrarily adjust the frequency of the control reference clock signal RCK output to the timing generation circuits 31 and 32 of the semiconductor integrated circuit 1. The clock generation circuit 20 outputs the generated control reference clock signal RCK having a predetermined frequency to the timing generation circuits 31 and 32 via the buffer 40.

  Here, the clock generation circuit 20 can output a control reference clock signal RCK having an arbitrary frequency to the plurality of timing generation circuits 31 and 32, respectively. By making the frequency variable as necessary, the frequency can be lowered and power consumption can be reduced when high-speed operation is unnecessary.

  The clock generation circuit 20 and the buffer 40 may be provided inside the semiconductor integrated circuit 1.

  In the semiconductor integrated circuit 1, the timing generation circuits (timing generators) 31 and 32 have the same function, and based on the control reference clock signal RCK output from the clock generation circuit 20, a plurality of control clock signals CK 1 to CKn are received. Generate. Specifically, the two timing generation circuits 31 and 32 generate a plurality of control clock signals CK1 to CKn in synchronization with a control reference clock RCK having an arbitrary frequency output from the clock generation circuit 20.

  In the parallel processing circuit unit 10, a plurality of circuit blocks 10a and 10b having the same function are arranged in parallel, and the control clock signals CK1 to CKn which are a plurality of input signals can be processed in parallel. The circuit blocks 10a and 10b are divided in the parallel processing circuit unit 10 so that their areas are substantially equal to each other.

N clock distribution networks 11 _{1 to} 11 _n and 12 _{1 to} 12 _n are formed for the plurality of control clock signals CK1 to CKn supplied from the timing generation circuits 31 and 32 for each circuit block 10a and 10b. Yes.

The circuit block 10a includes n input buffer circuits 41 (41 _{1 to} 41 _n ), n clock buffer circuits 51 (51 _{1 to} 51 _n ), and n × number of output terminal elements 61 (n × 61). _{1 to} 61 _p ), and these are connected by a clock wiring 71 (71 _{1 to} 71 _n ).

Similarly, the circuit block 10b includes n input buffer circuits 42 (42 _{1 to} 42 _n ), n clock buffer circuits 52 (52 _{1 to} 52 _n ), and an end element 62 (n × number of outputs p) ( n × 62 _{1 to} 62 _p ), and these are connected by a clock wiring 72 (72 _{1 to} 72 _n ).

In the circuit blocks 10a and 10b having the same function, in the n × 2 clock distribution networks 11 _{1 to} 11 _n and 12 _{1 to} 12 _n , the same number of the same constituent elements are arranged in the same manner. Become.

  A circuit (circuit blocks 10a and 10b including a clock distribution network) having the same function constituting the parallel processing circuit unit 10 is at least one of analog signal processing, analog / digital (A / D) conversion, and digital signal processing. Execute.

  Control clock signals CK1 to CKn output from the timing generation circuits 31 and 32 are independently supplied to the clock distribution networks 11 and 12 of the circuit blocks 10a and 10b, respectively. Note that the same control clock signal (for example, CKx) is supplied from the timing generation circuits 31 and 32 to the corresponding clock distribution networks 11 and 12 of the circuit blocks 10a and 10b at the same timing.

  In each of the clock distribution networks 11 and 12, input buffer circuits 41 and 42 are disposed at the ends of the circuit blocks 10a and 10b, and a plurality of control clock signals CK1 to CKn are directly transmitted.

  Specifically, the input buffer circuits 41 and 42 consider each signal attenuation at the clock wirings 71 and 72 and input each control clock signal so as to have a logical value suitable for the threshold value of the end elements 61 and 62. The waveforms of CK1 to CKn are appropriately amplified and shaped.

  The terminal elements 61 and 62 are switches, for example, or may be connected to a logic circuit such as an FF (flip flop), an inverter, a NAND, or a NOR circuit.

  The clock buffer circuits 51 and 52 are connected in series with the input buffer circuits 41 and 42, respectively. The clock buffer circuits 51 and 52 are arranged near the center with respect to the longitudinal direction of the semiconductor substrate of each circuit block 10a and 10b.

The clock buffer circuits 51 and 52 are provided to prevent the signal level from being attenuated. Specifically, the clock buffer circuits 51 and 52 are portions where the clock wirings 71 and 72 are long. For example, the terminal wirings 61 ₁ , 61 _p , 62 ₁ and 62 _p at the end of FIG. The signals arranged in the input buffer circuits 41 and 42 are adjusted so as to prevent delay from the end elements 61 _c and 62 _c near the center, which is a short part. That is, the buffer circuits 51 and 52 are, for example, signals of the control output clock signal CKxOUT between the plurality of terminal elements 61 _{1 to} 61 _p and 62 _{1 to} 62 _p arranged to be spread in the left-right direction. Prevents timing errors such as rising and falling edges.

A control output clock signal CKxOUT output from the clock buffer circuits 51 and 52 is supplied to the plurality of terminal elements 61 _{1 to} 61 _p and 62 _{1 to} 62 _p (having a predetermined output number p) and output to the output destination. To do.

The clock wirings 71 and 72 are output from the timing generation circuits 31 and 32 in the respective clock distribution networks 11 and 12 ⇒ each input buffer circuit 41 and 42 ⇒ each clock buffer circuit 51 and 52 ⇒ branch ⇒ a plurality of terminal elements 61. _{1 to} 61 _p and 62 _{1 to} 62 _p .

Specifically, clock wirings 71 and 72 for transmitting a plurality of control clock signals CK1 to CKn, respectively, are output terminals of the timing generation circuits 31 and 32, and an input buffer circuit 41 disposed at the end of each circuit block 10a and 10b. , 42 input terminals. The clock wirings 71 and 72 connect the output terminals of the input buffer circuits 41 and 42 to the input terminals of the clock buffer circuits 51 and 52 disposed near the center in the longitudinal direction of the semiconductor substrate of each circuit block. The clock lines 71 and 72 are connected so as to distribute the control output clock signal CKxOUT from the output terminals of the clock buffer circuits 51 and 52 to the plurality of terminal elements 61 _{1 to} 61 _p and 62 _{1 to} 62 _p .

Connected to the output terminal of the clock buffer circuit 51, clock wiring 71, 72 for distributing the control output clock signal CKxOUT, the terminal device ₆₁ 1 respectively included in circuits having the same function of forming a parallel processing circuit section 10 to The number of branches 61 _p and 62 _{1 to} 62 _p is branched, and connected to the plurality of terminal elements 61 _{1 to} 61 _p and 62 _{1 to} 62 _p .

When the end elements 61 _{1 to} 61 _p and 62 _{1 to} 62 _p are switches (loads), they can be configured by, for example, transistor gates (capacitive loads). As described above, by connecting the clock wirings 71 and 72, the control clock signal CKx generated by the timing generation circuits 31 and 32 is stored in the buffers (41x and 42x) and (41x) in the clock distribution networks 11x and 12x. 51x, 52x), and based on the control output clock signal CKxOUT, the plurality of end elements (switches) 61 _{1 to} 61 _p and 62 _{1 to} 62 _p are simultaneously turned on and off.

  In the above configuration, in the semiconductor integrated circuit formed on the rectangular semiconductor substrate, the timing generation circuits 31 and 32 that generate the plurality of control clock signals CK1 to CKn that determine the drive timing in synchronization with the control reference clock signal RCK. Are provided on a semiconductor chip. For example, in the example of FIG. 1, if the control clock signals CK1 to CKn are arranged at two left and right end portions in the longitudinal direction of the semiconductor substrate, the plurality of control clock signals CK1 to CKn are respectively left and right from the two timing generation circuits 31 and 32 toward the center of the substrate. It is possible to supply from.

  By adopting such a configuration, as shown in FIGS. 10A and 10B, the wiring length of the signal wiring can be shortened as compared with the case where only one timing generation circuit is arranged at one end. Can be reduced. Even when the same number of terminal elements are arranged, the number of elements connected to the clock wiring terminal can be reduced, so that the gate capacitance to be driven can be distributed to each timing generation circuit, and the load can be reduced.

  With the above, wiring can be shortened by installing multiple timing generation circuits, so wiring resistance, wiring capacitance, etc. that cause wiring delay, attenuation of signal voltage, deterioration of sharpness of rising and falling characteristics (rounding), etc. Can be reduced. As a result, it is possible to suppress arrival timing shift (clock skew) due to waveform disturbance or clock signal wiring delay, and to increase (fasten) the frequency of the clock signal, thereby enabling stable high-speed operation.

<Another configuration example of a semiconductor integrated circuit>
FIG. 2 shows a configuration example in the case where four timing generation circuits are provided in the lower part in the semiconductor integrated circuit of the present invention. In the configuration example of FIG. 2, four timing generation circuits 31 to 34 are provided in the semiconductor integrated circuit 2, and the parallel processing circuit unit 10-1 has four circuit blocks corresponding to the timing generation circuits 31 to 34. This is different from the configuration of FIG.

  The circuit blocks 10a to 10d are divided in the parallel processing circuit unit 10-1 so that their areas are substantially equal to each other.

Each of the clock distribution networks 11 _{1 to} 11 _n , 121 to 12 _n , 13 _{1 to} 13 _n , and 14 _{1 to} 14 _n of the circuit blocks 10 a, 10 b, 10 c, and 10 d includes timing generation circuits 31, 32, 33, and 34. The output control clock signals CK1 to CKn are supplied independently.

The internal configuration of the clock distribution networks 11 and 12 is the same as that shown in FIG. The clock distribution network 13 includes an input buffer circuit 43, a clock buffer circuit 53, and a plurality of terminal elements 63 _{1 to} 63 _p , which are connected by a clock wiring 73. The clock distribution network 14 includes an input buffer circuit 44, a clock buffer circuit 54, and a plurality of terminal elements 64 ₁ to 64 _p , which are connected by a clock wiring 74.

  In such a configuration, since four timing generation circuits 31 to 34 are provided, the wiring length of the signal wiring can be shortened as compared with the configuration in which only one timing generation circuit is arranged at one end. Resistance and wiring capacitance can also be reduced. In addition, since the number of elements connected to the end of the clock wiring can be reduced, the gate capacitance to be driven can be distributed to each timing generation circuit, and the load can be reduced.

  Also in the above, it is possible to reduce wiring resistance, wiring capacitance, and the like that cause wiring delay, signal voltage attenuation, and steep rise / fall characteristics.

  In the configuration example of FIG. 2, all of the timing generation circuits 31 to 34 are arranged below the parallel processing circuit unit 10-1, but in the semiconductor integrated circuit 2, the timing generation circuits 31 to 34 are located either vertically or horizontally. You may arrange.

<Schematic Configuration Example 1 of Clock Buffer Circuit of Parallel Processing Circuit Unit>
FIG. 3A shows an example in which the clock buffer circuits 51 and 52 included in the parallel processing circuit unit 10 (10-1) of the present invention have a two-stage configuration of inverters. As an example below, FIGS. 3A to 5B will be described using one clock distribution network 11 _x of the circuit block 10 a, but other clock distribution networks 11 _{1 to} 11 _n and circuit blocks of the circuit block 10 a Each of the clock distribution networks 12, 13, and 14 in 10b, 10c, and 10d has the same configuration.

  In the example shown in FIG. 3A, the clock buffer circuit 51α (52α) is composed of a two-stage inverter 210 including a first-stage inverter circuit 201 constituting the preceding stage and a second-stage inverter circuit 202 constituting the latter stage. Yes. Each inverter circuit 201, 202 is composed of a plurality of inverters.

In the first stage inverter circuit 201, N inverters 210 a _{1 to} 210 a _N are connected in parallel to a clock wiring connected to the output terminal of the input buffer circuit 41.

In the second stage inverter circuit 202, M inverters 210b _{1 to} 210b _M are connected in parallel to the output terminal of the first stage inverter circuit 201 which is a plurality of inverters constituting the previous stage.

The output of the clock buffer circuit 51α is connected to the plurality of terminal elements 61 _{1 to} 61 _p by the clock wiring 71, that is, the output signal from the second stage inverter circuit 202 is input to the plurality of terminal elements 61 ₁ to 61 _p . Is done.

  Symbols N and M indicating the number of inverters are set separately from the number n of n control clock signals CK1 to CKn. Regarding the number of inverters connected in parallel, the relationship “the number N of inverters in the first stage inverter circuit 201 <the number M of inverters in the second stage inverter circuit 202” is established. In other words, the drive capability of the second stage inverter circuit 202 which is the subsequent stage inverter is designed to be larger than that of the first stage inverter circuit 201 of the previous stage.

Figures N and M and the frequency of the control clock signal CK1-CKn, terminal devices ₆₁ 1 to 61 _p load (threshold gate capacitance) is determined by a high frequency, as the load is larger N and M to a large value Is set.

<Example 2 of schematic configuration of clock buffer circuit of parallel processing circuit section>
FIG. 3B shows an example in which the clock buffer circuit included in the parallel processing circuit unit 10 of the present invention has a two-output configuration.

In this example, as shown in FIG. 3B, the clock buffer circuit 51β has a dual output configuration having two outputs. In this configuration, a first stage inverter circuit 203 configured with _N inverters 210a _{1 to} 210a _N has the same configuration as the first stage inverter circuit 201, and includes M inverters 210b _{1 to} 210b _M. The second stage inverter circuit 204 has the same configuration as the second stage inverter circuit 202.

  By configuring the clock buffer circuit 51β to have a plurality of outputs, the load driving power can be improved and the inverters 210 as constituent elements can be distributed. In the above description, the two-output configuration has been described. However, a multi-output configuration having three or more outputs may be used.

<Example 3 of schematic configuration of clock buffer circuit of parallel processing circuit unit>
FIG. 4 shows an example in which the clock buffer circuit included in the parallel processing circuit unit of the present invention is configured to transmit a non-inverted signal and an inverted signal.

When it is necessary to invert the control clock signal CLK, for example, one of the first-stage inverter circuits 201 may be replaced with a transfer gate circuit 301 in a clock buffer circuit 51γ as shown in FIG. In this case as well, N transfer gates 310a _{1 to} 310a _N are connected in parallel to the clock wiring connected to the output terminal of the input buffer circuit 41 in the first-stage transfer gate circuit 301.

By providing the transfer gate, the delay of the signal generated in the first stage inverter circuit 201 passing through the wiring connected to the plurality of terminal elements 65 _{1 to} 65 _p is made uniform without inverting the signal.

Similarly to FIG. 3B, the second-stage inverter circuit 202 has a configuration in which _M inverters 210b _{1 to} 210b _M are connected in parallel to the first-stage transfer gate circuit 301, and has a relationship of N <M.

The output of the clock buffer circuit 51γ is connected to a plurality of terminal elements 61 _{1 to} 61 _p and 65 _{1 to} 65 _p by clock wirings 71 and 81, respectively. The end elements 61 _{1 to} 61 _p are, for example, gates of Pch transistors of a CMOS switch, and the end elements 65 _{1 to} 65 _p are, for example, gates of Nch transistors.

  Of course, a circuit configuration that uses only the inverted control output clock signal CKxOUTB obtained by inverting the control output clock signal CKxOUT may be used, or the number of stages of the clock buffer circuit is not limited to two, but may be three or more. good.

  When the number of stages is increased in this way, the drive capability can be increased by increasing the number of subsequent stages.

  In each stage, a plurality of inverters 210 and transfer gates 310 are connected in parallel to form an inverter circuit 201 and a transfer gate circuit 301, so that a semiconductor having a rectangular shape in which a semiconductor substrate is long in one direction like a linear sensor. A layout design with a high area efficiency is possible for the circuit.

<Circuit details of clock buffer circuit>
FIG. 5A is a circuit diagram showing a connection configuration of an inverter which is a part of the clock buffer circuit of FIG. 3A.

  FIG. 5A shows a part of the circuit shown in FIG. 3A. As described above, the first stage inverter circuit 201 and the second stage inverter circuit 202 of the clock buffer circuit 51α are obtained by connecting a plurality of inverters 210 in parallel. The first stage inverter circuit 201 and the second stage inverter circuit 202 are connected by a clock wiring 91.

  As described above, a layout in which a plurality of inverters are connected in parallel enables an area efficient layout.

  FIG. 5B shows a positional relationship of a layout in which the inverter of FIG. 5A is configured by transistors. FIG. 5B shows the internal structure of the inverter 210a constituting the first stage inverter circuit 201 and the inverter 210b constituting the second stage inverter circuit 202, and the layout positional relationship on the layout. In FIG. 5B, the inverters 210a and the inverters 210b are alternately arranged one by one. Of course, two or more inverters 210a and 210b may be alternately arranged as a set.

  Here, since there are N inverters 210a and M inverters 210b and N <M, the number of sets of inverters 210a: the number of sets of inverters 210b = N: M (or one of inverters 210a) The number of sets: the number of sets of inverters 210b ≈ N: M) may be formed and arranged alternately. The same applies when a transfer gate is used.

  As shown in FIG. 5B, each inverter 210a, 210b (inverter cell) of the inverter circuit (plural inverters) 201 (202) constituting the clock buffer circuit 51α is constituted by a Pch transistor 211 and an Nch transistor 212. Has been. Here, the size and shape of the Pch transistor 211 included in the inverter circuit 201 (or 202) are made the same, and the size and shape of the Nch transistor 212 are also made the same. With this configuration, a more efficient area layout is possible.

FIG. 5B shows an example in which terminal elements 61 ₂ and 61 _{3 serving} as loads are connected to a clock buffer circuit 51α configured by each inverter. As shown in FIG. 5B, two inverters 210a and 210b are associated with each of the end elements 61 ₂ and 61 ₃ .

In such a clock buffer 51α, each of the plurality of terminal elements 61 _{1 to} 61 _p that are spatially spread in the horizontal direction is arranged using inverters 210a and 210b that are arranged in close proximity to each other. Therefore, the operation timing among the plurality of end elements 61 _{1 to} 61 _p can be made uniform. Thereby, based on the control output clock signal CKxOUT output from the clock buffer 51α, the plurality of terminal elements (switches) 61 _{1 to} 61 _p can be turned on / off simultaneously without shifting timing.

Further, when the semiconductor integrated circuit 1 of the present invention is applied to a solid-state imaging device, there is a margin in the horizontal direction due to the structure of the fixed imaging device, but space saving is required in the vertical direction. By arranging as shown in FIG. 5B in the clock buffer circuit 51Arufa, while preventing the timing error between the plurality of terminal devices (switches) 61 ₁ to 61 _p, lateral is long in the vertical direction is short, the solid-state imaging device A layout suitable for application can be realized.

  As shown in FIG. 4, in the clock buffer circuit 51α, when a part of the inverter circuit 201 is replaced with the transfer gate circuit 301, each transfer gate 310 (transfer gate cell) of the transfer gate circuit 301 is It is composed of a Pch transistor and an Nch transistor.

  Also in this case, a layout with higher area efficiency can be achieved by the configuration in which the size and shape of the Pch transistor included in the transfer gate 301 are the same and the size and shape of the Nch transistor are the same.

  A configuration in which a plurality of inverters or transfer gates are connected in parallel as shown in FIG. 3 and FIG. 4 is one stage, and a plurality of stages are connected in series, as shown in FIG. Since an inverter can be disposed therein, an area efficient layout is possible.

  Further, in the longitudinal direction of the semiconductor substrate, it is preferable that the interval in which the inverter 210 or the transfer gate 310 is arranged in the clock buffer circuit 51α is not set to the minimum value of the design rule but is sufficiently widened. Specifically, by extending the distance between the inverters 210a and 210b in the horizontal direction in FIG. 5B, it is possible to suppress the extension of the wiring length due to the detouring of the wiring that occurs when the inverters 210a and 210b are too close to each other.

As described above, the inverter 210 or the transfer gate 310 is spatially expanded in the longitudinal direction (lateral direction) of the semiconductor substrate, so that the terminal elements 61 _{1 to} 61 _p arranged at the end portions and the clock buffer circuit 51α. The distance from the inverter or transfer gate arranged on the terminal element side (210b in FIG. 5B) becomes closer. Therefore, suppression of clock signal wiring delay and waveform disturbance becomes more effective.

Note that the cell spacing can be finely adjusted during circuit design. With this configuration, the end elements 61 _{1 to} 61 _p , which are the ends of the circuit, and the clock buffer circuit 51α approach each other.
Generally, a clock skew occurs when the terminal elements 61 and 62 are separated from the inverters constituting the clock buffer circuit 51. For example, if when the clock buffer circuit 51 is arranged only near the end element 61 _c in FIG. 1, the clock supplied to the terminal element 61 _c of the central portion, provided to the terminal device 61 _1, 61 _p of both sides A delay difference occurs in the clock to be transmitted. In order to avoid this, in the configuration of FIG. 5B, the inverters 210 constituting the clock buffer circuit 51α are spatially dispersed, and the terminal element side inverters 210b are arranged near the terminal elements 61 _{1 to} 61 _p. Thus, the delay difference (clock skew) can be reduced.

  Further, by using a common transistor, it is possible to further suppress waveform disturbance and timing deviation (clock skew) due to the position in the longitudinal direction of the semiconductor substrate. For this reason, in this configuration, even when the frequency of the clock signal is increased and high-speed operation is performed, the occurrence of abnormality can be suppressed and processing can be performed normally.

<Phase adjustment circuit example 1>
FIG. 6 shows an example in which phase adjustment circuits are arranged at the input stage and output stage of the timing generation circuit 31. As shown in FIG. 6, the phase adjustment circuit 33 is arranged at the input stage of the timing generation circuit 31, and the phase adjustment circuit 34 is arranged at the output stage of the timing generation circuit 31.

  In FIG. 6, the phase adjustment circuit 33 at the input stage generates a delay reference signal RCKDLY, and supplies the delay reference signal RCKDLY to the timing generation circuit 31 and the phase adjustment circuit 34 at the output stage. The timing generation circuit 31 generates a plurality of control clock signals CK1 to CKn using the delay reference signal RCKDLY as a reference clock for control.

  Then, the phase adjustment circuit 34 at the output stage adjusts the timing of the plurality of control clock signals CK1 to CKn generated based on the control reference clock signal RCK by the delay reference signal RCKDLY to generate the adjustment control clock signal CKxDLY. To the circuit block 10a.

  FIG. 7A shows a configuration example of the phase adjustment circuit 33 provided in the input stage of the timing generation circuit 31 (32) of FIG. FIG. 7B shows a configuration example of the phase adjustment circuit 34 provided at the output stage of the timing generation circuit 31 (32) of FIG.

  7A includes, for example, delay circuits 401, 402, 403, and 404 connected in multiple stages and a multiplexer 410 with multiple inputs. The control reference clock signal RCK input to the phase adjustment circuit 33 becomes a delay reference signal RCKDLY whose phase is delayed by about 0 to 1 cycle with respect to the control reference clock signal RCK by the multistage delay circuit. Is output.

  When the delay time is set more finely, the number of delay circuits is set to four or more. In this case, the multiplexer also has a plurality of stages. Alternatively, the phase adjustment circuit 33 in FIG. 7A may be connected in series.

  7B includes, for example, a multiplexer 411, a clock buffer 420, and a flip-flop (D-FF) 430. In the timing generation circuits 31 and 32 shown in FIG. 6, the phase adjustment can be switched for each signal.

  As described above, since the phase adjustment circuits 33 and 34 capable of arbitrarily adjusting the phase of the control reference clock signal RCK are connected to the timing generation circuit 31 (32), respectively, the phase-adjusted control reference clock is provided. A plurality of control clock signals CK1 to CKn can be generated based on the signal (delayed reference signal RCKDLY).

Here, in the configuration example shown in FIGS. 6 to 7B, the operation timing of the timing generation circuits 31 and 32 is slightly shifted for each of the clock distribution networks 11 _{1 to} 11 _n and 12 _{1 to} 12 _n , thereby Concentration can be prevented and noise caused by current fluctuation can be reduced.

  Further, by making the frequency of the control clock signals CK1 to CKn generated by the timing generation circuit 31 (32) finely variable as necessary, the frequency can be reduced when high-speed operation is unnecessary, and the power consumption can be reduced.

<Phase adjustment circuit example 2>
FIG. 8A shows an example in which a phase adjustment circuit 35 for 180-degree phase adjustment is arranged at the input stage of the timing generation circuit 31. FIG. 8B shows a configuration example of the phase adjustment circuit 35 provided in the input stage of the timing generation circuit 31 (32) of FIG. 8A.

  8A and 8B, the phase adjustment circuit 35 in the input stage generates a delay reference signal RCKDLY and supplies the delay reference signal RCKDLY to the timing generation circuit 31. The input stage phase adjustment circuit 35 shown in FIG. 8B includes an inverter 440, a multiplexer 411, and a clock buffer 420.

  In the phase adjustment circuit 35, the inverter 440 causes the phase difference between the control reference clock signal RCK input from the clock generation circuit 20 and the delay reference signal RCKDLY that is the phase adjusted signal output from the phase adjustment circuit 35 to be 180. It is set to be a degree. In this way, current concentration can be suppressed by shifting the operation timing.

  In the phase adjustment circuit 35 shown in FIG. 8B, the phase difference of the delay reference signal RCKDLY from the control reference clock signal RCK is set to 180 degrees, and therefore, for example, the control reference clock signal RCK only needs to be inverted by the inverter 440. Compared with FIGS. 6 to 7B, the configuration is simple. In this configuration, the multi-stage delay circuits 401 to 404 and the multi-input multiplexer 410 are not necessary, and can be realized by the configuration of the 2-input multiplexer 411, the clock buffer 420, and the inverter 440. That is, the phase adjustment circuit 34 on the output stage side as shown in FIGS. 6 and 7B may not be provided.

  However, in this configuration, the adjustment of the operation timing is limited to 180 degree phase reversal. Therefore, when fine adjustment is required, the configuration shown in FIGS. Select the configuration accordingly.

<Phase adjustment circuit example 3>
FIG. 9A shows an example in which a phase adjustment circuit 36 for 180 degree phase adjustment is arranged at the output stage of the timing generation circuit 31. FIG. 9B shows a configuration example of the phase adjustment circuit 36 provided at the output stage of the timing generation circuit 31 (32) of FIG. 9A.

  The phase adjustment circuit 36 in the output stage shown in FIG. 9B adjusts the timing of the plurality of control clock signals CK1 to CKn generated based on the control reference clock signal RCK by the inverter 440, and outputs the adjusted control clock signal CKxDLY adjusted in timing. Then, it is given to the circuit block 10a. The phase adjustment circuit 36 illustrated in FIG. 9B includes an inverter 440, two flip-flop circuits 430 and 430, an inverter 440, a multiplexer 411, and a clock buffer 420.

  In the configuration example in which the phase adjustment circuit 36 of the output stage shown in FIG. 9B is arranged, unlike FIG. 6, a circuit for generating the delayed reference signal RCKDLY serving as the reference clock is not necessary. Specifically, since the phase can be changed by additionally inserting an inverter 440 into the phase adjustment circuit 34 of the output stage shown in FIG. 7B, the phase adjustment circuit 33 on the input stage side as shown in FIGS. 6 and 7A is not provided. Also good. Therefore, the configuration can be simplified as compared with FIG.

  However, in this configuration, the adjustment of the operation timing is limited to 180 degree phase reversal. Therefore, when fine adjustment is required, the configuration shown in FIGS. Select the configuration accordingly.

  By using the phase adjustment circuit shown in FIGS. 6 to 9B and slightly shifting the operation timing, current concentration can be suppressed.

  Specifically, current fluctuations mainly occur when the clock signal rises and falls. By intentionally shifting the timing, current fluctuations can be dispersed, and noise caused by fluctuations in the power supply voltage or GND due to current fluctuations can be reduced. Can be reduced.

  As mentioned above, although this invention has been demonstrated based on each embodiment, this invention is not limited to the requirements shown in the said embodiment. With respect to these points, the gist of the present invention can be changed without departing from the scope of the present invention, and can be appropriately determined according to the application form.

1,2 semiconductor integrated circuit 10 and 10-1 parallel processing circuit unit 10a, 10b, the circuit block _{11 1 ~11 n, 12 1 ~12} n, 13 1 ~13 n, 14 1 ~14 n clock distribution network 20 clock generation Circuits 201 and 203 First stage inverter circuit (a plurality of inverters constituting the previous stage)
202, 204 Second stage inverter circuit (multiple inverters constituting the latter stage)
210 Inverters 210a, 210a _{1 to} 210a _N inverters (previous inverter cells)
210b, 210b _{1 to} 210b _M inverters (cells of inverters in the subsequent stage)
211 Pch transistor 212 Nch transistor 301 Transfer gate circuit (multiple transfer gates)
310 Transfer gates 310a _{1 to} 310a _N Transfer gates 31 and 32 Timing generation circuit 33 Phase adjustment circuit (input stage side)
34 Phase adjustment circuit (output stage side)
35 Phase adjustment circuit (input stage, phase 180 degree conversion)
36 Phase adjustment circuit (output stage, phase 180 degree conversion)
41, 42 Input buffer circuit 51 (51α, 51β, 51γ), 52 Clock buffer circuit 61 _{1 to} 61 _p , 62 _{1 to} 62 _p , 63 _{1 to} 63 _p , 64 ₁ to 64 _p Terminal element (Pch transistor gate)
65 _{1 to} 65 _p- terminal element (Nch transistor gate)
71, 72, 73, 74 Clock wiring RCK Control reference clock CK1, CKx, CKn Control clock signal CKxOUT Control output clock signal CKxOUTB Inverted control output clock signal RCKDLY Delay reference clock signal CKxDLY Delay clock signal

JP 2009-200546 A Japanese Patent Laid-Open No. 2015-204471

Claims (9)

A semiconductor integrated circuit formed on a rectangular semiconductor substrate having a pair of long sides and a pair of short sides,
A plurality of timing generation circuits having the same function for generating a plurality of control clock signals based on a control reference clock signal to be acquired;
A parallel processing circuit section divided into circuit blocks having substantially the same area as the plurality of timing generation circuits,
Each circuit block receives a plurality of control clock signals from the corresponding timing generation circuits,
In each of the circuit blocks, a plurality of clock distribution networks corresponding to the plurality of input control clock signals, the same number as the plurality of control clock signals, are formed.
The parallel processing circuit unit can process in parallel for each clock distribution network,
Each of the clock distribution networks is
An input buffer circuit to which each control clock signal is input; and
A clock buffer circuit connected in series with the input buffer circuit and disposed near the center with respect to the longitudinal direction of the semiconductor substrate of the circuit block;
A plurality of terminal elements connected to the clock buffer circuit by branching clock lines and supplied with a control output clock signal output from the clock buffer circuit. Integrated circuit. The clock buffer circuit has a configuration in which two or more stages constituted by a plurality of inverters connected in parallel or a plurality of transfer gates are connected in series.
2. The semiconductor integrated circuit according to claim 1, wherein the number of the plurality of inverters or transfer gates constituting the subsequent stage is connected in parallel is larger than the number of the plurality of inverters or transfer gates constituting the preceding stage being connected in parallel. circuit. Each inverter or each transfer gate of the plurality of inverters or the plurality of transfer gates constituting the clock buffer circuit includes a Pch transistor and an Nch transistor,
3. The semiconductor integrated circuit according to claim 1, wherein the Pch transistors included in the plurality of inverters or the plurality of transfer gates have a common size, and the Nch transistors have a common size. 4. circuit. The clock buffer circuit is configured so that the interval between the inverters of the plurality of inverters or the interval between the transfer gates of the plurality of transfer gates is widened in the longitudinal direction of the semiconductor substrate. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit extends spatially in the longitudinal direction. Each of the plurality of timing generation circuits includes a phase adjustment circuit capable of arbitrarily adjusting the phase of the control reference clock signal, and generates a plurality of control clock signals based on the phase-adjusted control reference clock signal. The semiconductor integrated circuit according to any one of claims 1 to 4. The phase adjustment circuit is set so that a phase difference between the control reference clock signal and the phase-adjusted control reference clock signal output from the phase adjustment circuit is 180 degrees. Item 6. The semiconductor integrated circuit according to Item 5. 7. The circuit block having the same function constituting the parallel processing circuit unit executes at least one of analog signal processing, A / D conversion, and digital signal processing. The semiconductor integrated circuit according to any one of the above. A clock generation circuit for generating the control reference clock signal;
The semiconductor integrated circuit according to claim 1, wherein the clock generation circuit is capable of outputting a control reference clock signal having an arbitrary frequency to each of the plurality of timing generation circuits. A clock supply method for a semiconductor integrated circuit, the semiconductor integrated circuit formed on a rectangular semiconductor substrate having a pair of long sides and a pair of short sides, comprising: a plurality of timing generation circuits; The circuit block includes the same number of circuit blocks as the plurality of timing generation circuits, and the circuit block includes a parallel processing circuit unit in which a plurality of clock distribution networks are formed.
The clock supply method is
Generating a plurality of control clock signals based on a control reference clock signal to be acquired in the plurality of timing generation circuits;
In each clock distribution network of the parallel processing circuit unit, each control clock signal is transmitted from each input buffer to each clock buffer circuit, distributed as a control output clock signal, and supplied to a plurality of terminal elements. Have
The clock supply circuit for a semiconductor integrated circuit, wherein each of the clock buffer circuits is arranged near the center with respect to the longitudinal direction of the semiconductor substrate of the circuit block.

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