JP2017168510A - Semiconductor element mounting substrate, semiconductor device, semiconductor element mounting substrate manufacturing method, and semiconductor device manufacturing method - Google Patents

Abstract

When a conductive substrate is dissolved and removed, plating peeling due to a dissolving solution or the like is prevented. A semiconductor element mounting substrate includes a conductive substrate, a semiconductor element mounting portion provided on a surface of the conductive substrate, and the conductive substrate around the semiconductor element mounting portion. A lead portion 30 made of a plating layer provided in a predetermined region on the surface of the substrate, wherein the plating layer includes a base plating layer 31 having a predetermined thickness in contact with the conductive substrate, and an upper side of the base plating layer The main plating layer 32 is provided, and the base plating layer is metal plating soluble in the same kind of etching solution as the conductive substrate. [Selection] Figure 1

Description

  The present invention relates to a semiconductor element mounting substrate, a semiconductor device, a semiconductor element mounting substrate manufacturing method, and a semiconductor device manufacturing method.

  In recent years, as represented by mobile phones, electronic devices are rapidly becoming smaller and lighter, and semiconductor devices used in these electronic devices are also required to be smaller, lighter, and more functional. In particular, the thickness of the semiconductor device is required to be reduced. In order to meet such a demand, a semiconductor device that finally removes a conductive substrate as described below from a semiconductor device using a lead frame processed from a metal material such as QFN (Quad Flat No-Lead) has been developed. Yes.

  Specifically, a resist mask subjected to predetermined patterning is formed on one surface side of a conductive substrate. A conductive metal is plated on the substrate exposed from the resist mask to form a die pad portion to be a semiconductor element mounting portion and a lead portion for connection to the outside, and the semiconductor mask is removed by removing the resist mask. Form. A semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, and the conductive substrate is removed to expose the bottom surfaces of the die pad portion and the lead portion, thereby completing the semiconductor device.

  As a semiconductor device and a method for manufacturing the semiconductor device, for example, in Patent Document 1, a semiconductor chip having electrode pads, a resin package for sealing the semiconductor chip, and a bottom surface of the resin package are exposed in substantially the same plane as the bottom surface. It is described as a semiconductor device having a metal film, one end bonded to the electrode pad, and the other end bonded to the metal film, and a method for manufacturing the device. Further, in Patent Document 2, a plurality of terminal portions arranged so that the external terminal surface forms one plane, a semiconductor element electrically connected to the internal terminal surface of each terminal portion by a wire, and at least each terminal portion A resin-encapsulated semiconductor device comprising a terminal portion and a resin member encapsulating a semiconductor element so that a part of the external terminal surface is exposed to the outside, and the terminal portion has a protrusion around the internal terminal surface The semiconductor device circuit member includes a circuit portion provided on the substrate, and a protrusion is formed around the surface of the circuit portion opposite to the contact surface with the substrate. Has been.

Japanese Patent Laid-Open No. 10-116935 JP 2002-287939 A

  The above-mentioned die pad part and lead part are formed by laminating various types of plating, but recently, the use of pre-plated frame (PPF) which does not require exterior plating for the external connection part after resin encapsulation has increased. ing. For example, a plating layer in which the conductive substrate is removed using this plating structure is formed by laminating each plating layer made of Au, first Pd, Ni, and second Pd in order from the lower layer on the conductive substrate. Often done.

  In the manufacturing process of the semiconductor device described above, a plurality of layers of die pad portions and lead portions as semiconductor element mounting portions are plated on the conductive substrate, and after sealing with resin, the conductive substrate is removed. Yes. As one method for removing the conductive substrate, a dissolution removal method has been devised.

  However, the following problems may occur in the dissolution removal method. That is, when the conductive substrate is dissolved and removed, a Cu alloy is generally used for the conductive substrate, and the plate thickness is generally 0.1 mm to 0.2 mm. In the dissolution removal method, it is necessary to dissolve all of this Cu alloy and expose the plated die pad portion, the bottom surface of the lead portion, and the bottom surface of the sealing resin portion. At this time, depending on the solution management method of the solution, the state of the plating plated on the conductive substrate, etc., depletion may occur between the first Pd plating layer and the Ni plating layer, resulting in a problem of plating peeling. is there. In particular, it is generated from the outer periphery of the lead portion formed of the plating layer.

  The present invention has been made in view of the above problems, and is new and improved that can prevent plating peeling due to the above-described solution when the conductive substrate is dissolved and removed after resin sealing. Another object is to provide a semiconductor element mounting substrate, a semiconductor device, a semiconductor element mounting substrate manufacturing method, and a semiconductor device manufacturing method.

  One aspect of the present invention includes a conductive substrate and a lead portion including a plating layer provided in a predetermined region on the surface of the conductive substrate, and the plating layer is in contact with the conductive substrate. For mounting a semiconductor element, wherein a base plating layer having a thickness and a main plating layer formed above the base plating layer are provided, and the base plating layer is a metal plating soluble in the same kind of etching solution as the conductive substrate Features a substrate.

  According to one aspect of the present invention, by adding a base plating layer, it is possible to prevent the occurrence of a bleed plating layer, and to prevent plating peeling due to the solution when the conductive substrate is dissolved and removed after resin sealing. Can do.

  At this time, in one aspect of the present invention, a semiconductor element mounting portion may be provided on the surface of the conductive substrate, and the lead portion may be provided around the semiconductor element mounting portion.

  In this way, by adding a base plating layer to the semiconductor element mounting substrate having the semiconductor element mounting portion, it is possible to prevent the occurrence of a bleed plating layer, and to dissolve and remove the conductive substrate after resin sealing. The plating peeling by the solution can be prevented.

  At this time, in one embodiment of the present invention, the thickness of the base plating layer may be at least 0.5 μm or more.

  By doing so, it is possible to prevent the bleeding portion of the Au plating layer and the first Pd plating layer of the main plating layer from being generated, and to further prevent plating peeling.

  In one embodiment of the present invention, the thickness of the base plating layer may be 2.0 μm or less.

  In this way, it is possible to prevent the bleeding portion of the Au plating layer and the first Pd plating layer of the main plating layer from occurring, prevent the plating from peeling off, and shorten the plating time and remove the conductive substrate. By shortening, productivity can be improved.

  In one embodiment of the present invention, the conductive substrate may be Cu or a Cu alloy, and the base plating layer may be Cu plating.

  In this way, in the substrate removal process for removing the conductive substrate, the underlying plating layer can be removed at the same time, and the bottom surface of the plated die pad portion and the lead portion can be easily exposed. Can be improved.

  In one embodiment of the present invention, the semiconductor element mounting portion may be a plating layer having the same stacked structure as the plating layer constituting the lead portion.

  According to this configuration, the semiconductor element mounting portion has the same stacked structure as the plating layer that forms the lead portion, so that productivity can be improved.

  According to another aspect of the present invention, there is provided a semiconductor element, a lead portion made of a plating layer, a connection body that electrically connects the semiconductor element and the lead portion, and at least a region other than the bottom surface of the lead portion. A region other than the bottom surface of the semiconductor element and a sealing resin portion that seals the connection body, and the bottom surface of the lead portion is at least 0.5 μm deeper than the bottom surface of the sealing resin portion. The semiconductor device is characterized by a concave portion having a thickness.

  In this way, after the resin sealing, in the semiconductor device in which the conductive substrate is removed and completed, by adding the base plating layer, the Au plating layer of the main plating layer and the bleeding portion of the first Pd plating layer are added. Generation | occurrence | production can be prevented, and when peeling a conductive substrate after resin sealing, plating peeling by a solution can be prevented more.

  In another aspect of the present invention, the semiconductor element may be provided on a semiconductor element mounting portion, and the lead portion may be provided around the semiconductor element mounting portion.

  In this way, by adding a base plating layer to a semiconductor device having a semiconductor element mounting portion, it is possible to prevent the occurrence of a spread plating layer, and when dissolving and removing the conductive substrate after resin sealing, Plating peeling due to can be prevented.

  In another aspect of the present invention, the depth of the recess may be 2.0 μm or less.

  By doing so, it is possible to prevent the bleeding portion of the Au plating layer and the first Pd plating layer of the main plating layer from being generated, and to further prevent plating peeling. Further, productivity can be improved by shortening the plating time and the time for removing the conductive substrate.

  In another aspect of the present invention, the semiconductor element mounting portion may be formed of a plating layer having the same stacked structure as the plating layer constituting the lead portion.

  According to this configuration, the semiconductor element mounting portion has the same stacked structure as the plating layer that forms the lead portion, so that productivity can be improved.

  According to another aspect of the present invention, there is provided a semiconductor element in which a lead portion made of a plating layer is provided in a predetermined region on the surface of the conductive substrate around the semiconductor element provided on the surface of the conductive substrate. A method for manufacturing a mounting substrate, wherein a resist layer is coated on the conductive substrate, a resist mask is formed by patterning a region where a lead portion is provided on the resist layer, and the opening of the resist mask is A base plating layer and a main plating layer for providing the lead portion are formed in a region where the conductive substrate is exposed, and the base plating layer is a metal plating that can be dissolved with the same type of etching solution as the conductive substrate. And the plating solution for base plating is a plating solution resistant to the resist mask.

  In this way, it is possible to add a base plating layer, and since the base plating solution is resistant to the resist mask, it is possible to prevent the resist mask from swelling and prevent the occurrence of a bleed plating layer. When the substrate is dissolved and removed, it is possible to prevent peeling of the plating due to the solution.

  In another aspect of the present invention, the conductive substrate is Cu or a Cu alloy, the resist mask is an alkaline resist mask, and the plating solution for the base plating is an acidic plating solution. It is good as well.

  In this way, in the substrate removal process for removing the conductive substrate, the underlying plating layer can be removed at the same time, and the bottom surface of the plated die pad portion and the lead portion can be easily exposed. Can be improved. Moreover, generation | occurrence | production of a bleed plating layer can be prevented more, and when the conductive substrate is dissolved and removed after resin sealing, plating peeling by the solution can be prevented.

  According to another aspect of the present invention, a semiconductor element is mounted on the semiconductor element mounting substrate manufactured by the method for manufacturing a semiconductor element mounting substrate, and the semiconductor element and the lead portion are electrically connected. The semiconductor device manufacturing method includes sealing at least a region other than the bottom surface of the lead portion, the semiconductor element, and the connection body, and dissolving and removing the conductive substrate.

  If it does in this way, generation | occurrence | production of a bleed plating layer can be prevented by adding a base plating layer, and when peeling a conductive substrate after resin sealing, plating peeling by a solution can be prevented.

  In another aspect of the present invention, the bottom surface of the lead portion may be a recess having a depth of at least 0.5 μm or more from the bottom surface of the sealing resin portion.

  By doing so, it is possible to prevent the bleeding portion of the Au plating layer and the first Pd plating layer of the main plating layer from being generated, and to further prevent plating peeling.

  In another embodiment of the present invention, the depth of the concave portion may be 2.0 μm or less.

  By doing so, it is possible to prevent the bleeding portion of the Au plating layer and the first Pd plating layer of the main plating layer from being generated, and to further prevent plating peeling. Further, productivity can be improved by shortening the plating time and the time for removing the conductive substrate.

  As described above, according to the present invention, by adding a base plating layer, the occurrence of a spread plating layer is prevented, and when the conductive substrate is dissolved and removed after resin sealing, plating peeling due to the solution is prevented. can do.

FIG. 1 is a cross-sectional view showing a semiconductor element mounting substrate according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIGS. 3A to 3F are diagrams schematically showing a series of steps of an example of a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention. 4A to 4D are diagrams schematically showing a series of steps of an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 5A and 5B are cross-sectional views of a semiconductor element mounting substrate and a semiconductor device according to the prior art of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are essential as means for solving the present invention. Not necessarily.

[Semiconductor element mounting substrate, semiconductor device]
A semiconductor element mounting substrate according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a semiconductor element mounting substrate according to an embodiment of the present invention.

  A semiconductor element mounting substrate 50 according to an embodiment of the present invention is provided around a conductive substrate 10, a semiconductor element mounting part 20 disposed thereon, and a semiconductor element mounting part 20 for connection to an external device. And a lead portion 30 in a predetermined area. The conductive substrate 10 functions as a support member for the semiconductor element mounting portion 20 and the lead portion 30. The semiconductor element mounting portion 20 is configured as a semiconductor element mounting area for mounting a semiconductor element. The lead part 30 is a connection terminal that is connected to the electrode of the mounted semiconductor element by wire bonding or the like when the semiconductor element is mounted on the semiconductor element mounting part 20. Depending on the pattern of the semiconductor element mounting substrate 50, there is a pattern in which the semiconductor element mounting portion 20 is not manufactured. For example, there is a type in which a semiconductor element is directly mounted on the conductive substrate 10 or a flip chip connection type in which an electrode of the semiconductor element is directly bonded to a lead portion.

  In the following description, an embodiment in which the semiconductor element mounting portion 20 is provided will be described. However, the present invention is a semiconductor element mounting type in which the semiconductor element mounting portion 20 does not exist and the semiconductor element is directly mounted on a conductive substrate. It can also be applied to a substrate.

  The conductive substrate 10 functions as a base material capable of forming the semiconductor element mounting portion 20 and the lead portion 30 on the conductive substrate surface 10a, and also functions as a support member for the semiconductor element mounting portion 20 and the lead portion 30 after formation. To do. The material of the conductive substrate 10 to be used is not limited as long as it can be dissolved and removed. As the conductive substrate 10, Cu or a Cu alloy having strength and excellent conductivity is often used. In the following embodiments, an example in which a Cu material is used for the conductive substrate 10 will be described.

  The semiconductor element mounting portion 20 and the lead portion 30 are configured by a plating layer formed by plating on one surface 10 a of the conductive substrate 10. This plating layer is composed of base plating layers 21 and 31 and main plating layers 22 and 32. The plating layer of the semiconductor element mounting portion 20 and the plating layer of the lead portion 30 are preferably the same constituent elements. Specifically, it is composed of a base plating layer and a main plating layer. The main plating layer is composed of, for example, a main plating layer in which Au, first Pd, Ni, and second Pd plating are sequentially laminated, and is composed of an undercoat layer and a main plating layer having the same thickness.

  The substrate 50 for mounting a semiconductor element according to the embodiment of the present invention is characterized in that the underlying plating layers 21 and 31 are metal plating that can be dissolved with an etching solution used in the step of dissolving and removing the conductive substrate 10. . Moreover, it is preferable that the plating solution for the base plating layer is a plating solution that does not peel off the resist mask curing portion 41 (see FIG. 3C) described later. Further, activation treatment is performed as a pretreatment for the base plating, and the activation treatment liquid is preferably an activation treatment liquid that resist film curing portion 41 (see FIG. 3C) described later does not peel off. Details of the base plating will be described later.

  The cross-sectional shapes of the semiconductor element mounting portion 20 and the lead portion 30 are not particularly limited, but may be, for example, a square, a rectangle, a rectangle having an overhanging shape on the top, or an inverted trapezoid. From the viewpoint of preventing removal from the sealing resin portion, a rectangular shape having an overhanging shape at the top or an inverted trapezoid is preferable.

  Next, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. The semiconductor device according to the embodiment of the present invention is manufactured using the semiconductor element mounting substrate 50 according to the embodiment of the present invention shown in FIG.

  In the semiconductor device 100 according to the embodiment of the present invention shown in FIG. 2, a semiconductor element 60 is mounted on the semiconductor element mounting portion 20, and the electrode of the semiconductor element 60 and the lead portion 30 are connected by a bonding wire 70 or the like. Thereafter, resin sealing is performed using a sealing resin including the semiconductor element 60 and the bonding wire 70, and finally the conductive substrate 10 is removed, and the bottom surface 20 b of the semiconductor element mounting portion 20 constituted by the main plating layer 22. In addition, the bottom surface 30b of the lead part 30 composed of the main plating layer 32 is exposed. At this time, since the underlying plating layers 21 and 31 (see FIG. 1) are dissolved and removed simultaneously with the conductive substrate 10 (see FIG. 1), the recesses 23, 33. The bottom surface 30b of the lead part 30 serves as an external electrode for soldering with an external device.

  Here, when the conductive substrate 10 is stainless steel such as SUS material, it is often peeled off and removed. However, in this case, it is difficult to adjust the adhesion between the conductive substrate and the plating layers 20 and 30, and when peeling off, the lead portion comes out of the sealing resin portion 80, and the lead portion is on the conductive substrate side. Many of the remaining defects occur. For this reason, it is necessary to take measures such as forming the lead portion in a shape preventing the lead portion or increasing the thickness of the lead portion. For this reason, a method of dissolving and removing the conductive substrate instead of peeling off has been devised.

  Since the method of dissolving and removing the conductive substrate 10 is removed by dissolving with a solution without applying force to the conductive substrate, the lead portion can be prevented from coming off by an easier and simpler method than the peeling method. However, when the conductive substrate 10 is dissolved and removed, Cu or Cu alloy is generally used for the conductive substrate, and the plate thickness is generally 0.1 mm to 0.2 mm. In the dissolution removal method, it is necessary to dissolve all of the conductive substrate 10 and expose the plated semiconductor element mounting portion, the bottom surfaces 20b and 30b of the lead portion, and the bottom surface 80b of the sealing resin portion. At this time, depending on the solution management method of the solution, the state of plating plated on the conductive substrate, etc., when plating bleeding occurs, depletion occurs between the first Pd plating layer and the Ni plating layer, and the plating peels off. May occur. In particular, plating peeling occurs from the outer peripheral edge of the lead portion formed of the plating layer. Therefore, in the embodiment of the present invention, when the conductive substrate is dissolved and removed after resin sealing, the above problem is solved by adding a base plating layer in order to prevent plating peeling due to the above-described solution or the like. It has been made.

  Next, the base plating layer on which the semiconductor element mounting portion 20 and the lead portion 30 are formed, which is a feature of the semiconductor element mounting substrate 50 and the semiconductor device 100 according to an embodiment of the present invention, will be described. First, the mechanism of occurrence of plating peeling that occurs in the peripheral portion of the lead outer shape, which is a conventional problem, will be described.

  In general, the conductive substrate 10 used for the semiconductor element mounting substrate 50 according to the embodiment of the present invention is often made of Cu or a Cu alloy, and the plate thickness is 0.1 mm to 0.2 mm. It is common. Conventionally, the lead portion and the semiconductor element mounting portion are formed by plating on a conductive substrate. Since the plating layer employs Pre-Plated Frame (PPF) that does not require exterior plating at the external connection portion, Au, first Pd, Ni, and second Pd plating are sequentially laminated from the conductive substrate. . In many cases, the plating solution used for Au plating and Pd plating is an alkaline plating solution having high current efficiency. Also, resist masks that are swollen with an alkaline solution having good releasability are often used.

  Therefore, as shown in FIG. 5 (A), when Au plating and first Pd plating are performed, the adhesion between the conductive substrate in contact with the plating solution and the resist mask is weakened, and the resist mask and the conductive properties are reduced. The plating solution may ooze into the gaps between the substrates and may be plated in a foil shape. This portion is referred to as a spread plating layer 130. In addition, as shown in FIG. 5B, when the conductive substrate after resin sealing is dissolved and removed, the foil-like spread plating layer 130 formed in the spread is weak in resin adhesion and is turned over from the sealing resin portion. Thus, the Ni plating layer formed on the Pd plating layer may come into contact with the solution of the conductive substrate. When the solution of the conductive substrate comes into contact with the Ni plating layer, a Ni corrosion potential is generated due to a difference in metal potential between Au, Pd, and Ni, thereby causing a problem that Ni plating is eluted. In particular, when the solution is deteriorated and the halogen balance of the solution is poor, a corrosion potential is likely to occur. In addition, the Au plating and the first Pd plating layer where the Ni plating is eluted cause plating peeling problems. The reason why there are many plating peeling problems in the lead outer portion is that the cause of the plating peeling is due to the spread plating layer 130 generated in the lead outer portion.

  As a result of intensive studies in order to solve the above-described problems of the present invention, the present inventors have applied the Au plating and the first Pd plating to remove the plating layer generated after the resin sealing as described above. In this case, the plating solution bleeds under the resist mask layer, a bleed plating layer is formed, and since the resin adhesion of the bleed plating layer is weak, it is turned up when the conductive substrate is dissolved. It has been found that a Ni corrosion potential is caused by the difference in metal potential due to contact and a part of the Ni plating layer is eluted. In addition, the inventors have found that the problem of peeling of plating can be prevented by newly adding a base plating layer below the conventional plating layer.

  As described above, in order to prevent plating peeling, it is important to eliminate bleeding of the plating solution under the resist mask. The base plating to be performed on the conductive substrate, particularly the thickness and the plating solution are important. For the conductive substrate, Cu or Cu alloy is used, and for the resist mask, an alkaline resist mask having good peelability is generally used. Conventionally, the first plating to be performed is Au plating, and the Au plating solution is an alkaline solution having high current efficiency, and since the plating time is short, the resist mask is not peeled off. In some cases, the plating solution smeared under the mask.

  Therefore, in the semiconductor element mounting substrate 50 according to one embodiment of the present invention, base plating is added. The base plating is metal plating that can be dissolved by the same kind of etching solution as the conductive substrate. Specifically, when the conductive substrate is Cu or Cu alloy, the base plating is preferably Cu plating. In this way, by using metal plating that can be dissolved with the same type of etching solution as the conductive substrate, it is possible to dissolve and remove the conductive substrate and simultaneously remove the underlying plating layer in the manufacturing process of the semiconductor device. In addition, the main plating layer of the semiconductor element mounting portion can be exposed.

  The plating solution for the base plating layer is a solution that does not swell the resist mask. For example, if the base plating is Cu plating, if the resist mask layer is a resist mask that swells with an alkaline stripping solution, the plating solution for the base plating is weakly alkaline, neutral, and more preferably acidic. In the case of a resist mask in which the resist mask layer swells with an acidic stripping solution, the Cu plating solution is a weak acid, neutral, and more preferably an alkaline plating solution. As a result, the resist mask is swollen and plating is performed while maintaining the adhesion between the conductive substrate and the resist mask without causing a gap between the resist mask and the conductive substrate. For this reason, bleeding of the plating solution does not occur. The activation treatment liquid used for the pretreatment for the base plating is preferably a liquid that does not swell the resist as in the above example.

  Thereafter, a main plating layer is formed on the base plating. The main plating layer is a plating layer in which a lead portion and a semiconductor element mounting portion are formed. For example, Au, Pd, Ni, and Pd plating are sequentially laminated. Au, Pd, Ni, and Pd plating can be either electroless plating or electrolytic plating. Preferably, electrolytic plating is used for shortening the plating time. The plating solutions used for Au plating and Pd plating are both alkaline plating solutions. However, when the base plating is performed first, the base plating layer dams the Au and Pd plating solutions, thereby swelling the resist mask. As a result, the plating solution bleeds under the resist mask and no bleed plating layer is generated.

  The thickness of the base plating may be a thickness that can block the boundary between the conductive substrate and the resist mask layer and can dam the Au plating solution and the Pd plating solution. The thickness of the base plating is preferably 0.5 μm or more. When the thickness is less than 0.5 μm, it is difficult to dam the Au plating solution and the Pd plating solution, and it is difficult to prevent the bleeding portion of the Au plating layer and the first Pd plating layer from occurring. More preferably, it is 2.0 μm or less. Still more preferably, the thickness is 0.5 μm or more and 2.0 μm or less. When the thickness is greater than 2.0 μm, the occurrence of a bleeding portion can be prevented, but productivity decreases due to an increase in plating time and an increase in etching time when the conductive substrate is dissolved and removed. Furthermore, the depth of the recessed part mentioned later becomes large and lacks in flatness.

  In the case of a semiconductor device, the base plating is removed simultaneously with the conductive substrate. Therefore, the position of the main plating layer is recessed from the bottom surface of the sealing resin portion to form a concave portion corresponding to the thickness of the base plating. Since the bottom surface of the conventional semiconductor device is flat, it is better to minimize the depth of the recess. If the thickness can block the boundary between the conductive substrate and the resist mask layer and can dam the Au plating solution, the thickness is almost flat, and there is little possibility of causing a problem when connecting to an external device. It is preferably 0.5 μm or more, more preferably 2.0 μm or less, and even more preferably 0.5 μm or more and 2.0 μm or less.

  As described above, in the semiconductor element mounting substrate 50 and the semiconductor device 100 according to the embodiment of the present invention, it is important to control the thickness of the base plating and the depth of the recess as described above. Can solve the problem.

[Manufacturing method of semiconductor element mounting substrate]
Next, with reference to FIG. 3, the manufacturing method of the semiconductor element mounting substrate 50 according to the embodiment of the present invention will be described. 3A to 3F are diagrams schematically showing a series of steps of an example of a method for manufacturing a semiconductor element mounting substrate 50 according to an embodiment of the present invention. In addition, about the component demonstrated so far, the same referential mark is attached | subjected and the description is abbreviate | omitted.

  FIG. 3A is a diagram illustrating an example of a substrate preparation process. In the substrate preparation step, the conductive substrate 10 is prepared. The material of the conductive substrate 10 to be used is not particularly limited as long as it is conductive and can be dissolved and removed, but Cu or Cu alloy is generally used.

  FIG. 3B is a diagram showing an example of a resist coating process. In the resist coating process, the surface 10 a of the conductive substrate 10 is covered with the resist 40. As the resist 40 to be used, a conventionally known method such as laminating a dry film resist, coating a liquid resist, or coating a resist layer by drying can be used.

  FIG. 3C illustrates an example of a resist mask forming process. More specifically, the resist mask formation step includes an exposure step and a development step. In the exposure process, after the resist 40 is coated in the previous resist coating process, a mask (ultraviolet light shielding glass mask) in which the pattern of the desired semiconductor element mounting part 20 and the lead part 30 is formed on the resist 40 is used. Exposure is performed by covering or by laser direct drawing (LDI). Note that the exposure process is not shown in FIG.

  Next, a development process is performed. In the developing step, the resist 40 is developed to remove a portion (uncured portion) where the plating layer is to be formed, and a resist mask is formed by the resist mask curing portion 41 and the resist mask opening 34. The surface 10a is exposed.

  FIG. 3D is a diagram showing an example of the base plating step. In the base plating step, activation processing of the surface 10a of the conductive substrate 10 is performed as a pre-plating process on a portion where the conductive substrate is exposed in the resist mask opening 34, and then the base plating 21 and 31 are performed. Apply. The base plating is metal plating that can be dissolved by the same kind of etching solution as the conductive substrate. When the conductive substrate is Cu or Cu alloy, the underlying plating is preferably Cu plating. If it does in this way, generation | occurrence | production of a bleed plating layer can be prevented, and when the conductive substrate is dissolved and removed after resin sealing, plating peeling by the dissolving liquid can be prevented.

  The plating solution for the base plating layer is a solution that does not swell the resist mask. For example, if the base plating is Cu plating, if the resist mask layer is a resist mask that swells with an alkaline stripping solution, the plating solution for the base plating is weakly alkaline, neutral, and more preferably acidic. In the case of a resist mask in which the resist mask layer swells with an acidic stripping solution, the Cu plating solution is a weak acid, neutral, more preferably an alkaline plating solution. As a result, the resist mask is swollen and plating is performed while maintaining the adhesion between the conductive substrate and the resist mask without causing a gap between the resist mask and the conductive substrate, thereby preventing the occurrence of bleeding of the plating solution. When the conductive substrate is removed after the resin sealing, plating peeling by the solution can be prevented.

  FIG. 3E shows an example of the main plating process. In the main plating step, the main plating layers 22 and 32 are plated following the base plating layer. Conventionally, the main plating layer is a plating layer in which lead portions and die pad portions are formed, and, for example, Au, Pd, Ni, and Pd plating are sequentially laminated. Au, Pd, Ni, and Pd plating can be either electroless plating or electrolytic plating. Preferably, electrolytic plating is used for shortening the plating time.

  FIG. 3F illustrates an example of a resist mask peeling process. In the resist mask peeling step, the hardened resist mask hardening portion 41 is peeled off. The semiconductor element mounting portion 20 and the lead portion 30 are formed on the surface 10 a of the conductive substrate 10.

  Thereafter, the semiconductor element mounting substrate 50 according to the embodiment of the present invention is obtained by cutting the conductive substrate 10 on which the semiconductor element mounting portion 20 and the lead portion 30 are formed into desired dimensions as necessary. . Further, depending on the pattern of the semiconductor element mounting substrate 50, there is a pattern in which the semiconductor element mounting portion 20 is not created. However, the semiconductor element mounting substrate 50 according to the embodiment of the present invention includes the semiconductor element mounting portion 20. And those in which the semiconductor element 60 is directly mounted on the conductive substrate 10 and the semiconductor element mounting portion 20 is not present.

  Since the base plating layer is added by passing through each of the above steps in order, the occurrence of a bleed plating layer is prevented, and when the conductive substrate is dissolved and removed after sealing with the resin, plating peeling due to the solution is prevented. A semiconductor element mounting substrate 50 according to an embodiment of the present invention is manufactured.

[Method for Manufacturing Semiconductor Device]
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram schematically showing a series of steps of an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Since the semiconductor device 100 according to the embodiment of the present invention is manufactured using the semiconductor element mounting substrate 50 according to the embodiment of the present invention, FIGS. 4 (A) to 4 (D) show the semiconductor shown in FIG. This is a continuous process from the manufacturing method of the element mounting substrate 50.

  FIG. 4A is a diagram showing an example of a semiconductor element mounting process. In the semiconductor element mounting step, the semiconductor element 60 is mounted on the semiconductor element mounting portion 20.

  FIG. 4B is a diagram illustrating an example of a wire bonding process. In the wire bonding step, the electrode of the semiconductor element 60 is electrically connected to the lead portion 30 via the bonding wire 70 by wire bonding. As described with reference to FIG. 3E, since the noble metal plating layer for bonding suitable for wire bonding is formed on the surface of the lead portion 30, the bonding wire 70 can be connected smoothly and reliably.

  FIG. 4C is a diagram illustrating an example of a resin sealing process. In the resin sealing step, the region other than the bottom surface of the lead portion 30, the semiconductor element 60, and the bonding wire 70 are sealed with the sealing resin portion 80. In addition, when the semiconductor element mounting portion 20 exists, the region other than the bottom surface of the semiconductor element mounting portion 20 is also sealed in addition to the above.

  FIG. 4D is a diagram illustrating an example of the substrate removing process. In the substrate removal step, the conductive substrate 10 is dissolved and removed from the lower surface of the sealing resin portion 80. At the same time, the base plating is also removed. As a result, the main plating layer is exposed at the bottom surfaces 20b and 30b of the semiconductor element mounting portion 20 and the lead portion 30. Further, the bottom surfaces 20 b and 30 b of the main plating layer are recessed from the sealing resin portion 80 by the thickness of the base plating, and become concave portions 23 and 33.

  Finally, the semiconductor device 100 is completed by cutting to a predetermined semiconductor device size.

  Since the base plating layer was added by passing through the above-mentioned steps in order, the occurrence of a bleed plating layer is prevented, and when the conductive substrate is dissolved and removed after sealing with the resin, plating peeling by the solution is prevented. A semiconductor device 100 according to an embodiment of the present invention that can be manufactured is manufactured.

  Next, the semiconductor element mounting substrate 50 and the semiconductor device 100 according to an embodiment of the present invention will be described in detail with reference to examples. The present invention is not limited to these examples.

  In Example 1 of the semiconductor element mounting substrate and the semiconductor device, a 0.15 mm thick Cu alloy (EFTEC-64T manufactured by Furukawa Electric) was used as the conductive substrate, and after degreasing and acid cleaning treatment, a resist mask (AQ2558 manufactured by Asahi Kasei Co., Ltd., thickness 25 μm) was attached to both sides of the substrate. Next, exposure / development processing was performed on one surface to prepare a predetermined pattern. Then, after pre-plating the part exposed from the resist mask of the board | substrate, 1 micrometer-thick Cu plating was given using the acidic Cu plating bath, and it was set as foundation | substrate plating. Next, 0.03 μm of Au plating and 0.1 μm of first Pd plating were applied. At this time, since the boundary between the conductive substrate and the resist mask was closed with the base plating, plating bleeding did not occur. Thereafter, Ni plating was applied to 10 μm and second Pd plating was applied to 0.1 μm, and the resist mask was peeled and removed to produce a semiconductor element mounting substrate.

  Thereafter, a semiconductor element was mounted on the substrate, and after bonding with a bonding wire, resin sealing was performed. Next, the conductive substrate was dissolved and removed, and at the same time, the base plating was dissolved and removed. Thus, the semiconductor device according to the embodiment of the present invention was completed.

  In Example 2, the thickness of the base plating of Example 1 was 0.5 μm. Others were the same as in Example 1.

  In Example 3, the thickness of the base plating of Example 1 was 2.0 μm. Others were the same as in Example 1.

  On the other hand, in Comparative Example, the base plating was not performed in Example 1, and the main plating layer was directly applied to the conductive substrate. Others were the same as in Example 1.

  About the said Examples 1-3 and the comparative example, it confirmed below. 1000 semiconductor devices according to Examples 1 to 3 and the comparative example were prepared. In addition, about the dissolution removal liquid of the electroconductive board | substrate after the said resin sealing, it adjusted by adjusting pH to the value which falls below a manufacturer's designated lower limit as an acceleration test. As a result of the appearance inspection of the completed samples of Examples 1 to 3, no plating peeling or generation of plating peeling with burrs in the Au plating layer and the first Pd plating layer was observed. It was.

  On the other hand, as a result of visual inspection of the completed sample of the comparative example, a part of plating peeling of about 10 μm was found on the external terminal. About 1% of the Ni plating layer was eluted and the Au plating layer and the first Pd plating layer were peeled off.

  Therefore, in the example of the semiconductor element mounting substrate and the semiconductor device according to one embodiment of the present invention, the plating peeling can be prevented by adding the base plating.

  Although the embodiments and examples of the present invention have been described in detail as described above, it will be understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. It will be easy to understand. Therefore, all such modifications are included in the scope of the present invention.

  For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. In addition, the configuration of the semiconductor element mounting substrate and the semiconductor device, the method of manufacturing the semiconductor element mounting substrate and the semiconductor device, and the operation are not limited to those described in the embodiments and examples of the present invention, and various modifications can be made. It is.

DESCRIPTION OF SYMBOLS 10 Conductive substrate 10a Conductive substrate surface 20 Semiconductor element mounting part 20b Bottom surface of semiconductor element mounting part 21 Underplating layer 22 Main plating layer 30 Lead part 30b Bottom of lead part 31 Underplating layer 32 Main plating layer 34 Resist mask opening DESCRIPTION OF SYMBOLS 40 Resist 41 Resist mask hardening part 50 Semiconductor element mounting substrate 60 Semiconductor element 70 Bonding wire 80 Sealing resin part 80b Bottom surface of sealing resin part 100 Semiconductor device 150 Conventional semiconductor element mounting substrate 130 Bleeding layer 200 Conventional semiconductor device

Claims (15)

A conductive substrate;
A lead portion made of a plating layer provided in a predetermined region on the surface of the conductive substrate,
The plating layer is provided with a base plating layer having a predetermined thickness in contact with the conductive substrate and a main plating layer formed above the base plating layer, and the base plating layer is etched in the same type as the conductive substrate. A substrate for mounting semiconductor elements, which is a metal plating soluble in liquid. A semiconductor element mounting portion is provided on the surface of the conductive substrate,
The semiconductor element mounting substrate according to claim 1, wherein the lead portion is provided around the semiconductor element mounting portion.   The substrate for mounting a semiconductor element according to claim 1 or 2, wherein the thickness of the base plating layer is at least 0.5 µm or more.   4. The substrate for mounting a semiconductor element according to claim 1, wherein a thickness of the base plating layer is 2.0 μm or less. 5.   5. The semiconductor element mounting substrate according to claim 1, wherein the conductive substrate is made of Cu or a Cu alloy, and the base plating layer is made of Cu plating.   6. The semiconductor element mounting substrate according to claim 2, wherein the semiconductor element mounting portion includes a plating layer having the same stacked configuration as the plating layer forming the lead portion. 7. A semiconductor element;
A lead portion made of a plating layer;
A connection body for electrically connecting the semiconductor element and the lead portion;
At least a region other than the bottom surface of the lead portion, a sealing resin portion that seals the semiconductor element and the connection body,
The semiconductor device according to claim 1, wherein a bottom surface of the lead portion is a recess having a depth of at least 0.5 μm or more from a bottom surface of the sealing resin portion. The semiconductor element is provided on a semiconductor element mounting portion,
The semiconductor device according to claim 7, wherein the lead portion is provided around the semiconductor element mounting portion.   The semiconductor device according to claim 7, wherein a depth of the concave portion is 2.0 μm or less.   10. The semiconductor device according to claim 8, wherein the semiconductor element mounting portion includes a plating layer having the same stacked configuration as the plating layer constituting the lead portion. A method for manufacturing a substrate for mounting a semiconductor element, wherein a lead portion comprising a plating layer is provided in a predetermined region on the surface of the conductive substrate around the semiconductor element provided on the surface of the conductive substrate,
Coating a resist layer on the conductive substrate;
Patterning a region where the lead portion is provided in the resist layer to form a resist mask;
Forming a base plating layer and a main plating layer for providing the lead portion in a region where the conductive substrate is exposed in the opening of the resist mask;
The method of manufacturing a semiconductor mounting substrate, wherein the base plating layer is metal plating that can be dissolved by the same kind of etching solution as the conductive substrate, and the plating solution of the base plating is a plating solution resistant to the resist mask .   12. The semiconductor element mounting substrate according to claim 11, wherein the conductive substrate is Cu or a Cu alloy, the resist mask is an alkaline resist, and the plating solution for the base plating is an acidic plating solution. Method. A semiconductor element is mounted on the semiconductor element mounting substrate manufactured by the method for manufacturing a semiconductor element mounting substrate according to claim 11 or 12,
Electrically connecting the semiconductor element and the lead portion;
At least a region other than the bottom surface of the lead portion, the semiconductor element, and the connection body are sealed,
A method for manufacturing a semiconductor device, wherein a conductive substrate is dissolved and removed.   The method of manufacturing a semiconductor device according to claim 13, wherein the bottom surface of the lead portion is a recess having a depth of at least 0.5 μm or more from the bottom surface of the sealing resin portion.   The method of manufacturing a semiconductor device according to claim 14, wherein the depth of the recess is 2.0 μm or less.