JP2017037866A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure capable of reducing stress on a semiconductor substrate or reducing peeling at a bonding interface. A semiconductor device 100 includes a base 2, a metal layer 3 arranged on the base 2, a substantially rectangular semiconductor substrate 1 arranged on the metal layer 3, a base 2 and a metal layer 3. A support portion 8 is provided between the base 2 and the semiconductor substrate 1 and directly below the corner portion of the semiconductor substrate 1, and the support portion 8 is provided. The adhesion between the metal layer 3 and the sealing resin 4 is stronger than the adhesion between the metal layer 3 and the sealing resin 4. [Selection diagram] Fig. 1

Description

  The present invention relates to a semiconductor device having a structure capable of reducing stress on a semiconductor substrate.

  Conventionally, a semiconductor device is packaged by resin sealing after a semiconductor substrate is mounted on a lead frame via a die bonding material. In particular, in a package represented by TO-220, HSOP, etc., a semiconductor substrate is joined to the lead frame via solder in order to achieve excellent thermal conductivity and electrical conductivity. Since the lead frame used here is mainly made of Cu, curing of the die bonding process, the wire bonding process, and the resin sealing process is caused by the difference in the thermal expansion coefficients of the semiconductor substrate, the lead frame, and the sealing resin. Or warp due to thermal history in reflow such as a motherboard mounting (secondary mounting) process. This warpage is transmitted as stress to the semiconductor substrate, causing abnormal electrical characteristics, cracks, peeling at the bonding interface, and the like.

  Furthermore, semiconductor packages are becoming more susceptible to warping due to thinner lead frames for the purpose of further reducing the size, height and performance.

  In general, the die bonding material plays a role of relieving stress by increasing the thickness. In a certain prior art, a support portion is provided immediately below a semiconductor substrate to increase the thickness of the die bonding material (see Patent Document 1).

JP 2007-311577 A

  In general, when stress is generated based on the difference in thermal expansion coefficient between the semiconductor substrate, the lead frame, and the sealing resin, it is known that peeling occurs from the place where the bonding strength between the members is the lowest. Yes. As the bonding strength, the bonding strength between the sealing resin and the die bonding material is the weakest. Further, the maximum stress is likely to occur around the corner of the semiconductor substrate. Conventionally, there has been a problem in which peeling is likely to occur because there is an interface having the weakest bonding strength at a location where the maximum stress is generated. This peeling triggered the peeling to the interface between the semiconductor substrate and the die bonding material, the interface between the sealing resin and the lead frame, and the interface between the wire and the lead frame. In the worst case, the function of the entire semiconductor device There was a possibility of falling into a defect.

  In the technique of Patent Document 1, a spot-like support portion is provided and the thickness of the die bonding material is increased to relieve stress. However, the die bonding material spreads more wet than the outside of the corner portion of the semiconductor substrate. In this case, the interface between the most fragile sealing resin and the die bonding material exists at the corner of the semiconductor substrate where the stress is most applied. Therefore, peeling at the interface between the sealing resin and the die bonding material is easy to occur.

  On the other hand, if the die bonding material does not spread more than the outside of the corner of the semiconductor substrate and the sealing resin is also formed directly under the semiconductor substrate, the interface between the most fragile sealing resin and the die bonding material is Since it is formed directly under the semiconductor, peeling may occur due to stress from the semiconductor substrate and the lead frame. In addition, it is difficult to control the amount of wetting and spreading of the die bonding material when the semiconductor substrate is mounted after the die bonding material is applied to the lead frame. For this reason, the area of the die bonding material in contact with the semiconductor substrate may be extremely reduced, and the heat or electric signal generated from the semiconductor substrate may not be sufficiently transmitted to the lead frame.

  An object of this invention is to provide the semiconductor device provided with the structure which can reduce the stress to a semiconductor substrate or can reduce peeling in a joining interface.

  In order to achieve the above object, a semiconductor device of the present invention comprises a base, a metal layer disposed on the base, a substantially rectangular semiconductor substrate disposed on the metal layer, a base and a metal layer. A sealing resin for sealing the semiconductor substrate, and a support portion is disposed between the base and the semiconductor substrate and immediately below the corner of the semiconductor substrate, and the adhesion between the support portion and the sealing resin Is characterized by being stronger than the adhesion between the metal layer and the sealing resin.

  As a result, since there is no interface between the sealing resin and the metal layer with the weakest bonding strength around the corner of the semiconductor substrate where the greatest stress occurs, peeling at the interface between the sealing resin and the metal layer occurs. Can be suppressed. Furthermore, because the metal layer is closed inside the corner of the semiconductor substrate by the support portion, the metal layer is disposed on the bottom surface of the central portion of the semiconductor substrate, so that the heat dissipation effect and electrical characteristics of the semiconductor substrate can be maintained. it can. Furthermore, the thickness of the metal layer can be controlled by the support portion on the base, and the stress can be suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the highly reliable semiconductor device which suppresses peeling with a semiconductor substrate and a base is implement | achieved.

It is a top view which shows an example of the semiconductor device which concerns on this invention. It is II-II sectional drawing of the semiconductor device of FIG. FIG. 3 is a III-III cross-sectional view of the semiconductor device of FIG. 1. It is a partial expanded sectional view which shows the modification of the support part in FIG. FIG. 4 is a partial enlarged cross-sectional view showing the behavior of solder when solder that hardly segregates is used for the metal layer in FIG. 3. FIG. 4 is a partial enlarged cross-sectional view showing a modification of the semiconductor substrate in FIG. 3. It is a top view which shows the modification of the support part in FIG. It is a top view which shows the other modification of the support part in FIG. It is a top view which shows the further another modification of the support part in FIG. FIG. 3 is a cross-sectional view showing a modification of the semiconductor substrate in FIG. 2. It is a perspective view of the wafer used for manufacture of the semiconductor device of FIG. (A), (b) and (c) is a front view which shows the method of providing a support part in a base. (A), (b) and (c) is a front view which shows the other method of providing a support part in a base. (A), (b), (c), (d) and (e) are front views showing a method of mounting a semiconductor substrate on a base. (A), (b) and (c) is sectional drawing which shows the resin sealing process of the base with which the semiconductor substrate was mounted.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a plan view showing an example of a semiconductor device according to the present invention. 2 is a cross-sectional view taken along the line II-II of the semiconductor device of FIG. 3 is a III-III cross-sectional view of the semiconductor device of FIG.

  The semiconductor device 100 shown in FIGS. 1 to 3 includes a base 2, a metal layer 3 disposed on the base 2, a substantially rectangular semiconductor substrate 1 disposed on the metal layer 3, and a base 2. And a sealing resin 4 that seals the metal layer 3 and the semiconductor substrate 1. A support portion 8 is disposed between the base 2 and the semiconductor substrate 1 and immediately below the corner portion of the semiconductor substrate 1, and the adhesion between the support portion 8 and the sealing resin 4 is the same as that of the metal layer 3. It is stronger than the adhesion with the sealing resin 4.

Here, the base 2 is a lead frame made of, for example, a Cu base material. The metal layer 3 is one of Ag-containing resin paste, solder (PbSn, Bi, AuSn, etc.) and the like. The sealing resin 4 is, for example, an epoxy resin. For example, the support 8 may be a part of the base 2 raised by upset processing. In this case, the material of the support portion 8 is the same as the material of the base 2. Further, the support portion 8 may be a metal, a resin, or the like prepared separately from the base 2, and specifically, a metal such as Au or Ag, or an inorganic material such as SiO ₂ is preferable.

  With such a configuration, the semiconductor device 100 according to the embodiment of the present invention has the following effects.

  That is, the sealing resin at the corner portion of the semiconductor substrate 1 is not present around the corner portion of the semiconductor substrate 1 where the greatest stress is generated, by preventing the interface between the sealing resin 4 and the metal layer 3 having the weakest bonding strength. The occurrence of peeling at the interface between 4 and the metal layer 3 can be suppressed. In other words, around the corner of the semiconductor substrate 1, the interface between the sealing resin 4 and the metal layer 3 is stronger than the interface between the sealing resin 4 and the metal layer 3. It is possible to suppress peeling around the part.

  In addition, since the metal layer 3 is closed inside the corner of the semiconductor substrate 1 by the support portion 8, the metal layer 3 is disposed on the bottom surface of the central portion of the semiconductor substrate 1. Effects and electrical characteristics can be maintained.

  Furthermore, the thickness of the metal layer 3 can be freely controlled by having the support portion 8 on the base 2, and the stress from the semiconductor substrate 1 and the base 2 can be suppressed by increasing the thickness.

  As another configuration, an electrode pad 6 may be provided on the first main surface of the semiconductor substrate 1 as illustrated. An electrode land 9 may be provided on the upper surface of the base 2 as illustrated. The electrode land 9 and the electrode pad 6 may be connected by a wire 5 as illustrated. The base 2 may have a laminated structure of a ceramic and a metal layer in order to improve the high frequency characteristics of the semiconductor device 100.

  In FIG. 1 to FIG. 3, the support portion 8 is disposed so as to straddle adjacent sides of the semiconductor substrate 1 when viewed from above and on the inner side of the outer shape of the semiconductor substrate 1, and outside the support portion 8. In addition, the size and shape are such that the sealing resin 4 exists between the base 2 and the semiconductor substrate 1. In other words, the sealing resin 4 covers the first main surface of the semiconductor substrate 1 and is directly below the corner of the second main surface of the semiconductor substrate 1 and the first main surface of the base 2. Exists between. By having such a configuration, the sealing resin 4 has reached the bottom surface of the corner portion of the semiconductor substrate 1, so that an effect of reducing stress applied to the semiconductor substrate 1 can be expected.

  Further, it is preferable to provide at least two support portions 8 symmetrically with respect to the center of the base 2. Thereby, the thickness of the metal layer 3 immediately below the semiconductor substrate 1 is stabilized, and the metal layer 3 can be provided with a sufficient thickness to alleviate the stress applied to the semiconductor substrate 1. More preferably, there are a total of four at each corner of the semiconductor substrate 1.

  Further, the height of the support portion 8, that is, the distance from the main surface of the base 2 to the second main surface of the semiconductor substrate 1 is preferably approximately 20 μm or more. If the thickness is less than 20 μm, the stress from the base 2, the semiconductor substrate 1, and the sealing resin 4 cannot sufficiently absorb the stress, and when peeling occurs, the semiconductor substrate 1 and the metal layer 3 Separation proceeds in the meantime.

  Furthermore, you may have a groove | channel (not shown) around the support part 8. FIG. Thereby, the shape of the support portion 8 can be efficiently manufactured by press working of a mold or the like.

  As shown in FIG. 4, the cross-sectional shape of the support portion 8 may be a shape having a slope on the side in contact with the metal layer 3. Thereby, the risk that the metal layer 3 reaches the corner of the semiconductor substrate 1 can be suppressed.

  Further, the metal layer 3 may be present outside the outer shape of the semiconductor substrate 1 when viewed from above. That is, it is desirable that the metal layer 3 is wet and spread beyond the periphery of the semiconductor substrate 1. Thereby, it can be confirmed from the upper surface that the metal layer 3 is sufficiently present immediately below the semiconductor substrate 1.

  When the metal layer 3 is made of solder, the electrical resistance and thermal resistance of the metal layer 3 itself can be reduced, and the electrical resistance of the semiconductor substrate 1 is stabilized.

  Here, the point that this configuration is extremely effective when the die bonding material is solder will be described in detail.

  In the unlikely event that peeling occurs around the semiconductor substrate 1, the segregation of the solder proceeds, and the peeling proceeds directly below the semiconductor substrate 1. In particular, in solder containing Pb (the same applies to Bi and the like), Pb crystals are enlarged and segregation is promoted due to thermal shock (temperature cycle) after secondary mounting of the semiconductor device 100 and thermal history such as high-temperature storage. The location where segregation has occurred is extremely fragile, and separation may proceed or cracks may occur due to the effects of stress from the semiconductor substrate 1, the base 2, and the sealing resin 4. In this configuration, the metal layer 3 does not exist around the corner of the semiconductor substrate 1 having the highest stress, and the support 8 and the sealing resin 4 are present to suppress the progress of separation due to segregation, and The influence of cracks is reduced. Moreover, even when the segregation of solder (particularly Pb, Bi, etc.) occurs, the metal layer 3 sufficiently thicker than the crystal grains where the segregation has occurred makes it possible to peel the interface between the semiconductor substrate 1 and the base 2. Can be suppressed.

  Segregation is due to enlargement of crystals, and peeling occurs on a part of the interface between the semiconductor substrate 1 and the base 2 or on the entire surface with the portion as a base point. Therefore, by adding Ag (or Cu) to the PbSn solder, the Pb crystal is distorted to prevent the segregation of Pb.

  FIG. 5 shows the behavior of the solder when a solder that hardly segregates is used for the metal layer 3 in FIG. As shown in FIG. 5, by adding Ag (or Cu) particles 11 to the PbSn solder, distortion is caused to the Pb crystal 10, and segregation of Pb hardly occurs. This means that the solder is not sufficiently melted even at the solder melting temperature. In other words, it means that the solder particles are difficult to move. When the solder is sufficiently melted, the molten solder is sucked directly under the semiconductor substrate 1 by capillary action at the moment when the semiconductor substrate 1 is mounted on the base 2, so that the solder thickness can be kept at a certain thickness or more. it can. Conventionally, when the solder is not sufficiently melted, the capillary phenomenon hardly occurs and the thickness of the solder is reduced. However, according to the present configuration, even when a solder that hardly segregates in the metal layer 3 (for example, PbSnAg, PbSnAgCu, etc.) is used, a certain thickness can be obtained in the metal layer 3 by the support portion 8. The stress from the base 2 can be absorbed and peeling between the semiconductor substrate 1 and the base 2 can be suppressed.

  As shown in FIG. 6, grooves 12 may be provided at least at the corners of the second main surface of the semiconductor substrate 1, preferably in the peripheral region of the second main surface of the semiconductor substrate 1. Thereby, the thickness of the sealing resin 4 or the metal layer 3 can be increased in the corner portion of the semiconductor substrate 1 where stress is concentrated or the peripheral region of the semiconductor substrate 1, and the stress can be efficiently suppressed. .

  Furthermore, since the groove 12 of the semiconductor substrate 1 is rougher than the average roughness of the second main surface of the semiconductor substrate 1, the surface area in contact with the sealing resin 4 and the metal layer 3 is increased, and the bonding strength is improved. In addition, peeling at the interface can be suppressed.

  FIG. 7 shows a modification of the support portion 8 in FIG. As shown in FIG. 7, the support portion 8 may be arcuate around the corner portion of the semiconductor substrate 1. Thereby, each support part 8 can be arrange | positioned in the equal position from the corner | angular part of the semiconductor substrate 1, and the stress to the semiconductor substrate 1 can be equalized.

  FIG. 8 shows another modification of the support portion 8 in FIG. As shown in FIG. 8, the support portion 8 may be substantially perpendicular to the corner portion of the semiconductor substrate 1 in a symmetrical manner. Thereby, when the semiconductor substrate 1 is mounted on the base 2, the metal layer 3 does not protrude from the corner of the semiconductor substrate 1 even when the semiconductor substrate 1 is displaced on the plane with respect to the support portion 8. Can afford.

  FIG. 9 shows still another modification of the support portion 8 in FIG. As shown in FIG. 9, the support portion 8 may be sized and shaped so as to protrude from the corner portion of the semiconductor substrate 1 when viewed from above. Thereby, the semiconductor substrate 1 can be stably mounted by the support portion 8. In addition, when the semiconductor substrate 1 is mounted on the base 2, the metal layer 3 does not protrude from the corner of the semiconductor substrate 1 even when the semiconductor substrate 1 is displaced on the plane with respect to the support portion 8. Can afford.

  As shown in FIG. 10, a metal film 7 may be provided on the second main surface of the semiconductor substrate 1. The material of the metal film 7 is preferably, for example, a Ti—Ni—Ag or Cr—NiCr—Cr—Ag layer from the second main surface of the semiconductor substrate 1. By having the metal film 7 on the surface where the semiconductor substrate 1 is connected to the metal layer 3, the electrical resistance and thermal resistance at the interface between the semiconductor substrate 1 and the metal layer 3 can be lowered, and the electrical characteristics of the semiconductor substrate 1 are reduced. Stabilize.

  Then, the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention is demonstrated.

  FIG. 11 is a perspective view of a wafer 1a used for manufacturing the semiconductor device 100 of FIG. The wafer 1a is an aggregate in which a plurality of the aforementioned semiconductor substrates 1 are formed. The semiconductor substrate 1 is formed by a known method.

  Next, the plurality of semiconductor substrates 1 are singulated (not shown) by dicing. At this time, dicing may be performed in two stages from the second main surface of the semiconductor substrate 1 to form the groove 12 as shown in FIG.

  FIGS. 12A to 12C show a method of providing the support portion 8 on the base 2. Here, pressure is applied from the second main surface of the base 2 with the mold 13 to form the support portion 8 using a half-cut method. In this case, as shown in FIG. 12C, the shape of the groove 14 is formed on the second main surface of the base 2.

  As shown in FIGS. 13A to 13C, the support portion 8 may be formed by pressing with the mold 13 from the first main surface of the base 2. In this case, as shown in FIG. 13C, the shape of the groove 14 is formed around the support portion 8.

  FIG. 14A to FIG. 14E show a method of mounting the semiconductor substrate 1 on the base 2. First, as shown in FIG. 14A, the metal layer 3 is applied on the base 2 on which the support portion 8 is formed. The material of the metal layer 3 is preferably solder. However, before the metal layer 3 is applied, the base 2 is heated to the melting point of the metal layer 3 or higher, and the metal layer 3 is melted and applied to approximately the center of the first main surface of the base 2.

  Thereafter, with the heating state maintained, as shown in FIGS. 14B to 14D, the separated semiconductor substrate 1 is mounted at approximately the center of the first main surface of the base 2. At this time, a hollow region is formed immediately below the corner of the semiconductor substrate 1 by the support portion 8 on the base 2, and the thickness of the metal layer 3 existing between the semiconductor substrate 1 and the base 2 is It is formed stably.

  Here, the semiconductor substrate 1 is mounted while being pushed into the base 2. At this time, since the metal layer 3 is sufficiently melted, there is a risk that the metal layer 3 will be scattered if the mounting speed is high. In particular, when the mounting speed is reduced in order to suppress scattering of the metal layer 3, the contact time between the semiconductor substrate 1 and the base 2 becomes long. Therefore, when the semiconductor substrate 1 has the metal film 7, the semiconductor substrate 1 metal film 7 and base 2 are joined. Therefore, conventionally, the melted metal layer 3 is not sucked directly under the semiconductor substrate 1 due to a capillary phenomenon, and it has been difficult to keep the solder thickness above a certain thickness. However, in the present invention, the support portion 8 can maintain a constant distance between the semiconductor substrate 1 and the base 2, and the metal layer 3 is sucked directly under the semiconductor substrate 1 by capillary action, so that the solder thickness Can be kept above a certain thickness.

  When the metal layer 3 is a resin material containing Ag, the room temperature is desirable when the metal layer 3 is applied on the base 2, and the base 2 is preferably heated after the semiconductor substrate 1 is mounted.

  Next, as shown in FIG. 14 (e), the semiconductor substrate 1 and the base 2 are electrically connected by the wire 5. The wire 5 is preferably an Au wire, a Cu wire, or an Ag wire.

  FIG. 15A to FIG. 15C show a resin sealing process of the base 2 on which the semiconductor substrate 1 is mounted. In this step, the base 2 is fixed to the mold, and the sealing resin 4 is injected into the hollow structure between the mold and the base 2 and is thermoset. At this time, the sealing resin 4 is injected into the hollow region immediately below the corner of the semiconductor substrate 1 by the support portion 8 on the base 2. Thereby, since the interface between the sealing resin 4 and the metal layer 3 having the weakest bonding strength does not exist around the corner portion of the semiconductor substrate 1 where the maximum stress is generated, the occurrence of peeling can be suppressed. Furthermore, the thickness of the metal layer 3 can be controlled and the stress can be suppressed by having the support portion 8 on the base 2.

  In each of the above-described plan view and cross-sectional view, the corners and sides of each component are linearly described. However, the present invention also includes those in which the corners and sides are rounded for manufacturing reasons. include.

  In addition, the materials and numerical values used in the above examples are all exemplified for specifically explaining the present invention, and the present invention is not limited to the exemplified materials and numerical values.

  As described above, the semiconductor device according to the present invention has an effect of reducing stress on the semiconductor substrate, and is useful for semiconductor devices in general.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Wafer 2 Base 3 Metal layer 4 Sealing resin 5 Wire 6 Electrode pad 7 Metal film 8 Support part 9 Electrode land 10 Pb crystal 11 Ag particle 12 Semiconductor substrate groove 13 Mold 14 Base groove 100 Semiconductor apparatus

Claims (7)

The base,
A metal layer disposed on the base;
A substantially rectangular semiconductor substrate disposed on the metal layer;
A sealing resin for sealing the base, the metal layer, and the semiconductor substrate;
A support portion is disposed between the base and the semiconductor substrate and immediately below a corner portion of the semiconductor substrate,
The semiconductor device according to claim 1, wherein an adhesion force between the support portion and the sealing resin is stronger than an adhesion force between the metal layer and the sealing resin. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the support portion is disposed so as to protrude from a corner portion of the semiconductor substrate when viewed from above. The semiconductor device according to claim 1,
The support portion is disposed so as to straddle adjacent sides of the semiconductor substrate when viewed from above and on the inner side of the outer shape of the semiconductor substrate,
A semiconductor device characterized in that the sealing resin exists outside the support portion and between the base and the semiconductor substrate. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein at least two of the support portions are present so as to include two corner portions of the semiconductor substrate facing each other. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device according to claim 1, wherein the metal layer protrudes from an outer shape of the semiconductor substrate when viewed from above. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the semiconductor substrate has a metal film on a surface connected to the metal layer. The semiconductor device according to claim 6.
The semiconductor device, wherein the metal layer is made of solder.

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