JP2017037441A - Process simulator, layout editor and simulation system - Google Patents

Abstract

A process simulator, a layout editor, and a simulation system capable of efficiently designing a semiconductor device are provided. A process simulator 122 includes a layout processing unit 213, an initial mesh generation unit 212, and simulator units 221 to 225. The layout processing unit extracts the coordinates of the vertices of the first figure of the layout of the semiconductor device described in the layout file used for the simulation. The initial mesh generation unit generates a first initial mesh that passes through the coordinates of the vertexes in the plane direction of the layout. The simulator unit executes a process simulation of the semiconductor device based on the simulation data describing the process flow of the semiconductor device, the layout, and the first initial mesh. [Selection] Figure 2

Description

  Embodiments described herein relate generally to a process simulator, a layout editor, and a simulation system.

  A TCAD (Technology CAD) system is known as a simulation system for semiconductor devices. A TCAD system usually includes a process simulator, a device simulator, and a program (such as an electrical characteristic extraction program) that supports their execution and functions.

  The process simulator is an aggregation of simulators that execute simulations of each unit process in the semiconductor manufacturing process. The process simulator calculates the structure (physical quantities such as shape and impurity distribution) of the semiconductor device based on a given manufacturing process (process flow called POR (Process of Record)) and the layout of the semiconductor device. Although there are shape simulators that handle only the shape of semiconductor devices, only process simulations that involve shape changes are collected from process simulators and are included in the process simulator. Called a simulator.

  The device simulator calculates the electrical characteristics of the semiconductor device from the structure of the semiconductor device obtained by the process simulator, the voltage applied to the electrode of the semiconductor device, and the operation mode (static characteristics, dynamic characteristics, etc.) of the semiconductor device. . Some device simulators are called Mixed-mode using a compact model of each element mounted on the circuit simulator, and the same calculation as the circuit simulation is possible. Called a simulator.

  It is desired to efficiently design a semiconductor device using such a TCAD system.

JP 2001-22963 A

  An object of the present invention is to provide a process simulator, a layout editor, and a simulation system that can efficiently design a semiconductor device.

  According to the embodiment, the process simulator includes a layout processing unit, an initial mesh generation unit, and a simulator unit. The layout processing unit extracts the coordinates of the vertices of the first figure of the layout of the semiconductor device described in the layout file used for the simulation. The initial mesh generation unit generates a first initial mesh that passes through the coordinates of the vertexes in the plane direction of the layout. The simulator unit executes a process simulation of the semiconductor device based on simulation data describing a process flow of the semiconductor device, the layout, and the first initial mesh.

It is a block diagram which shows the structure of the TCAD system which concerns on 1st Embodiment. It is a block diagram which shows the structure of the process simulator of FIG. FIG. 3 is a block diagram illustrating a configuration of an initial mesh generation / refinement unit in FIG. 2. FIG. 2 is a block diagram illustrating a configuration of a layout editor / simulation region setting unit in FIG. 1. It is a figure which shows the content of the process simulation input data of FIG. 1, device simulation input data, and characteristic extraction input data. It is a flowchart which shows the algorithm of the initial stage mesh production | generation / refinement part of FIG. It is a top view which shows an example of the layout of MOSFET in the simulation area | region which performs three-dimensional simulation. 6B is a perspective view showing a structure of a MOSFET manufactured using the layout of FIG. 6B. FIG. It is a figure which shows the initial stage mesh produced | generated according to the algorithm of FIG. 6A. It is a flowchart which shows the algorithm of the initial mesh setting of a depth direction. It is a figure which shows a one-dimensional simulation position. It is a figure which shows the simulation result of all the processes using the one-dimensional simulation position of FIG. 7B. It is a flowchart which shows the algorithm of a mesh refinement. It is a figure explaining calculation of the logical product of the figure A and the figure B. FIG. It is a figure which shows the area | region calculated by the logical product of the mask AA and the mask GC. It is a block diagram which shows the structure of the initial stage mesh production | generation / refinement part of a comparative example. It is a block diagram which shows the structure of the layout editor and simulation area | region setting part of a comparative example. It is a flowchart which shows the algorithm of the initial stage mesh setting of the plane direction of a comparative example. It is a figure which shows the shape of the initial stage mesh of a comparative example. It is a figure explaining the problem of the initial stage mesh setting of the plane direction of a comparative example. It is a block diagram which shows the structure of the initial stage mesh production | generation / refinement part of the process simulator which concerns on 2nd Embodiment. It is a flowchart which shows the algorithm of the initial mesh production | generation of the initial mesh production | generation / refinement part of FIG. It is a figure which shows a three-dimensional simulation area | region, a two-dimensional simulation area | region, and a one-dimensional simulation position. It is a perspective view which shows the result of having performed 3D simulation in the 3D simulation area | region. It is a figure which shows the result of having performed 2D simulation in the 2D simulation area | region. It is a figure which shows the mesh of the depth direction produced | generated with the algorithm shown in FIG. 14 in the one-dimensional simulation position in FIG. 15A. It is a top view which shows an example of the layout of MOSFET. It is sectional drawing which followed the BB line of FIG. 16A. It is a figure which shows the mesh in sectional drawing along the BB line of FIG. 16A. It is a block diagram which shows the structure of the initial stage mesh production | generation / refinement part of the process simulator which concerns on 3rd Embodiment. It is a flowchart which shows the algorithm of the mesh refinement which concerns on 3rd Embodiment. It is a figure which shows the three-dimensional simulation area | region set to the layout for simulation of a NAND cell array, and a one-dimensional simulation position. It is a figure which shows an example of the layout of a CMOS inverter. It is a figure which shows an example of the layout of a NAND cell array. It is a block diagram which shows the structure of the layout editor and simulation area | region setting part which concerns on 4th Embodiment. It is a block diagram which shows the structure of the TCAD system which concerns on 4th Embodiment. It is a figure which shows the area | region which should refine a mesh at the time of extracting the normal characteristic etc. of MOSFET. It is a figure which shows the area | region which should refine a mesh at the time of extracting the hot carrier characteristic of MOSFET. It is a figure which shows the line segment which should be refined when extracting the leakage current due to the silicon-insulating film of the MOSFET. It is a figure which shows the area | region which should refine a mesh at the time of extracting the contact resistance of MOSFET. It is a figure which shows the area | region which should refine a mesh at the time of extracting the gate depletion of MOSFET. It is a figure which shows the area | region which should refine a mesh at the time of extracting the influence of the adjacent element of MOSFET.

  Embodiments of the present invention will be described below with reference to the drawings. These embodiments do not limit the present invention.

  FIG. 1 is a block diagram showing a configuration of a TCAD system (simulation system) according to the first embodiment. The TCAD system includes a man-machine interface unit (input / output unit) 10, an editor unit 20, a result display unit 30, and a simulation execution unit 40.

  The man-machine interface unit 10 is for inputting / outputting information, and includes a display device 101, an input device 102, and an output device 103. The engineer performs input such as system control instruction and input data creation using the input device 102 while viewing the display on the display device 101, and outputs information in the system from the output device 103 when necessary. Examples of input data creation include creation of a process flow (POR) and simulation conditions.

  The editor unit 20 includes a text file editor 111 and a layout editor / simulation region setting unit (layout editor) 112. A GUI (Graphical User Interface) may be provided instead of or in addition to the text file editor 111. The layout editor / simulation region setting unit 112 displays and processes layout data used for manufacturing a semiconductor device.

  The engineer creates process simulation input data (simulation data) 161, device simulation input data 162, and characteristic extraction input data 163 using the text file editor 111 via the man-machine interface unit 10.

  Further, the engineer uses the layout editor / simulation area setting unit 112 to input / output the layout file (first layout file) 152, layout processing, simulation area setting, and simulation layout file (second layout file). 164 is created. The simulation layout file 164 is used for simulation of a semiconductor device.

  The result display unit 30 includes a graphics table processing unit 131 that draws numerical data and processes the simulation condition table 182 and the simulation result table 174. The engineer uses graphics table processing to set parameter names and numerical values for changing conditions in the process simulation input data 161, the device simulation input data 162, and the characteristic extraction input data 163 created using the editor unit 20. This is performed by the unit 131. Also, operations such as confirmation of the contents of the simulation result table 174, which is the result of the graphics table processing unit 131 performing aggregation of simulation result files 171 to 173 described later, and output to the outside are performed. This operation may be performed via the controller 121 of the simulation execution unit 40 described later.

  The simulation execution unit 40 includes a controller 121, a 1-3D high-precision process simulator (hereinafter referred to as a process simulator) 122, a 1-3D high-precision device simulator (hereinafter referred to as a device simulator) 123, and electrical characteristics. And at least an extraction unit 124. The simulation execution unit 40 is configured to hold data such as a simulation execution flow 181, simulation result files 171 and 172, and an extraction result file 173 as external files. The engineer creates a simulation execution flow 181 via the controller 121 and gives an execution instruction for simulation and result aggregation.

  The controller 121 takes in the simulation execution flow 181, the simulation condition table 182, the process simulation input data 161, the device simulation input data 162, the characteristic extraction input data 163, and the simulation layout file 164 in accordance with an instruction from the engineer. The controller 121 performs processing such as condition change described in the simulation condition table 182 according to the contents described in the simulation execution flow 181, and input data for the process simulator 122, the device simulator 123, and the electrical characteristic extraction unit 124. Prepare and run the simulation. Note that the process simulation input data 161, the device simulation input data 162, or the characteristic extraction input data 163 are directly targeted without going through the controller 121 if they are not related to the change conditions described in the simulation condition table 182. It may be passed to the process simulator 122, the device simulator 123, or the electrical characteristic extraction unit 124.

  The process simulator 122 executes process simulation using the process simulation input data 161 and the simulation layout file 164 prepared by the controller 121, and stores the simulation result in the simulation result file 171.

  The device simulator 123 executes device simulation using the device simulation input data 162 prepared by the controller 121 and the simulation result file 171 and stores the simulation result in the simulation result file 172.

  The electrical characteristic extraction unit 124 uses the characteristic extraction input data 163 prepared by the controller 121 and the simulation result file 172 to extract the electrical characteristics of the devices in the semiconductor device, and the extracted result to the extraction result file 173. save.

Next, the configuration of the process simulator 122 of FIG. 1 will be described in detail with reference to FIG.
FIG. 2 is a block diagram showing a configuration of the process simulator 122 of FIG. The process simulator 122 includes a controller 201, a program internal data holding unit 202, a basic processing unit 210, a simulator unit 220, and a model / numerical value calculation setting unit 230.

  The controller 201 performs overall control. The program internal data holding unit 202 holds data used in common by each unit. The basic processing unit 210 performs basic processing necessary for executing simulations of various processes. The simulator unit 220 executes various process simulations. The model / numerical calculation setting unit 230 sets a physical / chemical model, model parameters, and a numerical calculation method used in the simulation.

  The basic processing unit 210 includes an initialization unit 211, an initial mesh generation / refinement unit 212, a layout / graphic processing unit 213, and a file input / output unit (file IO unit) 214. The initialization unit 211 performs initial settings for process simulation. The initial mesh generation / refinement unit 212 generates an initial mesh and refines the mesh used for the simulation of the semiconductor device. The layout / graphic processing unit 213 performs layout information processing and layout graphic data processing. The file input / output unit 214 reads and writes simulation results.

  The simulator unit 220 includes at least an ion implantation simulation unit 221, an oxidation / diffusion simulation unit 222, a deposition simulation unit 223, an etching simulation unit 224, and a CMP (Chemical Mechanical Polishing) simulation unit 225.

  The model / numerical calculation setting unit 230 includes a model setting unit 231, a model parameter unit 232, and a numerical calculation setting unit 233. The model setting unit 231 sets and changes a physical / chemical model used in each simulation. The model parameter unit 232 sets and changes model parameters of the physical / chemical model. The numerical calculation setting unit 233 sets and changes how numerical calculation is performed in each physical / chemical model. The model setting unit 231, the model parameter unit 232, and the numerical calculation setting unit 233 are not used for what may be a default setting.

  The controller 201 reads the process simulation input data 161 and activates each unit (each function) of the basic processing unit 210, the simulator unit 220, and the model / numerical value calculation setting unit 230 in accordance with the contents. Each unit 211 to 214, 221 to 225, 231 to 233 uses the data passed from the controller 201 at the time of activation, takes out necessary data from the program internal data holding unit 202, executes each simulation, and stores the result in the program Save to the data holding unit 202.

Next, the initial mesh generation / refinement unit 212 of the process simulator of FIG. 2 will be described with reference to FIG.
FIG. 3 is a block diagram showing a configuration of the initial mesh generation / refinement unit 212 of FIG. The initial mesh generation / refinement unit 212 includes an initial mesh generation / refinement control unit 300, an initial mesh generation control unit 310, a planar direction mesh setting processing unit (mesh setting processing unit) 311, and a depth direction mesh setting processing unit 312. A one-dimensional simulation execution unit 313, an initial mesh generation unit 314, a joint position extraction unit 315 in silicon, a simulation layout processing unit (layout processing unit) 316, a mesh refinement control unit 320, and a planar mesh A refinement setting processing unit 321, a depth direction mesh refinement setting processing unit 322, a graphic calculation unit 323, and a mesh refinement unit 324 are included.

  The initial mesh generation / refinement control unit 300 activates the initial mesh generation control unit 310 or the mesh refinement control unit 320 according to the instructions and parameters given from the controller 201 in FIG. 2, and sends the instructions and necessary information. In addition, the initial mesh generation / refinement control unit 300 sends information of the simulation layout file 164 to the simulation layout processing unit 316 via the initial mesh generation control unit 310 when necessary.

  Based on the instructions and information received from the initial mesh generation / refinement control unit 300, the initial mesh generation control unit 310 performs plane direction mesh setting processing in the plane direction mesh setting processing unit 311. The plane direction is an in-plane direction of a plane parallel to the plane of the layout, that is, a plane parallel to the silicon substrate surface.

  When there is an instruction to use the simulation layout file 164, the simulation layout processing unit 316 extracts the coordinates of the vertices of the semiconductor device layout graphic (first graphic) described in the simulation layout file 164.

  The plane direction mesh setting processing unit 311 performs a plane direction mesh setting process using the extracted vertex coordinates.

  Thereafter, the initial mesh generation control unit 310 performs depth direction mesh setting processing by the depth direction mesh setting processing unit 312, and generates an initial mesh by the initial mesh generation unit 314.

  When there is an instruction to execute the one-dimensional simulation in the depth direction, the depth direction mesh setting processing unit 312 executes the one-dimensional simulation with the one-dimensional simulation execution unit 313. Thereafter, the depth direction mesh setting processing unit 312 extracts the bonding position in the silicon substrate based on the one-dimensional simulation result by the bonding position extraction unit 315 in silicon, and uses the extracted bonding position and the like to obtain the depth. Set the direction mesh.

  Based on the instructions and information received from the initial mesh generation / refinement control unit 300, the mesh refinement control unit 320 performs setting processing for the mesh refinement relationship in the plane direction in the plane direction mesh refinement setting processing unit 321. Thereafter, the mesh refinement control unit 320 performs a mesh refinement setting process in the depth direction with the depth direction mesh refinement setting processing unit 322, and refines the mesh with the mesh refinement unit 324.

  The plane direction mesh refinement setting processing unit 321 performs the figure calculation by the figure calculation unit 323 when there is an instruction to perform the figure calculation, and performs setting processing of the mesh refinement relationship in the plane direction using the result.

Next, the configuration of the layout editor / simulation region setting unit 112 in FIG. 1 will be described with reference to FIG.
FIG. 4 is a block diagram showing a configuration of the layout editor / simulation area setting unit 112 of FIG. The layout editor / simulation area setting unit 112 includes a controller 401, a graphic processing unit 412, a graphic calculation unit 413, a file input / output unit 414, and a mesh setting information processing unit 415.

  The controller 401 controls processing of each unit in cooperation with the display device 101 that performs screen display and the input device 102 that detects key typing or pointer movement performed by an engineer. That is, the controller 401 processes information input from the man-machine interface unit 10 for creating the layout of the semiconductor device.

  The graphic processing unit 412 controls the layout 401 (Point, Edge, Polygon) with respect to the layout before processing under the control of the controller 401 based on the information input to the input device 102. Etc.), processing of the figure, adding an identifier to the figure, and creating a figure indicating a simulation region in which the simulation is performed.

  The graphic computation unit 413 creates a new graphic by performing graphic computation on the graphic created by the graphic processing unit 412 under the control of the controller 401.

  The mesh setting information processing unit 415 lays out the mesh setting information of the initial mesh using the identifier under the control of the controller 401 in accordance with an instruction from the engineer via the input device 102 and the display device 101 (man machine interface unit 10). Correspond to the figure. The mesh setting information includes, for example, initial mesh space information (mesh interval information). Specifically, the mesh setting information processing unit 415 sets mesh setting information for at least one line segment of the layout figure.

  The file input / output unit 414 reads the layout file 152 in which the layout before processing is described, and information on the layout processed by the graphic processing unit 412 and mesh setting information associated with the graphic of the layout using the identifier And a graphic indicating the simulation area are written to the simulation layout file 164.

  The layout file 152 stores semiconductor device layout information and is described in a general format such as the GDS format.

  The simulation layout file 164 includes a layout part, a simulation area part, and a mesh setting information part.

  The layout section describes the layout used in the patterning process (lithography process) of process simulation, and holds the same information as the layout file 152. The layout unit holds a figure obtained by extracting a layout used for an actual simulation based on a mask name (mask ID) and a layer number in the layout file 152.

  The simulation area portion holds a graphic indicating the simulation area (coordinates of the vertex of the simulation area) and the same information (mask ID, layer number, graphic information) as the layout area in the simulation area. The mask ID and, if necessary, the layer number are used to identify one simulation area by extracting one piece of graphic information from a plurality of layout information at the start of process simulation.

  The mesh setting information section includes a plurality of sets of simulation region identifiers and mesh setting information.

  In this way, in the simulation layout file 164, the mesh setting information is associated with each figure (point, edge, polygon) of the layout portion and the simulation region portion as necessary by the identifier of the simulation region. Therefore, it can be understood which figure the mesh setting information is set for.

  Next, the contents of the process simulation input data 161, the device simulation input data 162, and the characteristic extraction input data 163 in FIG. 1 will be described with reference to FIG.

  The process simulation input data 161 includes an initial setting unit, a POR description unit, and a post-process processing unit. In the initial setting section, model settings, model parameter settings, numerical calculation settings, and initial mesh settings used in each process simulation section described in the POR description section are described as necessary. That is, the initialization unit describes a simulation initialization method. The initial mesh setting may include coordinates indicating the simulation region where the initial mesh is set, and numerical values related to the mesh setting in the depth direction.

  Each process simulation part of the POR description part makes a description related to the simulation of the corresponding process according to the POR in which the manufacturing process (process flow) of the semiconductor device is described. At this time, in a process that requires specific settings, description is also made regarding layout processing, model setting, model parameter setting, numerical calculation setting, and mesh refinement setting.

  The post-process processing unit describes electrode settings for device simulation to be performed later and simulation result output settings for display.

  The device simulation input data 162 includes a calculation setting unit, an electrical characteristic calculation unit, and a post-process processing unit.

  The calculation setting unit describes process simulation result input setting, model setting, model parameter setting, numerical calculation setting, and mesh setting. The mesh setting includes information on mesh refinement used when a mesh different from the process simulation mesh is set by device simulation.

  The electrical characteristics calculator sets the voltage control settings that set the voltage (current, charge, etc.) applied to the electrodes, and what analysis methods (static characteristics analysis, dynamic characteristics analysis, etc.) to implement Describe analysis method settings & electrical property calculation settings.

  The post-process processing unit describes the simulation result output setting for subsequent electrical characteristic extraction and display.

  The characteristic extraction input data 163 includes a device simulation result input setting that describes a setting for capturing a device simulation result, an electric characteristic extraction calculation setting that describes how to extract the electric characteristic, and a setting that actually extracts the electric characteristic. And an electrical characteristic extraction setting that describes.

  A semiconductor device is simulated using the TCAD system configured as described above.

  Next, as an example, FIG. 6A to FIG. 8C show initial mesh setting and mesh refinement in process simulation when a three-dimensional simulation of a single MOSFET (Metal-oxide-semiconductor field-effect transistor) is executed with high accuracy. The details will be described.

  FIG. 6A is a flowchart showing an algorithm of the initial mesh generation / refinement unit 212. The initial mesh setting is performed at the initial stage of the process simulation.

  First, in step S1, the initial mesh generation control unit 310 sets silicon substrate information (silicon substrate thickness, impurity type and concentration, etc.).

  Next, in step S2, the plane direction mesh setting processing unit 311 converts the coordinates indicating the simulation area described in the process simulation input data 161 or the simulation layout file 164 into the simulator mesh setting information (second mesh setting information). Add to. Thereby, the outline of the initial mesh in the plane direction (the boundary of the simulation area) is generated so as to pass through the coordinates.

  Next, in step S 3, the simulation layout processing unit 316 extracts the coordinates of the vertices of the figure of the layout described in the simulation layout file 164. Then, the plane direction mesh setting processing unit 311 adds the extracted vertex coordinates to the mesh setting information of the simulator.

  Next, in step S4, the plane direction mesh setting processing unit 311 converts the mesh setting information (first mesh setting information) described in the simulation layout file 164 in association with the figure of the layout into the mesh setting information of the simulator. Add.

  Thereafter, in step S5, the initial mesh generation unit 314 generates an initial mesh in the plane direction (first initial mesh) in the simulation region according to the mesh setting information of the simulator. Specifically, the initial mesh generation unit 314 generates an initial mesh in the plane direction passing through the coordinates of the vertices of the layout figure in the plane direction of the layout (the silicon substrate surface of the semiconductor device).

  FIG. 6B is a plan view showing an example of a MOSFET layout in the simulation region R1 in which the three-dimensional simulation is executed. This layout is composed of five masks AA, GC, V0, M0, and WC. 6C is a perspective view showing the structure of a MOSFET manufactured using the layout of FIG. 6B. In FIG. 6C, the insulating film is not shown in order to clarify the structure.

  FIG. 6D shows an initial mesh generated according to the algorithm of FIG. 6A. A plane simulation region R1 in which a three-dimensional simulation is executed is defined by coordinates Xmin and Xmax in the X-axis direction indicating the simulation region and coordinates Ymin and Ymax in the Y-axis direction. These coordinates Xmin, Xmax and coordinates Ymin, Ymax are described in the process simulation input data 161 or the simulation layout file 164 as described above.

  In FIG. 6D, an initial mesh is generated for the MOSFET layout of FIG. 6B by using a method of designating a space as a mesh generation method. Here, in order to facilitate understanding, a case where the space SP1 is set only for one line segment 1310 of the mask GC is shown. Since the coordinates of the vertices of the figure of the layout are added to the simulator mesh setting information in step S3, a straight line (solid line) 1311 passing through the coordinates of these vertices is generated inside the simulation region R1. In step S4, since mesh setting information including space information of the space SP1 associated with the figure of the mask GC is added to the mesh setting information of the simulator, there is a space on both sides of one line segment 1310 of the mask GC. A straight line (broken line) 1312 is added with the SP1. In this way, since appropriate space information (mesh setting information) can be set for each figure in the layout, the space between the initial mesh and the line segment (edge) of the layout can be set appropriately.

  Next, the depth direction will be described. FIG. 7A is a flowchart showing an algorithm for initial mesh setting in the depth direction. First, after the initial mesh generation process shown in FIG. 6A is performed in step S11, it is determined in step S12 whether or not a numerical value related to mesh setting in the depth direction is described in the process simulation input data 161. When the numerical value related to the mesh setting in the depth direction is described (step S12; Yes), the numerical value described in the process simulation input data 161 is extracted in step S13, and the process proceeds to step S16.

  On the other hand, when the numerical value related to the mesh setting in the depth direction is not described in the process simulation input data 161 (step S12; No), the entire process simulation is executed at the one-dimensional simulation position designated by the engineer in step S14. . The one-dimensional simulation position is a point or a minute region. In step S15, after extracting the bonding position in the silicon substrate based on the one-dimensional simulation result, the process proceeds to step S16.

  Here, the reason why it is divided into step S13 and step S14 will be described. If the impurity concentration distribution in the silicon substrate is known in advance, the position where the mesh should be made fine and the position where the mesh should be made rough can be set in order to perform the numerical calculation accurately and efficiently, but when the impurity concentration distribution is not known. Cannot be set. Therefore, as a solution, a one-dimensional simulation that is faster than the three-dimensional simulation is executed to obtain an impurity concentration distribution. Thereby, for example, the simulation results of all processes using the one-dimensional simulation position P1 of FIG. 7B are as shown in FIG. 7C. From this simulation result, the maximum density position and the joining position are known, and it is possible to determine how to set the mesh density.

  Next, in step S16, the mesh setting in the depth direction is performed based on the value extracted in step S13 or S15. Finally, in step S17, an initial mesh in the depth direction (second initial mesh) is generated.

  The simulator unit 220 of the process simulator 122 performs process simulation of the semiconductor device based on the process simulation input data 161 describing the process flow of the semiconductor device, the layout of the simulation layout file 164, and the initial mesh in the plane direction. Execute.

  Next, with reference to FIGS. 8A to 8C, mesh refinement performed as necessary during each process simulation after the initial mesh is generated will be described. The mesh refinement is performed, for example, in a process in which a description relating to the mesh refinement setting is performed in the POR description part of the process simulation input data 161.

  If the mesh required for the process simulation is different from the mesh required for the device simulation, the mesh refinement is also performed when the device simulation is executed.

  FIG. 8A is a flowchart showing a mesh refinement algorithm. First, in step S <b> 21, a simulation layout file 164 is acquired by the mesh refinement control unit 320.

  Next, in step S22, the graphic calculation process described in the mesh refinement setting of the process simulation input data 161 is performed on the graphic information in the simulation layout file 164 by the graphic calculation unit 323. In this graphic operation processing, for example, as shown in FIG. 8B, when the process simulation input data 161 is designated to calculate the logical product (AND) of the graphic A and the graphic B, the graphic C is created. For example, in the MOSFET having the layout of FIG. 6B, a region calculated by the logical product of the mask AA and the mask GC is a region 810 surrounded by a broken line in FIG. 8C. This region 810 is a region that becomes a channel of the MOSFET, and is a region where a fine mesh should be set. By this calculation, it is possible to determine a region where a fine mesh is to be set, that is, a region to be refined, regardless of how the mask shape changes.

  Next, in step S23, the plane direction mesh refinement setting processing unit 321 acquires a mesh refinement region in the plane direction of the simulation region from the graphic obtained in step S22.

  Next, in step S <b> 24, the depth direction mesh refinement setting processing unit 322 acquires a mesh refinement region in the depth direction described in the process simulation input data 161.

  Next, in step S25, the mesh refinement unit 324 performs mesh refinement using the mesh refinement region acquired in steps S23 and S24 and the mesh refinement method described in the process simulation input data 161.

  The initial mesh setting and the mesh refinement in the process simulation of the semiconductor device are performed as described above.

  Here, a TCAD system of a comparative example will be described. The TCAD system of the comparative example is different from the first embodiment in the functions of the layout editor / simulation region setting unit 112X and the initial mesh generation / refinement unit 212X. Other configurations are the same as those of the first embodiment shown in FIG.

  FIG. 9 is a block diagram illustrating a configuration of the initial mesh generation / refinement unit 212X of the comparative example. The initial mesh generation / refinement unit 212X of the comparative example is not provided with the simulation layout processing unit 316 of the first embodiment. Therefore, as will be described later, the function of the planar direction mesh setting processing unit 311X is also different from that of the first embodiment.

  FIG. 10 is a block diagram illustrating a configuration of the layout editor / simulation region setting unit 112X of the comparative example. The layout editor / simulation region setting unit 112X of the comparative example is not provided with the mesh setting information processing unit 415 of the first embodiment. Therefore, the simulation layout file 164X of the comparative example does not include the mesh setting information unit of the first embodiment.

  FIG. 11A is a flowchart illustrating an algorithm of initial mesh setting in the planar direction of the comparative example. In step S1X of FIG. 11A, the same processing as step S1 of the algorithm of the first embodiment of FIG. 6A is performed.

  Next, in step S2X, the plane direction mesh setting processing unit 311X converts the coordinates described in the process simulation input data 161 or the coordinates of the simulation area described in the simulation layout file 164X into an initial mesh in the plane direction. Set.

  Next, in step S3X, the plane direction mesh setting processing unit 311X adds the internal mesh to the plane direction initial mesh using the space information described in the process simulation input data 161.

  FIG. 11B shows specific information processed by the algorithm shown in FIG. 11A and the shape of the initial mesh in the case of the same MOSFET as that of the first embodiment. The space space01 is associated with the coordinate Xmin, the space space02 is associated with the coordinate Xmax, the space space11 is associated with the coordinate Ymin, and the space space12 is associated with the coordinate Ymax and is described in the process simulation input data 161. The initial mesh of FIG. 11B is generated by the initial mesh generation unit 314 using these data. The interval between adjacent straight lines of the initial mesh is space space01, space02, space11, or space12.

  In such an initial mesh setting in the plane direction of the comparative example, as shown in FIG. 12, the initial mesh M1 and the line segment (edge) of the layout shift, so a new mesh M2 is added to the layout line segment portion. Is done. When the distance d between the new mesh M2 and the initial mesh M1 cannot be ignored, a rectangular mesh Ma flat in the depth direction or a triangular mesh Mb flat in the depth direction is generated at that portion. The flat rectangular mesh Ma or the flat triangular mesh Mb is a mesh having a length in the depth direction longer than the length in the plane direction. In the flat rectangular mesh Ma or the flat triangular mesh Mb, there is a problem that the numerical calculation accuracy is remarkably lowered.

  In order to improve the flat rectangular mesh Ma and the flat triangular mesh Mb, new meshes Ma1 and Mb1 may be generated so that the mesh interval in the depth direction is approximately the same as the distance d. As the number of fine meshes increases, the numerical calculation speed decreases significantly. Moreover, the time for the mesh generation itself is also required. For this reason, there is a problem that due to time constraints, the semiconductor device cannot be sufficiently designed especially when three-dimensional simulation is required.

  On the other hand, in the first embodiment, the coordinates of the vertices of the figure of the layout are extracted, and an initial mesh in the plane direction passing through the coordinates of the extracted vertices is generated. As a result, as shown in FIG. 6D, the initial mesh and the line segment (edge) of the layout can be prevented from shifting. For this reason, compared with FIG. 12 of a comparative example, generation | occurrence | production of the rectangular mesh flat in the depth direction or the triangular mesh flat in the depth direction is suppressed, and the fall of numerical calculation accuracy can be suppressed.

  Further, since it is not necessary to generate a mesh for improving the flat rectangular mesh or the like, it is possible to suppress a decrease in numerical calculation speed. For this reason, it is possible to design a semiconductor device efficiently even when enormous calculations are required, particularly as in a three-dimensional simulation.

(Second Embodiment)
In the second embodiment, in addition to the processing of the first embodiment, an appropriate initial mesh is also generated for the upper structure of the silicon substrate.

  In the TCAD system of the second embodiment, the function of the initial mesh generation / refinement unit 212A of the process simulator 122 is different from that of the first embodiment. Below, it demonstrates centering around difference with 1st Embodiment.

  FIG. 13 is a block diagram illustrating a configuration of the initial mesh generation / refinement unit 212A of the process simulator according to the second embodiment. The difference from the configuration of the initial mesh generation / refinement unit 212 of the first embodiment of FIG. 3 is that a material boundary position extraction unit (hereinafter referred to as a material boundary position extraction unit) 317 on the silicon substrate is added. It is. In FIG. 13, the same reference numerals are given to components common to FIG. 3. In FIG. 13, the mesh refinement control unit 320 and the like related to the mesh refinement are the same as those in the first embodiment of FIG.

  In the present embodiment, the simulation layout file 164 also describes a plurality of one-dimensional simulation positions.

  The one-dimensional simulation execution unit 313 executes a process simulation in the depth direction at a plurality of one-dimensional simulation positions described in the simulation layout file 164.

  The material boundary position extraction unit 317 extracts the material boundary position in the depth direction of the upper part of the silicon substrate (structure on the semiconductor substrate) in the semiconductor device from the result of the process simulation in the depth direction by the one-dimensional simulation execution unit 313.

  The depth direction mesh setting processing unit 312A performs setting for generating a mesh at the material boundary position on the silicon substrate using the extracted material boundary position information.

  The initial mesh generation / refinement control unit 300A and the initial mesh generation control unit 310A send necessary information to the depth direction mesh setting processing unit 312A.

  The simulator unit 220 of the process simulator 122 executes process simulation based on the process simulation input data 161, the layout, the initial mesh in the plane direction, and the initial mesh in the depth direction.

  FIG. 14 is a flowchart showing an initial mesh generation algorithm of the initial mesh generation / refinement unit 212A. First, in step S41, the processes of steps S1 to S5 in FIG. 6A of the first embodiment are performed to generate an initial mesh in the plane direction of the simulation region.

  Next, in step S42, the initial mesh generation control unit 310A makes a list of a plurality of one-dimensional simulation positions in the target simulation region from among the plurality of one-dimensional simulation positions described in the simulation layout file 164. get.

  Next, in step S43, the one-dimensional simulation execution unit 313 executes all process simulations (process simulation) in the depth direction of one one-dimensional simulation position in the list acquired in step S42.

  Next, in step S44, the bonding position extraction unit 315 in silicon extracts the bonding position in the silicon substrate from the result of the one-dimensional simulation. In step S44, the maximum density position may be extracted.

  Next, in step S45, the depth direction mesh setting processing unit 312A performs mesh setting in the depth direction in the silicon substrate based on the extracted bonding position.

  Next, in step S46, the substance boundary position extraction unit 317 extracts the substance boundary position on the silicon substrate from the result of the one-dimensional simulation.

  Next, in step S47, the depth direction mesh setting processing unit 312A performs mesh setting in the depth direction above the silicon substrate based on the extracted substance boundary position.

  Next, in step S48, the initial mesh generation control unit 310A determines whether or not the processing of the one-dimensional simulation position list acquired in step S42 is completed. Then, after the process of step S43 to step S48 is repeated until the process of the list of one-dimensional simulation positions is completed, the process proceeds to step S49.

  In step S49, the initial mesh generation unit 314 generates an initial mesh in the depth direction based on the mesh settings set in steps S45 and S47. That is, an initial mesh in the depth direction passing through the extracted substance boundary position is generated. Thereafter, the process ends.

  Thus, the main difference from FIG. 7A of the first embodiment is that steps S46 and S47 for performing processing relating to the upper part of the silicon substrate are added.

  15A to 15D are diagrams for explaining a mesh in the depth direction generated by the processing of the second embodiment. FIG. 15A is a diagram showing a 3D simulation region R3 for executing a 3D simulation, a 2D simulation region R2 for executing a 2D simulation, and 1D simulation positions P11 to P15 for setting a mesh in the depth direction. is there. FIG. 15B is a perspective view showing a result of executing a three-dimensional simulation in the three-dimensional simulation region R3. FIG. 15C is a diagram illustrating a result of executing the two-dimensional simulation in the two-dimensional simulation region R2.

FIG. 15D is a diagram showing a mesh in the depth direction generated by the algorithm shown in FIG. 14 at the one-dimensional simulation positions P11, P12, and P14 in FIG. 15A. Through the processing in steps S46 and S47 in FIG. 14, a mesh is generated at the material boundary position of the upper structure of the silicon substrate as shown in FIG. 15D. That is, the mesh and the material boundary position of the superstructure are not shifted. In the example of FIG. 15D, the substance boundary position at the one-dimensional simulation position P11 is a boundary position between the via (Via) and the metal wiring (M0). The material boundary position at the one-dimensional simulation position P12 is the boundary position between the interlayer insulating film (ILD) and the gate (Gate), and the boundary position between the gate (Gate) and the gate oxide film (Gox). The material boundary position at the one-dimensional simulation position P14 includes the boundary position between the via (Via) and the metal wiring (M0), the boundary position between the metal wiring (M0) and the gate (Gate), and the gate (Gate) and the trench. (STI) is a boundary position.
Note that, in order to clarify the drawing, FIG. 15D does not show a mesh according to the bonding position in the silicon substrate.

  Here, the problem of the initial mesh setting in the depth direction in the first embodiment will be described with reference to FIGS. In the initial mesh setting in the depth direction in the first embodiment, only the mesh setting in the silicon substrate is performed, and there is a problem that the upper structure above the silicon substrate is not considered. This is sufficient if it is a two-dimensional simulation of only the active area of a single element. However, in the case of a three-dimensional simulation, the superstructure is also complicated. Need to set mesh.

  Here, in the first embodiment, it is conceivable that a space is specified in the same manner as the initial mesh setting in the planar direction of the comparative example, and an initial mesh is also generated in the superstructure. In this case, since the mesh and the material boundary position of the superstructure are deviated, a new mesh is added to the deviated portion. For example, in the single MOSFET shown in FIG. 16A, a low-quality mesh as shown in FIG. Occurs in the structure. FIG. 16C is a diagram showing a mesh in the cross-sectional view along the line BB in FIG. 16A. 16B is a cross-sectional view taken along line BB in FIG. 16A. The low quality mesh represents a fine mesh generated in the insulating film 100 or the like that originally does not require a fine mesh. In such a case, there is a problem that the simulation accuracy of the device simulation is lowered or the simulation speed is lowered.

  In order to consider even the superstructure, it is necessary to execute a one-dimensional simulation at a plurality of points where the superstructure is different. That is, in the two-dimensional simulation, it is necessary to perform a one-dimensional simulation of at least four points P1 to P4 in FIG. 16A, and to execute a one-dimensional simulation of at least five points P1 to P5 in the three-dimensional simulation. However, in the first embodiment, since the one-dimensional simulation deals only with the silicon substrate, there is a problem that the structure in the silicon substrate is limited to the simulation of three points P1, P2, and P4 which are different from each other.

  On the other hand, in the second embodiment, the material boundary position in the depth direction of the structure on the silicon substrate is extracted from the result of the process simulation in the depth direction, and the depth direction passing through the extracted material boundary position. Generate an initial mesh of. That is, in the initial mesh setting in the depth direction, not only the bonding position in the silicon substrate as in the first embodiment but also the upper structure above the silicon substrate is considered. In the two-dimensional simulation, a one-dimensional simulation of at least four points of the one-dimensional simulation positions P11 to P14 in FIG. 15A is executed, and in the three-dimensional simulation, a one-dimensional simulation of at least five points of the one-dimensional simulation positions P11 to P15 is executed. To do.

  Thereby, in the case of a single MOSFET, a low quality mesh as shown in FIG. 16B does not occur in the structure above the silicon substrate. Therefore, even when the upper structure is complicated as in the three-dimensional simulation, it is possible to suppress a decrease in simulation accuracy and a decrease in simulation speed in device simulation. That is, the semiconductor device can be designed efficiently.

(Third embodiment)
In the third embodiment, in addition to the processing of the second embodiment, mesh refinement of a selected region is performed.

  The TCAD system of the third embodiment is different from the second embodiment in the function of the initial mesh generation / refinement unit 212B of the process simulator 122. Below, it demonstrates centering around difference with 2nd Embodiment.

  FIG. 17 is a block diagram illustrating a configuration of the initial mesh generation / refinement unit 212B of the process simulator 122 according to the third embodiment. The difference from the configuration of the initial mesh generation / refinement unit 212A of the second embodiment in FIG. 13 is that a one-dimensional simulation position inclusion determination unit (graphic selection unit) 325 is added. In FIG. 17, the same reference numerals are given to components common to FIG. 13. In FIG. 17, the initial mesh generation control unit 310A and the like related to the initial mesh generation are the same as those in FIG.

  The engineer designates one of a plurality of one-dimensional simulation positions described in the simulation layout file 164 via the man-machine interface unit 10.

  The one-dimensional simulation position inclusion determination unit 325, when a plurality of figures are generated by the figure calculation unit 323, the one-dimensional simulation position specified in advance by the engineer described in the simulation layout file 164 has a plurality of figures. It is determined whether each is included, and a figure including a one-dimensional simulation position designated in advance is selected from a plurality of figures.

  The plane direction mesh refinement setting processing unit 321 sets a mesh refinement region in the plane direction at the position of the graphic selected by the inclusion determination unit 325 of the one-dimensional simulation position.

  The initial mesh generation / refinement control unit 300B and the mesh refinement control unit 320B send an instruction and necessary information to the planar direction mesh refinement setting processing unit 321.

  FIG. 18A is a flowchart illustrating a mesh refinement algorithm according to the third embodiment. FIG. 18A corresponds to FIG. 8A.

  Similar to the mesh refinement algorithm of the first embodiment shown in FIG. 8A, first, in step S51, a simulation layout is acquired, and in step S52, the graphic operation processing described in the process simulation input data 161 is performed. . Specifically, in step S52, the graphic calculation unit 323 performs graphic calculation described in the process simulation input data 161 on the layout graphic (first graphic), and a new graphic (second graphic) is obtained. Generate. The graphic operation includes, for example, a logical product operation.

  Next, in step S53, when there are a plurality of figures (polygons) obtained by the figure calculation in step S52 by the one-dimensional simulation position inclusion determination unit 325, the simulation layout file 164 specified in advance by the engineer is stored in the simulation layout file 164. It is determined whether or not a one-dimensional simulation position is included, and one is selected from a plurality of figures.

  Next, in step S54, the plane direction mesh refinement setting processing unit 321 sets a mesh refinement area in the plane direction in the simulation area using the selected figure. If there is one figure obtained by the figure calculation in step S52, a mesh refinement region may be set using the obtained figure.

  In step S55, the mesh refiner 324 refines the mesh in the planar direction in the mesh refinement region in the planar direction based on the mesh refinement information in the simulation layout file 164 during the process simulation.

  Next, in step S56, the mesh refiner 324 refines the mesh in the depth direction based on the mesh refinement information in the simulation layout file 164.

  Here, the information obtained from the simulation layout file 164 in steps S53 to S56 may be configured to use the information described in the process simulation input data 161 for the case where exception processing or the like is performed. Good.

  FIG. 18B shows a three-dimensional simulation region 1550 and one-dimensional simulation positions 1560 and 1571 set in the NAND cell array simulation layout. A plurality of regions are generated only by the graphic operation of the mask AA and the mask GC. However, for example, the mesh refinement region 1572 of the cell transistor 1570 at the intersection of the bit line BL2 and the word line DWLD0 is a region obtained by the graphic operation of the mask AA and the mask GC and includes the one-dimensional simulation position 1571. One can be determined depending on the conditions. In this way, by specifying the one-dimensional simulation position in advance, one mesh refinement region can be determined.

  Here, the problem of the mesh refinement of the first embodiment will be described with reference to FIGS. 19A and 19B. FIG. 19A shows an example of a layout of a CMOS inverter, and FIG. 19B shows an example of a layout of a NAND cell array. As described above, in the mesh refinement according to the first embodiment, the AND graphic operation of the mask AA and the mask GC is performed in order to specify the region to make the mesh fine. In the example shown in FIGS. 19A and 19B, Since there are a plurality of regions R10 obtained by performing the graphic operation, there is a problem that the region R10 cannot be specified as one.

  In the example of FIG. 19A, the channel widths of the PMOS transistor and the NMOS transistor are the same, but these channel widths are often different due to the difference in mobility and the convenience of design. When the channel widths are different, it is necessary to perform different mesh refinement between the NMOS transistor and the PMOS transistor, and thus it is necessary to specify one region R10. In the case of the layout of the CMOS inverter, in addition to the AND operation of the mask AA and the mask GC, the region R10 can be specified as one by performing the AND operation of the N well mask or the contact mask. However, in the case of handling the difference between the SG (select gate) part and the cell part of the NAND cell array shown in FIG. 19B and the dimensional variation, or in the case of an SRAM (not shown), for example, the existing mask alone is not sufficient. The region R10 cannot be specified as one. In such a case, in the first embodiment, it is necessary to define a new mask for specifying the region R10 as one. However, in the case of the NAND cell array of FIG. 19B, it is very troublesome. There is a point.

  In contrast, in the third embodiment, when a plurality of figures are generated, a figure including a one-dimensional simulation position designated in advance is selected. This makes it possible to specify a single mesh refinement region even when a plurality of regions (figures) are obtained by AND graphic operation of the mask AA and the mask GC, as in the layout of the NAND cell array shown in FIG. 19B. Different mesh refinement settings can be made for each mesh refinement region. Therefore, even when the difference between the select gate portion and the cell portion of the NAND cell array shown in FIG. 19B and the dimensional variation of the cell transistors and the like are handled, a good mesh can be generated.

  In addition, since the engineer only designates one one-dimensional simulation position, it is possible to design the semiconductor device efficiently without much time and effort.

  Furthermore, compared with the case where a mask is added to specify a single region, the one-dimensional simulation position has a small amount of data and is easy to determine.

  In the third embodiment, the substance boundary position extraction unit 317 of the second embodiment may not be provided. That is, in addition to the processing of the first embodiment, mesh refinement of a selected region may be performed.

(Fourth embodiment)
In the fourth embodiment, in addition to the processing of the first embodiment, selected electrical characteristics are extracted with high accuracy.

  FIG. 20 is a block diagram showing a configuration of a layout editor / simulation region setting unit 112C according to the fourth embodiment. In FIG. 20, the same components as those in FIG. 4 are denoted by the same reference numerals, and different points will be mainly described below.

  The layout editor / simulation region setting unit 112C includes a device information processing unit 416, a device name / characteristic name list file 1613, and a voltage application condition list file 1614 in addition to the configuration of the first embodiment of FIG. .

  The device name / characteristic name list file 1613 includes a list of device names and device characteristic names from which electrical characteristics are extracted in the semiconductor device.

  For example, the device name / characteristic name list file 1613 includes the normal characteristics of the MOSFET, the contact resistance of the MOSFET, the hot carrier characteristics of the MOSFET, the gate depletion of the MOSFET, and the leakage current due to the silicon insulating film of the MOSFET shown in FIGS. And a list of the influence of adjacent elements of the MOSFET and the like. As shown in FIGS. 22A to 22F, the region R20 or the line segment L1 to be refined is different depending on the device characteristics.

  The device information processing unit 416 receives information necessary for simulation of the semiconductor device under the control of the controller 401 in accordance with an instruction from the engineer (information input to the man-machine interface unit 10) via the input device 102 and the display device 101. Associate. Specifically, the device information processing unit 416 includes the device name and device characteristic name of the device name / characteristic name list file 1613, the voltage application condition of the device characteristic of the voltage application condition list file 1614, and mesh setting information (mesh The refinement setting), the graphic calculation information, the one-dimensional simulation position information, and the device characteristic electrical characteristic extraction setting are associated with each other. The graphic operation is for setting a mesh refinement region for refining the mesh, and is an operation such as logical product of layout graphics. The one-dimensional simulation position is used for selecting one figure when a plurality of figures are generated by the figure calculation.

  The file input / output unit 414C writes the semiconductor device layout information and the information associated with the device information processing unit 416 to the simulation layout file 164C.

  The simulation layout file 164C further includes a device simulation condition unit and a characteristic extraction unit in addition to the layout unit, the simulation region unit, and the mesh setting information unit of the first embodiment.

  The mesh setting information section includes an identifier, mesh setting information (mesh refinement setting), graphic calculation information, and one-dimensional simulation in addition to the simulation region identifier and mesh setting information (not shown) of the first embodiment. A plurality of sets of position information. The device simulation condition section includes a plurality of sets of identifiers and voltage application conditions. The characteristic extraction unit includes a plurality of sets of identifiers and electrical characteristic extraction settings.

  By using the identifier, for each of a plurality of device names and device characteristic names, mesh setting information, voltage application conditions, graphic calculation information, one-dimensional simulation position information, electrical characteristic extraction settings, Are associated.

  FIG. 21 is a block diagram showing a configuration of a TCAD system of a semiconductor device according to the fourth embodiment. In FIG. 21, the same components as those in FIG. 1 are denoted by the same reference numerals, and different points will be mainly described below. The TCAD system includes a layout editor / simulation region setting unit 112C shown in FIG. 20 in the editor unit 20C.

  The process simulator 122 of the simulation execution unit 40C will be described as being the process simulator 122 of the first embodiment, but may be the process simulator 122 of the second or third embodiment.

  The controller 121C of the simulation execution unit 40C is configured to read two files of the process simulation input data 161 and the simulation layout file 164C and execute the simulation. That is, the device simulation input data 162 and the characteristic extraction input data 163 of the first embodiment are not provided.

  The engineer designates a device name and a device characteristic name via the input device 102 and the display device 101.

  As in the first embodiment, the process simulator 122 is based on the layout described in the simulation layout file 164C, the process simulation input data 161 describing the process flow of the semiconductor device, and the initial mesh. Run process simulation.

  After the process simulation, the simulation execution unit 40C performs mesh setting information, figure calculation, one-dimensional simulation position, voltage application conditions, and electrical characteristics of the simulation layout file 164C associated with the specified device name and device characteristic name. Device simulation and electrical property extraction are performed according to the extraction settings.

  Specifically, the device simulator 123C generates a mesh used for the simulation of the semiconductor device in the mesh refinement region (predetermined region) based on the graphic operation information associated with the specified device name and device characteristic name. Refine. That is, the device simulator 123C performs a graphic operation associated with the designated device name and device characteristic name on the graphic of the layout (first graphic) to generate a new graphic (second graphic), A mesh refinement area is set at the position of a new figure. When a plurality of figures are generated, the device simulator 123C sets the mesh refinement region at the position of the figure including the one-dimensional simulation position associated with the designated device name and device characteristic name. In the mesh refinement region, the device simulator 123C refines the mesh according to the mesh setting information associated with the designated device name and device characteristic name. Next, the device simulator 123C executes device simulation based on the refined mesh, the process simulation result, and the voltage application condition associated with the specified device name and device characteristic name.

  Finally, the electrical characteristic extraction unit 124 extracts the electrical characteristics of the device from the result of the device simulation according to the designated device name and the electrical characteristic extraction setting associated with the device characteristic name.

  Thus, more accurate electrical characteristics can be extracted after refining the mesh in an appropriate region according to the designated device name and device characteristic name.

  Note that, similarly to the device simulator 123C, the process simulator 122 also meshes according to the mesh setting information, the graphic calculation, and the one-dimensional simulation position of the simulation layout file 164C associated with the specified device name and device characteristic name. May be refined.

  Here, problems of the TCAD system of the first embodiment will be described. In the TCAD system according to the first embodiment, the process simulation input data 161, the device simulation input data 162, and the characteristic extraction input data 163 are separated. Characteristic extraction can be performed. Further, as shown in FIGS. 22A to 22F, since the region R20 or the line segment L1 to be refined differs depending on the device characteristics for executing the device simulation, a plurality of sets of device simulation input data for one process simulation input data 161 are obtained. 162 and characteristic extraction input data 163 need to be prepared.

  If the engineer who prepares the input data set is the same as the engineer who uses it to perform the simulation, this form is not a problem. As this increases, the time required to maintain and manage the input data set increases.

  Furthermore, if the engineer who prepares the input data set is different from the engineer who uses it to perform simulation, in addition to maintenance and management problems, information transmission problems occur, and simple mistakes, unexpected and Use in conditions outside the warranty may occur, and problems such as application to semiconductor device development may occur without noticing them. This leads to a decrease in the development efficiency of the semiconductor device, and in some cases, the development of the semiconductor device itself may be meaningless.

  On the other hand, in the fourth embodiment, the device name, device characteristic name, voltage application condition, mesh setting information, graphic calculation information, one-dimensional simulation position information, and device characteristic electrical characteristic extraction Settings are associated with each other, and the associated information is written to the simulation layout file 164D. As a result, as shown in FIGS. 22A to 22F, the device simulation input data 162 and the characteristic extraction input data 163 are converted into a single process simulation input data 161 even if the region to be refined is different according to the device characteristics for executing the simulation. There is no need to prepare more than one. For this reason, in the case where the engineer who prepares the input data set is the same as the engineer who executes the simulation using the same, even if the number of device types and generations increases and the number of input data sets increases, Management can be performed efficiently.

  Even if the engineer who prepares the input data set is different from the engineer who executes the simulation using the input data set, the device name, device characteristic name, mesh refinement area (graphic calculation), and mesh setting information (mesh) Since the association with the refinement setting) has been completed, it is possible to prevent a mistake in use in an unexpected or out-of-warranty condition such as use of an incorrect input data set. Therefore, a highly accurate simulation can be executed efficiently.

  As described above, engineers who only use input data prepared by other engineers can perform simulations efficiently and with high accuracy with minimal effort. Can be done automatically.

  Note that at least a part of the TCAD system described in the first to fourth embodiments may be configured by hardware or software. When configured by software, a program for realizing at least a part of the functions of the TCAD system may be stored in a recording medium such as a flexible disk or a CD-ROM, and read and executed by a computer. The recording medium is not limited to a removable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory.

  Further, a program that realizes at least a part of the functions of the TCAD system may be distributed via a communication line (including wireless communication) such as the Internet. Further, the program may be distributed in a state where the program is encrypted, modulated or compressed, and stored in a recording medium via a wired line such as the Internet or a wireless line.

  As an example in which a program that realizes a part of the functions of the TCAD system is stored in a computer-readable recording medium, the following mode can be considered.

(Appendix 1)
A recording medium storing a computer-readable program,
Extract the coordinates of the vertices of the first figure of the layout of the semiconductor device described in the layout file used for simulation,
Generating a first initial mesh that passes through the coordinates of the vertices in the plane direction of the layout;
Executing a process simulation of the semiconductor device based on simulation data describing a process flow of the semiconductor device, the layout, and the first initial mesh;
A computer-readable recording medium for storing a simulation program including the above.

(Appendix 2)
The simulation program includes the extracted coordinates of the vertices, first mesh setting information associated with the first graphic and described in the layout file, and simulation area described in the simulation data or the layout file. Adding coordinates to the second mesh setting information,
Generating the first initial mesh in the simulation region according to the second mesh setting information;
The computer-readable recording medium according to appendix 1, wherein the first mesh setting information includes space information of the first initial mesh.

(Appendix 3)
The simulation program is
At a plurality of simulation positions described in the layout file, execute a process simulation in the depth direction,
From the result of the process simulation in the depth direction, extract the material boundary position in the depth direction of the structure on the semiconductor substrate in the semiconductor device,
Generating a second initial mesh through the extracted material boundary position;
The computer-readable recording medium according to claim 1, further comprising: executing the process simulation based on the simulation data, the layout, the first initial mesh, and the second initial mesh.

(Appendix 4)
The simulation program is
A graphic operation including a logical product operation described in the simulation data is performed on the first graphic to generate a second graphic,
When a plurality of second figures are generated by the figure calculation unit, the second figure including a simulation position designated in advance in the layout file is selected from the plurality of second figures,
A mesh refinement region is set at the position of the second graphic selected by the graphic selector,
The computer-readable recording medium according to claim 1, further comprising: refining the first initial mesh in the mesh refinement area during the process simulation.

(Appendix 5)
The simulation program is
A graphic operation described in the simulation data is performed on the first graphic to generate a second graphic,
When a plurality of second figures are generated by the figure calculation unit, the simulation unit includes a simulation position designated in advance among the plurality of simulation positions described in the layout file from the plurality of second figures. Select the second figure,
A mesh refinement region is set at the position of the second graphic selected by the graphic selector,
The computer-readable recording medium according to appendix 3, further comprising: refining the first initial mesh in the mesh refinement region during the process simulation.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 Man-machine interface (input / output unit)
20, 20C editor unit 30 result display unit 40, 40C simulation execution unit 112, 112C layout editor / simulation region setting unit (layout editor)
121, 121C Controller 122 1-3 dimensional high-precision process simulator (process simulator)
123,123C 1-3 dimensional high-precision device simulator (device simulator)
124 electrical characteristic extraction unit 212, 212A, 212B initial mesh generation / refinement unit 220 simulator unit 311 plane direction mesh setting processing unit (mesh setting processing unit)
312, 312A Depth direction mesh setting processing unit 313 One-dimensional simulation execution unit 314 Initial mesh generation unit 315 Joint position extraction unit 316 in silicon Layout processing unit for simulation (layout processing unit)
317 Material boundary position extraction unit (material boundary position extraction unit) above the silicon substrate
321 Planar direction mesh refinement setting processing unit 322 Depth direction mesh refinement setting processing unit 323 Graphic calculation unit 324 Mesh refinement unit 325 One-dimensional simulation position inclusion determination unit (graphic selection unit)
401 Controller 412 Graphic processing unit 413 Graphic calculation unit 414, 414C File input / output unit 415 Mesh setting information processing unit 416 Device information processing unit

Claims (6)

A layout processing unit for extracting the coordinates of the vertices of the first figure of the layout of the semiconductor device described in the layout file used for the simulation;
An initial mesh generation unit that generates a first initial mesh that passes through the coordinates of the vertex in the plane direction of the layout;
A simulator unit that executes a process simulation of the semiconductor device based on simulation data describing a process flow of the semiconductor device, the layout, and the first initial mesh;
A process simulator comprising: The extracted coordinates of the vertex, the first mesh setting information associated with the first graphic and described in the layout file, the coordinates indicating the simulation data or the simulation area described in the layout file, Is added to the second mesh setting information.
The initial mesh generation unit generates the first initial mesh in the simulation region according to the second mesh setting information,
The process simulator according to claim 1, wherein the first mesh setting information includes space information of the first initial mesh. A controller that processes information input from an input / output unit for creating a layout of a semiconductor device;
Under the control of the controller, a simulation area in which a graphic of the layout is created, the graphic is processed, an identifier is added to the graphic, and a simulation of the semiconductor device is performed with respect to the layout before processing A graphic processing unit for creating a graphic indicating
Under the control of the controller, mesh setting information processing unit for associating mesh setting information of the initial mesh used for the simulation with the graphic using the identifier,
The first layout file describing the layout before processing is read, the layout information processed by the graphic processing unit, the mesh setting information associated with the graphic, and the graphic indicating the simulation area A file input / output unit for writing to a second layout file used for the simulation;
Layout editor with An input / output unit for inputting / outputting information;
In accordance with the information input to the input / output unit, a device information processing unit that associates information necessary for simulation of the semiconductor device;
A file input / output unit for writing the layout information of the semiconductor device and the information associated with the device information processing unit to a layout file used for the simulation;
A process simulator for executing a process simulation of the semiconductor device based on the layout described in the layout file and simulation data describing a process flow of the semiconductor device;
Based on the information required for the simulation associated with the electrical characteristic extraction target specified by the input / output unit, the mesh used for the simulation of the semiconductor device is refined in a predetermined region, and the refined mesh And a device simulator for executing device simulation based on the result of the process simulation and information necessary for the simulation associated with the designated extraction target,
According to information necessary for the simulation associated with the specified extraction target, an electrical characteristic extraction unit that extracts an electrical characteristic from the result of the device simulation;
A simulation system comprising: The device information processing unit associates the extraction target, information on the graphic calculation, and the simulation position according to information input to the input / output unit,
The device simulator performs the graphic operation associated with the specified extraction target on the first graphic of the layout, generates a second graphic, and when a plurality of second graphic is generated, The simulation system according to claim 4, wherein the predetermined area is set at a position of the second graphic including the simulation position associated with the designated extraction target. The process simulator is
A layout processing unit for extracting coordinates of vertices of the first graphic of the layout described in the layout file;
An initial mesh generation unit that generates a first initial mesh that passes through the coordinates of the vertex in the plane direction of the layout;
A simulator unit that executes the process simulation based on the simulation data, the layout, and the first initial mesh;
The simulation system according to claim 4, comprising: