JP2017034025A - Semiconductor wafer processing damage evaluation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method capable of evaluating the processing damage to a semiconductor wafer, where the damage depth is shallow compared with a silicon wafer, like a single crystal silicon carbide wafer, with high accuracy over the whole area of the wafer.SOLUTION: A method for evaluating the processing damage occurring on the processed surface of a semiconductor wafer includes a step of polishing at least a part of the processed surface of a semiconductor wafer obliquely, a step of setting a three-dimensional coordinate axis having one point on the orientation flat formed on the semiconductor wafer as an original point, measuring the surface shape of the semiconductor wafer and storing as a three-dimensional coordinate, a step of observing or measuring the inclined plane of the semiconductor wafer and storing the position where the processing damage disappears as the two-dimensional coordinate, and a step of calculating the damage depth of the semiconductor wafer based on the two-dimensional coordinate indicating the surface shape of the semiconductor wafer and the two-dimensional coordinate indicating the position where the processing damage disappear.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a method for evaluating processing damage occurring on a processed surface of a semiconductor wafer during processing of the semiconductor wafer.

The manufacturing process of a semiconductor wafer generally includes a process of chamfering, mechanical polishing (lapping), etching, mirror polishing (polishing), and cleaning a wafer sliced from a single crystal ingot.
A processed deteriorated layer (processing damage) is formed on the processed surface of the semiconductor wafer that has undergone the above processing process. It is known that this processing damage induces crystal defects such as slip dislocation in the device manufacturing process, lowers the mechanical strength of the semiconductor wafer, and adversely affects electrical characteristics. Therefore, it is necessary to evaluate and completely remove the processing damage generated on the processing surface of the semiconductor wafer.

There are the following methods for processing damage evaluation of semiconductor wafers that have been conventionally performed.
For example, Non-Patent Document 1 describes an angle polishing method (an oblique polishing method). In Non-Patent Document 1, a test piece cut out from a wafer is obliquely polished at an inclination angle of 5 ° with respect to the processed surface, and the inclined surface is observed with a scanning electron microscope to determine the crack length from the scale on the micrograph. Reading and calculating the crack depth (damage depth) in the thickness direction. When an inclined surface with an inclination angle of 5 ° is formed on the processed surface of the test piece, the damage depth is enlarged about 11 times, and the damage depth can be easily measured.

Non-Patent Document 2 discloses a step etching method in which a wafer surface etched stepwise to have a step height of 5 μm is observed by an X-ray topography method to determine at which depth the processing damage disappears. Have been described.
The X-ray topography method is sensitive to crystal distortion and is suitable for observation of processing damage. In the X-ray topography method, as in the Lang method or the Bergvalet method, primary X-rays generated from an X-ray source are directly incident on a sample crystal, and an image is formed by X-rays diffracted by the sample crystal 1 A crystal method and two crystals that form an image with X-rays diffracted by the sample crystal by causing the primary X-ray generated from the X-ray source to enter the first crystal, causing the X-ray diffracted by the first crystal to enter the sample crystal (For example, refer to Patent Document 1).

  As another method, there is an iterative polishing method in which the wafer surface polishing and the wafer surface observation by the X-ray topography method are alternately repeated, and the wafer damage depth is calculated from the polishing amount when the processing damage disappears. .

Japanese Patent Laid-Open No. 3-148055

Toshiyasu Komatsu, 6 others, “Development of processing technology and inspection technology for stable supply of high-quality silicon wafers—Measurement and analysis of silicon wafer processing alteration layer”, Yamanashi Prefectural Industrial Technology Center research report, No. 26, 2012, p. 6-9 Takao Abe, “Silicon crystal growth and wafer processing”, Advanced Electronics Series I-5, Baifukan, May 1994, p. 75-78

  Silicon carbide (SiC) has excellent physical properties such as a wide band gap, high dielectric breakdown electric field strength, and high thermal conductivity compared to silicon (Si), which is an existing semiconductor material. It is expected as a semiconductor material for power devices that can save energy.

However, single crystal silicon carbide wafers have high strength and tend to have a shallower damage depth than silicon wafers.
In the case of the angle polishing method described above, since the side of the test piece is as small as several mm to 10 mm, the maximum damage is not always included in the test piece. Although the inclination angle must be reduced, if the inclination angle is reduced, the boundary between the machined surface and the inclined surface becomes unclear and it is difficult to calculate the damage depth.
On the other hand, the step etching method can observe the entire wafer, but has a problem that the measurement resolution depends on the height of the step. In addition, the repeated polishing method requires a lot of work because the wafer surface polishing and wafer surface observation must be repeated until the damage depth is specified, and the measurement resolution depends on the amount of polishing performed once. There is.

  The present invention has been made in view of such circumstances, and it is possible to evaluate the processing damage of a semiconductor wafer having a shallower damage depth than a silicon wafer, such as a single crystal silicon carbide wafer, over the entire surface of the wafer with high accuracy. The aim is to provide a possible method.

In order to achieve the above object, the present invention is a method for evaluating processing damage generated on a processed surface of a semiconductor wafer during processing of the semiconductor wafer, and includes the following steps.
(1) A first step of polishing at least a part of the processed surface of the semiconductor wafer obliquely with respect to the processed surface in order to form an inclined surface on the processed surface of the semiconductor wafer.
(2) The semiconductor wafer polished obliquely with respect to the processing surface is viewed in plan and extends from the origin in a direction orthogonal to the orientation flat with one point on the orientation flat formed on the semiconductor wafer as the origin. A three-dimensional coordinate axis having an X axis as an axis, an Y axis extending from the origin in the direction of the orientation flat as a Y axis, and an axis passing through the origin and orthogonal to the X axis and the Y axis as a Z axis; A second step of measuring the surface shape of the wafer and storing the surface shape of the semiconductor wafer as (X, Y, Z) coordinates in the three-dimensional coordinate axis;
(3) A third step of observing or measuring the inclined surface formed on the semiconductor wafer and storing the position at which the processing damage exposed on the inclined surface disappears as (X, Y) coordinates on the three-dimensional coordinate axis.
(4) The damage depth of the semiconductor wafer is calculated based on the (X, Y, Z) coordinates indicating the surface shape of the semiconductor wafer and the (X, Y) coordinates indicating the position where the processing damage disappears. Fourth step.

In the semiconductor wafer processing damage evaluation method according to the present invention, it is preferable that the fourth step includes the following steps.
(1) A step of plotting a surface shape of the semiconductor wafer polished obliquely with respect to the processed surface on an XZ plane.
(2) Plotting the processed surface of the semiconductor wafer as an approximate straight line on the XZ plane.
(3) The Z coordinate of the inclined surface and the approximate straight line in the X coordinate indicating the position where the processing damage disappears is obtained, and the difference between the Z coordinate of the inclined surface and the Z coordinate of the approximate straight line is determined on the semiconductor wafer. Step to damage depth.

  In this specification, the processed surface of a semiconductor wafer refers to a surface region of a semiconductor wafer that is not obliquely polished, and is distinguished from an inclined surface formed by oblique polishing.

In the present invention, the surface shape of the semiconductor wafer polished obliquely with respect to the processing surface is the (X, Y, Z) coordinates based on the orientation flat, and the position where the processing damage disappears is based on the orientation flat (X , Y) is stored as coordinates, and the damage depth of the semiconductor wafer is calculated using the coordinate values.
At that time, the processing surface of the semiconductor wafer is obtained as an approximate line on the XZ plane, and the difference between the Z coordinate of the inclined surface and the Z coordinate of the approximate line in the X coordinate indicating the position where the processing damage disappears is determined as the damage of the semiconductor wafer. In terms of depth, the damage depth can be calculated with high accuracy even when the inclination angle of the oblique polishing is small and the boundary between the processed surface and the inclined surface is unclear.

  Moreover, in the processing damage evaluation method for a semiconductor wafer according to the present invention, when the processing surface of the semiconductor wafer is polished obliquely with respect to the processing surface, the thickness of the outer peripheral portion of the semiconductor wafer that becomes the thinnest by polishing is the thickness before polishing. It is preferable to set the inclination angle so as to be 1/2 or more of the thickness.

  In the present invention, the inclination angle refers to an angle formed between the processing surface of the semiconductor wafer and the inclined surface in a plane constituted by the X axis and the Z axis.

For example, when the thickness of the semiconductor wafer is about 0.4 mm and the diameter of the semiconductor wafer is 100 mm, half of the thickness of the semiconductor wafer remains so that the end of the semiconductor wafer is not lost by the oblique polishing. To obliquely polish half of the processed surface of the semiconductor wafer, the inclination angle is 0.2 ° (= tan ⁻¹ (0.2 / 50)). Therefore, it is preferable that the inclination angle when the semiconductor wafer processing surface is polished obliquely with respect to the processing surface is 0.2 ° or less.

  In the semiconductor wafer processing damage evaluation method according to the present invention, the surface shape of the semiconductor wafer polished obliquely with respect to the processing surface and the position where the processing damage disappears are stored as coordinate values based on the orientation flat. Since the damage depth of the semiconductor wafer is calculated using the value, the processing damage of the semiconductor wafer having a shallow damage depth compared with the silicon wafer can be evaluated with high accuracy over the entire wafer surface.

It is the schematic diagram which showed the method of slantingly grinding the semiconductor wafer which has a process damage with respect to a process surface. It is the schematic diagram which showed the method of grind | polishing the semiconductor wafer diagonally with respect to a process surface. It is the schematic diagram of the orientation flat orthogonal cross section of the semiconductor wafer polished diagonally with respect to the processing surface. It is a top view of the semiconductor wafer slanted with respect to the processing surface. It is the graph which showed the XZ cross section of the semiconductor wafer slantingly polished with respect to the process surface. It is the graph of the XZ cross section of this semiconductor wafer by which the calculation method of the damage depth of the semiconductor wafer ground diagonally with respect to the process surface was shown. It is a test result graph which showed each damage depth of Si surface (one processing surface) and C surface (the other processing surface) of a semiconductor wafer after processing.

  Next, embodiments of the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention.

A procedure of a processing damage evaluation method for a semiconductor wafer according to an embodiment of the present invention will be described below.
[First step]
In this step, an inclined surface is formed on the processed surface of the semiconductor wafer. At that time, the processing surface of the semiconductor wafer 10 is obliquely ground with respect to the processing surface using the grinding device 14 shown in FIG. 1, and then the polishing device 25 shown in FIG. Polish the inclined surface. The inclination angle θ of the inclined surface formed on the semiconductor wafer 10 is more than 0 ° and not more than 0.2 °.
3 and 4, the inclined surface 12 of the semiconductor wafer 10 is an orientation flat 31 (hereinafter referred to as “orientation flat”) formed on the semiconductor wafer 10 with the central axis of the semiconductor wafer 10 interposed therebetween. It is formed on at least a part of the opposite processing surface. However, when the direction of the processing mark on the processing surface is parallel to the orientation flat 31, it is desirable to respond by rotating the coordinate system by 90 °.

  The semiconductor wafer 10 is fixed with wax or the like on the upper surface of the tilt table 13 which has a short cylindrical shape and the upper surface is inclined at an inclination angle θ with respect to the lower surface. After the wax is uniformly applied to the semiconductor wafer 10 using a spin coater or the like, the semiconductor wafer 10 is fixed to the upper surface of the tilt table 13 with a precision press.

As shown in FIG. 1, the grinding device 14 is provided at a rotary table 18 that holds the semiconductor wafer 10, a spindle 17 that is disposed above the rotary table 18, and whose axis is in the vertical direction, and a lower end of the spindle 17. And a grinding wheel 15 mounted on the lower surface of the grinding wheel 16.
An inclined base 13 having a semiconductor wafer 10 fixed to the upper surface is fixed on a rotary table 18, and the spindle 17 is gradually lowered while rotating, and about half of the processing surface of the semiconductor wafer 10 is processed by the rotating grinding wheel 15. Grind at an angle to the surface.

  As shown in FIG. 2, the polishing jig 20 used in the present embodiment includes a cylindrical guide 21 whose axis is in the vertical direction, and a circle that slides inside the guide 21 and pressurizes the semiconductor wafer 10. A columnar weight 22 and a reference plate 23 that is fixed to the lower end of the guide 21 and constitutes a polishing reference surface are provided. The lower surface of the inclined base 13 is fixed to the lower surface of the weight 22.

The polishing jig 20 is placed on the polishing pad 24 attached to the rotating surface plate 19 of the polishing apparatus 25. On the lower surface of the weight 22 of the polishing jig 20, the semiconductor wafer 10 obliquely ground by the grinding device 14 is fixed via an inclined table 13.
The polishing surface of the semiconductor wafer 10 is polished by rotating the polishing pad 24 (the rotating surface plate 19) while dripping the polishing slurry onto the polishing pad 24.

  FIG. 3 shows a schematic diagram of a cross section in the direction orthogonal to the orientation flat 31 of the semiconductor wafer 10 after polishing. As shown in the figure, a processing damage 30 generated during wafer processing is formed on the processing surface 11 of the semiconductor wafer 10. In the semiconductor wafer 10 that has been polished, about half of one processed surface 11 is an inclined surface 12 having an inclination angle θ with respect to the processed surface 11. In addition, the code | symbol 32 in a figure has shown the vanishing position where the processing damage 30 exposed to the inclined surface 12 lose | disappears. The depth from the processing surface 11 to the disappearance position 32 of the processing damage 30 is the damage depth.

[Second step]
The polished semiconductor wafer 10 is removed from the tilting table 13 and cleaned, and the surface shape of the semiconductor wafer 10 is measured using a flatness measuring machine (not shown) or a three-dimensional measuring machine (not shown). Then, the surface shape of the semiconductor wafer 10 is stored in a storage device (not shown) as (X, Y, Z) coordinates on a three-dimensional coordinate axis.

The three-dimensional coordinate axis of the semiconductor wafer 10 is determined as follows.
The semiconductor wafer 10 polished obliquely with respect to the processing surface 11 is viewed in plan, with one point on the orientation flat 31 formed on the semiconductor wafer 10 as the origin, an axis extending from the origin in a direction orthogonal to the orientation flat 31 is the X axis, An axis extending from the origin in the direction of the orientation flat 31 is a Y axis, and an axis passing through the origin and orthogonal to the X axis and the Y axis is a Z axis (see FIG. 4).

[Third step]
Observe or measure the inclined surface 12 formed on the semiconductor wafer 10, particularly the damage depth discrimination region 33, using a measurement microscope (not shown), a differential interference microscope (not shown) with a coordinate display function, or the like, or The disappearance position 32 where the processing damage 30 exposed to the inclined surface 12 disappears is determined from the surface data of X-ray topography and Raman spectroscopy (see FIGS. 3 and 4). Then, the determined disappearance position 32 is stored in the storage device as (X, Y) coordinates on the three-dimensional coordinate axis.

The measurement microscope is a microscope for measuring a sample, has a measuring machine and a measurement scale on the stage, and can display a micron-order scale and a template on the visual field.
The differential interference microscope has a configuration in which a polarizer and a Nomarski prism are sequentially arranged between the illumination light source and the condenser lens, and a Nomarski prism and an analyzer are sequentially arranged between the objective lens and the imaging plane. . After the light from the illumination light source is converted to linearly polarized light by a polarizer, it is separated into an ordinary ray and an extraordinary ray by a Nomarski prism. The light beam is combined on the same optical path by a Nomarski prism through an objective lens, and then interfered by an analyzer to form an interference image on the imaging surface. By using the differential interference microscope, the position where the processing damage disappears can be measured with higher accuracy.

[Fourth step]
In this step, the damage depth of the semiconductor wafer 10 is calculated based on the (X, Y, Z) coordinates indicating the surface shape of the semiconductor wafer 10 and the (X, Y) coordinates indicating the disappearance position 32 where the processing damage 30 disappears. To do.
Specifically, the damage depth of the semiconductor wafer 10 is calculated by the following procedure.

(1) First, as an image for calculating the damage depth, the surface shape of the semiconductor wafer 10 polished obliquely with respect to the processed surface 11 is plotted on the XZ plane and graphed. FIG. 5 is a graph in which the X and Z coordinate values of the surface shape of the semiconductor wafer 10 obtained at an interval of 10 mm from the origin in the Y-axis direction are superimposed on a single XZ plane. In the present embodiment, the depth of processing damage is measured using such cross-sectional shape data.

(2) In the actual measurement of the processing damage depth, the X and Z coordinate values of the processing surface 11 of the semiconductor wafer 10 obtained at a predetermined position in the Y-axis direction from the origin, that is, the position where the processing damage depth is to be measured. Then, an approximate straight line 40 of the machining surface 11 is obtained by regression analysis or the like and plotted on the XZ plane (see FIG. 6).

(3) The Z coordinate 43 of the inclined surface 12 and the Z coordinate 42 of the approximate line 40 at the X coordinate 41 indicating the disappearance position 32 where the machining damage 30 disappears are obtained, and the Z coordinate 43 of the inclined surface 12 and the Z coordinate of the approximate line 40 are obtained. The difference from 42 is taken as the damage depth of the semiconductor wafer 10 (see FIG. 6).

  Although one embodiment of the present invention has been described above, the present invention is not limited to the configuration described in the above-described embodiment, and is within the scope of matters described in the claims. Other possible embodiments and modifications are also included. For example, in the above embodiment, when forming the inclined surface on the processed surface of the semiconductor wafer, the processed surface of the semiconductor wafer is obliquely ground using a grinding device, and then the inclined surface is obliquely polished using a polishing jig. However, the inclined surface may be formed only by oblique polishing using a polishing jig without using a grinding apparatus.

A verification test carried out to verify the effects of the present invention will be described.
As the semiconductor wafer, a single crystal 4 inch 4H-SiC wafer with an off angle of 4 ° was used. A semiconductor wafer is fixed to an inclined table having an inclination angle of 1/538 (= 0.106 °), and a processing surface of the semiconductor wafer is obliquely ground with respect to the processing surface using a grinding apparatus, and then a polishing jig is used. The inclined surface of the semiconductor wafer was polished by a polishing apparatus using The inclination angle of the inclined surface after polishing was 1/526.

  The damage depth was measured for each of the Si surface (one processed surface) and the C surface (the other processed surface) of the semiconductor wafer immediately after slicing and immediately after lapping. A flatness measuring machine (an example of a three-dimensional measuring machine) was used to measure the surface shape of the semiconductor wafer, and a measurement microscope was used to determine the position at which the processing damage exposed on the inclined surface disappeared. For the measurement of the processing damage disappearance position, four positions for each specimen were selected as positions where it was determined that the processing damage was deep, and the coordinates of the processing damage disappearance position were read. FIG. 7 shows the test results.

The figure shows the following.
・ Processing damage to semiconductor wafers is greater immediately after lapping than immediately after slicing.
・ Difference in damage depth is greater on the C surface than on the Si surface.

  From these results, it is possible to accurately grasp the depth of processing damage to be removed, that is, the required processing removal amount, in the next step after each processing step. Although it is necessary to change the machining conditions in order to reduce the cost of the machining process and improve the efficiency, it is possible to accurately grasp whether or not the damage depth has changed due to the condition change.

10: Semiconductor wafer, 11: Work surface, 12: Inclined surface, 13: Inclined table, 14: Grinding device, 15: Grinding wheel, 16: Grinding wheel, 17: Spindle, 18: Rotary table, 19: Rotary surface plate 20: polishing jig, 21: guide, 22: weight, 23: reference plate, 24: polishing pad, 25: polishing device, 30: processing damage, 31: orientation flat (orientation flat), 32: disappearance position, 33: damage Depth discrimination region, 40: approximate line, 41: X coordinate, 42, 43: Z coordinate, θ: inclination angle

Claims (3)

A method for evaluating processing damage generated on a processing surface of a semiconductor wafer during processing of the semiconductor wafer,
A first step of polishing at least a part of the processed surface of the semiconductor wafer obliquely with respect to the processed surface in order to form an inclined surface on the processed surface of the semiconductor wafer;
The semiconductor wafer polished obliquely with respect to the processing surface is viewed in plan, and an axis extending from the origin in a direction perpendicular to the orientation flat is defined as X on the orientation flat formed on the semiconductor wafer as an origin X An axis extending from the origin in the direction of the orientation flat is set as a Y axis, and a three-dimensional coordinate axis passing through the origin and orthogonal to the X axis and the Y axis is set as a Z axis, and the surface of the semiconductor wafer A second step of measuring the shape and storing the surface shape of the semiconductor wafer as (X, Y, Z) coordinates in the three-dimensional coordinate axis;
A third step of observing or measuring the inclined surface formed on the semiconductor wafer and storing the position at which the processing damage exposed on the inclined surface disappears as (X, Y) coordinates in the three-dimensional coordinate axis;
A fourth step of calculating the damage depth of the semiconductor wafer based on the (X, Y, Z) coordinates indicating the surface shape of the semiconductor wafer and the (X, Y) coordinates indicating the position where the processing damage disappears. And a processing damage evaluation method for a semiconductor wafer. The semiconductor wafer processing damage evaluation method according to claim 1, wherein the fourth step includes:
Plotting a surface shape of the semiconductor wafer polished obliquely with respect to the processing surface on an XZ plane;
Plotting the processed surface of the semiconductor wafer as an approximate line on the XZ plane;
The Z coordinate of the inclined surface and the approximate line in the X coordinate indicating the position where the processing damage disappears is obtained, and the difference between the Z coordinate of the inclined surface and the Z coordinate of the approximate line is determined as the damage depth of the semiconductor wafer. A processing damage evaluation method for a semiconductor wafer.   3. The semiconductor wafer processing damage evaluation method according to claim 1, wherein when the processing surface of the semiconductor wafer is polished obliquely with respect to the processing surface, the thickness of the outer peripheral portion of the semiconductor wafer that becomes the thinnest by the polishing is before polishing. A process damage evaluation method for a semiconductor wafer, characterized in that the angle of inclination is at least 1/2 of the thickness of the semiconductor wafer.

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