JP2017033336A - Voltage Regulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage regulator capable of reducing a drop amount of an output voltage from a power supply voltage when a power supply voltage is lowered. In an output stage, a load current source side is a PMOS transistor P11 having a common source, and a load current sink side is a source follower of a PMOS transistor P12. The differential pair 2 compares the divided voltage Vfb obtained by dividing the output voltage Vout of the output stage 1 by the resistors R101 and R102 with the reference voltage Vref, and the PMOS transistor P11 and the PMOS transistor P12 so that the output voltage Vout becomes a constant voltage. To control the conduction. The idling current setting unit 3 sets the magnitude of the idling current that flows through the PMOS transistor P11 and the PMOS transistor P12 in order to cause the output stage 1 to perform class AB operation. [Selection] Figure 1

Description

  Embodiments described herein relate generally to a voltage regulator.

  In a voltage regulator, the resistance voltage of the output voltage is compared with a reference voltage with a differential pair, and the output voltage is controlled to a constant voltage by controlling the gate voltage of the MOS transistor in the output stage by the output of the differential pair. Is done.

  Normally, this voltage regulator is used as a step-down regulator that outputs a voltage lower than the power supply voltage. However, when the power supply voltage drops to a voltage lower than a desired constant voltage value, it is desirable to obtain an output voltage having the same magnitude as the power supply voltage.

  However, the configuration of the conventional output stage has a common structure with a source follower of an NMOS transistor connected between the power supply voltage terminal and the output terminal, and a source follower of a PMOS transistor connected between the output terminal and the ground terminal. Source output.

  Therefore, when the power supply voltage is lowered, there is a problem that only the output voltage that is lower than the power supply voltage by the threshold voltage of the NMOS transistor can be obtained.

JP 2012-185595 A

  The problem to be solved by the present invention is to provide a voltage regulator that can reduce the amount of drop in the output voltage from the power supply voltage when the power supply voltage drops.

  The voltage regulator according to the embodiment includes an output stage, a differential pair, and an idling current setting unit. In the output stage, the load current source side is a first grounded PMOS transistor, and the load current sink side is a source follower of the second PMOS transistor. The differential pair compares a voltage obtained by dividing the output voltage of the output stage with a resistor with a reference voltage, and controls conduction of the first and second PMOS transistors so that the output voltage becomes a constant voltage. The idling current setting unit sets the magnitude of the idling current that flows to the first and second PMOS transistors in order to cause the output stage to perform class AB operation.

The block diagram which shows the example of a structure of the voltage regulator of embodiment. A circuit diagram showing an example of circuit composition of a voltage regulator of an embodiment. The figure which shows the example of the output voltage characteristic of the voltage regulator of embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment)
FIG. 1 is a block diagram illustrating an example of the configuration of the voltage regulator according to the embodiment.

  In the voltage regulator of the embodiment, the load current source side is the source grounded PMOS transistor P11, the load current sink side is the source follower of the PMOS transistor P12, and the output voltage Vout of the output stage 1 is the resistors R101 and R102. The divided voltage Vfb divided by the reference voltage Vref is compared with the reference voltage Vref, the differential pair 2 for controlling the conduction of the PMOS transistor P11 and the PMOS transistor P12 so that the output voltage Vout becomes a constant voltage, and the output stage 1 operates in the class AB. And an idling current setting unit 3 for setting the magnitude of the idling current flowing through the PMOS transistor P11 and the PMOS transistor P12.

  The output stage 1 has a source grounded PMOS transistor having a source side connected to the power supply voltage terminal VDD and a drain terminal connected to the output terminal Vout on the load current source side for supplying current from the power supply voltage terminal VDD to the output terminal Vout. P11.

  The load current sink side that draws current from the output terminal Vout to the ground terminal GND is a source follower of the PMOS transistor P12 whose drain terminal is connected to the ground terminal GND and whose source terminal is connected to the output terminal Vout. .

  In the present embodiment, the output stage 1 is set to a class AB operation in order to speed up the response of the output voltage stabilization to the load fluctuation. Therefore, when there is no difference between the divided voltage Vfb that is the input of the differential pair 2 and the reference voltage Vref (during idling), an idling current flows through the PMOS transistor P11 and the PMOS transistor P12.

  As the idling current is increased, the response of the output stage 1 to the load change is improved, but the consumption current of the voltage regulator is increased correspondingly.

  Thus, in the present embodiment, the idling current setting unit 3 is provided so that the magnitude of the idling current of the output stage 1 can be set as necessary.

  The idling current setting unit 3 includes a first current mirror circuit including the PMOS transistor P11 as a component and a second current mirror circuit including the PMOS transistor P12 as a component, and is supplied to the differential pair 2. The magnitude of the idling current is set based on the mirror ratio of the first and second current mirror circuits with reference to the reference current. In the present embodiment, the magnitude of the idling current can be set to a desired value by changing the setting of the mirror ratio.

  FIG. 2 shows an example of an internal circuit of the differential pair 2 and the idling current setting unit 3 constituted by MOS transistors.

  In the differential pair 2, an NMOS transistor N21 and an NMOS transistor N22 are arranged in the differential input stage. In the NMOS transistor N21, the reference voltage Vref is input to the gate terminal, and the current source I21 that generates the reference current Iref is connected to the source terminal. In the NMOS transistor N22, the divided voltage Vfb of the output voltage Vout is input to the gate terminal, and the current source I22 that generates the reference current Iref is connected to the source terminal. A resistor R21 is connected between the source terminals of the NMOS transistor N21 and the NMOS transistor N22 in order to reduce the open loop gain of the differential pair 2.

  The drain terminal of the NMOS transistor N21 is connected to a cascode current mirror circuit CCM1 composed of PMOS transistors P21 and P22 and PMOS transistors P23 and P24 via an NMOS transistor N23 with high breakdown voltage compensation.

  The idling current setting unit 3 includes a PMOS transistor P31 that forms a current mirror circuit CM1 with a pair with the PMOS transistor P11, and a PMOS transistor P32 that forms a current mirror circuit CM2 with a pair with the PMOS transistor P12.

  Here, the source terminal of the PMOS transistor P32 is connected to the drain terminal of the PMOS transistor P22 which is the output terminal of the cascode current mirror circuit CCM1 of the differential pair 2, and the gate terminal and drain terminal common to the PMOS transistor P31 are It is connected to the drain terminal of the NMOS transistor N22 of the differential pair 2.

  In order to operate the PMOS transistor P32 and the PMOS transistor P12 as a current mirror when the output terminal 1 is idling, it is necessary to match the potentials of the respective source terminals.

  Therefore, in the present embodiment, the NMOS transistor N31 having the gate terminal connected to the output terminal Vout between the output terminal Vout and the output terminal of the cascode current mirror circuit CCM1, and the source terminal connected to the source terminal of the NMOS transistor N31. The PMOS transistor P33 whose drain terminal is connected to the current source I31 and whose gate terminal is connected to its own drain terminal, the NMOS transistor N32 whose gate terminal is connected to the output terminal of the cascode current mirror circuit CCM1, and the source A feedback circuit including a PMOS transistor P34 having a terminal connected to the source terminal of the NMOS transistor N32, a drain terminal connected to the ground terminal GND, and a gate terminal connected to the gate terminal of the PMOS transistor P33 is provided. It is.

  Here, the ratio of the electrical characteristic values of the pair of the NMOS transistor N31 and the NMOS transistor N32 and the pair of the PMOS transistor P33 and the PMOS transistor P34 are set to 1: 1. Further, the magnitude of the current of the DC power supply I31 is made equal to the reference current Iref.

  As a result, when the output terminal 1 is idling, the voltage at the output terminal of the cascode current mirror circuit CCM1 becomes equal to the voltage at the output terminal Vout.

  When the output terminal 1 is idling, the reference current Iref of the differential pair 2 flows through the PMOS transistor P32.

Therefore, if the mirror ratio between the PMOS transistor P32 and the PMOS transistor P12 is set to 1: M, the idling current Iidle flowing through the PMOS transistor P12 is
Idle = M × Iref
It becomes.

  That is, when the mirror ratio of the current mirror circuit CM2 is set to 1: M, the idling current Iidle flowing through the PMOS transistor P12 can be set to M times the reference current Iref.

  On the other hand, the PMOS transistor P31 of the current mirror circuit CM1 has a source terminal connected to the power supply voltage terminal VDD and a drain terminal connected in parallel with a resistor R31 and a resistor R32. The resistance value ratio of the resistor R31 and the resistor R32 is set to 1: 1.

  The other end of the resistor R31 is connected to the drain terminal of the NMOS transistor N31 and to the gate terminal of the PMOS transistor P31.

  The other end of the resistor R32 is connected to the drain terminal of the NMOS transistor N32 and to the gate terminal of the PMOS transistor P11.

  When the output terminal 1 is idling, the reference current Iref flows through the resistor R31. Accordingly, the reference current Iref also flows through the resistor R32 through which a current having the same magnitude as the current flowing through the resistor R31 flows. Therefore, 2 · Iref which is the total current flows through the PMOS transistor P31 to which the resistor R31 and the resistor R32 are connected.

  At this time, the voltage at the other end of the resistor R31 and the voltage at the other end of the resistor R32 have the same magnitude, so the gate voltage of the PMOS transistor P31 and the gate voltage of the PMOS transistor P11 have the same magnitude.

Thus, if the mirror ratio between the PMOS transistor P31 and the PMOS transistor P11 is set to 2: M, the idling current Iidle flowing through the PMOS transistor P11 is
Idle = M × Iref
It becomes.

  That is, when the mirror ratio of the current mirror circuit CM1 is set to 2: M, the idling current Iidle flowing through the PMOS transistor P11 can be set to M times the reference current Iref.

  Thus, in the present embodiment, the idling current Iidle of the output stage 1 is set to the reference current Iref by setting the mirror ratio of the current mirror circuit CM1 to 2: M and the mirror ratio of the current mirror circuit CM2 to 1: M. M times can be set.

  In the example shown in FIG. 2, a capacitor C is connected between the gate terminal of the PMOS transistor P12 and the ground terminal GND. By this capacitor C, the gate terminal of the PMOS transistor P12 is grounded in terms of AC (alternating current). Therefore, the gain in the high frequency region is reduced. As a result, the response to fluctuations in the load current can be accelerated, and the oscillation margin for the capacitive load can be increased.

  FIG. 3 shows how the output voltage Vout changes with respect to the change in the power supply voltage VDD of the voltage regulator of this embodiment shown in FIG. Here, an example is shown in which the reference voltage Vref and the resistance ratio of the resistors R101 and R102 are set so that 5V is obtained as a constant voltage.

  As shown in FIG. 3, when the power supply voltage VDD is 5V or higher, the output voltage Vout is maintained at a constant voltage of 5V.

  On the other hand, when the power supply voltage VDD becomes lower than 5V, the divided voltage Vfb of the output voltage Vout becomes lower than the reference voltage Vref. Therefore, the current flowing through the NMOS transistor N22 of the differential pair 2 to which the divided voltage Vfb is input decreases, and the voltage at the output terminal of the cascode current mirror circuit CCM1 of the differential pair 2 increases.

  For this reason, the current flowing through the NMOS transistor N32 in which the voltage at the output terminal of the cascode current mirror circuit CCM1 is input to the gate terminal increases, and the current flowing through the resistor R32 also increases. As a result, the voltage drop in the resistor R32 increases, and the gate voltage of the PMOS transistor P11 at the output terminal 1 where the terminal voltage of the resistor R32 is input to the gate terminal decreases. As a result, the PMOS transistor P11 becomes conductive.

  At this time, since the source of the PMOS transistor P11 is grounded, a voltage having a value substantially equal to the power supply voltage VDD is output to the drain terminal as the output voltage Vout.

  In the example shown in FIG. 3, the output voltage Vout having a value substantially equal to the power supply voltage VDD is obtained when the power supply voltage VDD is about 5V to 2V.

  According to the present embodiment, since the load current source side of the output stage 1 is the grounded PMOS transistor P11, when the power supply voltage VDD is lowered to a voltage lower than a desired constant voltage value, An output voltage Vout having a value substantially equal to the voltage VDD can be obtained.

  Also, since the idling current setting unit 3 sets a desired idling current and causes the output stage 1 to operate in class AB, the responsiveness of the output stage 1 to load fluctuation can be improved.

  Further, since the gate terminal of the PMOS transistor P12 is grounded in an AC manner by the capacitor C connected between the gate terminal of the PMOS transistor P12 and the ground terminal GND, the response to the fluctuation of the load current can be accelerated, The oscillation margin with respect to the capacitive load can be increased.

  According to the voltage regulator of the embodiment described above, the amount of drop from the power supply voltage of the output voltage when the power supply voltage is reduced can be reduced.

  Moreover, although embodiment of this invention was described, this embodiment is shown as an example and is not intending limiting the range of invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Output stage 2 Differential pair 3 Idling current setting part P11, P12, P21-P24, P31-P34 PMOS transistor N21-N23, N31, N32 NMOS transistor I21, I22, I31 Current source R21, R31, R32 Resistor C Capacitor

Claims (5)

An output stage in which the load current source side is a first PMOS transistor with a common source and the load current sink side is a source follower of the second PMOS transistor;
A differential pair for controlling the conduction of the first and second PMOS transistors so that the output voltage of the output stage is divided by a resistor is compared with a reference voltage, and the output voltage becomes a constant voltage;
A voltage regulator comprising: an idling current setting unit configured to set a magnitude of an idling current to be supplied to the first and second PMOS transistors in order to cause the output stage to perform a class AB operation. The idling current setting unit is
A third PMOS transistor constituting a first current mirror circuit by a pair with the first PMOS transistor;
A fourth PMOS transistor constituting a second current mirror circuit by a pair with the second PMOS transistor;
2. The voltage regulator according to claim 1, wherein a magnitude of the idling current is set according to a mirror ratio of the first and second current mirror circuits with reference to a reference current supplied to the differential pair. . The idling current setting unit is
A first resistor having one end connected to the drain terminal of the third PMOS transistor and the other end connected to the gate terminal of the third PMOS transistor;
A second resistor having one end connected to the drain terminal of the third PMOS transistor and the other end connected to the gate terminal of the first PMOS transistor;
A first NMOS transistor having a drain terminal connected to the other end of the first resistor and a gate terminal connected to the output terminal of the output end;
A source terminal is connected to the source terminal of the first NMOS transistor, a drain terminal is connected to a current source that generates a current having a magnitude equal to the reference current, and a gate terminal is connected to its own drain terminal. PMOS transistors of
A second NMOS transistor having a drain terminal connected to the other end of the second resistor and a gate terminal connected to the output terminal of the differential pair;
A sixth PMOS transistor having a source terminal connected to the source terminal of the second NMOS transistor, a drain terminal connected to the ground terminal, and a gate terminal connected to the gate terminal of the fifth PMOS transistor; The voltage regulator according to claim 2. The first resistor and the second resistor, the first NMOS transistor and the second NMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor have an electrical characteristic value ratio, respectively. The voltage regulator according to claim 2, wherein the voltage regulator is a 1: 1 pair. The voltage regulator according to claim 1, further comprising a capacitor connected between a gate terminal and a ground terminal of the second PMOS transistor.