JP2017028530A - Solid-state imaging device - Google Patents

Abstract

A solid-state imaging device satisfies a required frame rate. A counter 4c counts the number of clocks from when the potential level of the reference voltage starts to change during the reset level detection period until the output signal of the comparator is inverted. The control circuit changes the reference voltage from the first level to the second level for a predetermined time from the first level with the first input terminal and the output terminal of the comparator being conductive during the first auto-zero period. To do. While the first input terminal and the output terminal of the comparator are electrically cut off during the first reset level detection period, the count value of the counter is changed while changing the reference voltage with time from the first level to the second slope. To get. Based on the difference between the acquired count value and the target count value, a third gradient that is the gradient of the reference voltage to be used in the second auto-zero period is calculated. [Selection] Figure 5

Description

  The present embodiment relates to a solid-state imaging device.

  In the solid-state imaging device, the potential of the reference voltage that changes with time and the analog signal from the pixel are compared by a comparator, the level of the analog signal of the pixel is converted to time, and the time is counted by a counter (pixel count) Thus, the analog signal of the pixel is AD converted into a digital value. In the solid-state imaging device, prior to this pixel count, an auto-zero process may be performed to cancel the influence of the offset of the comparator and determine the operating point of the comparator. At this time, in the solid-state imaging device, it is desired to satisfy the frame rate requirement.

JP 2014-165845 A

  An object of one embodiment is to provide a solid-state imaging device capable of satisfying a frame rate requirement.

  According to one embodiment, a solid-state imaging device having a pixel, a signal line, a comparator, a counter, and a control circuit is provided. The signal line is electrically connected to the pixel. The comparator has a first input terminal, a second input terminal, and an output terminal. A level corresponding to the potential of the signal line is transmitted to the first input terminal. A reference voltage is supplied to the second input terminal. The counter counts the number of clocks from when the potential level of the reference voltage starts to change during the reset level detection period until the output signal of the comparator is inverted. The control circuit changes the reference voltage from the first level to the second level for a predetermined time from the first level with the first input terminal and the output terminal of the comparator being conductive during the first auto-zero period. To do. The control circuit changes the reference voltage temporally from the first level to the second slope with the first input terminal and the output terminal of the comparator being electrically cut off during the first reset level detection period. Get the count value of the counter. The control circuit calculates a third slope based on the difference between the acquired count value and the target count value. The third slope is a slope of the reference voltage to be used in the second auto zero period.

The figure which shows the structure of the imaging system to which the solid-state imaging device concerning embodiment is applied. The figure which shows the structure of the imaging system to which the solid-state imaging device concerning embodiment is applied. 1 is a diagram showing a configuration of a solid-state imaging device according to an embodiment. FIG. 3 is a diagram illustrating a configuration of a pixel in the embodiment. The figure which shows the structure of the column ADC circuit in embodiment. FIG. 6 is a diagram illustrating an operation of the solid-state imaging device according to the embodiment. FIG. 6 is a diagram illustrating an operation of the solid-state imaging device according to the embodiment. FIG. 6 is a diagram illustrating an operation of the solid-state imaging device according to the embodiment.

  Exemplary embodiments of a solid-state imaging device will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

(Embodiment)
A solid-state imaging device 1 according to an embodiment will be described. The solid-state imaging device 1 is applied to, for example, the imaging system 91 illustrated in FIGS. 1 and 2. 1 and 2 are diagrams illustrating a schematic configuration of the imaging system 91. FIG.

  The imaging system 91 may be, for example, a digital camera, a digital video camera, or the like, or a camera module applied to an electronic device (for example, a mobile terminal with a camera). As shown in FIG. 2, the imaging system 91 includes an imaging unit 92 and a post-processing unit 93. The imaging unit 92 is, for example, a camera module. The imaging unit 92 includes an imaging optical system 94 and the solid-state imaging device 1. The post-processing unit 93 includes an ISP (Image Signal Processor) 96, a storage unit 97, and a display unit 98.

  The imaging optical system 94 includes a photographing lens 947, a half mirror 943, a mechanical shutter 946, a lens 944, a prism 945, and a viewfinder 948. The photographing lens 947 includes photographing lenses 947a and 947b, a diaphragm (not shown), and a lens driving mechanism 947c. The stop is disposed between the photographic lens 947a and the photographic lens 947b, and adjusts the amount of light guided to the photographic lens 947b. In FIG. 1, the case where the photographing lens 947 includes two photographing lenses 947a and 947b is exemplarily shown, but the photographing lens 947 may include a plurality of photographing lenses.

  The solid-state imaging device 1 is disposed on the planned imaging plane of the photographic lens 947. For example, the photographic lens 947 refracts incident light, guides it to the imaging surface of the solid-state imaging device 1 via the half mirror 943 and the mechanical shutter 946, and images the subject on the imaging surface (pixel array PA) of the solid-state imaging device 1. Form. The solid-state imaging device 1 generates an image signal corresponding to the subject image.

  Next, the configuration of the solid-state imaging device 1 will be described with reference to FIGS. FIG. 3 is a diagram illustrating a configuration of the solid-state imaging device 1. FIG. 4 is a diagram illustrating a configuration of each pixel. FIG. 5 is a diagram showing a configuration of each column ADC circuit.

  As shown in FIG. 3, the solid-state imaging device 1 includes a pixel array PA, a timing control circuit 7, a vertical scanning circuit 2, an AD conversion block 3, and a horizontal scanning circuit 5.

  In the pixel array PA, a plurality of pixels PC (1, 1) to PC (m, n) are arranged in a plurality of rows and a plurality of columns. For example, in FIG. 3, when m and n are integers of 2 or more, a plurality of pixels PC are arranged in m rows and n columns.

  As illustrated in FIG. 4, each pixel PC includes, for example, a photoelectric conversion unit PD, a transfer unit TG, a charge voltage conversion unit FD, a reset unit RST, and an output unit AMP. FIG. 4 is a diagram illustrating a configuration of the pixel PC. In FIG. 4, the configuration of the pixel PC (1, 1) is exemplarily shown, but the configurations of the other pixels are the same.

  The photoelectric conversion unit PD performs photoelectric conversion and generates and accumulates charges corresponding to the received light. The photoelectric conversion unit PD is, for example, a photodiode.

  When receiving the active level control signal φREAD from the vertical scanning circuit 2, the transfer unit TG transfers the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD. The transfer unit TG is, for example, a transfer transistor that functions as a transfer gate, and turns on when the gate receives an active level control signal φREAD to transfer the charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD. To do.

  The charge-voltage conversion unit FD converts the transferred charge into a voltage using the parasitic capacitance. The charge-voltage conversion unit FD is, for example, a floating diffusion.

  When receiving the active level control signal φRESET from the vertical scanning circuit 2, the reset unit RST resets the potential of the charge voltage conversion unit FD to a predetermined potential. The reset unit RST is a reset transistor, for example, and resets the potential of the charge-voltage conversion unit FD to a predetermined potential by turning on when receiving an active level control signal φRESET at its gate.

  The reset unit RST performs an operation for bringing the pixel PC into a selected state / non-selected state. For example, when the power supply VDD is controlled to VDD1 (for example, the power supply level) by the vertical scanning circuit 2, the reset unit RST resets the potential of the charge-voltage conversion unit FD to VDD1 to select the pixel PC. . The reset unit RST resets the potential of the charge-voltage conversion unit FD to VDD2 when the power supply VDD is controlled to VDD2 (a potential at which the output unit AMP is turned off, for example, a ground level) by the vertical scanning circuit 2. Thus, the pixel PC may be in a non-selected state. Further, the power source of the reset unit RST may be configured such that the potential can be changed independently of the power source of other components in the pixel.

  The output unit AMP outputs a signal corresponding to the voltage of the charge-voltage conversion unit FD to the signal line Vlin-1 via the selection unit ADR when the pixel PC is in a selected state. The output unit AMP is, for example, an amplifier transistor, and performs charge source voltage conversion by performing a source follower operation together with a load current source G connected via the signal line Vlin-1 when the pixel PC is in a selected state. A signal corresponding to the voltage of the unit FD is output to the signal line Vlin-1. The load current source G has one end connected to the signal line Vlin and the other end connected to the ground potential.

  The pixel PC may have a configuration in which a selection unit ADR (not shown) is added, as indicated by a broken line in FIG. In that case, the power supply VDD may be maintained at VDD1 (for example, the power supply level). When the selection unit ADR receives the active level control signal φADD from the vertical scanning circuit 2, the selection unit ADR selects the pixel PC and receives the non-active level control signal φADD from the vertical scanning circuit 2. Deselect PC. The selection unit ADR is, for example, a selection transistor. The selection unit ADR is turned on when receiving an active level control signal φADD at its gate, thereby selecting the pixel PC and receiving a non-active level control signal φADD at its gate. When turned off, the pixel PC is brought into a non-selected state.

  Returning to FIG. 3, the timing control circuit 7 generates a clock for controlling various timings in accordance with a control signal (for example, the horizontal synchronization signal φH) received from the ISP 96. For example, the timing control circuit 7 generates a vertical scanning clock φVCK according to the horizontal synchronization signal φH and supplies the vertical scanning clock φVCK to the vertical scanning circuit 2. The timing control circuit 7 generates a reference voltage generation clock φRCK according to the horizontal synchronization signal φH and supplies it to the reference voltage generation circuit 6. The timing control circuit 7 generates a counter clock φCCK according to the horizontal synchronization signal φH and supplies it to each of the plurality of column ADC circuits 4-1 to 4-n. The timing control circuit 7 generates a horizontal scanning clock φHCK and supplies it to the horizontal scanning circuit 5 in accordance with the horizontal synchronization signal φH.

  The vertical scanning circuit 2 scans the pixel array PA in the vertical direction according to the clock φVCK. Thereby, the vertical scanning circuit 2 selects a row of pixels from which signals in the pixel array PA are to be read. For example, the vertical scanning circuit 2 transmits an active level control signal (for example, in FIG. 4) to the pixels in the selected row via the control line Hlin corresponding to the selected row among the plurality of control lines Hlin-1 to Hlin-m. A reset control signal φRESET) is supplied. Accordingly, the vertical scanning circuit 2 outputs signals in parallel from the pixels in the selected row to the signal lines Vlin-1 to Vlin-n in a plurality of columns.

  The AD conversion block 3 is disposed between the pixel array PA and the horizontal scanning circuit 5. The AD conversion block 3 includes a plurality of AD conversion circuits 9-1 to 9-n. Each of the AD conversion circuits 9-1 to 9-n converts the analog signal of the pixel read out through the signal line Vlin of the corresponding column into a digital value using the reference voltage, and the ISP 96 (see FIG. 2). Output to. Each AD conversion circuit 9 includes a reference voltage generation circuit 6, a column ADC circuit 4, and a digital signal processing circuit (control circuit) 8. In the plurality of AD conversion circuits 9-1 to 9-n, as shown in FIG. 3, the reference voltage generation circuit 6 and the digital signal processing circuit 8 are common to the plurality of column ADC circuits 4-1 to 4-n. It has become.

  The reference voltage generation circuit 6 generates a reference voltage VREF at a predetermined timing according to the clock φRCK and supplies it to each of the plurality of column ADC circuits 4-1 to 4-n. The reference voltage VREF has a ramp-like waveform that temporally changes from the reference level with a predetermined slope (<0) (see FIG. 6).

  As shown in FIG. 6, in the reset level detection period TPr for sampling the reset level of the pixel PC, the reference voltage generation circuit 6 performs an integration operation in response to the integration enable signal being at the active level, and the reference voltage VREF. To change the level. As a result, the reference voltage VREF changes with time from the level V1 to the level V5 with a slope S_reset (<0). Further, in the signal level detection period TPs for sampling the signal level of the pixel PC, the reference voltage generation circuit 6 performs an integration operation and changes the level of the reference voltage VREF in response to the integration enable signal being at the active level. . As a result, the reference voltage VREF changes with time from the level V1 to the level V6 with a slope S_reset. The difference between level V1 and level V6 is greater than the difference between level V1 and level V5. The level V5 can be a level closer to the level V1 than the intermediate level between the levels V1 and V6. FIG. 6 is a waveform diagram showing the operation of the solid-state imaging device 1.

  As shown in FIG. 3, the plurality of column ADC circuits 4-1 to 4-n are provided corresponding to the plurality of columns of the pixel array PA. Each column ADC circuit 4-1 to 4-n AD converts a signal (analog signal) read from the pixel via the signal line Vlin of the corresponding column to generate a digital signal Vout.

  As shown in FIG. 5, each column ADC circuit 4-1 to 4-n includes a comparator 4a, an edge detection circuit 4b, a counter 4c, a latch circuit 4d, a switch 4e, and a capacitive element 4f. The configuration of the column ADC circuit 4-1 is illustrated, but the configurations of the other column ADC circuits 4-2 to 4-n are the same.

  The comparator 4a compares the potential level of the reference voltage VREF with the potential level of the pixel signal (analog signal), and outputs the comparison result to the edge detection circuit 4b. For example, when the potential level of the reference voltage VREF is higher than the potential level of the pixel signal (analog signal), the comparator 4a outputs an H level, and the potential level of the reference voltage VREF is lower than the potential level of the pixel signal (analog signal). In this case, L level is output. That is, when the magnitude relationship between the potential level of the reference voltage VREF and the potential level of the pixel signal (analog signal) is inverted, the comparator 4a inverts the comparison result from the H level to the L level and outputs the result.

  The comparator 4a has an inverting input terminal (first input terminal) 4a1, a non-inverting input terminal (second input terminal) 4a2, and an output terminal 4a3. The inverting input terminal 4a1 is connected to the signal line Vlin-1 via the capacitive element 4f, and a level corresponding to the potential VSIG of the signal line Vlin-1 is transmitted via the capacitive element 4f. The non-inverting input terminal 4a2 is connected to the reference voltage generation circuit 6 and supplied with the reference voltage VREF. The output terminal 4a3 is connected to the edge detection circuit 4b.

  The switch 4e makes the inverting input terminal 4a1 and the output terminal 4a3 conductive or electrically cut off according to the control signal φSW from the timing control circuit 7. The switch 4e has one end 4e1 connected to the inverting input terminal 4a1, the other end 4e2 connected to the output terminal 4a3, and a control signal φSW supplied to the control terminal 4e3. The switch 4e is turned on when the active level control signal φSW is supplied to the control terminal 4e3, thereby turning on the inverting input terminal 4a1 and the output terminal 4a3, and the active level control signal φSW is supplied to the control terminal 4e3. When turned on, the inverting input terminal 4a1 and the output terminal 4a3 are electrically cut off.

  The capacitive element 4f is electrically connected between the signal line Vlin-1 and the inverting input terminal 4a1. The capacitive element 4f has one end 4f1 connected to the inverting input terminal 4a1 and one end 4e1, and the other end 4f2 connected to the signal line Vlin-1 and the load current source G.

  Here, the signal output from the comparator 4a to the edge detection circuit 4b may include a component corresponding to the offset of the comparator 4a. The operating point of the comparator 4a needs to be an appropriate operating point in consideration of the operating margin of the column ADC circuit 4-1. Therefore, the column ADC circuit 4-1 cancels the influence of the offset of the comparator 4a and performs auto-zero processing that determines the operating point of the comparator 4a. Details of the auto-zero process will be described later.

  When the edge detection circuit 4b receives the comparison result from the comparator 4a and detects that the comparison result of the comparator 4a is inverted, the edge detection circuit 4b supplies the detection result to the counter 4c. For example, the edge detection circuit 4b supplies a pulse indicating that the comparison result of the comparator 4a is inverted to the counter 4c as a detection result.

  The counter 4c counts the number of clocks (the number of pulses of the clock φCCK) from when the potential level of the reference voltage VREF starts to change until the comparison result of the comparator 4a is inverted. For example, the counter 4c starts counting when the potential level of the reference voltage VREF starts to change, and counts when receiving a detection result (for example, a pulse) indicating that the comparison result of the comparator 4a is inverted from the edge detection circuit 4b. It is configured to stop operation. The counter 4c outputs the count value to the latch circuit 4d.

  The counter 4c has a number of bits corresponding to the cycle of the clock φCCK and the time width of the reference voltage VREF. The counter 4c starts counting up from the zero count value according to the number of clocks φCCK at the timing when the potential level of the reference voltage VREF starts to change from the level V1, and at the timing when the level reaches the level V6 that is the full amplitude of the reference voltage VREF. It is configured to have a full count value.

  As shown in FIG. 6, in the reset level detection period TPr for sampling the reset level of the pixel PC, the potential corresponding to the reset level output by the output unit AMP in a state where the charge voltage conversion unit FD is reset by the reset unit RST. Level V4 is input to the comparator 4a. The level V4 is a potential level that is lower than the potential of the signal line Vlin corresponding to the reset level output from the pixel PC by the offset voltage Voffset as the potential level of the reference voltage VREF decreases, and the column ADC circuit 4-1. Is treated as the reset level Vr of the pixel PC.

  The offset voltage Voffset is a capacitive offset voltage due to the influence of capacitive coupling inside the comparator 4a. That is, the offset voltage Voffset means a reduced amount of voltage when the potential of the inverting input terminal 4a1 also decreases as the reference voltage VREF (the potential of the non-inverting input terminal 4a2) decreases (FIG. 6). reference).

  For the reset level Vr, the counter 4c counts the number of clocks from when the potential level of the reference voltage VREF starts to change until the comparison result of the comparator 4a is inverted, and outputs the count value N_reset of the reset level Vr to the latch circuit 4d. To do. The count value N_reset of the reset level Vr corresponds to the level difference (auto-zero voltage Vaz ′) between the level V1 and the reset level Vr. That is, the counter 4c converts the level difference (auto-zero voltage Vaz ') between the level V1 and the reset level Vr into time, and counts the time (pixel count).

  In the signal level detection period TPs for sampling the signal level of the pixel PC, a potential corresponding to the signal level output by the output unit AMP in a state where the charge of the photoelectric conversion unit PD is transferred to the charge voltage conversion unit FD by the transfer unit TG. Level V7 is input to the comparator 4a. The level V7 is a potential level that is lower than the potential of the signal line Vlin corresponding to the signal level output from the pixel PC by the offset voltage Voffset, and is treated as the signal level Vs of the pixel PC in the column ADC circuit 4-1. For the signal level Vs, the counter 4c counts the number of clocks from when the potential level of the reference voltage VREF starts to change until the comparison result of the comparator 4a is inverted, and outputs the count value N_signal of the signal level Vs to the latch circuit 4d. To do. The count value N_signal of the signal level Vs corresponds to a level difference (pixel signal voltage Vps) between the level V1 and the signal level Vs. That is, the counter 4c converts the level difference (pixel signal voltage Vps) between the level V1 and the signal level Vs into time, and counts the time (pixel count).

  In FIG. 6, the potential of the non-inverting input terminal 4a2 of the comparator 4a is indicated as “COMP input (+)”, and the potential of the inverting input terminal 4a1 of the comparator 4a is indicated as “COMP input (−)”. In addition, a clock used for pixel count in the clock φCCK supplied to the counter 4c is shown as a “counter clock”.

  The latch circuit 4d receives the count value from the counter 4c, and receives the horizontal scanning pulse φPH from the horizontal scanning circuit 5 in the horizontal period of the column. The latch circuit 4 d latches the count value at the timing when the horizontal scanning pulse φPH becomes the active level and transfers it to the digital signal processing circuit 8.

  As shown in FIG. 6, the latch circuit 4 d transfers the count value of the reset level Vr to the digital signal processing circuit 8 after the reset level detection period TPr for sampling the reset level of the pixel PC is completed. The latch circuit 4d transfers the count value of the signal level Vs to the digital signal processing circuit 8 after the signal level detection period TPs for sampling the signal level of the pixel PC is completed.

  The horizontal scanning circuit 5 scans the plurality of column ADC circuits 4-1 to 4-n in the horizontal direction according to the clock φHCK. That is, the horizontal scanning circuit 5 sequentially selects the plurality of column ADC circuits 4-1 to 4-n by sequentially and selectively setting the horizontal scanning signals φPH-1 to φPH-n of the respective columns to the active level. Thus, the digital signal is transferred to the digital signal processing circuit 8.

  The digital signal processing circuit 8 receives digital signals from the column ADC circuits 4-1 to 4-n in each column. The digital signal processing circuit 8 generates a digital value Data corresponding to the count value of the counter 4c and outputs it to the ISP 96 in the horizontal period of each column.

  The digital signal processing circuit 8 performs interphase double sampling (CDS) processing on the digital signal to generate a digital value Data. For example, when receiving a digital signal corresponding to the count value N_reset of the reset level Vr, the digital signal processing circuit 8 holds a digital signal corresponding to the auto-zero voltage Vaz ′ (see FIG. 6). Thereafter, when the digital signal processing circuit 8 receives a digital signal corresponding to the count value N_signal of the signal level Vs, the digital signal processing circuit 8 corresponds to the digital signal corresponding to the count value N_reset of the reset level Vr and the count value N_signal of the signal level Vs. A difference from the digital signal (digital signal corresponding to the count value N_signal ′) is taken. That is, the digital signal processing circuit 8 takes a difference between a digital signal corresponding to the auto-zero voltage Vaz ′ and a digital signal corresponding to the pixel signal voltage Vps (see FIG. 6). The digital signal processing circuit 8 outputs a digital signal corresponding to the difference, that is, the processed pixel signal voltage Vps ′ (= Vps−Vaz ′) as a digital value Data. Thereby, the influence of the fixed pattern noise of the pixel included in the pixel signal can be removed and the influence of the offset voltage Voffset of the comparator 4a can be removed, and a highly accurate digital value can be generated and output.

  Here, as shown in FIG. 6, prior to the reset level detection period TPr for sampling the reset level of the pixel PC and the signal level detection period TPs for sampling the signal level of the pixel PC, an auto-zero period TPaz for performing auto-zero processing is provided. Is provided. In the first half of the integration period T_zero in the reset level detection period TPr, the reference voltage generation circuit 6 performs an integration operation and changes the level of the reference voltage VREF in response to the integration enable signal being at the active level. As a result, the reference voltage VREF changes with time from the level V1 to the level V2 with a slope S_preset (<0). The level V2 is a level determined in advance as an appropriate operating point of the comparator 4a in consideration of the operation margin of the column ADC circuit 4-1, and is, for example, a level in the vicinity of an intermediate value between the level V1 and the level V5. The integration period T_zero is an integration period for the integration circuit in the reference voltage generation circuit 6 to perform an integration operation to generate an integration waveform (ramp wave) of the reference voltage VREF, and is a predetermined substantially constant period. The slope S_preset is an integration coefficient corresponding to a gain when the integration circuit in the reference voltage generation circuit 6 performs the integration operation. The slope S_preset is a slope that is adjusted in advance so that the level of the reference voltage VREF becomes V2 at the completion timing of the integration period T_zero when the reference voltage VREF is changed from the level V1 in the integration period T_zero. In the second half period T1 in the reset level detection period TPr to be sampled, the reference voltage VREF is maintained at the level V2.

  In the auto-zero period TPaz, the switch 4e is maintained in the ON state, and the inverting input terminal 4a1 and the output terminal 4a3 are made conductive. Therefore, the comparator 4a causes the potential of the output terminal 4a3 to become the potential of the non-inverting input terminal 4a2 by the voltage follower. Following this, the potential becomes the same, and V2 is charged in the capacitive element 4f. The length of the period T1 is a length that is determined in advance as time necessary for the potential of the signal line Vlin-1 and the voltage of the capacitor 4f to be stabilized.

  When the switch 4e is turned off at the timing t1 when the auto-zero period TPaz is completed, the operating point of the comparator 4a is set to the level V2.

  When the level of the reference voltage VREF, that is, the potential of the non-inverting input terminal 4a2 starts to decrease from the level V1, the potential of the inverting input terminal 4a1 of the comparator 4a also starts to decrease from the level V2 due to capacitive coupling inside the comparator 4a. Thereby, the operating point of the comparator 4a in the reset level detection period TPr deviates from the operating point set in the period T1. In order to set the operating point of the comparator 4a in the reset level detection period TPr to an appropriate operating point, the potential of the inverting input terminal 4a1 of the comparator 4a in the reset level detection period TPr needs to be close to the level V2. That is, the potential of the inverting input terminal 4a1 to be adjusted in the auto-zero period (the level to be maintained in the period T1) needs to be corrected by the amount of deviation from the level V2, that is, the offset voltage Voffset of the comparator 4a. Since the integration period T_zero in the auto-zero process is determined to be substantially constant, the reference voltage generation circuit 6 is controlled to generate the reference voltage VREF with an appropriate slope S_adjust according to the level difference between the level V1 and the level (V2 + Voffset). There is a need to. The amount of deviation, that is, the offset voltage Voffset of the comparator 4a can vary depending on the operating conditions (clock frequency, reference voltage level, etc.) of the solid-state imaging device 1.

  If the digital signal processing circuit 8 is configured to perform preset processing for adjusting the slope of the reference voltage VREF during auto-zero processing by a certain step ΔS in order to keep the circuit scale of the circuit that performs auto-zero processing small. think of. In this case, the digital signal processing circuit 8 verifies whether the slope of the reference voltage VREF is an appropriate slope S_adjust while adjusting the slope of the reference voltage VREF in the integration period T_zero by a certain step ΔS in the preset process. I do. Then, the digital signal processing circuit 8 repeats the adjustment and verification a plurality of times until the verification that the inclination of the reference voltage VREF is an appropriate inclination S_adjust is successful in the preset process.

  For example, in the digital signal processing circuit 8, a target count value corresponding to the level V2 is set in advance for each operation condition (clock frequency, reference voltage level, etc.). The digital signal processing circuit 8 specifies a target count value N_target corresponding to the level V2 according to the current operating condition. Here, it is assumed that the first to third rows in the pixel array PA are optical black regions, and the fourth to m-th rows are effective pixel regions. Since the pixels in the first to third rows are light-shielding pixels, they are used to perform auto-zero processing that does not require a light receiving operation.

  The reset level is read out from each pixel PC (1,1) to PC (1, n) in the first row in the pixel array PA to the column ADC circuit 4 in each column. The column ADC circuit 4 of each column causes the potential of the inverting input terminal 4a1 to be the level V2 during the auto-zero period TPaz, and performs the pixel count of the reset level Vr (level V4) during the reset level detection period TPr to obtain the count value N_preset. . The digital signal processing circuit 8 averages the count value N_preset for each pixel PC (1,1) to PC (1, n) in the first row, and averages the count value AVE (N_preset) and the target count value N_target. And compare.

  When the averaged count value AVE (N_preset) is larger than the target count value N_target, the digital signal processing circuit 8 generates a reference voltage with the control signal φAZ so that the slope of the reference voltage VREF in the integration period T_zero is changed to S_preset + ΔS. The circuit 6 is controlled. For example, the reference voltage generation circuit 6 reduces the current flowing through the integration circuit from I to I−ΔI so that the slope of the reference voltage VREF generated by the integration operation of the integration circuit changes from S_preset to S_preset + ΔS.

  The reset level is read out from the pixels PC (2, 1) to PC (2, n) in the second row in the pixel array PA to the column ADC circuit 4 in each column. The column ADC circuit 4 in each column causes the potential of the inverting input terminal 4a1 to be level V2 + ΔV during the auto-zero period TPaz, and performs the pixel count of the reset level Vr (level V4 + ΔV) during the reset level detection period TPr, and count value N_preset−ΔN. Get. The digital signal processing circuit 8 averages the count value N_preset−ΔN for each pixel PC (2,1) to PC (2, n) in the second row, and the averaged count value AVE (N_preset−ΔN) and the target Are compared with the count value N_target.

  When the averaged count value AVE (N_preset−ΔN) is larger than the target count value N_target, the digital signal processing circuit 8 changes the control signal φAZ to change the slope of the reference voltage VREF in the integration period T_zero to S_preset + ΔS × 2. To control the reference voltage generation circuit 6. For example, the reference voltage generation circuit 6 reduces the current flowing through the integration circuit from I−ΔI to I−ΔI × 2, and the slope of the reference voltage VREF generated by the integration operation of the integration circuit is changed from S_preset + ΔS to S_preset + ΔS × 2. To.

  The reset level is read from each pixel PC (3, 1) to PC (3, n) in the third row in the pixel array PA to the column ADC circuit 4 in each column. The column ADC circuit 4 in each column causes the potential of the inverting input terminal 4a1 to be level V2 + ΔV × 2 during the auto-zero period TPaz, and causes the pixel count of the reset level Vr (level V4 + ΔV × 2) to be performed during the reset level detection period TPr. The value N_preset−ΔN × 2 is obtained. The digital signal processing circuit 8 averages the count value N_preset−ΔN × 2 for each pixel PC (3,1) to PC (3, n) in the third row, and averages the count value AVE (N_preset−ΔN × 2) is compared with the target count value N_target.

  When the averaged count value AVE (N_preset−ΔN × 2) is substantially equal to the target count value N_target, the digital signal processing circuit 8 determines that the verification is successful and sets the slope S_preset + ΔS × 2 to an appropriate slope S_adjust. And Thereby, the preset process is completed. Thereafter, a normal readout operation (for example, readout of signals from the pixels PC (4, 1) to PC (4, n) in the fourth row) is started.

  As described above, when the preset process for adjusting the slope of the reference voltage VREF by a certain step ΔS is performed, the adjustment and verification need to be repeated a plurality of times, and a large number of lines (for example, three lines) are required until the preset process is completed. Pixel readout time is required. However, when the request for the frame rate becomes strict (for example, when it is required to maintain the frame rate while increasing the number of pixels or when the frame rate is required to be reduced), the preset process is performed. If the readout time for a large number of rows is secured, the frame rate of the image signal output from the solid-state imaging device 1 may exceed the required length. When the frame rate exceeds the required length, if the image obtained from the image signal is a moving image, it is difficult to secure the number of frames within a predetermined time, and it becomes difficult to obtain a smooth moving image. Alternatively, when the image obtained from the image signal is a still image, the release time lag increases, and it may be difficult to capture a photo opportunity.

  Therefore, in the embodiment, in the solid-state imaging device 1, the deviation amount (offset voltage) is calculated based on the difference between the count value N_reset acquired by the pixel count of the reset level Vr and the target count value N_target in the reset level detection period TPr. The slope of the reference voltage VREF in the next auto-zero period is calculated and calculated so as to correct the deviation amount. As a result, the number of adjustments of the preset process is reduced to one and verification is not required, and the time for performing the preset process is shortened.

  Specifically, as shown in FIG. 3, the digital signal processing circuit (control circuit) 8 includes an average value calculation circuit 8a and an auto-zero voltage calculation circuit 8b. After the auto zero process and the reset level detection process are performed in the column ADC circuit 4 of each column, the average value calculation circuit 8a acquires the count value of the column ADC circuit 4 of each column. The average value calculation circuit 8a averages the count values of the column ADC circuit 4 in each column. The average value calculation circuit 8a supplies the averaged count value to the auto zero voltage calculation circuit 8b. Based on the difference between the averaged count value and the target count value, the auto-zero voltage calculation circuit 8b calculates the slope of the reference voltage to be used during the next auto-zero process.

  For example, as shown in FIG. 7, the digital signal processing circuit (control circuit) 8 controls the reference voltage generation circuit 6 with the control signal φAZ so that the slope of the reference voltage VREF becomes S_preset during the auto-zero period TPaz1. FIG. 7 is a waveform diagram showing the operation of the solid-state imaging device 1. The slope S_preset is an integration coefficient corresponding to a gain when the integration circuit in the reference voltage generation circuit 6 performs the integration operation. The slope S_preset is a slope that is adjusted in advance so that the level of the reference voltage VREF becomes V2 at the completion timing of the integration period T_zero when the reference voltage VREF is changed from the level V1 in the integration period T_zero.

  Prior to the auto-zero period TPaz1, the reset level is read from each pixel PC (1, 1) to PC (1, n) in the first row in the pixel array PA to the column ADC circuit 4 in each column.

  In the auto-zero period TPaz1, the column ADC circuit 4 in each column sets the potential of the inverting input terminal 4a1 to the level V2. In the auto zero period TPaz1, the control signal φSW is maintained at the active level. In other words, the switch 4e in the column ADC circuit 4 in each column keeps the inverting input terminal 4a1 and the output terminal 4a3 of the comparator 4a in the column ADC circuit 4 in each column in the auto-zero period TPaz1. In this state, the digital signal processing circuit 8 changes the reference voltage VREF from the level V1 with the slope S_preset to the level V2 in the substantially constant integration period T_zero which is the first half of the auto zero period TPaz1, and the second half period of the auto zero period TPaz1. At T11, the reference voltage generation circuit 6 is controlled so that the reference voltage VREF is maintained at the level V2.

  When the switch 4e is turned off in the column ADC circuit 4 of each column at the timing t1 'at which the auto zero period TPaz1 is completed, the operating point of the comparator 4a is set to the level V2.

  In the reset level detection period TPr1, the digital signal processing circuit 8 controls the reference voltage generation circuit 6 so as to change the reference voltage VREF from the level V1 with a slope S_reset. When the level of the reference voltage VREF, that is, the potential of the non-inverting input terminal 4a2 starts to decrease, the potential of the inverting input terminal 4a1 of the comparator 4a also starts to decrease due to capacitive coupling inside the comparator 4a. Then, the potential of the inverting input terminal 4a1 of the comparator 4a becomes the level V4 that is lower than the level V2 by the offset voltage Voffset. At the same time, the column ADC circuit 4 of each column performs a pixel count of the reset level Vr (level V4) to obtain a count value N_preset. The digital signal processing circuit 8 acquires the count value N_preset from the column ADC circuit 4 of each column. The digital signal processing circuit 8 averages the count value N_preset of the column ADC circuit 4 in each column for each pixel PC (1,1) to PC (1, n) in the first row. Based on the difference between the averaged count value AVE (N_preset) and the target count value N_target, the digital signal processing circuit 8 calculates the slope S_adjust of the reference voltage VREF to be used in the next auto-zero period TPaz2.

  For example, the average value calculation circuit 8a (see FIG. 3) averages the count value N_preset of the column ADC circuit 4 in each column, and supplies the averaged count value AVE (N_preset) to the auto-zero voltage calculation circuit 8b. The auto-zero voltage calculation circuit 8b (see FIG. 3), based on the difference between the averaged count value AVE (N_preset) and the target count value N_target (count value difference), performs an auto-zero process TPaz2 for performing auto-zero processing next. The slope S_adjust of the reference voltage VREF to be used for (see FIG. 8) is calculated. The auto-zero voltage calculation circuit 8b calculates a difference (offset voltage Voffset) between the level V2 of the inverting input terminal 4a1 of the comparator 4a adjusted in the auto-zero period TPaz1 and the level V4 of the inverting input terminal 4a1 of the comparator 4a in the reset level detection period TPr1. The slope S_adjust is calculated so that it can be corrected to the next auto-zero period TPaz2.

  For example, the auto zero voltage calculation circuit 8b obtains the time T_preset by multiplying the averaged count value AVE (N_preset) by the period of the counter clock φCCK. The auto-zero voltage calculation circuit 8b obtains the time T_target by multiplying the target count value N_target by the period of the counter clock φCCK. The auto-zero voltage calculation circuit 8b obtains a difference time (T_target−T_preset) between the time T_preset and the time T_target as a time corresponding to the difference between the count values. The auto-zero voltage calculation circuit 8b multiplies the difference time (T_target−T_preset) by the slope S_reset of the reference voltage VREF to obtain a deviation amount Voffset = S_reset * (T_target−T_preset).

The auto-zero voltage calculation circuit 8b divides the deviation amount Voffset = S_reset * (T_target−T_preset) by the length of the integration period T_zero in the auto-zero process, and obtains the inclination correction amount S_reset * (T_target−T_preset) / T_zero. The auto-zero voltage calculation circuit 8b calculates the slope S_adjust of the reference voltage VREF to be used in the next auto-zero period TPaz2 by adding the correction amount of the slope to the slope S_preset of the reference voltage VREF in the auto-zero period TPaz1. .
S_adjust = S_reset * (T_target−T_preset) / T_zero + S_preset Equation 1

  In Equation 1, the slope S_preset is a slope that is adjusted in advance so that the level of the reference voltage VREF becomes V2 at the completion timing of the integration period T_zero when the reference voltage VREF is changed from the level V1 in the integration period T_zero. This corresponds to the auto-zero voltage Vaz (= V1-V2). The slope S_adjust is a slope calculated so that the level of the reference voltage VREF becomes V3 (= V2 + Voffset) at the completion timing of the integration period T_zero when the reference voltage VREF is changed from the level V1 in the integration period T_zero. The slope S_adjust corresponds to a voltage (Vaz−Voffset) obtained by subtracting the offset voltage Voffset from the auto-zero voltage Vaz.

  Thereafter, the digital signal processing circuit (control circuit) 8 controls the reference voltage generation circuit 6 with the control signal φAZ so that the slope of the reference voltage VREF becomes S_adjust during the next auto-zero period TPaz2.

  For example, as shown in FIG. 8, before the auto-zero period TPaz2, the reset level from each pixel PC (4, 1) to PC (4, n) in the fourth row in the pixel array PA to the column ADC circuit 4 in each column is reset. Is read out. FIG. 8 is a waveform diagram showing the operation of the solid-state imaging device 1.

  In the auto-zero period TPaz2, the column ADC circuit 4 in each column sets the potential of the inverting input terminal 4a1 to the level V3. In the auto zero period TPaz2, the control signal φSW is maintained at the active level. That is, the switch 4e in the column ADC circuit 4 of each column is in a state in which the inverting input terminal 4a1 and the output terminal 4a3 of the comparator 4a of the column ADC circuit 4 of each column are in conduction during the auto-zero period TPaz2. In this state, the digital signal processing circuit 8 changes the reference voltage VREF from the level V1 with the slope S_adjust to the level V3 in the substantially constant integration period T_zero which is the first half of the auto zero period TPaz2, and the second half period of the auto zero period TPaz2. At T12, the reference voltage generation circuit 6 is controlled to maintain the reference voltage VREF at the level V3.

  At the timing t1 ″ at which the auto-zero period TPaz2 is completed, when the switch 4e is turned off in the column ADC circuit 4 of each column, the operating point of the comparator 4a is set to the level V3.

  In the reset level detection period TPr2, the digital signal processing circuit 8 controls the reference voltage generation circuit 6 so as to change the reference voltage VREF from the level V1 with a slope S_reset. When the level of the reference voltage VREF, that is, the potential of the non-inverting input terminal 4a2 starts to decrease, the potential of the inverting input terminal 4a1 of the comparator 4a also starts to decrease due to capacitive coupling inside the comparator 4a. Then, the potential of the inverting input terminal 4a1 of the comparator 4a becomes a level V2 that is lower than the level V3 by the offset voltage Voffset. At the same time, the column ADC circuit 4 of each column performs a pixel count of the reset level Vr ′ (level V2) to obtain a count value N_reset. This count value N_reset is a value substantially equal to the target count value N_target. Thus, the operating point of the comparator 4a in the reset level detection period TPr is an appropriate operating point in consideration of the operating margin of the column ADC circuit 4.

  7 and 8, the potential of the non-inverting input terminal 4a2 of the comparator 4a is indicated as “COMP input (+)”, and the potential of the inverting input terminal 4a1 of the comparator 4a is indicated as “COMP input (−)”. Yes. In addition, a clock used for pixel count in the clock φCCK supplied to the counter 4c is shown as a “counter clock”.

  As described above, in the embodiment, in the solid-state imaging device 1, the digital signal processing circuit 8 performs auto-zero processing in the auto-zero period, and the count value N_reset acquired by the pixel count of the reset level Vr in the reset level detection period TPr. And a target count value N_target, a shift amount (offset voltage) is calculated, and a slope of the reference voltage VREF in the next auto-zero period is calculated and calculated so as to correct the shift amount. The digital signal processing circuit 8 changes the reference voltage VREF in the next auto-zero period with the calculated slope. Thereby, the operating point of the comparator 4a in the reset level detection period TPr can be set to an appropriate operating point in consideration of the operating margin of the column ADC circuit 4. That is, the number of adjustments of the preset process can be reduced to one, verification can be made unnecessary, and the time for performing the preset process can be shortened, so that the frame rate requirement can be easily satisfied.

  In the embodiment, in the solid-state imaging device 1, the digital signal processing circuit 8 acquires the count value N_reset acquired by the pixel count of the reset level Vr from the column ADC circuit 4 of each column and averages it. The digital signal processing circuit 8 calculates a shift amount (offset voltage) according to the difference between the averaged count value AVE (N_reset) and the target count value N_target and corrects the shift amount by the next auto zero. The slope of the reference voltage VREF for the period is calculated and obtained. Thereby, in the adjustment of the slope of the reference voltage VREF used in common for each column in the pixel array PA, it is possible to reduce the influence of variations in the offset voltage Voffset of each column.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 solid-state imaging device, PC pixel, Vlin signal line, 4a comparator, 4c counter, 4e switch, 4f capacitive element, 8 digital signal processing circuit.

Claims (5)

Pixels,
A signal line electrically connected to the pixel;
A comparator having a first input terminal to which a level corresponding to the potential of the signal line is transmitted, a second input terminal to which a reference voltage is supplied, and an output terminal;
A counter that counts the number of clocks from when the potential level of the reference voltage starts to change during the reset level detection period until the output signal of the comparator is inverted;
In a state where the first input terminal and the output terminal of the comparator are made conductive during the first auto-zero period, the reference voltage is changed from the first level to the second level by a first slope for a predetermined time. The reference voltage is temporally changed from the first level with a second slope in a state where the first input terminal and the output terminal of the comparator are electrically cut off during the first reset level detection period. A control circuit that obtains a count value of the counter while calculating, and calculates a third slope of the reference voltage to be used in the second auto-zero period based on a difference between the obtained count value and a target count value; ,
A solid-state imaging device. A second pixel;
A second signal line connected to the second pixel;
A second comparator having a first input terminal to which a level corresponding to the potential of the second signal line is transmitted, a second input terminal to which the reference voltage is supplied, and an output terminal;
A second counter that counts the number of clocks from when the potential level of the reference voltage starts to change during a reset level detection period until the output signal of the second comparator is inverted;
Further comprising
The control circuit sets the reference voltage from the first level in a state where the first input terminal and the output terminal of the comparator and the second comparator are turned on in the first auto-zero period, respectively. The first slope is changed for the predetermined time to the second level, and the first input terminal and the output terminal of each of the comparator and the second comparator are set in the first reset level detection period. Obtaining the count value of the counter and the count value of the second counter while temporally changing the reference voltage from the first level with the second slope in an electrically interrupted state, An averaged count value is obtained based on the count value of the counter and the count value of the second counter, and the averaged count value and the target The solid-state imaging device according to claim 1, wherein calculating the third gradient based on the difference between the count value. The control circuit sets the reference voltage at the third slope from the first level in a state where the first input terminal and the output terminal of the comparator are turned on during the second auto-zero period. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is changed to a third level by changing the time. The control circuit multiplies the time corresponding to the difference by the second slope, divides the multiplication result by the length of the predetermined time, adds the first slope to the division result, and The solid-state imaging device according to claim 1, wherein an inclination of 3 is obtained. A switch having one end connected to the first input terminal of the comparator and the other end connected to the output terminal of the comparator;
A capacitive element having one end connected to the signal line and the other end connected to the first input terminal;
The solid-state imaging device according to any one of claims 1 to 4, further comprising:

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