JP2017017272A - Capacitor, semiconductor device, capacitor manufacturing method, and semiconductor device manufacturing method - Google Patents

Abstract

The present invention relates to a capacitor, a semiconductor device, a method for manufacturing a capacitor, and a method for manufacturing a semiconductor device. A first electrode, a first dielectric film provided in a central portion of the first electrode, and a film smaller than the first dielectric film provided surrounding the first dielectric film. A second dielectric film having a thickness and a relative dielectric constant smaller than or equal to the first dielectric film; a second dielectric film covering the first dielectric film; and a second dielectric film covering at least a part of the second dielectric film. And a third electrode is provided between the first electrode and the second electrode. [Selection] Figure 1

Description

  The present invention relates to a capacitor, a semiconductor device, a method for manufacturing a capacitor, and a method for manufacturing a semiconductor device. For example, the high breakdown voltage and high reliability used in a high-frequency / high-power device such as a GaN-based HEMT (high electron mobility transistor). The present invention relates to a capacitor, a semiconductor device, a capacitor manufacturing method, and a semiconductor device manufacturing method.

  In high-frequency / high-power devices such as GaN-based HEMTs, research and development of devices with higher withstand voltage and higher reliability are being promoted to cope with the expected increase in operating voltage as well as high-frequency characteristics. Among various device elements, MIM (Metal-Insulator-Metal) capacitors used in MMICs (Monolithic Microwave Integrated Circuits) and the like are similarly required to have improved breakdown voltage and reliability (for example, Patent Document 1). reference).

  The basic structure of an MIM capacitor is an electrode in which an insulator is sandwiched between electrodes. Generally, a lower electrode / dielectric film / upper electrode are sequentially stacked in the vertical direction and viewed from above. The shape is formed to be rectangular or circular.

  However, when this shape is used, there is a problem that the probability of destruction near the inner center when viewed from the top of the capacitor is relatively high as a destruction situation when a high voltage is applied to the capacitor. Will be described with reference to FIG. FIG. 23 is an explanatory view of the problem of the conventional capacitor, FIG. 23 (a) is a plan view, and FIG. 23 (b) is taken along the alternate long and short dash line connecting AA 'in FIG. 23 (a). It is sectional drawing.

  As shown in FIG. 23B, the capacitor having the conventional structure has a laminated structure of a lower electrode 72 / SiN film 73 / upper electrode 74 on a base insulating film 71. In the figure, a capacitor having a circular planar shape using a SiN film as a dielectric film is described as an example. In the capacitor of this conventional composition, as shown in FIG. 23A, when a breakdown occurs, a breakdown part 75 is generated at the center. This is presumed that a current leak path is formed by pinholes (defects) existing in the SiN film 73 as a dielectric film, and that the electric field is more concentrated in the center of the dielectric of the capacitor. ing.

JP 2014-120732 A

  In order to avoid such a problem, a method of increasing the thickness of the dielectric film is often used, and the circumstances will be described with reference to FIG. FIG. 24 is an explanatory diagram of a withstand voltage improving means, FIG. 24 (a) is a cross-sectional view of a conventional capacitor, and FIG. 24 (b) has the same capacitance using the same dielectric film as the conventional capacitor. It is sectional drawing of a capacitor. FIG. 24C is a cross-sectional view of a capacitor using a high-k film having the same plane area and the same capacitance as a conventional capacitor.

As shown in FIG. 24B, if the dielectric film is thickened while maintaining the capacitance using the same dielectric film as that of the conventional capacitor, the area of the capacitor increases. That is, the capacitance C of the capacitor is as follows: ε ₀ is the dielectric constant of vacuum, ε is the relative dielectric constant of the dielectric film, S is the plane area of the capacitor, and d is the film thickness of the dielectric film.
C = ε ₀ × ε × S / d. Therefore, for example, when the film thickness d of the SiN film 73 is 1.5 times the film thickness d of the capacitor having the conventional structure, the area S is 1.5 times, and thus the diameter R is (1.5) ^{1. / 2} is required. As described above, when the plane area of the capacitor increases, the layout of the capacitor becomes difficult, which leads to an increase in the chip area.

On the other hand, as shown in FIG. 24C, when the high-k film 76 is used, the capacitor can be configured while maintaining the plane area S and the capacitance C. However, the film thickness of the high-k film 76 in this case needs to be (ε _high-k / ε _SiN ) times the film thickness d of the conventional capacitor. For example, if the relative permittivity of the SiN film 73 is 7.0 and the relative permittivity of the high-k film 76 is 15, the capacitor thickness is 2.15 times (≈15 / 7). As described above, when the film thickness is increased by a factor of two or more, a problem of coverage in a post-process step occurs due to a step, and there is a concern that it may be difficult to apply to a device for MMIC.

  Accordingly, an object of the present invention is to improve the breakdown voltage without increasing the area of the capacitor and suppressing the occurrence of a coverage problem in the semiconductor device.

  From one aspect to be disclosed, the first dielectric film provided around the periphery of the first dielectric film, the first dielectric film provided at the center of the first electrode, and the first dielectric film. A second dielectric film having a smaller film thickness and a dielectric constant smaller than or equal to the first dielectric film; and covering the first dielectric film and covering at least a part of the second dielectric film. There is provided a capacitor comprising: a second electrode; and a third electrode provided between the first electrode and the second electrode.

  According to another aspect of the disclosure, the semiconductor substrate includes a semiconductor substrate and a capacitor provided on the semiconductor substrate, and the capacitor is provided with a first electrode and a first electrode provided at a central portion of the first electrode. A second dielectric having a dielectric film, a thickness smaller than the first dielectric film provided surrounding the first dielectric film, and a relative dielectric constant smaller than or equal to the first dielectric film; A body electrode; a second electrode that covers the first dielectric film and covers at least a portion of the second dielectric film; and a third electrode provided between the first electrode and the second electrode A semiconductor device is provided.

  According to still another aspect of the disclosure, a step of forming a first electrode on an insulating film, a step of providing a first dielectric film at the center of the first electrode, and a periphery of the first dielectric film Providing a second dielectric film having a thickness smaller than that of the first dielectric film and a relative dielectric constant smaller than or equal to the first dielectric film, and covering the first dielectric film. And manufacturing a capacitor comprising: a step of covering at least a part of the second dielectric film with a second electrode; and a step of providing a third electrode between the first electrode and the second electrode. A method is provided.

  From another viewpoint to be disclosed, a step of providing a first electrode on a semiconductor substrate via an insulating film, a step of providing a first dielectric film at the center of the first electrode, and the first dielectric Providing a second dielectric film having a thickness smaller than the first dielectric film and a relative dielectric constant smaller than or equal to the first dielectric film so as to surround the periphery of the body film; and the first dielectric A step of covering a body film and covering at least a part of the second dielectric film with a second electrode; and a step of providing a third electrode between the first electrode and the second electrode. A method of manufacturing a semiconductor device is provided.

  According to the disclosed capacitor, semiconductor device, capacitor manufacturing method, and semiconductor device manufacturing method, the breakdown voltage can be improved without increasing the area of the capacitor and suppressing the occurrence of a coverage problem.

It is explanatory drawing of the semiconductor device provided with the capacitor of embodiment of this invention. It is explanatory drawing of the capacitor structure in implementation of this invention. It is explanatory drawing of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 4 of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 5 of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 6 of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 7 of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 8 of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 9 of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 10 of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing after FIG. 11 of the manufacturing process of the compound semiconductor device of Example 1 of this invention. It is explanatory drawing of the compound semiconductor device of Example 2 of this invention. It is explanatory drawing to the middle of the manufacturing process of the compound semiconductor device of Example 2 of this invention. It is explanatory drawing to the middle after FIG. 14 of the manufacturing process of the compound semiconductor device of Example 2 of this invention. It is explanatory drawing to the middle after FIG. 15 of the manufacturing process of the compound semiconductor device of Example 2 of this invention. FIG. 17 is an explanatory diagram after FIG. 16 of the manufacturing process of the compound semiconductor device of Example 2 of the present invention. It is explanatory drawing of the compound semiconductor device of Example 3 of this invention. It is explanatory drawing to the middle of the manufacturing process of the compound semiconductor device of Example 4 of this invention. It is explanatory drawing to the middle after FIG. 19 of the manufacturing process of the compound semiconductor device of Example 4 of this invention. It is explanatory drawing after FIG. 20 of the manufacturing process of the compound semiconductor device of Example 4 of this invention. It is explanatory drawing of the compound semiconductor device of Example 5 of this invention. It is explanatory drawing of the problem of the capacitor of a conventional structure. It is explanatory drawing of a pressure | voltage resistant improvement means.

  Here, with reference to FIG.1 and FIG.2, the capacitor and semiconductor device of embodiment of this invention are demonstrated. FIG. 1 is an explanatory view of a semiconductor device including a capacitor according to an embodiment of the present invention, FIG. 1 (a) is a cross-sectional view of a main part, and FIG. 1 (b) is an enlarged cross-sectional view of the capacitor. . In the semiconductor device according to the embodiment of the present invention, a capacitor 10 is provided on a semiconductor body 1 with an insulating film 4 interposed therebetween. In the figure, an interlayer insulating film 5 or the like for protecting the element portion 3 is provided on the insulating film 4.

  The semiconductor substrate 1 may be a silicon substrate itself, a laminated substrate in which a GaN-based semiconductor layer is laminated on a silicon substrate, GaN substrate, SiC substrate or sapphire substrate, or a III-V group compound semiconductor on a GaAs substrate or InP substrate. A laminated substrate or the like in which layers are laminated is used. The semiconductor substrate 1 is provided with an element isolation region 2, and an element part 3 surrounded by the element isolation region 2 is provided with at least one element such as a transistor such as a HEMT, a resistor, and an inductor. The element isolation region 2 may be formed by implanting ions such as Ar, or may be formed by an STI (Shallow Trench Isolation) structure.

  In the capacitor 10, a first dielectric film 13 is disposed at the center of the first electrode 11, and a first film having a thickness smaller than that of the first dielectric film 13 is formed so as to surround the first dielectric film 13. A two-dielectric film 14 is provided. A second electrode 15 is provided to cover the first dielectric film 13 and to cover at least a part of the second dielectric film 14. The relative dielectric constant of the first dielectric film 13 is greater than or equal to the relative dielectric constant of the second dielectric film 14.

  Further, the third electrode 12 is provided so as to compensate for the difference in film thickness between the first dielectric film 13 and the second dielectric film 14, whereby the lower or upper bottom surface of the first dielectric film 13 and the first The lower surface or upper surface of the dielectric film 13 is flush with the upper surface of the capacitor 10.

  The third electrode 12 may be provided in contact with the lower bottom surface of the second dielectric film 14. In this case, the third electrode 12 may have a taper structure on the side close to the first dielectric film 13. By providing the taper structure, the overall structure of the first electrode 11 and the third electrode 12 changes from a structure that changes stepwise to a structure in which the film thickness changes gradually, so that the electric field can be relaxed. This makes it possible to increase the breakdown voltage. In order to form the taper structure, a conductive material that becomes the third electrode 12 may be sputtered or vacuum-deposited from an oblique direction using a multilayer resist pattern having a saddle-like structure.

  Alternatively, the third electrode may be provided in contact with the upper bottom surface of the second dielectric film 14. In this case, the third electrode may be integrally formed simultaneously with the second electrode 15.

  The first dielectric film 13 is a dielectric film having a relative dielectric constant of 10.0 or more, and the second dielectric film 14 is a dielectric film having a relative dielectric constant of less than 10.0. However, in some cases, the first dielectric film 13 and the second dielectric film 14 may be the same dielectric film having a relative dielectric constant of less than 10.0. A relative dielectric constant of 10.0 or more is a typical value of the relative dielectric constant of a high dielectric material.

As shown in FIG. 1 (b), in a state where the plane area on the entire capacitor of (πR _{2 ^2/4)} were the same as the plane area of the conventional capacitor, the film thickness d ₁ of the first dielectric layer 13 provided on the central portion By making this thicker than the thickness of the dielectric film of the capacitor having the conventional structure, the breakdown voltage can be improved. For example, the breakdown voltage can be increased by 100 V or more by making the film thickness d ₁ of the first dielectric film 13 about 100 nm thicker than the thickness of the dielectric film of the capacitor having the conventional structure.

In this case, in order to maintain the same capacity as that of the conventional structure, when the thickness of the first dielectric film 13 is not so large, the thickness of the second dielectric film 14 is also the dielectric film of the capacitor having the conventional structure. The withstand voltage of the peripheral portion can be improved. Alternatively, when the thickness of the second dielectric film 14 is the same as the thickness of the dielectric film of the capacitor having the conventional structure, the plane area of the second dielectric film 14 is maintained in order to maintain the same capacitance as that of the conventional structure. , therefore, the overall diameter R ₂ may be smaller than the conventional capacitor, it is possible to reduce the area occupied by the capacitor.

Examples of the dielectric film having a relative dielectric constant of 10.0 or more include HfSiO, HfSiON, HfO ₂ , Y ₂ O ₃ , HfAlON, ZrO ₂ , Hf ₃ N ₄ , Zr ₃ N ₄ , TiO ₂ or Ta ₂ O ₅ . It is desirable to use either one. As the dielectric film having a relative dielectric constant of less than 10.0, either SiN (Si ₃ N ₄ ) or SiON is desirable.

  In any dielectric film structure, in order to maintain the same capacitance with the same plane area, it is thicker than a capacitor having a conventional structure. Therefore, in order to improve the step coverage, the second dielectric film 14 is made of a semiconductor. It is desirable to extend on the element part 3 provided in the base | substrate 1. FIG. In this way, by extending the second dielectric film 14 on the element portion 3 provided on the semiconductor substrate 1, impurities penetrate due to a crack in the interlayer insulating film 6 due to a step, It is possible to avoid a concern that causes a low breakdown voltage.

  In order to form such a structure, the first electrode 11 is provided on the semiconductor substrate 1 via the insulating film 4 (5), and the first dielectric film 13 is provided at the center of the first electrode 11. Next, a second dielectric film 14 having a thickness smaller than that of the first dielectric film 13 and a relative dielectric constant smaller than or equal to that of the first dielectric film 13 is provided so as to surround the periphery of the first dielectric film 13. . Next, the first dielectric film 13 is covered, and at least a part of the second dielectric film 14 is covered with the second electrode 14. At this time, the third electrode 12 may be provided between the first electrode 11 and the second electrode 15.

  FIG. 2 is an explanatory diagram of a capacitor structure according to an embodiment of the present invention, FIG. 2 (a) is a cross-sectional view of a capacitor having a conventional structure, and FIGS. 2 (b) to 2 (d) are embodiments. It is sectional drawing of the capacitor of. Here, for specific numerical evaluation, it is assumed that the relative dielectric constant of the first dielectric film 13 is 15, and the relative dielectric constant of the second dielectric film 14 is 5 to simplify the calculation.

First, as shown in FIG. 2 (a), case where the whole of SiN film, the overall diameter and the r ₁ and 30 [mu] m, the diameter R ₁ of the central portion corresponding to the first dielectric film and 20 [mu] m, the film thickness _{d 1} and 200nm. In this case, the capacitance C is 9.73 × 10 ⁻¹⁴ F in the central portion and 12.2 × 10 ⁻¹⁴ F in the peripheral portion, which is about 21.9 × 10 ⁻¹⁴ F as a whole. Become.

As shown in FIG. 2B, in the state where the plane area and the capacitance are maintained, only the central portion of the diameter R ₁ is replaced with the first dielectric film 13 having the thickness D ₁ which is an equivalent capacitance. In this case, D ₁ is about 427 nm, which is about 2.14 times the thickness. However, the step can be eliminated by extending the second dielectric film 14 to the element portion (3) and using it as an interlayer insulating film.

As shown in FIG. 2 (c), in order not to excessively increase the total thickness D ₂ while maintaining the planar area and volume, an increase in the capacity of the first dielectric film 13, the second peripheral portion the thickness d ₂ of the dielectric film 14 it is sufficient to reduce the capacity of the second dielectric film 14 is increased from the conventional structure. For example, when D ₂ = 300 nm, d ₂ ≈0.243 nm may be set. In this case, since the step is smaller than that in FIG. 2B, it is not always necessary to extend the second dielectric film 14 to the element portion (3).

As shown in FIG. 2D, in order to maintain the film thickness d ₁ of the second dielectric film 14 without increasing the overall thickness D ₂ while maintaining the plane area and the capacity. , the plane area of the second dielectric film 14, therefore, may be reduced overall diameter r _2. For example, when d ₁ = 200 nm, r ₂ ≈27.2 μm may be set, and the occupied area of the capacitor can be reduced. Here, the planar shape of the capacitor has been described as circular, but the same applies to shapes such as a square and a rectangle. Note that although the MIM capacitor mounted on the semiconductor device is described here, the capacitor may be unrelated to the semiconductor device.

  Next, a compound semiconductor device according to Example 1 of the present invention will be described with reference to FIGS. FIG. 3 is an explanatory diagram of the compound semiconductor device according to the first embodiment of the present invention, FIG. 3 (a) is a cross-sectional view of the main part, and FIG. 3 (b) is an enlarged view of the MIM capacitor. In the compound semiconductor device of Example 1 of the present invention, the MIM capacitor is provided on the semiconductor substrate via the SiN film 31 and the interlayer insulating film 36.

  The semiconductor substrate has a laminated structure in which an i-type GaN electron transit layer 23, an n-type AlGaN electron supply layer 24, and an n-type GaN cap layer 25 are sequentially laminated on a silicon substrate 21 via an AlN buffer layer 22. . An element isolation region 26 is formed to provide element formation. In this element formation region, a gate electrode 35 is provided on the n-type GaN cap layer 25, and a source electrode 29 and a drain electrode 30 are provided with the gate electrode 35 interposed therebetween, and an HEMT is formed. Forming. Note that a gate recess structure may be used as the gate structure.

  In the MIM capacitor, an HfSiO film 40 is provided as a high-k film at the center of the lower electrode 39, a peripheral lower electrode 44 is provided so as to surround the HfSiO film 40, and an SiN film 45 is formed on the peripheral lower electrode 44. Provide. After the surfaces of the HfSiO film 40 and the SiN film 45 are flush with each other, an upper electrode 50 is provided and the whole is covered with an interlayer insulating film 51. At this time, the SiN film 45 is extended to the element formation region where the HEMT is formed and used as an interlayer insulating film.

In Example 1 of the present invention, as shown in FIG. 3B, the diameter R ₁ of the HfSiO film 40 is 20 μm and the thickness d ₁ is 300 nm. Further, the entire diameter R _{2 is set} to 30 μm, and the thickness d ₂ of the SiN film 45 is set to 243 nm. With such a configuration, an MIM capacitor having a capacity of about 2 × 10 ⁻¹³ F is obtained.

Next, with reference to FIGS. 4 to 12, a manufacturing process of the compound semiconductor device of Example 1 of the present invention will be described. First, as shown in FIG. 4A, an AlN buffer layer 22 having a thickness of 200 nm is formed on a silicon substrate 21 by using a MOVPE method (metal organic chemical vapor deposition method). Subsequently, an i-type GaN electron transit layer 23 having a thickness of 1 μm, an n-type AlGaN electron supply layer 24 having a thickness of 30 nm and an Si concentration of 5 × 10 ¹⁸ cm ⁻³ , and an Si concentration of 5 nm in thickness. The 5 × 10 ¹⁸ cm ⁻³ n-type GaN cap layer 25 is sequentially grown. At this time, a two-dimensional electron gas layer is formed in the vicinity of the interface between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24.

As growth conditions at this time, when AlN is grown, a mixed gas of trimethylaluminum (TMAl) gas and ammonia (NH ₃ ) gas is used as a source gas. When growing GaN, a mixed gas of trimethylgallium (TMGa) gas and NH ₃ gas is used as a source gas. When growing AlGaN, a mixed gas of TMAl gas, TMGa gas, and NH ₃ gas is used as a source gas. The flow rate of NH ₃ gas, which is a common raw material, is about 100 sccm to 10000 sccm. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C. Further, when the n-type AlGaN electron supply layer 24 and the n-type GaN cap layer 25 are grown, silane (SiH ₄ ) gas is used as an impurity source.

  Next, as shown in FIG. 4B, argon (Ar) is ion-implanted to form an element isolation region 26, and a region surrounded by the element isolation region 26 is defined as an element formation region.

  Next, as shown in FIG. 4C, a lift-off resist pattern 27 having openings for forming source / drain electrodes is provided, and then a Ti / Al film 28 is deposited by sputtering. Here, the thickness of the Ti film is 20 nm, and the thickness of the Al film is 200 nm.

  Next, as shown in FIG. 5D, the source electrode 29 and the drain electrode 30 are formed by removing the Ti / Al film 28 deposited thereon together with the resist pattern 27 by lift-off. Next, as shown in FIG. 5E, a nitride film 31 having a thickness of 40 nm serving as a surface protective film is provided on the entire surface by plasma CVD.

Next, as shown in FIG. 5F, a resist pattern 32 having a gate opening 33 is provided, and the SiN film 25 exposed in the gate opening 33 is selectively removed by dry etching using CF ₄ .

  Subsequently, as shown in FIG. 6G, a Ni / Au film 34 is deposited by sputtering. Here, the thickness of the Ni film is 30 nm, and the thickness of the Au film is 400 nm. Next, as shown in FIG. 6H, the gate electrode 35 is formed by removing the Ni / Au film 34 deposited thereon together with the resist pattern 32 by lift-off. Next, as shown in FIG. 6I, a SiN film having a thickness of 100 nm is deposited as an interlayer insulating film 36 for protecting the element portion by using the CVD method.

  Next, as shown in FIG. 7 (j), after providing a resist pattern 37 having an opening for the lower electrode, a Ti / Pt / Au film 38 is deposited by sputtering. Here, the thickness of the Ti film is 50 nm, the thickness of the Pt film is 100 nm, and the thickness of the Au film is 50 nm.

Next, as shown in FIG. 7 (k), the lower electrode 39 is formed by removing the Ti / Pt / Au film 38 deposited thereon together with the resist pattern 37 by lift-off. Next, a 300 nm thick HfSiO film 47 is deposited by using a low pressure chemical vapor deposition method (LPCVD method). In the film forming step, using the _{(t-C 4 H 9 O} ) 4 Hf as Hf source, using _Si 2 _{H 6} as a source of Si, and _{O 2} is used as O source, using _{N 2} gas as a carrier gas To form a film.

Next, as shown in FIG. 8L, a resist pattern 41 having a diameter (R ₁ ) of 20 μm is provided, and the exposure of the HfSiO film 40 is etched to form the central portion of the capacitor dielectric film. Next, as shown in FIG. 8 (m), after removing the resist pattern 41, a new resist pattern 42 is provided, and then a Ti / Pt / Au film 43 is deposited so that the total film thickness becomes 57 nm. .

  Next, as shown in FIG. 9 (n), the peripheral lower electrode 44 is formed by removing the Ti / Pt / Au film 43 deposited thereon together with the resist pattern 42 by lift-off. Next, as shown in FIG. 9 (o), a SiN film 45 having a thickness of 243 nm is deposited by plasma CVD.

Next, as shown in FIG. 10P, a resist pattern 46 having an opening surrounding the protruding portion of the SiN film 45 is provided. Next, as shown in FIG. 10 (q), the protruding portion of the SiN film 45 is etched by dry etching using CF ₄ using the resist pattern 46 as a mask, so that the surface of the SiN film 45 is substantially the same as the upper surface of the HfSiO film 40. Try to be flush.

  Next, as shown in FIG. 11 (r), after removing the resist pattern 46, a two-layer resist pattern is newly formed by the resist pattern 47 and the resist pattern 48. At this time, the resist pattern 48 in the upper layer protrudes in the horizontal direction to form a resist pattern having a hook-shaped portion.

  Next, as shown in FIG. 11 (s), a Ti / Pt / Au film 49 is deposited on the entire surface by sputtering. Here, the thickness of the Ti film is 50 nm, the thickness of the Pt film is 100 nm, and the thickness of the Au film is 50 nm.

Next, as shown in FIG. 12 (t), the upper electrode 50 is formed by removing the Ti / Pt / Au film 49 deposited thereon together with the resist patterns 47 and 48 by lift-off. Next, as shown in FIG. 12 (u), the basic structure of the compound semiconductor device of Example 1 of the present invention is completed by depositing a SiO ₂ film to be the interlayer insulating film 51 on the entire surface by using the CVD method. . Although illustration is omitted, wiring is connected to the lower electrode 39 and the upper electrode 50 to form a predetermined circuit.

  In the first embodiment of the present invention, since the center portion of the capacitor dielectric film is formed of a high dielectric constant film, it can be formed thicker than the SiN film, and the breakdown voltage of the MIM capacitor can be improved. Can do. In addition, since the SiN film 45 serving as the peripheral capacitor dielectric film is extended to the element formation region to be a part of the interlayer insulating film, the surface step can be reduced and the coverage can be improved.

  Next, a compound semiconductor device according to Example 2 of the present invention will be described with reference to FIGS. 13 to 17. In Example 2, the peripheral electrode that compensates for the film thickness difference between the HfSiO film and the SiN film is used as the peripheral upper electrode. The basic manufacturing process and the like are the same as those in the first embodiment. FIG. 13 is an explanatory diagram of a compound semiconductor device according to a second embodiment of the present invention, FIG. 13 (a) is a cross-sectional view of the main part, and FIG. 13 (b) is an enlarged view of the MIM capacitor. In the compound semiconductor device of Example 2 of the present invention, the MIM capacitor is provided on the semiconductor substrate via the SiN film 31 and the interlayer insulating film 36.

  In the MIM capacitor of the second embodiment, an HfSiO film 40 is provided as a high-k film at the center of the lower electrode 39 and an SiN film 45 is provided so as to surround the HfSiO film 40. After the peripheral upper electrode 54 is provided on the upper surface of the SiN film 45 so that the surfaces of the HfSiO film 40 and the peripheral upper electrode 54 are flush with each other, the upper electrode 50 is provided and the whole is covered with the interlayer insulating film 51. Also at this time, the SiN film 45 is extended to the element formation region where the HEMT is formed and used as an interlayer insulating film.

Also in Example 2 of the present invention, as shown in FIG. 13B, the diameter R ₁ of the HfSiO film 40 is 20 μm and the thickness d ₁ is 300 nm. Further, the entire diameter R _{2 is set} to 30 μm, and the thickness d ₂ of the SiN film 45 is set to 243 nm. With such a configuration, an MIM capacitor having a capacity of about 2 × 10 ⁻¹³ F is obtained.

  Next, with reference to FIGS. 14 to 17, a manufacturing process of the compound semiconductor device of Example 2 of the present invention will be described. First, as shown in FIG. 14A, in the same process as the process up to FIG. 8L of the first embodiment, a thickness of 300 nm and a diameter of 20 μm are formed in the central portion of the lower electrode 39. An HfSiO film 40 is formed. Next, as shown in FIG. 14B, a SiN film 45 having a thickness of 243 nm is deposited by plasma CVD.

Next, as shown in FIG. 15C, a resist pattern 46 having an opening surrounding the protruding portion of the SiN film 45 is provided. Next, as shown in FIG. 15D, the protruding portion of the SiN film 45 is etched by dry etching using CF ₄ using the resist pattern 46 as a mask to flatten the exposed surface of the SiN film 45.

  Next, as shown in FIG. 16 (e), after removing the resist pattern 46, a new resist pattern 52 having a donut-shaped opening having a diameter between 20 μm and 30 μm is provided. A Ti / Pt / Au film 53 is deposited to 57 nm. Next, as shown in FIG. 16 (f), the peripheral upper electrode 54 is formed by removing the Ti / Pt / Au film 53 deposited thereon together with the resist pattern 52 by lift-off.

  Next, as shown in FIG. 17G, a two-layer resist pattern is newly formed by the resist pattern 55 and the resist pattern 56. At this time, the resist pattern 56 in the upper layer protrudes in the lateral direction to form a resist pattern having a hook-shaped portion. Next, a Ti / Pt / Au film 57 is deposited on the entire surface by sputtering. Here, the thickness of the Ti film is 50 nm, the thickness of the Pt film is 100 nm, and the thickness of the Au film is 50 nm.

Next, as shown in FIG. 17H, the upper electrode 58 is formed by removing the Ti / Pt / Au film 57 deposited thereon together with the resist patterns 55 and 56 by lift-off. Next, a basic structure of the compound semiconductor device of Example 2 of the present invention is completed by depositing a SiO ₂ film to be the interlayer insulating film 59 on the entire surface by using the CVD method. Although illustration is omitted, wiring is connected to the lower electrode 39 and the upper electrode 58 to form a predetermined circuit.

  Also in the second embodiment of the present invention, since the central portion of the capacitor dielectric film is formed of a high dielectric constant film, it can be formed thicker than the SiN film, and the breakdown voltage of the MIM capacitor can be improved. Can do. In addition, since the SiN film 45 serving as the peripheral capacitor dielectric film is extended to the element formation region to be a part of the interlayer insulating film, the surface step can be reduced and the coverage can be improved.

  Next, the compound semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. 18. The structure of the compound semiconductor device is the same as that of the second embodiment except that the peripheral upper electrode is formed integrally with the upper electrode. Only shown. FIG. 18 is an explanatory diagram of a compound semiconductor device according to a third embodiment of the present invention, FIG. 18 (a) is a cross-sectional view of the main part, and FIG. 18 (b) is an enlarged view of the MIM capacitor. In the compound semiconductor device of Example 3 of the present invention, the MIM capacitor is provided on the semiconductor substrate via the SiN film 31 and the interlayer insulating film 36.

  In the MIM capacitor of the second embodiment, an HfSiO film 40 is provided as a high-k film at the center of the lower electrode 39 and an SiN film 45 is provided so as to surround the HfSiO film 40. An upper electrode 60 integrally formed with the peripheral upper electrode is provided so as to cover the upper surface of the SiN film 45 and the upper surface of the HfSiO film 40. Next, the whole is covered with an interlayer insulating film 59. Also at this time, the SiN film 45 is extended to the element formation region where the HEMT is formed and used as an interlayer insulating film. When forming the upper electrode, a conductor film to be the upper electrode is formed on the entire surface, and then flattened by a CMP (Chemical Mechanical Polishing) method and processed into a circular pattern by etching.

Also in Example 3 of the present invention, as shown in FIG. 18B, the diameter R ₁ of the HfSiO film 40 is set to 20 μm and the thickness d _{1 is set} to 300 nm. Further, the entire diameter R _{2 is set} to 30 μm, and the thickness d ₂ of the SiN film 45 is set to 243 nm. With such a configuration, an MIM capacitor having a capacity of about 2 × 10 ⁻¹³ F is obtained.

  Also in the third embodiment of the present invention, since the center portion of the capacitor dielectric film is formed of a high dielectric constant film, it can be formed thicker than the case of the SiN film, and the breakdown voltage of the MIM capacitor is improved. Can do. In addition, since the SiN film 45 serving as the peripheral capacitor dielectric film is extended to the element formation region to be a part of the interlayer insulating film, the surface step can be reduced and the coverage can be improved.

  Next, the compound semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIGS. 19 to 21. The structure of the MIM capacitor is the same as that of the first embodiment except for the structure of the MIM capacitor. I will explain only. As shown in FIG. 19A, the lower electrode 39 is formed in the same process as the process up to FIG. Next, a two-layer resist pattern is formed by the resist pattern 61 and the resist pattern 62 having a donut-shaped opening having a diameter of 20 μm and a diameter of 30 μm. At this time, the resist pattern 62 in the upper layer protrudes in the horizontal direction to form a resist pattern having a hook-shaped portion. Next, a Ti / Pt / Au film 63 having a total thickness of 57 nm is deposited on the entire surface by using an inclined sputtering method. At this time, since the resist pattern 62 becomes a shadow during the inclined sputtering, tapered portions are formed at both ends of the opening.

  Next, as shown in FIG. 19B, the peripheral lower electrode 64 having a tapered portion is formed by removing the Ti / Pt / Au film 63 deposited thereon along with the resist patterns 61 and 62 by lift-off. The Next, an HfSiO film 40 having a thickness of 300 nm is deposited by CVD. Next, as shown in FIG. 19C, a resist pattern 65 having a diameter of 20 μm is provided, and the exposed portion of the HfSiO film 40 is etched.

Next, as shown in FIG. 20D, after removing the resist pattern 65, a SiN film 45 having a thickness of 243 nm is deposited by plasma CVD. Next, as shown in FIG. 20E, a resist pattern 66 having an opening surrounding the protruding portion of the SiN film 45 is provided, and the protruding portion of the SiN film 45 is formed by dry etching using CF ₄ using the resist pattern 66 as a mask. Etch. At this time, the surface of the SiN film 45 is made to be substantially flush with the upper surface of the HfSiO film 40.

  Next, as shown in FIG. 21 (f), after removing the resist pattern 66, a two-layer resist pattern is newly formed by the resist pattern 47 and the resist pattern 48. At this time, the resist pattern 48 in the upper layer protrudes in the horizontal direction to form a resist pattern having a hook-shaped portion. Next, a Ti / Pt / Au film 49 is deposited on the entire surface by sputtering. Here, the thickness of the Ti film is 50 nm, the thickness of the Pt film is 100 nm, and the thickness of the Au film is 50 nm.

  Next, as shown in FIG. 21G, the upper electrode 50 is formed by removing the Ti / Pt / Au film 49 deposited thereon together with the resist patterns 47 and 48 by lift-off.

  In Example 4 of the present invention, since the end portion of the peripheral lower electrode 64 is tapered, the change in film thickness becomes gradual as compared with the case where it changes stepwise, and the electric field at the end portion of the peripheral lower electrode 64 is reduced. Concentration can be eased. Thereby, the breakdown voltage can be further improved.

  Next, a compound semiconductor device according to Example 5 of the present invention will be described with reference to FIG. 22, which is the same as Example 4 except that the capacitor dielectric film of the MIM capacitor is formed of only a SiN film. Therefore, only the structure of the MIM capacitor is illustrated. As shown in FIG. 22, the central dielectric film having a diameter of 20 μm is formed with a SiN film 67 having a thickness of 300 nm, and the peripheral capacitor dielectric film is formed with a SiN film 45 having a thickness of 173 nm.

  In the fifth embodiment, the central portion is formed of the 300 nm SiN film 67 having a thickness 1.5 times that of the conventional capacitor. The breakdown voltage can be improved as compared with a capacitor having a conventional structure. Further, the SiN film 45 in the peripheral portion is 173 nm thinner than 200 nm in order to maintain the same capacitance with the same plane area, but there is no problem with the breakdown voltage because the peripheral portion is not easily broken. Further, since the capacitor dielectric film is formed of only the SiN film as in the conventional case, only one kind of source gas or etching gas may be used, and the manufacture becomes easy.

Here, the following supplementary notes are attached to the embodiments of the present invention including Examples 1 to 5.
(Appendix 1) A first electrode, a first dielectric film provided at the center of the first electrode, and a film smaller than the first dielectric film provided surrounding the first dielectric film A second dielectric film having a thickness and a relative dielectric constant smaller than or equal to the first dielectric film; a second dielectric film covering the first dielectric film; and a second dielectric film covering at least a part of the second dielectric film. A capacitor comprising: an electrode; and a third electrode provided between the first electrode and the second electrode.
(Supplementary note 2) The capacitor according to supplementary note 1, wherein the third electrode is in contact with the first electrode.
(Supplementary Note 3) The supplementary note 1 or the supplementary note 2, wherein the first dielectric film has a relative dielectric constant of 10.0 or more, and the second dielectric film has a relative dielectric constant of less than 10.0. Capacitor.
(Supplementary note 4) The capacitor according to Supplementary note 1 or Supplementary note 2, wherein the first dielectric film and the second dielectric film are the same dielectric film having a relative dielectric constant of less than 10.0.
(Supplementary note 5) The capacitor according to any one of supplementary notes 1 to 4, wherein the third electrode is provided between the second dielectric film and the first electrode.
(Supplementary note 6) The capacitor according to any one of supplementary notes 1 to 4, wherein the third electrode is provided between the second dielectric film and the second electrode.
(Additional remark 7) The said 3rd electrode is integrally formed with the said 2nd electrode, The capacitor of Additional remark 6 characterized by the above-mentioned.
(Supplementary note 8) The capacitor according to any one of supplementary notes 1 to 4, wherein the third electrode includes a portion whose film thickness increases as the distance from the first dielectric film increases.
(Supplementary Note 9) The dielectric film having a relative dielectric constant of 10.0 or more is HfSiO, HfSiON, HfO ₂ , Y ₂ O ₃ , HfAlON, ZrO ₂ , Hf ₃ N 4, Zr ₃ N ₄ , TiO ₂ or Ta _2. The capacitor according to any one of appendix 1 to appendix 7, wherein the capacitor is any one of O ₅ .
(Supplementary note 10) The capacitor according to any one of supplementary notes 1 to 9, wherein the dielectric film having a relative dielectric constant of less than 10.0 is either Si ₃ N ₄ or SiON.
(Supplementary Note 11) A semiconductor substrate and a capacitor provided on the semiconductor substrate, wherein the capacitor includes a first electrode, a first dielectric film provided in a central portion of the first electrode, and the capacitor A second dielectric film having a thickness smaller than the first dielectric film and surrounding the first dielectric film and having a relative dielectric constant smaller than or equal to the first dielectric film; And a second electrode covering at least a part of the second dielectric film, and a third electrode provided between the first electrode and the second electrode. A semiconductor device.
(Additional remark 12) The said 2nd dielectric film is extended on the element part provided in the said semiconductor base | substrate, The semiconductor device of Additional remark 11 characterized by the above-mentioned.
(Supplementary note 13) The semiconductor device according to supplementary note 12, wherein the element portion is at least one of a resistor, a transistor, and an inductor.
(Supplementary Note 14) A step of forming a first electrode on the insulating film, a step of providing a first dielectric film at the center of the first electrode, and the first dielectric film so as to surround the first dielectric film Providing a second dielectric film having a thickness smaller than that of the dielectric film and having a relative dielectric constant smaller than or equal to that of the first dielectric film; and covering the first dielectric film and the second dielectric film A method of manufacturing a capacitor comprising: a step of covering at least a part of the first electrode with a second electrode; and a step of providing a third electrode between the first electrode and the second electrode.
(Supplementary Note 15) A step of providing a first electrode on a semiconductor substrate via an insulating film, a step of providing a first dielectric film at the center of the first electrode, and surrounding the first dielectric film Providing a second dielectric film having a film thickness smaller than the first dielectric film and a relative dielectric constant smaller than or equal to the first dielectric film, covering the first dielectric film and A method for manufacturing a semiconductor device, comprising: a step of covering at least a part of a two-dielectric film with a second electrode; and a step of providing a third electrode between the first electrode and the second electrode.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Element part 4 Insulating film 5 Interlayer insulating film 6 Interlayer insulating film 10 Capacitor 11 1st electrode 12 3rd electrode 13 1st dielectric film 14 2nd dielectric film 15 2nd electrode 21 Silicon substrate 22 AlN buffer layer 23 i-type GaN electron transit layer 24 n-type AlGaN electron supply layer 25 n-type GaN cap layer 26 element isolation region 27 resist pattern 28 Ti / Al film 29 source electrode 30 drain electrode 31 SiN film 32 resist pattern 33 opening Part 34 Ni / Au film 35 Gate electrode 36 Interlayer insulating film 37 Resist pattern 38, 43, 49, 53, 57, 63 Ti / Pt / Au film 39 Lower electrode 40 HfSiO film 41, 65 Resist pattern 42, 52 Resist pattern 44 64 Lower peripheral electrode 45 SiN film 46, 66 Resist pattern 4 7, 55 Resist pattern 48, 56 Resist pattern 50, 58, 60 Upper electrode 51, 59 Interlayer insulating film 54 Upper peripheral electrode 61 Resist pattern 62 Resist pattern 67 SiN film 71 Underlying insulating film 72 Lower electrode 73 SiN film 74 Upper electrode 75 Breaking part 76 high-k film

Claims (10)

A first electrode;
A first dielectric film provided at the center of the first electrode;
A second dielectric film having a thickness smaller than the first dielectric film provided around the first dielectric film and a relative dielectric constant smaller than or equal to the first dielectric film;
A second electrode covering the first dielectric film and covering at least a part of the second dielectric film;
A capacitor having a third electrode provided between the first electrode and the second electrode.   The capacitor according to claim 1, wherein the third electrode is in contact with the first electrode.   The relative dielectric constant of the first dielectric film is 10.0 or more, and the relative dielectric constant of the second dielectric film is less than 10.0. Capacitor.   3. The capacitor according to claim 1, wherein the first dielectric film and the second dielectric film are the same dielectric film having a relative dielectric constant of less than 10.0. 4.   5. The capacitor according to claim 1, wherein the third electrode includes a portion whose film thickness increases as the distance from the first dielectric film increases. 6. A semiconductor substrate;
A capacitor provided on the semiconductor substrate;
The capacitor is
A first electrode;
A first dielectric film provided at the center of the first electrode;
A second dielectric film having a thickness smaller than the first dielectric film provided around the first dielectric film and a relative dielectric constant smaller than or equal to the first dielectric film;
A second electrode covering the first dielectric film and covering at least a part of the second dielectric film;
A semiconductor device comprising: a third electrode provided between the first electrode and the second electrode.   The semiconductor device according to claim 6, wherein the second dielectric film extends on an element portion provided on the semiconductor substrate.   The semiconductor device according to claim 7, wherein the element unit is at least one of a resistor, a transistor, and an inductor. Forming a first electrode on the insulating film;
Providing a first dielectric film at the center of the first electrode;
Providing a second dielectric film having a thickness smaller than the first dielectric film and a relative dielectric constant smaller than or equal to the first dielectric film so as to surround the first dielectric film;
Covering the first dielectric film and covering at least part of the second dielectric film with a second electrode;
And a step of providing a third electrode between the first electrode and the second electrode. Providing a first electrode on the semiconductor substrate via an insulating film;
Providing a first dielectric film at the center of the first electrode;
Providing a second dielectric film having a thickness smaller than the first dielectric film and a relative dielectric constant smaller than or equal to the first dielectric film so as to surround the first dielectric film;
Covering the first dielectric film and covering at least part of the second dielectric film with a second electrode;
And a step of providing a third electrode between the first electrode and the second electrode.

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