JP2017009801A - Storage type display device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage type display device and an electronic apparatus with which it is possible to shorten a time and reduce power consumption needed for writing a data signal to a pixel electrode when rewriting only some of lines.SOLUTION: The storage type display device comprises first control lines provided for n columns, second control lines provided for m rows, and a display unit consisting of n×m pixels. The display unit is provided with a pixel electrode, a counter electrode, a pixel switching element, and a pixel memory circuit. Provided for each row are a branch power supply line for supplying power to the pixel electrode, a trunk power supply line, a pixel electrode switch circuit, a power supply line switch circuit connected between the trunk power supply line and per-row branch power supply line and selecting a connection state between the trunk power supply line and per-row branch power supply line, a control circuit, and a scanning line drive circuit for outputting a signal to a second control line. The scanning drive circuit is arranged on a prescribed end side of the display unit, and the power supply line switch circuit is arranged on an end side of the display unit that is different from the prescribed end side.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a memory type display device and an electronic apparatus.

  It is known that when an electric field is applied to a dispersion system in which charged fine particles are dispersed in a liquid, the charged fine particles move (migrate) in the liquid. This phenomenon is referred to as electrophoresis. In recent years, electrophoretic display devices that display desired information (images) using this electrophoresis have generally started to spread.

  For example, Patent Document 1 discloses an electrophoretic display device including a microcapsule type electrophoretic element including a pixel electrode, a counter electrode, and a microcapsule disposed between the pixel electrode and the counter electrode. Yes. The microcapsule encloses a dispersion medium for dispersing the electrophoretic particles in the microcapsule, a plurality of white particles, and a plurality of black particles.

JP 2010-256919 A

  In the device of Patent Document 1, a memory is built in for each pixel, and a voltage to be applied to the pixel electrode is set according to the contents of the memory. Specifically, the voltage supplied to the power supply line is applied to the pixel electrode by connecting any one of the plurality of branch power supply lines and the pixel electrode according to the contents of the memory. The plurality of branch power supply lines in each row are connected to a plurality of common trunk power supply lines, and a voltage is supplied from the plurality of trunk power supply lines to the plurality of branch power supply lines in each row.

  Therefore, even when the display of only some rows is changed, the voltage necessary for the change is supplied to a plurality of trunk power supply lines, and the voltage is supplied to a plurality of branch power supply lines in all rows. Is done. As a result, in a line where the display is not changed, a complicated sequence for preventing the display from being changed is required, and the rewriting time is increased. In addition, it is necessary to rewrite the contents of the memory even in a line where the display is not changed, resulting in an increase in power consumption.

  An object of the present invention is to provide a memory-type display device and an electronic apparatus capable of realizing a reduction in time required for writing a data signal to a pixel electrode and a reduction in power consumption when rewriting only a part of rows. Is to provide.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

The memory type display device of the present invention includes a first control line provided for n columns (n is an integer of 2 or more),
a second control line provided for m (m is an integer of 2 or more) rows;
A display unit comprising a display element sandwiched between a pair of substrates, and a display unit composed of n × m pixels,
The display unit is connected to a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the display element, and the first control line and the second control line. A pixel switching element that switches an application state of power to the pixel electrode, and a pixel memory circuit connected to the pixel switching element,
A branch power line for supplying power to the pixel electrode for each row;
A trunk power supply line that is provided in common to the branch power supply line for each row and supplies power to the branch power supply line;
A pixel electrode switch circuit that switches a connection state between the branch power supply line and the pixel electrode according to the content stored in the pixel memory circuit;
A power line switch circuit connected between the trunk power line and the branch power line for each row, and selecting a connection state between the main power line and the branch power line for each row;
A control circuit that cuts off or connects the main power supply line and the branch power supply line for each row in response to the presence or absence of rewriting of the contents stored in the pixel memory circuit;
A scanning line driving circuit for outputting a signal to the second control line,
The scanning line driving circuit is disposed on a predetermined end portion side of the display portion, and the power line switch circuit is disposed on an end portion side different from the predetermined end portion of the display portion. And

  Thus, when the contents stored in the pixel memory circuit are rewritten, the branch power line and the trunk power line may be connected by the control circuit in the row corresponding to the pixel memory circuit. If the contents stored in the pixel memory circuit are not rewritten, the branch power line and the main power line may be cut off by the control circuit in the row corresponding to the pixel memory circuit. To rewrite the contents of the pixel memory circuit, the pixel switch connected to the pixel memory circuit is turned on by the second control line, and a data signal corresponding to the rewrite is sent from the first control line connected to the pixel switch. This is done by supplying. For example, when a high level data signal is written in the pixel memory circuit, the pixel electrode switch circuit connects the branch power supply line for supplying a voltage corresponding to the high level to the pixel electrode. In the row corresponding to the pixel memory circuit to be rewritten, since the branch power supply line and the trunk power supply line are connected, the voltage corresponding to the high level is supplied from the trunk power supply line to which the voltage corresponding to the high level is supplied. The voltage corresponding to the high level is supplied to the branch power supply line for supplying the voltage, the voltage corresponding to the high level is applied to the pixel electrode, and rewriting according to the contents of the pixel memory circuit is performed. When a low level data signal is written to the pixel memory circuit, the branch power supply line for supplying a voltage corresponding to the low level is connected to the pixel electrode. In the row corresponding to the pixel memory circuit to be rewritten, since the branch power supply line and the trunk power supply line are connected, the voltage corresponding to the low level is supplied from the trunk power supply line to which the voltage corresponding to the low level is supplied. A voltage corresponding to the low level is supplied to the branch power supply line for supplying the voltage, a voltage corresponding to the low level is applied to the pixel electrode, and rewriting according to the contents of the pixel memory circuit is performed. On the other hand, when the contents of the pixel memory circuit are not rewritten, the branch power supply line and the trunk power supply line are cut off in the row corresponding to the pixel memory circuit. Therefore, even when the pixel electrode switch circuit connects the branch power supply line and the pixel electrode according to the contents of the pixel memory circuit, no voltage is supplied to the branch power supply line. No voltage is applied. Therefore, the display is not changed in the row corresponding to the memory circuit. As described above, it is only necessary to connect the branch power supply line and the trunk power supply line and drive the pixel switching element by the second control line only in the row in which the contents of the pixel memory circuit are rewritten. At the same time, power consumption is reduced.

  Further, the scanning line driving circuit is disposed on a predetermined end side of the display unit, and the power line switch circuit is disposed on an end side different from the predetermined end portion of the display unit, whereby a predetermined part of the display unit is provided. The dimensions of the frame (non-display area) located on the end side and the end side different from the predetermined end can be made substantially uniform. In this case, for example, the scanning line driving circuit is arranged on one end side of the display unit, and the power line switch circuit is arranged on the other end side of the display unit, so that the frames are located on one end side and the other end side of the display unit. Can be made substantially uniform.

  The first control line is a concept including a data line and the like, and a plurality of first control lines may be provided in each column. The second control line is a concept including a scanning line and the like, and a plurality of second control lines may be provided in each row. The display element is a concept including an electrophoretic element, a liquid crystal, an electrochromic element, and the like. The pixel switching element is a concept including a transistor, a transfer gate, and the like. The pixel memory circuit is a concept including a capacitor, a latch circuit, and the like. A plurality of branch power supply lines may be provided in each row, and a plurality of trunk power supply lines may be provided corresponding to the branch power supply lines.

  In the memory type display device of the present invention, it is preferable that the scanning line driving circuit and the power line switching circuit are arranged along the row direction via the display section.

  Thereby, the dimension of the frame (non-display area | region) located in the one end side and other end side of the direction of the row | line | column of a display part can be substantially equalized.

The memory type display device of the present invention includes a first control line provided for n columns (n is an integer of 2 or more),
a second control line provided for m (m is an integer of 2 or more) rows;
A display unit comprising a display element sandwiched between a pair of substrates, and a display unit composed of n × m pixels,
The display unit is connected to a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the display element, and the first control line and the second control line. A pixel switching element that switches an application state of power to the pixel electrode, and a pixel memory circuit connected to the pixel switching element,
A branch power line for supplying power to the pixel electrode for each row;
A trunk power supply line that is provided in common to the branch power supply line for each row and supplies power to the branch power supply line;
A pixel electrode switch circuit that switches a connection state between the branch power supply line and the pixel electrode according to the content stored in the pixel memory circuit;
A power line switch circuit connected between the trunk power line and the branch power line, and having a plurality of unit power line switch circuits for selecting a connection state between the trunk power line and the branch power line;
A control circuit that shuts off or connects the trunk power line and the branch power line in response to whether or not the contents stored in the pixel memory circuit are rewritten,
The unit power line switch circuits are respectively disposed on one end side and the other end side in the row direction of the display unit, and the unit power line switch circuits disposed on the one end side and the other end side are: The branch power supply lines are connected to the same row.

  Thereby, similarly to the above, the rewriting time is shortened and the power consumption is reduced.

  The unit power line switch circuits are arranged on one end side and the other end side in the row direction of the display unit, respectively, and the unit power line switch circuits arranged on the one end side and the other end side are arranged in the same row. Since it is connected to the power supply line, display unevenness in the row direction of the display portion can be eliminated or reduced.

The memory type display device of the present invention includes a first control line provided for n columns (n is an integer of 2 or more),
a second control line provided for m (m is an integer of 2 or more) rows;
A display unit comprising a display element sandwiched between a pair of substrates, and a display unit composed of n × m pixels,
The display unit is connected to a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the display element, and the first control line and the second control line. A pixel switching element that switches an application state of power to the pixel electrode, and a pixel memory circuit connected to the pixel switching element,
A branch power line for supplying power to the pixel electrode for each row;
A trunk power supply line that is provided in common to the branch power supply line for each row and supplies power to the branch power supply line;
A pixel electrode switch circuit that switches a connection state between the branch power supply line and the pixel electrode according to the content stored in the pixel memory circuit;
A power line switch circuit connected between the trunk power line and the branch power line, and having a plurality of unit power line switch circuits for selecting a connection state between the trunk power line and the branch power line;
A control circuit that shuts off or connects the trunk power line and the branch power line in response to whether or not the contents stored in the pixel memory circuit are rewritten,
The unit power supply line switch circuit is disposed on one end side and the other end side in the row direction of the display unit, and one unit power supply line switch circuit is provided for one branch power supply line. And

  Thereby, similarly to the above, the rewriting time is shortened and the power consumption is reduced.

  In addition, since the unit power line switch circuits are arranged on one end side and the other end side in the row direction of the display unit, the direction of display unevenness in the row direction of the display unit is the row arranged on the one end side. The direction is opposite to the row arranged on the other end side, and the display unevenness in the row direction of the display portion is canceled or reduced.

  In the memory-type display device of the present invention, it is preferable that the unit power line switch circuits are alternately arranged on one end side and the other end side in the row direction of the display unit.

  Thereby, the direction of the display unevenness in the direction of the row of the display unit is reversed in every line, and the display unevenness in the direction of the row of the display unit is offset or reduced.

In the memory-type display device of the present invention, the power line switch circuit is connected between the main power line and the branch power line for each row, and the main power line and the branch power line for each row are connected. Select each connection status,
It is preferable that the control circuit cuts off or connects the trunk power supply line and the branch power supply line for each row in accordance with whether or not the contents stored in the pixel memory circuit are rewritten.
Thereby, each pixel can be individually controlled.

In the memory-type display device of the present invention, the power line switch circuit is connected between the trunk power line and the branch power line for each of a plurality of rows, and the trunk power line and the branch power line for each of a plurality of rows. Select the connection status with
It is preferable that the control circuit cuts off or connects the main power supply line and the branch power supply line for each of a plurality of rows in accordance with whether or not the contents stored in the pixel memory circuit are rewritten.

  Thereby, the configuration of the power line switch circuit can be simplified, that is, the scale of the power line switch circuit can be reduced. Thereby, power consumption can be reduced and the size of the outer frame (non-display area) of the display unit can be reduced.

The memory type display device of the present invention includes a first control line provided for n columns (n is an integer of 2 or more),
a second control line provided for m (m is an integer of 2 or more) rows;
A display unit comprising a display element sandwiched between a pair of substrates, and a display unit composed of n × m pixels,
The display unit is connected to a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the display element, and the first control line and the second control line. A pixel switching element that switches an application state of power to the pixel electrode, and a pixel memory circuit connected to the pixel switching element,
A branch power line for supplying power to the pixel electrode for each row;
A trunk power supply line that is provided in common to the branch power supply line for each row and supplies power to the branch power supply line;
A pixel electrode switch circuit that switches a connection state between the branch power supply line and the pixel electrode according to the content stored in the pixel memory circuit;
A power line switch circuit connected between the trunk power line and the branch power line for each of a plurality of rows, and selecting a connection state between the trunk power line and the branch power line for each of a plurality of rows;
And a control circuit that cuts off or connects the main power supply line and the branch power supply line for every plurality of rows in accordance with whether or not the contents stored in the pixel memory circuit are rewritten.

  Thereby, similarly to the above, the rewriting time is shortened and the power consumption is reduced.

  Further, since the power supply line switch circuit is configured to select the connection state between the trunk power supply line and the branch power supply line for each of the plurality of rows, the configuration of the power supply line switch circuit can be simplified, that is, The scale of the power line switch circuit can be reduced. Thereby, power consumption can be reduced and the size of the outer frame (non-display area) of the display unit can be reduced.

In the memory type display device of the present invention, a first power line connected to the high potential power terminal of the pixel memory circuit;
A second power line connected to the low potential power terminal of the pixel memory circuit;
A first common power line to which the first power line is connected;
A second common power line to which the second power line is connected,
It is preferable that at least one of the first common power supply line and the second common power supply line is shared by the two pixels adjacent to each other in the row direction.

  Thereby, the pixel pitch in the row direction can be reduced, high definition can be achieved, and the circuit configuration can be simplified.

  In the memory-type display device of the present invention, it is preferable that the storage type display device further includes a connection circuit that connects the branch power supply line that is cut off with respect to the trunk power supply line to a power supply line connected to the common electrode.

  As a result, in a row where the contents of the pixel memory circuit are not rewritten, the voltage applied to the common electrode is applied to the pixel electrode via the branch power supply line. Therefore, the pixel electrode and the common electrode have the same potential, and the display is not changed.

  In the memory type display device of the present invention, it is preferable that the pixel memory circuit is a capacitor.

  Thus, the connection state between the branch power supply line and the pixel electrode is switched by the pixel electrode switch circuit in accordance with the voltage accumulated in the capacitor.

  In the memory type display device of the present invention, it is preferable that the pixel memory circuit includes a latch circuit.

  Thereby, the connection state between the branch power supply line and the pixel electrode is switched by the pixel electrode switch circuit according to the voltage written in the latch circuit.

  In the memory-type display device of the present invention, it is preferable that the power line switch circuit includes a transfer gate.

  Thereby, the voltage applied to the trunk power supply line is reliably supplied to the branch power supply line by the transfer gate having a low connection resistance.

  The memory type display device of the present invention includes a power line memory circuit that is connected to the power line switch circuit and determines a driving state of the power line switch circuit, and a reset circuit that resets the contents of the power line memory circuit. It is preferable.

  As a result, the power supply line switch circuit is turned on or off based on the contents written in the power supply line memory circuit. That is, the connection state between the trunk power supply line and the branch power supply line is determined by the contents written in the power supply line memory circuit. When changing the display, the contents of all power line memory circuits are reset by a reset circuit as an initial setting. Therefore, at the time of initial setting, all the trunk power supply lines and branch power supply lines are cut off, and the branch power supply lines and trunks corresponding to the pixel memory circuits whose contents are rewritten according to the contents written in the power supply line memory circuit. The power line is connected.

  In the memory type display device of the present invention, the connection state between the power line memory circuit and the power line selection signal line that is connected to the second control line in the reset circuit and supplies a voltage to be written to the power line memory circuit is switched. A memory switching element, and a gate enable circuit that shuts off the pixel switching element and the second control line when the memory switching element connects the power line memory circuit and the power line selection signal line. It is preferable to comprise.

  Thus, when resetting the power line memory circuit, a voltage for turning on the memory switching element is supplied from the second control line, and the power line selection signal line and the power line memory circuit are connected, The voltage supplied to the power line selection signal line is written into the power line memory circuit. Further, when the power supply line selection signal line and the power supply line memory circuit are connected, the gate enable circuit blocks the pixel switching element and the second control line. Therefore, when the power supply line memory circuit is reset, even if the voltage supplied to the second control line fluctuates, the pixel switching element is not affected.

An electronic apparatus according to the present invention includes the memory-type display device according to the present invention.
Thereby, in the electronic device, even when the display of only a part of the rows is changed, the rewriting time is shortened and the power consumption is reduced. The electronic device is a concept including a tablet, an electronic book, a smartphone, and the like.

1 is a block diagram showing a main configuration of a memory type display device according to a first embodiment of the present invention. It is a figure which shows the structural example of a pixel circuit. It is sectional drawing of a display part. It is a block diagram of a microcapsule. It is a figure explaining operation | movement of a microcapsule. It is a figure explaining operation | movement of a microcapsule. It is a figure which shows one structural example of a data line drive circuit. It is a figure explaining the partial line which performs rewriting. It is a timing chart concerning rewriting display of a partial line. It is a figure which shows the structural example of the pixel circuit which concerns on 2nd Embodiment. It is a figure which shows the structural example of the pixel circuit which concerns on 3rd Embodiment. It is a figure which shows the structural example of the pixel circuit which concerns on 3rd Embodiment. It is a figure which shows the structural example of the pixel circuit which concerns on 3rd Embodiment. It is a block diagram which shows the main structures of the memory | storage type display apparatus which concerns on a modification. It is a figure which shows the structural example of the pixel circuit which concerns on a modification. It is a figure which shows the structural example of the pixel circuit which concerns on a modification. It is a figure which shows the structural example of the pixel circuit which concerns on a modification. It is a figure which shows the structural example of the pixel circuit which concerns on a modification. It is a block diagram which shows the main structures of the memory | storage type display apparatus which concerns on 4th Embodiment of this invention. It is a block diagram which shows the main structures of the memory type display apparatus which concerns on 5th Embodiment of this invention. It is a block diagram which shows the main structures of the memory type display apparatus which concerns on 6th Embodiment of this invention. It is a pattern layout figure which shows the main structures of the memory type display apparatus which concerns on 7th Embodiment of this invention. It is a pattern layout figure which shows the main structures of the memory type display apparatus which concerns on 7th Embodiment of this invention. It is a pattern layout figure which shows the main structures of the memory type display apparatus which concerns on 8th Embodiment of this invention. It is a pattern layout figure which shows the main structures of the memory type display apparatus which concerns on 8th Embodiment of this invention. It is a pattern layout figure which shows the main structures of the memory | storage type display apparatus which concerns on 9th Embodiment of this invention. It is a pattern layout figure which shows the main structures of the memory | storage type display apparatus which concerns on 9th Embodiment of this invention. It is a perspective view of an electronic device (information terminal). It is a perspective view of an electronic device (electronic paper). It is a block diagram which shows the main structures of the memory type display apparatus which concerns on a comparative example. It is a figure which shows the structural example of the pixel circuit which concerns on a comparative example. It is a timing chart concerning the rewriting display of the partial line concerning a comparative example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, a memory type display device and an electronic apparatus according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

<First Embodiment>
The first embodiment of the present invention will be described below.

  FIG. 1 is a diagram showing a main configuration of an electrophoretic display device 100 as an example of a memory type display device according to the first embodiment of the present invention.

  In the following, for convenience of explanation, as shown in FIG. 1, two axes orthogonal to each other are defined as an X axis and a Y axis (the same applies to other drawings). In addition, directions parallel to the X axis are also referred to as “X direction” and “row direction”, and directions parallel to the Y axis are also referred to as “Y direction” and “column direction”. That is, the X direction and the row direction have the same meaning, and the Y direction and the column direction have the same meaning.

  As shown in FIG. 1, the electrophoretic display device 100 includes an electrophoretic panel 10 and a control circuit 20.

  The electrophoretic panel 10 includes a display unit 30 in which a plurality of pixel circuits P are arranged, a drive unit 40 that drives each pixel circuit P, and a branch power supply line selection circuit 80. The drive unit 40 includes a scanning line drive circuit 42 and a data line drive circuit 44.

  The control circuit 20 comprehensively controls each part of the electrophoresis panel 10 based on a video signal, a synchronization signal, and the like supplied from the host device.

  The display unit 30 includes m scanning lines 32 extending in the X direction as an example of second control lines, and n extending in the Y direction as an example of the first control lines and intersecting the scanning lines 32. Data lines 34 are formed (m and n are integers of 2 or more). The plurality of pixel circuits P are arranged at intersections of the scanning lines 32 and the data lines 34 and arranged in a matrix of m rows × n columns.

  FIG. 2 is a diagram illustrating a configuration example of the pixel circuit P. In FIG. 2, only one pixel circuit (pixel) P located in the j-th column (1 ≦ j ≦ n) of the i-th row (1 ≦ i ≦ m) is illustrated. As shown in the figure, the pixel circuit P includes an electrophoretic element 50, a selection switch Ts, a memory circuit 25, and a switch circuit 35.

  The selection switch Ts as an example of the pixel switching element is configured by an N-MOS (Negative Metal Oxide Semiconductor). A scanning line 32 is connected to the gate portion of the selection switch Ts, a data line 34 is connected to the source side, and a memory circuit 25 is connected to the drain side. The selection switch Ts connects the data line 34 and the memory circuit 25 to connect the data line 34 from the data line driving circuit 44 during a period in which the scanning signal is input from the scanning line driving circuit 42 via the scanning line 32. This is used to input a data signal input via the memory circuit 25 to the memory circuit 25.

  The memory circuit 25 as an example of the pixel memory circuit is a latch circuit, and includes two P-MOSs (Positive Metal Oxide Semiconductors) 25p1 and 25p2 and two N-MOSs 25n1 and 25n2. The first power supply line 13 is connected to the source side of the P-MOSs 25p1 and 25p2, and the second power supply line 14 is connected to the source side of the N-MOSs 25n1 and 25n2. Therefore, the source sides of the P-MOS 25 p 1 and the P-MOS 25 p 2 are high potential power terminals of the memory circuit 25, and the source sides of the N-MOS 25 n 1 and N-MOS 25 n 2 are low potential power terminals of the memory circuit 25.

  The switch circuit 35 as an example of the pixel electrode switch circuit includes a first transfer gate 36 and a second transfer gate 37. The first transfer gate 36 includes a P-MOS 36p and an N-MOS 36n. The second transfer gate 37 includes a P-MOS 37p and an N-MOS 37n.

  The source side of the first transfer gate 36 is connected to the first branch power supply line 63, and the source side of the second transfer gate 37 is connected to the second branch power supply line 64. The drain sides of the transfer gates 36 and 37 are connected to the pixel electrode 51.

  The memory circuit 25 includes an input terminal N1 connected to the drain side of the selection switch Ts, and a first output terminal N2 and a second output terminal N3 connected to the switch circuit 35.

  The gate portion of the P-MOS 25p1 and the gate portion of the N-MOS 25n1 of the memory circuit 25 function as the input terminal N1 of the memory circuit 25. The input terminal N1 is connected to the drain side of the selection switch Ts and is also connected to the first output terminal N2 of the memory circuit 25 (the drain side of the P-MOS 25p2 and the drain side of the N-MOS 25n2).

  Further, the first output terminal N 2 is connected to the gate portion of the P-MOS 36 p of the first transfer gate 36 and the gate portion of the N-MOS 37 n of the second transfer gate 37.

  The gate portion of the P-MOS 25p2 and the gate portion of the N-MOS 25n2 of the memory circuit 25 function as the second output terminal N3 of the memory circuit 25.

  The second output terminal N3 is connected to the drain side of the P-MOS 25p1 and the drain side of the N-MOS 25n1, and the gate portion of the N-MOS 36n of the first transfer gate 36 and the P of the second transfer gate 37. -It is connected to the gate part of the MOS 37p.

  The memory circuit 25 holds the data signal sent from the selection switch Ts and is used to input the data signal to the switch circuit 35.

  The switch circuit 35 functions as a selector that selectively selects one of the first and second branch power supply lines 63 and 64 based on the data signal input from the memory circuit 25 and connects to the pixel electrode 51. . At this time, only one of the first and second transfer gates 36 and 37 operates according to the level of the data signal.

  Specifically, when a low level (L) is input to the input terminal N1 of the memory circuit 25 as a data signal, a low level (L) is output from the first output terminal N2. Of the transistors connected to the terminal N2 (input terminal N1), the P-MOS 36p operates, and the N-MOS 36n connected to the second output terminal N3 operates to drive the transfer gate 36. Therefore, the first branch power line 63 and the pixel electrode 51 are electrically connected.

  On the other hand, when a high level (H) is input as a data signal to the input terminal N1 of the memory circuit 25, a high level (H) is output from the first output terminal N2, so that the first output terminal N2 (input Among the transistors connected to the terminal N1), the N-MOS 37n operates, and the P-MOS 37p connected to the second output terminal N3 operates to drive the transfer gate 37. Therefore, the second branch power supply line 64 and the pixel electrode 51 are electrically connected.

  Then, the first branch power supply line 63 or the second branch power supply line 64 is electrically connected to the pixel electrode 51 through the operated transfer gate, and a voltage is applied to the pixel electrode 51.

  In addition, the memory circuit 25 can hold the data signal input via the selection switch Ts as a voltage as described above, and holds the state of the switch circuit 35 without performing a refresh operation at regular intervals. be able to. Therefore, the voltage of the pixel electrode 51 can be held by the function of the memory circuit 25. In addition, since a plurality of output terminals for outputting different signals can be provided, appropriate control in accordance with the configuration of the switch circuit 35 is possible.

  As illustrated in FIG. 3, the electrophoretic element 50 includes a pixel electrode 51 and a common electrode 52 facing each other, and a plurality of microcapsules 53 disposed between the pixel electrode 51 and the common electrode 52. In the present embodiment, the common electrode 52 side is the observation side electrode. The common electrode 52 is also referred to as a counter electrode because it is an electrode facing the pixel electrode 51, but in the present embodiment, the common electrode 52 will be described as a common electrode.

  An electrophoretic element 50 as an example of a display element includes a plurality of microcapsules 53. The electrophoretic element 50 is fixed between the element substrate 28 and the counter substrate 29 using an adhesive layer 31. That is, the adhesive layer 31 is formed between the electrophoretic element 50 and both the substrates 28 and 29.

  The adhesive layer 31 on the element substrate 28 side is necessary for bonding to the surface of the pixel electrode 51, but the adhesive layer 31 on the counter substrate 29 side is not essential. In this case, the common electrode 52, the plurality of microcapsules 53, and the adhesive layer 31 on the counter substrate 29 side are built in a consistent manufacturing process and then handled as an electrophoretic sheet with respect to the counter substrate 29. In this case, the reason why the adhesive layer 31 is necessary is that only the adhesive layer 31 on the element substrate 28 side is assumed.

  The element substrate 28 is a substrate made of, for example, glass or plastic. A pixel electrode 51 is formed on the element substrate 28, and the pixel electrode 51 is formed in a rectangular shape for each pixel circuit P. Although not shown, the scanning lines 32, the data lines 34, and the first lines shown in FIGS. 1 and 2 are provided on the region between the pixel electrodes 51 and the lower surface of the pixel electrode 51 (the layer on the element substrate 28 side). A branch power supply line 63, a second branch power supply line 64, a first power supply line 13, a second power supply line 14, a selection switch Ts, a memory circuit 25, a switch circuit 35, and the like are formed.

  Since the counter substrate 29 is on the image display side, the counter substrate 29 is a substrate having translucency such as glass. The common electrode 52 formed on the counter substrate 29 is made of a material having translucency and conductivity. For example, MgAg (magnesium silver), ITO (indium tin oxide), IZO (indium zinc). Oxide) or the like.

  The electrophoretic element 50 is generally formed in advance on the counter substrate 29 side and is handled as an electrophoretic sheet including the adhesive layer 31. A protective release paper is attached to the adhesive layer 31 side.

  In the manufacturing process, the display unit 30 is formed by attaching the electrophoretic sheet from which the release paper is peeled off to the separately manufactured element substrate 28 on which the pixel electrode 51 and the circuit are formed. Yes. For this reason, in a general configuration, the adhesive layer 31 exists only on the pixel electrode 51 side.

  FIG. 4 is a configuration diagram of the microcapsule 53. The microcapsule 53 is formed of a polymer resin having a particle size of, for example, about 50 μm and having translucency such as acrylic resin such as polymethyl methacrylate and polyethyl methacrylate, urea resin, and gum arabic. The microcapsule 53 is sandwiched between the common electrode 52 and the pixel electrode 51 described above, and a plurality of microcapsules 53 are arranged vertically and horizontally in one pixel. A binder (not shown) for fixing the microcapsule 53 is provided so as to fill the periphery of the microcapsule 53.

  The microcapsule 53 is a spherical body, and inside thereof, a dispersion medium 54 that is a solvent for dispersing the electrophoretic particles, a plurality of white particles (electrophoretic particles) 55 as the electrophoretic particles, and a plurality of black particles Charged fine particles with (electrophoretic particles) 56 are enclosed. In this embodiment, the white particles are positively charged and the black particles are negatively charged. The present invention is not limited to such an embodiment, and white particles may be negatively charged and black particles may be positively charged.

  The dispersion medium 54 is a liquid that disperses the white particles 55 and the black particles 56 in the microcapsules 53.

  Examples of the dispersion medium 54 include alcohol solvents such as water, methanol, ethanol, isopropanol, butanol, octanol, and methyl cellosolve, various esters such as ethyl acetate and butyl acetate, and ketones such as acetone, methyl ethyl ketone, and methyl isobutyl ketone. , Aliphatic hydrocarbons such as pentane, hexane and octane, alicyclic hydrocarbons such as cyclohexane and methylcyclohexane, benzene, toluene, xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene , Aromatic hydrocarbons such as benzenes having a long chain alkyl group such as undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene, etc., and methylene chloride, chloroform, carbon tetrachloride, 1,2-dichloroethane, etc. Gen hydrocarbons include those obtained by blending a surfactant or the like alone or a mixture thereof such as carboxylic acid salts, or various other oils.

  The white particles 55 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are positively charged, for example.

  The black particles 56 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are negatively charged, for example.

  For this reason, the white particles 55 and the black particles 56 can be migrated by an electric field generated by a potential difference between the pixel electrode 51 and the common electrode 52 in the dispersion medium 54.

  These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, charge control agents composed of particles such as compounds, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.

  The white particles 55 and the black particles 56 are covered with ions in the solvent, and an ion layer 57 is formed on the surfaces of these particles. An electric double layer is formed between the charged white particles 55 and black particles 56 and the ion layer 57. Generally, it is known that charged fine particles such as white particles 55 and black particles 56 hardly react to an electric field and hardly migrate even when an electric field having a frequency of 10 kHz or more is applied. It is known that ions around charged fine particles migrate much in response to an electric field when an electric field having a frequency of 10 kHz or higher is applied because the particle diameter is much smaller than that of charged fine particles.

  5 and 6 are diagrams illustrating the operation of the microcapsule 53. FIG. Here, an ideal case where the ion layer 57 is not formed will be described as an example.

  In the relationship between the pixel electrode 51 and the common electrode 52, when the pixel electrode 51 is set to a low potential and the common electrode 52 is set to a high potential, the white particles 55 that are positively charged are generated in the microcapsule 53 by the electric field generated thereby. Migrates to the 51 side. On the other hand, the negatively charged black particles 56 migrate to the common electrode 52 side in the microcapsule 53. As a result, the black particles 56 gather on the display surface side (the common electrode 52 side) in the microcapsule 53. When the pixel circuit P is viewed from the common electrode 52 side on the observation side, the color of the black particles 56 is increased. “Black” is recognized.

  On the other hand, in the relationship between the pixel electrode 51 and the common electrode 52, when the pixel electrode 51 is set to a high potential and the common electrode 52 is set to a low potential, the black particles 56 that are negatively charged are generated in the microcapsule 53 by the electric field generated thereby. It migrates to the pixel electrode 51 side. On the other hand, the positively charged white particles 55 migrate to the common electrode 52 side in the microcapsule 53. As a result, the white particles 55 are collected on the display surface side (the common electrode 52 side) of the microcapsule 53. When the pixel circuit P is viewed from the common electrode 52 side, which is the observation side, the color of the white particles 55 is obtained. A certain “white” is recognized.

  In this way, the voltage between the pixel electrode 51 and the common electrode 52 is set to a value corresponding to the gradation (brightness) to be displayed, and the electrophoretic particles are migrated, thereby achieving a desired gradation display. Can be obtained.

  Note that when the application of voltage between the pixel electrode 51 and the common electrode 52 is stopped, the electric field disappears, and thus the electrophoretic particles are stopped by the viscous resistance of the solvent. Since the electrophoretic particles can remain at a predetermined position for a long time due to the viscous resistance of the solvent, the display state when the predetermined voltage is applied is maintained even after the application of the predetermined voltage is stopped. It has the property to obtain (memory).

  Here, the description has been made with two particle types of white and black, but one particle type or three or more particle types may be used, and the color of the particles is not limited to white and black, and may be any combination of colored particles. May be.

  In addition to the configuration in which particles and a dispersion medium are enclosed in a microcapsule, for example, a partition wall that is divided into fine spaces is formed on the element substrate 28 with an epoxy resin or the like, and the particles and the dispersion medium are filled in the partition. A structure in which the counter substrate 29 on which the electrode 52 is formed is bonded to the top of the partition wall with the adhesive layer 31 may be employed.

Returning to FIG.
The scanning line drive circuit 42 and the branch power supply line selection circuit 80 are connected to one end side and the other end side in the X direction (row direction) (left and right direction in FIG. 1) of the display unit 30 via the display unit 30. Has been placed. That is, the scanning line driving circuit 42 is disposed on the right side of the display unit 30 in FIG. 1, and the branch power supply line selection circuit 80 is disposed on the opposite side, that is, on the left side of the display unit 30 in FIG. . Thereby, the dimension of the frame (non-display area | region) located in the right and left of the display part 30 can be made substantially equal. In the configuration shown in the figure, the scanning line driving circuit 42 is arranged on the right side and the branch power supply line selection circuit 80 is arranged on the left side. However, the configuration is not limited to this. For example, the scanning line driving circuit 42 is arranged on the left side. The branch power supply line selection circuit 80 may be arranged on the right side. Alternatively, for example, the branch power supply line selection circuit 80 is disposed on one side of the display unit 30 configured in a square shape, and the scanning line driving circuit 42 is disposed on any one of the three sides other than the one side. Good. That is, the scanning line driving circuit 42 is disposed on a predetermined end side of the display unit 30, and the branch power line selection circuit 80 is disposed on an end side different from the predetermined end of the display unit 30. Good.

  The scanning line drive circuit 42 outputs scanning signals (signals) GW [1] to GW [m] to each scanning line 32. Here, the scanning signal output to the i-th scanning line 32 is denoted as GW [i]. The scanning line driving circuit 42 sets the scanning signal GW [i] to the active level (high level) for a predetermined period, so that the selection switches Ts of the n pixel circuits P belonging to the i-th row are turned on all at once. Change. The transition of the scanning signal GW [i] to the high level means selection of the scanning line 32 in the i-th row. The scanning line driving circuit 42 normally selects the scanning lines 32 one by one and applies a high level voltage. However, if necessary, all the scanning lines 32 are simultaneously selected to apply the high level voltage. It has a function to apply. Further, the scanning line driving circuit 42 has a function of sequentially selecting only specific scanning lines 32 and applying a high level voltage.

  The data line driving circuit 44 generates data signals (signals) Vx [1] to Vx [n] corresponding to one row (n) of pixel circuits P selected by the scanning line driving circuit 42 to generate each data line. 34. Here, the data signal output to the data line 34 in the j-th column is denoted as Vx [j].

  Here, it is assumed that the data signal Vx is supplied to the pixel circuit P located in the i-th row and the j-th column. In this case, the data line driving circuit 44 is synchronized with the timing at which the scanning line driving circuit 42 selects the i-th scanning line 32 (“specified gradation”) for the pixel circuit P. ) Is output to the data line 34 in the j-th column as a data signal Vx [j]. The data line driving circuit 44 also has a function of setting all the data lines 34 to high impedance as necessary.

  The data signal Vx [j] is supplied to the input terminal N1 of the memory circuit 25 of the pixel circuit P via the selection switch Ts (see FIG. 2) in the on state, and the content of the memory circuit 25 is set to the designated gradation. Programmed. Thereby, the voltage between both ends of the electrophoretic element 50 of the pixel circuit P (the voltage between the pixel electrode 51 and the common electrode 52) is set to a value corresponding to the designated gradation of the pixel circuit P.

  In this way, the drive unit 40 selects the i-th scanning line 32, and the data signal Vx [j having a magnitude corresponding to the designated gradation of the pixel circuit P located in the i-th row and the j-th column. ] Is output to the data line 34 in the j-th column. This operation is referred to as a writing operation of the data signal Vx [j] for the pixel circuit P.

  FIG. 7 is a diagram illustrating a configuration example of the data line driving circuit 44. As shown in the figure, the data line driving circuit 44 includes a shift register 44-1, a first latch circuit 44-2, and a second latch circuit 44-3.

  The shift register 44-1 shifts the start pulse SP according to the clock signal CK supplied from the control circuit 20, and shifts from the first stage corresponding to the first column data line 34 to the nth column data line 34. Sampling signals s1 to sn are sequentially output up to the corresponding n-th stage.

  The first latch circuit 44-2 sequentially takes in the video signal VIDEO for a period corresponding to the sampling signals s1 to sn from the stage where the sampling signals s1 to sn are input, and outputs them to the second latch circuit 44-3. The video signal VIDEO is supplied from the control circuit 20 to the first latch circuit 44-2.

  The second latch circuit 44-3 receives the video signal VIDEO (data signals Vx [1] to Vx [n]) supplied from each stage of the first latch circuit 44-2 at the timing when the latch pulse LAT becomes active. The data signals Vx [1] to Vx [n] for one row are simultaneously supplied from the first column to the data line 34 in the nth column.

Specifically, under the control of the control circuit 20, for example, after the data signals Vx [1] to Vx [n] for one row corresponding to the i-th row are taken from the video signal VIDEO into the first latch circuit 44-2, The latch pulse LAT is activated, and the data signals Vx [1] to Vx [n] for one row corresponding to the i row are simultaneously supplied to the data lines 34 from the first column to the nth column. In synchronization with this, the scanning line driving circuit 42 sets the scanning signal Gw [i] to an active level.
As a result, the memory circuits 25 of all the pixel circuits P on the i row are programmed to the designated gradation.

The configuration and operation of the branch power supply line selection circuit 80 will be described below.
As shown in FIG. 1, the branch power supply line selection circuit 80 as an example of the power supply line switch circuit includes a selection switch Tra whose gate portion is connected to each scanning line 32 and a drain side of each selection switch Tra. A capacitor C1, a first branch power supply line selection switch Trb whose drain side is connected to each first branch power supply line 63, and a second branch power supply line selection switch Trc whose drain side is connected to each second branch power supply line 64. I have.

  The selection switch Tra as an example of the memory switching element is configured by an N-MOS. A scanning line 32 is provided at the gate of the selection switch Tra, a signal line 60 as an example of a power supply line selection signal line on the source side, and a capacitor C1 and an example of the first branch power supply line as an example of a power supply line memory circuit on the drain side. The gates of the switch Trb and the second branch power supply line selection switch Trc are connected to each other. The selection switch Tra is used to set the voltage of the capacitor C1 to the voltage VSEL of the signal line 60 by connecting the signal line 60 and the capacitor C1.

  The first branch power line selection switch Trb is composed of an N-MOS. A capacitor C1 is connected to the gate portion of the first branch power supply line selection switch Trb, the first trunk power supply line 61 is connected to the source side, and the source side of the first transfer gate 36 is connected to the drain side. The first branch power supply line selection switch Trb connects the first trunk power supply line 61 and the first branch power supply line 63 to thereby change the voltage of the pixel electrode 51 through the first transfer gate 36 to the first trunk power supply line. 61 is used to set the voltage VEPS0.

  The second branch power line selection switch Trc is configured by an N-MOS (Negative Metal Oxide Semiconductor). A capacitor C1 is connected to the gate portion of the second branch power supply line selection switch Trc, the second trunk power supply line 62 is connected to the source side, and the source side of the second transfer gate 37 is connected to the drain side. The second branch power supply line selection switch Trc connects the second trunk power supply line 62 and the second branch power supply line 64 to thereby change the voltage of the pixel electrode 51 through the second transfer gate 37. Used to set 62 voltage VEPS1.

  Next, a driving method of the electrophoretic display device 100 according to the present embodiment will be described with reference to the drawings. FIG. 9 is a timing chart according to the driving method of the electrophoretic display device 100. This timing chart includes an initial setting period, a program period, a driving period, and a display holding period. In the following description, as shown in FIG. 8, the letter “A” of the alphabet is displayed in a part of the display section 30 (hereinafter referred to as a partial line). A case where the display is changed to the letter “B” of the alphabet will be described. That is, in this example, the display in the lines other than the partial line may be any display and is not changed. Here, of the two voltages used in the present embodiment, a low voltage is referred to as a voltage (VL) with a reference (0 V) as a reference, and a high voltage is referred to as a voltage VH.

[Initial setting period]
As shown in FIG. 9, in the initial setting period ST1, the control circuit 20 applies the voltage VL as the voltage VSEL of the signal line 60 and controls the scanning line driving circuit 42 to apply the voltage VH to all the scanning lines 32. Supply. As a result, all the selection switches Tra are turned on, and the voltage VSEL of the signal line 60, that is, the voltage VL is applied to all the capacitors C1, and the voltage of the capacitor C1 becomes the voltage VL. In FIG. 9, the numbers and characters in parentheses in C <b> 1 [1] to C <b> 1 [m] indicate the number C of the capacitor C <b> 1 connected to the scanning line 32. Therefore, for example, C1 [1] to C1 [m] indicate from the capacitor C1 connected to the first scanning line 32 to the capacitor C1 connected to the mth scanning line 32. ing. When the voltages of the capacitors C1 in all rows become the voltage VL, the first branch power supply line selection switch Trb and the second branch power supply line selection switch Trc are both turned off, and the first trunk power supply line 61 and the first The branch power supply line 63 is electrically disconnected, and the second trunk power supply line 62 and the second branch power supply line 64 are electrically disconnected. The initial setting period ST1 is a very short period of 1 millisecond or less.

[Program period]
When changing the display, it is necessary to rewrite the contents of the memory circuit 25 as a pixel memory circuit. Therefore, the control circuit 20 determines whether or not the content is rewritten in the memory circuit 25, and identifies a row corresponding to the memory circuit 25 having the content rewrite as a partial row. Then, as shown in FIG. 9, in the program period ST2, the control circuit 20 applies the voltage VH as the voltage VSEL of the signal line 60 and controls the scanning line driving circuit 42 to control the partial row. A high level voltage VH is sequentially supplied to only the scanning line 32 line by line. In this example, the description will be made on the assumption that the first line to the j-th line are partial lines. That is, it is assumed that the lines displaying the letters “A” and “B” of the alphabet shown in FIG. 8 are the lines from the first line to the j-th line. Further, the control circuit 20 controls the scanning line driving circuit 42 so that the voltage VL is continuously supplied to the rows other than the partial rows, that is, the scanning lines 32 from the (j + 1) th row to the mth row in this example. Further, the control circuit 20 controls the data line driving circuit 44 to sequentially supply the voltage VH to the scanning lines 32 of the partial rows one row at a time. In synchronization with this, a data signal corresponding to an image to be displayed in each pixel circuit P is output to the data line 34 corresponding to each pixel circuit P in the partial row. That is, the data line driving circuit 44 supplies the data signal of the voltage VL to the data line 34 corresponding to the pixel circuit P that displays black in order to display the letter “B” of the alphabet, and the alphabet “B”. The data signal of voltage VH is supplied to the data line 34 corresponding to the pixel circuit P that displays white in order to display the character.

  By sequentially supplying the voltage VH to the scanning lines 32 of the partial rows from the first row to the j-th row, the selection switch Ts in the pixel circuit P connected to the scanning lines 32 from the first row to the j-th row. Is turned on, and the voltage of the data line 34 connected to the selection switch Ts is written in the memory circuit 25 connected to the selection switch Ts. That is, in the pixel circuit P that displays black, the data signal of voltage VL is written in the memory circuit 25, and in the pixel circuit P that displays white, the data signal of voltage VH is written in the memory circuit 25.

  As a result, when a data signal having a voltage VL is written to the memory circuit 25, the first transfer gate 36 among the transfer gates connected to the memory circuit 25 is turned on, and the second transfer gate 37 is turned on. Is turned off. Accordingly, the first branch power supply line 63 becomes conductive with the pixel electrode 51 through the first transfer gate 36. Further, when the voltage VH is written in the memory circuit 25, the second transfer gate 37 among the transfer gates connected to the memory circuit 25 is turned on, and the first transfer gate 36 is turned off. Become. Accordingly, the second branch power supply line 64 becomes conductive with the pixel electrode 51 through the second transfer gate 37.

  The control circuit 20 connects the first trunk power supply line and the second trunk power supply line to the first branch power supply line and the first branch power supply line for the partial row, and the first row for the rows other than the partial row. The trunk power line and the second trunk power line are disconnected from the first branch power line and the first branch power line. That is, when the voltage VH is supplied to the scanning line 32 of the partial row, the selection switch Tra connected to the scanning line 32 is turned on, and the voltage VSEL of the signal line 60 connected to the selection switch Tra That is, the voltage VH is applied to the capacitor C1 connected to the selection switch Tra. As a result, the voltage of the capacitor C1 becomes the voltage VH. In this example, the voltages of the capacitors C1 [1] to C1 [j] are the voltage VH. Accordingly, the first branch power supply line selection switch Trb and the second branch power supply line selection switch Trc connected to the capacitors C1 [1] to C1 [j] are both turned on, and the first trunk power supply line 61 and the first The branch power supply line 63 is electrically connected, and the second trunk power supply line 62 and the second branch power supply line 64 are electrically connected. Thus, the first branch power supply line 63 and the second branch power supply line 64 corresponding to the partial row are electrically connected to the first trunk power supply line 61 and the second trunk power supply line 62, respectively. Become.

  On the other hand, since the voltage VL is supplied to the scanning lines 32 other than the partial rows, the selection switch Tra connected to the scanning line 32 is turned off, and the voltage of the capacitor C1 connected to the selection switch Tra is the voltage. Maintain VL. In this example, the voltages of the capacitors C1 [j + 1] to C1 [m] maintain the voltage VL. Accordingly, the first branch power supply line selection switch Trb and the second branch power supply line selection switch Trc connected to the capacitors C1 [j + 1] to C1 [m] are both turned off, and the first trunk power supply line 61 and the first The branch power supply line 63 is electrically disconnected, and the second trunk power supply line 62 and the second branch power supply line 64 are electrically disconnected. In this way, the first branch power supply line 63 and the second branch power supply line 64 corresponding to the rows other than the partial row are electrically cut off by the first trunk power supply line 61 and the second trunk power supply line 62, respectively. Will be.

[Driving period]
Next, as shown in FIG. 9, in the driving period ST3, the control circuit 20 applies the voltage VL as the voltage VEPS0 of the first trunk power supply line 61 and applies the voltage VEPH as the voltage VEPS1 of the second trunk power supply line 62. To do. Here, the voltage VEPH is lower than the voltage VH. This is because the branch power supply line selection switches Trb and Trc can be turned on by lowering the gate voltage of the branch power supply line selection switches Trb and Trc by the threshold voltage of the branch power supply line selection switches Trb and Trc. . As a result, the first branch power line 63 and the second branch power line 64 corresponding to the partial row are electrically connected to the first trunk power line 61 and the second trunk power line 62, respectively. The voltage VEP0 [1] to voltage VEP0 [j] of the first branch power supply line 63 from the row to the jth row becomes the voltage VL, and the voltage VEP1 [1] to voltage VEP1 [j] of the second branch power supply line 64 is the voltage VEPH. It becomes. Note that the numbers and characters in parentheses when the voltage VEP0 [1] to the voltage VEP0 [j] and the voltage VEP1 [1] to the voltage VEP1 [j] are described are the first branch power supply line in the first row. 63 and the voltage of the second branch power supply line 64. As described above, in the pixel circuit P that displays black, the voltage VEP0 of the first branch power supply line 63 is applied to the pixel electrode 51 via the first transfer gate 36, so that the voltage VL is applied to the pixel electrode 51. Applied. In the pixel circuit P that displays white, the voltage VEP1 of the second branch power supply line 64 is applied to the pixel electrode 51 via the second transfer gate 37, and therefore the voltage VEPH is applied to the pixel electrode 51. .

  Further, in the driving period ST3, a pulse signal that repeats the voltage VL and the voltage VEPH as shown in FIG. 9 at a predetermined cycle is input to the common electrode 52 of each pixel circuit P by the control circuit 20. This driving method is referred to as “common swing driving” in the present application. The common swing drive is defined as a drive method in which a pulse signal that repeats the voltage VEPH and the voltage VL is applied to the common electrode 52 for at least one period in the drive period. According to the common swing drive, the black particles and the white particles can be more reliably migrated to a desired electrode, so that the contrast can be increased. That is, in the pixel circuit P that displays black, since the voltage VL is applied to the pixel electrode 51, the potential difference between the pixel electrode 51 and the common electrode 52 is not generated during the period when the voltage Vcom of the common electrode 52 is the voltage VL. The black particles 56 and the white particles 55 of the electrophoretic element 50 do not migrate. However, during the period when the voltage Vcom of the common electrode 52 is the voltage VEPH, a large potential difference is generated between the pixel electrode 51 and the common electrode 52, and the negatively charged black particles 56 of the electrophoretic element 50 migrate to the common electrode 52 side. The positively charged white particles 55 migrate to the pixel electrode 51 side. As a result, black is displayed in the pixel circuit P.

  Further, in the pixel circuit P that displays white, since the voltage VEPH is applied to the pixel electrode 51, there is no potential difference between the pixel electrode 51 and the common electrode 52 during the period when the voltage Vcom of the common electrode 52 is the voltage VEPH. The black particles 56 and the white particles 55 of the electrophoretic element 50 do not migrate. However, during the period when the voltage Vcom of the common electrode 52 is the voltage VL, a large potential difference is generated between the pixel electrode 51 and the common electrode 52, and the negatively charged black particles 56 of the electrophoretic element 50 migrate to the pixel electrode 51 side. The positively charged white particles 55 migrate to the common electrode 52 side. As a result, white is displayed in the pixel circuit P.

  On the other hand, the first branch power line 63 and the second branch power line 64 corresponding to the rows other than the partial row are electrically cut off by the first trunk power line 61 and the second trunk power line 62, respectively. Since the pixel electrode 51 that is in a high impedance state and thus in a conductive state with either the first branch power supply line 63 or the second branch power supply line 64 is also in a high impedance state, the pixel electrode 51 and the common electrode 52 are not connected. An electric field is not generated, and migration of the black particles 56 and the white particles 55 of the electrophoretic element 50 does not occur. Therefore, the display in the lines other than the partial lines does not change.

[Display retention period]
Next, as shown in FIG. 9, in the display holding period ST4, the control circuit 20 performs the voltage Vcom of the common electrode 52, the voltage VEP0 of the first branch power line 63, and the second until the next display content is rewritten. All the voltages VEP1 of the branch power lines 64 are set to the voltage VL. Therefore, in the display holding period ST4, the voltage VL is applied to both the pixel electrode 51 and the common electrode 52 of the pixel circuit P corresponding to the partial row, and no potential difference is generated. In this case, the display of the partial row is held by the holding performance of the electrophoretic element 50. Since the first branch power supply line 63 and the second branch power supply line 64 corresponding to the rows other than the partial row remain electrically cut off by the first trunk power supply line 61 and the second trunk power supply line 62, respectively, display holding is performed. The display does not change during the period ST4.

  As described above, in the present invention, the first branch power line 63 and the second branch power line 64 are switched by the switch circuit 35 as the pixel electrode switch circuit in accordance with the contents stored in the memory circuit 25 as the pixel memory circuit. And the connection state of the pixel electrode 51 are switched. Further, the branch power supply line selection circuit 80 as a power supply line switch circuit changes the connection state between the first trunk power supply line 61 and the second trunk power supply line and the first branch power supply line 63 and the second branch power supply line 64 for each row. Select each one. The branch power supply line selection circuit 80 as the power supply line switch circuit is controlled by the control circuit 20. In other words, the control circuit 20 responds to whether or not the contents stored in the memory circuit 25 as the pixel memory circuit are rewritten, so that the first trunk power supply line 61, the second trunk power supply line 62, the first branch power supply line 63, and the first branch power supply line 63 The two-branch power line 64 is cut off or connected for each row. Specifically, in the partial row in which the content stored in the memory circuit 25 as the pixel memory circuit is rewritten, the selection switch Tra is turned on and the first trunk power supply line 61 and the second trunk power supply line 62 are The first branch power supply line 63 and the second branch power supply line 64 are connected, and the display according to the data signal is changed in the partial row. As a result, the display of the letter “A” of the alphabet on the display unit 30 is changed to the display of the letter “B” of the alphabet. However, in the rows other than the partial row in which the contents stored in the memory circuit 25 as the pixel memory circuit are not rewritten, the selection switch Tra is turned off and the first trunk power line 61 and the second trunk power line 62, the first branch power supply line 63 and the second branch power supply line 64 are cut off, and no voltage is applied to the pixel circuit P in the row, so that the display does not change.

(Comparative example)
Next, the comparative example compared with embodiment of this invention is demonstrated. The comparative example shown in FIG. 30 is a diagram showing a main configuration of a conventional electrophoretic display device 500. As shown in the figure, the electrophoretic display device 500 includes an electrophoretic panel 510 and a control circuit 20. The configuration of the electrophoresis panel 510 is substantially the same as the configuration of the electrophoresis panel 10 of the first embodiment, but the electrophoresis panel 510 is not provided with the branch power supply line selection circuit 80. That is, in the electrophoresis panel 510, the first trunk power supply line 61 and the first branch power supply line 63, and the second trunk power supply line 62 and the second branch power supply line 64 are always electrically connected.

  FIG. 31 is a diagram illustrating a configuration example of the pixel circuit P of the comparative example. As shown in FIG. 31, the configuration of the pixel circuit P of the comparative example is the same as the configuration example of the pixel circuit P of the first embodiment, and common points with the pixel circuit P of the first embodiment shown in FIG. The same reference numerals are given.

  In the comparative example, the first trunk power supply line 61 and the first branch power supply line 63 and the second trunk power supply line 62 and the second branch power supply line 64 are always electrically connected. When the voltage VEPS0 of the first trunk power supply line 61 is set to the voltage VL and the voltage VEPS1 of the second trunk power supply line 62 is set to the voltage VEPH for rewriting, the voltage VEP0 of the first branch power supply line 63 and the second branch power supply in the partial row are set. In addition to the voltage VEP1 of the line 64, the voltage VEP0 of the first branch power supply line 63 and the voltage VEP1 of the second branch power supply line 64 in the rows other than the partial row are also the voltage VEPS0 and second voltage of the first trunk power supply line 61, respectively. The voltage VEPS1 of the main power supply line 62 is set. As a result, unlike the above-described embodiment of the present invention, a voltage is applied to the pixel electrode 51 of the pixel circuit P not only in the partial row but also in a row other than the partial row in the driving period. Therefore, in the comparative example, the data signal to be written to the memory circuit 25, the voltage VEP0 of the first branch power supply line 63, the voltage VEP1 of the second branch power supply line 64, and the like so that the display in the rows other than the partial row does not change. It is necessary to set the voltage Vcom of the common electrode 52.

  In order not to change the display in the rows other than the partial row, in the program period, the same data signal as the data signal used for the current display is written in the memory circuit 25 of the pixel circuit P in the row other than the partial row. In the driving period, it is also conceivable to maintain the current display by common swing driving as in the above-described embodiment. However, such processing increases power consumption and complicates control. Therefore, in the comparative example, when the alphabet “A” display is changed to “B” display, the pixel circuit P that continues to display white in the partial row, and the pixel circuit P in a row other than the partial row , A driving method is adopted in which the same voltage is applied to the pixel electrode 51 and the common electrode 52 so that the display is not changed without causing the black particles and the white particles of the electrophoretic element 50 to migrate. Therefore, in the comparative example, instead of directly changing the pixel circuit P displaying white in the partial row to black, the display of the partial row displaying the letter “A” of the alphabet is temporarily changed. White display. When displaying the letter “B” of the alphabet, the pixel circuit P that displays black causes a potential difference between the pixel electrode 51 and the common electrode 52, and changes from “A” to “B” in the alphabet. In the pixel circuit P that maintains the white display and the pixel circuit P in a row other than the partial row, the same voltage is applied to the pixel electrode 51 and the common electrode 52 to thereby blacken the electrophoretic element 50. The display is not changed without migration of particles and white particles.

  Hereinafter, a specific driving method of the electrophoretic display device 500 of the comparative example will be described with reference to the drawings. FIG. 32 is a timing chart according to the driving method of the electrophoretic display device 500. This timing chart includes a first program period, a first drive period, a second program period, a second drive period, and a display holding period. In the following description of the driving method, as in the embodiment of the present invention described above, the letter “A” of the alphabet is displayed in the partial line of the display unit 30, and the display in the partial line is represented by the letter “B”. The case where the character is changed to is described. Also in the comparative example, the display in the lines other than the partial line is not changed.

[First program period]
In the state in which the letter “A” of the alphabet is displayed in the partial row, the memory circuit 25 of the pixel circuit P displaying all the black “A” of the alphabet in the partial row is displayed in the first program period. The pixel circuit P other than black “A” and the memory circuits 25 of the pixel circuits P other than the partial row are programmed with the voltage VH.

[First driving period]
As shown in FIG. 32, in the first drive period ST3a, the control circuit 20 applies the voltage VEPH as the voltage VEPS0 to the first trunk power supply line 61 and applies the voltage VL as the voltage VEPS1 of the second trunk power supply line 62. . Further, the control circuit 20 applies the voltage VL as the voltage Vcom of the common electrode 52. As a result, the voltage VEPH is applied to the pixel electrode 51 of the pixel circuit P displaying black. Accordingly, the negatively charged black particles 56 of the electrophoretic element 50 migrate to the pixel electrode 51 side, and the positively charged white particles 55 migrate to the common electrode 52 side. As a result, in the pixel circuit P, the display changes from black to white.

  On the other hand, the voltage VL is applied to the pixel circuit 51 displaying the white color and the pixel electrode 51 of the pixel circuit P in a row other than the partial row. Accordingly, the pixel electrode 51 and the common electrode 52 have the same potential, and the black particles 56 and the white particles 55 of the electrophoretic element 50 do not migrate and the display does not change. By performing the driving as described above, the display of the partial rows is all white and the display of the rows other than the partial rows is not changed.

[Second program period]
In the second program period ST2b, the memory circuit 25 of the pixel circuit P displaying the black “B” of the alphabet in the partial row is programmed with the voltage VL, and the non-black pixel circuit P of “B” The memory circuits 25 of all the pixel circuits P other than the partial rows are programmed with the voltage VH.

[Second driving period]
As shown in FIG. 32, in the second drive period ST3b, the control circuit 20 applies the voltage VL as the voltage VEPS0 to the first trunk power supply line 61 and applies the voltage VEPH as the voltage VEPS1 to the second trunk power supply line 62. . Further, the control circuit 20 applies the voltage VEPH as the voltage Vcom to the common electrode 52. As a result, the voltage VL is applied to the pixel electrode 51 of the pixel circuit P at the position corresponding to black. Accordingly, the positively charged white particles 55 of the electrophoretic element 50 migrate to the pixel electrode 51 side, and the negatively charged black particles 56 migrate to the common electrode 52 side. As a result, in the pixel circuit P, the display changes from white to black.

  On the other hand, the voltage VEPH is applied to the pixel circuit P in the position corresponding to white and the pixel electrode 51 of the pixel circuit P in a row other than the partial row. Accordingly, the pixel electrode 51 and the common electrode 52 have the same potential, and the black particles 56 and the white particles 55 of the electrophoretic element 50 do not migrate and the display does not change. By performing the driving as described above, the display of the partial lines is changed from the white state to the state of displaying the letter “B” of the alphabet, and the display of the lines other than the partial lines is not changed. In this way, the display of only the partial line is rewritten.

  As is clear from the comparison between the comparative example as described above and the first embodiment of the present invention, when the display of the partial row is rewritten, in the comparative example, the first trunk power supply line 61 and the first branch power supply are used. Since the line 63 and the second trunk power supply line 62 and the second branch power supply line 64 are always electrically connected in all rows, programming and drive control in all the pixel circuits P are required. As a result, there is a need for a process in which the partial rows are once displayed in white and the display of the pixel circuits P that continue to display white and the pixel circuits P in rows other than the partial row are not changed. Two drive periods are required. On the other hand, in the first embodiment of the present invention, when rewriting the display of the partial row, the first branch power supply line 63 and the second branch power supply line 64 in the rows other than the partial row are Since the first main power line 61 and the second main power line 62 are electrically disconnected from each other, the current display in the partial row is displayed next without affecting the display of the rows other than the partial row. Can be directly rewritten, and one program period and one drive period are completed. In the first embodiment, an initial setting period is required, but there is no problem because the initial setting period is an extremely short period. Therefore, according to the present invention, the display rewriting time of the partial row can be greatly shortened. As a result, the present invention can also achieve a significant reduction in power consumption.

Second Embodiment
FIG. 10 is a diagram illustrating a configuration of the pixel circuit P and the branch power supply line selection circuit 80 for one row in the electrophoretic display device of the second embodiment.

  Hereinafter, although the second embodiment will be described, the description will focus on the differences from the above-described embodiment, and the description of the same matters will be omitted.

  As shown in FIG. 10, a branch power line selection circuit 80 as an example of a power line switch circuit includes transfer gates 90 and 91, a memory circuit 92 as an example of a power line memory circuit, and an example of a memory switching element. You may comprise by the selection switch Tra. In this example, a memory circuit 92 is provided in place of the capacitor C1, and transfer gates 90 and 91 are used in place of the first branch power supply line selection switch Trb and the second branch power supply line selection switch Trc. In this circuit, when the voltage VSEL of the signal line 60 is the voltage VH, the voltage VH is written into the memory circuit 92, the transfer gates 90 and 91 are turned on, and the first branch power supply line 63 and the second branch power supply line 64 are connected. It is connected to the first trunk power line 61 and the second trunk power line 62. However, when the voltage VSEL of the signal line 60 is the voltage VL, the voltage VL is written into the memory circuit 92, the transfer gates 90 and 91 are turned off, and the first branch power supply line 63 and the second branch power supply line 64 are in the first state. It is cut off from the trunk power line 61 and the second trunk power line 62.

  Even in such a configuration, the first trunk power supply line 61 and the second trunk power supply line 62 are connected to the first branch power supply line 63 and the second branch power supply line 64 only in the partial row to be rewritten, and other than the partial row. In the row, the first trunk power line 61 and the second trunk power line 62 and the first branch power line 63 and the second branch power line 64 can be cut off.

With this configuration, the upper limit of the voltage VEH supplied to the first trunk power supply line 61 and the second trunk power supply line 62 can be raised to the voltage VH. Then, the electric field strength between the pixel electrode 51 and the common electrode 52 can be increased, and higher-speed rewriting becomes possible.
In other words, since the voltage VH can be lowered, the power consumption can be reduced.

  Also according to this embodiment, the same effects as those of the first embodiment described above can be exhibited.

<Third Embodiment>
FIG. 11 is a diagram showing a configuration of each pixel circuit P and branch power supply line selection circuit 80 for one row in the electrophoretic display device of the third embodiment.

  In the following, the third embodiment will be described. The description will focus on the differences from the above-described embodiment, and the description of the same matters will be omitted.

  In the first embodiment, the first branch power supply line 63 and the second branch power supply line 64 in the rows other than the partial rows are disconnected from the first trunk power supply line 61 and the second trunk power supply line 62. In this configuration, it is also conceivable that some voltage is applied to the pixel electrode 51 of the pixel circuit P in a row other than the partial row due to a leak current or the like to change the display color of the pixel.

  Therefore, in the present embodiment, the first branch power supply line 63 and the second branch power supply line 64 in the rows other than the partial rows are disconnected from the first trunk power supply line 61 and the second trunk power supply line 62, and at the same time, A branch power supply line connection circuit 81 is provided as an example of a connection circuit connected to the power supply line 65.

  For example, as shown in FIG. 11, the branch power supply line connection circuit 81 is configured by resistors 93 and 94 and connected to the power supply line 65 of the common electrode 52. With this configuration, the first branch power supply line 63 and the second branch power supply line 64 in the rows other than the partial row are disconnected from the first trunk power supply line 61 and the second trunk power supply line 62 and are also branched. The power line connection circuit 81 is connected to the power line 65 of the common electrode 52 via the resistors 93 and 94. Therefore, the pixel electrode 51 has the same potential as the common electrode 52, and the display in the rows other than the partial row does not change.

  Since the current consumption increases in the circuit configuration shown in FIG. 11, the branch power supply line connection circuit 81 may be configured as shown in FIG. In the example shown in FIG. 12, the branch power supply line connection circuit 81 includes a selection switch Trd, a first branch power supply line connection switch Tre, and a second branch power supply line connection switch Trf. In this example, a signal line 66 to which a voltage obtained by inverting the voltage VSEL of the signal line 60 is applied by an inverter 95 is provided.

  The selection switch Trd is composed of an N-MOS. A gate portion of the selection switch Trd is connected to the scanning line 32, a signal line 66 is connected to the source side, a capacitor C2 is connected to the drain side, and gate portions of the connection switches Tre and Trf are connected. The selection switch Trd is used to set the voltage of the capacitor C2 to the voltage of the signal line 66, that is, the voltage obtained by inverting the voltage VSEL of the signal line 60 by connecting the signal line 66 and the capacitor C2.

  The connection switches Tre and Trf are composed of N-MOS. A capacitor C2 is connected to the gates of the connection switches Tre and Trf, a power supply line 65 of the common electrode 52 is connected to the source side, and a first branch power supply line 63 and a second branch power supply line 64 are connected to the drain side. The connection switches Tre and Trf are connected to the first branch power line 63 and the second branch power line 63 when the first branch power line 63 and the second branch power line 64 are disconnected from the first trunk power line 61 and the second trunk power line 62. This is used to connect the branch power line 64 and the power line 65 of the common electrode 52. With this configuration, the first branch power supply line 63 and the second branch power supply line 64 in the rows other than the partial row are disconnected from the first trunk power supply line 61 and the second trunk power supply line 62 and are also branched. The power supply line connection circuit 81 connects to the power supply line 65 of the common electrode 52. Therefore, the pixel electrode 51 has the same potential as the common electrode 52, and the display in the rows other than the partial row does not change.

  Further, as in the second embodiment, when the branch power line selection circuit 80 includes transfer gates 90 and 91, a memory circuit 92, and a selection switch Tra, as shown in FIG. The branch power supply line connection circuit 81 may be configured by transfer gates 96 and 97. In this circuit, when the voltage VSEL of the signal line 60 is the voltage VH, the voltage VH is written into the memory circuit 92, the transfer gates 90 and 91 are turned on, and the first branch power supply line 63 and the second branch power supply line 64 are connected. It is connected to the first trunk power line 61 and the second trunk power line 62. However, when the voltage VSEL of the signal line 60 is the voltage VL, the voltage VL is written into the memory circuit 92, the transfer gates 90 and 91 are turned off, and the first branch power supply line 63 and the second branch power supply line 64 are in the first state. It is cut off from the trunk power line 61 and the second trunk power line 62. However, when the voltage VL is written to the memory circuit 92, the transfer gates 96 and 97 are turned on, and the first branch power line 63 and the second branch power line 64 are connected to the power line 65 of the common electrode 52. The Therefore, the pixel electrode 51 has the same potential as the common electrode 52, and the display in the rows other than the partial row does not change.

  As described above, according to the present embodiment, the first branch power supply line 63 and the second branch power supply line 64 in rows other than the partial row are disconnected from the first trunk power supply line 61 and the second trunk power supply line 62. Even in this case, the first power supply line 61 and the second power supply line 62 are connected to the power supply line 65 of the common electrode 52 by the branch power supply line connection circuit 81, so that the pixel electrode 51 and the common electrode 52 have the same potential, A change in display in a line other than the partial line can be more reliably prevented.

  Also according to this embodiment, the same effects as those of the first embodiment described above can be exhibited.

<Modification>
Hereinafter, although a modification is demonstrated, it demonstrates centering around difference with embodiment mentioned above, and abbreviate | omits the description about the same matter.

(Modification 1)
In the first embodiment described above, the voltage VSEL of the signal line 60 is set to the voltage VL in the initial setting period, all the scanning lines 32 are selected by the scanning line driving circuit 42, and the capacitors C1 in each row are reset to the voltage VL. doing. At this time, the selection switches Ts in all the pixel circuits are turned on, and the input / output terminals of the memory circuits 25 of all the pixel circuits P in the same column are electrically connected to the source side of the selection switch Ts. Depending on the contents of the memory circuit 25, unnecessary current consumption may occur.

  In order to avoid this, the capacitors C1 in all rows may be reset to the voltage VL with a circuit configuration as shown in FIG. That is, the source and the drain of the selection switch Trg are connected to both ends of the capacitor C1, and a reset signal of the voltage VH is input from the reset signal line 67 to the gate of the selection switch Trg. In this way, the capacitor C1 can be reset while all the scanning lines 32 are not selected by the scanning line driving circuit 42. Note that the voltage VSEL of the signal line 60 may be arbitrary. Note that a reset circuit using a selection switch Trg may be provided in the circuit of the third embodiment shown in FIGS.

  10 and 13, when the memory circuit 92 is used instead of the capacitor C1, the contents of the memory circuit 92 are reset to the voltage VL using the selection switch Trh as shown in FIG. You may make it do. In this example, the source of the selection switch Trh is connected to the input / output terminal of the memory circuit 92, the gate portion is connected to the reset signal line 67, and the drain is connected to the power supply line to which the voltage VSS is applied. Therefore, by applying the voltage VH to the reset signal line 67 during the initial setting period, the selection switch Trh is turned on, the input / output terminal of the memory circuit 92 becomes the voltage VL, and the memory circuit 92 is reset to the voltage VL. Can do.

(Modification 2)
Further, a gate enable circuit 98 by an AND circuit may be provided as shown in FIG. 16 so that the gate signal is not transmitted to the pixel circuit P side at the time of initial setting. In this example, the scanning line 32 is connected to one input of the gate enable circuit 98 and the gate enable line 68 is connected to the other input. In such a configuration, it is possible to prevent the gate signal from being transmitted to the pixel circuit P side by applying the voltage VL to the gate enable line 68 during the initial setting period. The gate enable circuit 98 may be provided in the circuit of the first embodiment shown in FIG. 2, the circuit of the third embodiment shown in FIGS. 11 to 13, and the circuit of the modification shown in FIG.

(Modification 3)
The pixel circuit P may be configured as shown in FIG. In the example of FIG. 17, data lines 34 a and 34 b to which inverted data signals are supplied are provided, and selection switches Tsa and Tsb are provided corresponding to the data lines 34 a and 34 b, respectively. Are connected to the selection switches Tsa and Tsb, respectively. The driving transistors Tdra and Tdrb are connected to the capacitors Ca and Cb. The first branch power supply line 63 and the second branch power supply line 64 are connected to the source side of the drive transistors Tdra and Tdrb, respectively, and the pixel electrode 51 is connected to the drain side.

  In addition, as shown in FIG. 18, the selection switch may be configured only by the selection switch Tsa, the capacitor Ca as the pixel memory circuit, and the drive transistor Tdra. In this case, only the first branch power supply line 63 is used, and the second branch power supply line 64 is not necessary.

<Fourth embodiment>
FIG. 19 is a block diagram showing the main configuration of a memory-type display device according to the fourth embodiment of the present invention.

  Hereinafter, the fourth embodiment will be described. The description will focus on the differences from the above-described embodiment, and the description of the same matters will be omitted.

  As shown in FIG. 19, in this embodiment, the branch power supply line selection circuit 80 includes a plurality of unit branch power supply line selection circuits (unit power supply line switch circuits) 801, and the X direction (row direction) of the display unit 30. Are arranged on one end side and the other end side.

  The unit branch power line selection circuit 801 includes a selection switch Tra, a capacitor C1, a first branch power line selection switch Trb, and a second branch power line selection switch Trc, and is connected as described in the first embodiment. The connection state between the first trunk power supply line 61 and the first branch power supply line 63 and the connection state between the second trunk power supply line 62 and the second branch power supply line 64 are selected.

  The unit branch power supply line selection circuit 801 is arranged on one end side and the other end side in the X direction of the display unit 30 in each row, and two unit branch power supplies arranged on the one end side and the other end side thereof. The line selection circuit 801 is connected to the first branch power supply line 63 and the second branch power supply line 64 in the same row.

  The signal line 60, the first trunk power supply line 61, and the second trunk power supply line 62 each diverge into two in the middle, and one of them is a unit branch power supply line selection circuit 801 disposed on the one end side. The other is connected to a unit branch power line selection circuit 801 disposed on the other end side.

  According to the present embodiment, the unit branch power supply line selection circuit 801 is arranged on one end side and the other end side in the X direction of the display unit 30 in each row. Can be eliminated or reduced.

Also according to this embodiment, the same effects as those of the first embodiment described above can be exhibited.
Note that the present embodiment can also be applied to other embodiments and modifications.

<Fifth Embodiment>
FIG. 20 is a block diagram showing the main configuration of a memory-type display apparatus according to the fifth embodiment of the present invention.

  Hereinafter, the fifth embodiment will be described. The description will focus on the differences from the first embodiment described above, and the description of the same matters will be omitted.

  As shown in FIG. 20, in this embodiment, the branch power supply line selection circuit 80 includes a plurality of unit branch power supply line selection circuits (unit power supply line switch circuits) 801, and the X direction (row direction) of the display unit 30. Are arranged on one end side and the other end side.

  The unit branch power line selection circuit 801 includes a selection switch Tra, a capacitor C1, a first branch power line selection switch Trb, and a second branch power line selection switch Trc, and is connected as described in the first embodiment. The connection state between the first trunk power supply line 61 and the first branch power supply line 63 and the connection state between the second trunk power supply line 62 and the second branch power supply line 64 are selected.

  The unit branch power line selection circuits 801 are alternately arranged on one end side and the other end side in the X direction of the display unit 30. That is, the unit branch power line selection circuit 801 is arranged every other row on one end side in the X direction of the display unit 30, every other row on the other end side, and shifted by one row with respect to the one end side. Are arranged.

  The signal line 60, the first trunk power supply line 61, and the second trunk power supply line 62 each diverge into two in the middle, and one of them is a unit branch power supply line selection circuit 801 disposed on the one end side. The other is connected to a unit branch power line selection circuit 801 disposed on the other end side.

  According to the present embodiment, the direction of display unevenness in the X direction of the display unit 30 is reversed every line, and thereby the display unevenness of the display unit 30 in the X direction is offset or reduced.

  Also according to this embodiment, the same effects as those of the first embodiment described above can be exhibited.

  In the present embodiment, the unit branch power line selection circuit 801 is alternately arranged in units of one row on the one end side and the other end side in the X direction of the display unit 30. As a configuration example in which one unit branch power supply line selection circuit 801 is arranged in one row, the unit branch power supply line selection circuits 801 may be alternately arranged in units of a plurality of rows (for example, in units of two rows). Further, the unit branch power supply line selection circuits 801 may be arranged regularly (regularly) alternately or irregularly alternately.

That is, the unit branch power supply line selection circuit 801 is disposed on one end side and the other end side in the row direction of the display unit 30, and includes one (one set) of the first branch power supply line 63 and the second branch. One power supply line 64 (one branch power supply line) may be provided.
The present embodiment can also be applied to other embodiments and modifications.

<Sixth Embodiment>
FIG. 21 is a block diagram showing the main configuration of a memory-type display device according to the sixth embodiment of the present invention.

  Hereinafter, although the sixth embodiment will be described, the description will focus on the differences from the first embodiment described above, and description of similar matters will be omitted.

  As shown in FIG. 21, in this embodiment, the branch power supply line selection circuit 80 includes a plurality of unit branch power supply line selection circuits (unit power supply line switch circuits) 801, and the X direction (row direction) of the display unit 30. It is arrange | positioned at the one end side.

  The unit branch power line selection circuit 801 includes a selection switch Tra, a capacitor C1, a first branch power line selection switch Trb, and a second branch power line selection switch Trc, and is connected as described in the first embodiment. Has been.

  In this embodiment, one unit branch power line selection circuit 801 is provided for the pixel circuits P of two adjacent rows.

  In this case, the scanning line 32 is branched into two in the middle, and one of the branched scanning lines 321 is connected to the pixel circuit P belonging to one of the two rows, and the other scanned line 323 after branching. Are connected to the pixel circuit P belonging to the other of the two rows.

  Similarly, the first branch power supply line 63 branches into two on the way, and one branched first power supply line 631 is connected to the pixel circuit P belonging to one of the two rows, and after branching. The other first branch power line 632 is connected to the pixel circuit P belonging to the other of the two rows.

  Similarly, the second branch power supply line 64 branches into two in the middle, and one second branch power supply line 641 after branching is connected to the pixel circuit P belonging to one of the two rows, and after branching. The other second branch power supply line 642 is connected to the pixel circuit P belonging to the other of the two rows.

  The unit branch power supply line selection circuit 801 indicates the connection state between the first trunk power supply line 61 and the first branch power supply lines 631 and 632 and the connection state between the second trunk power supply line 62 and the second branch power supply lines 641 and 642, respectively. select.

  Thus, in this embodiment, the branch power supply line selection circuit 80 is provided between the first trunk power supply line 61 and the first branch power supply lines 631 and 632 every two rows, and between the second trunk power supply line 62 and every two rows. Are connected to the second branch power supply lines 641 and 642, respectively, and the connection state between the first trunk power supply line 61 and the first branch power supply lines 631 and 632 every two rows, and the second trunk power supply line 62 and two rows. Each connection state with the second branch power supply lines 641 and 642 is selected. Further, the control circuit 20 responds to whether or not the contents stored in the memory circuit 25 are rewritten, and the first trunk power supply line 61 and the first branch power supply line (that is, the first branch power supply line 631) are provided every two rows. 632), the second trunk power supply line 62 and the second branch power supply line (that is, the second branch power supply lines 641 and 642) are cut off or connected.

  Note that m ′ in the scanning signals (signals) GW [1] to GW [m ′] is ½ of m in the scanning signals GW [1] to GW [m] of the first embodiment.

  According to the present embodiment, the number of unit branch power supply line selection circuits 801 can be reduced, that is, the scale of the branch power supply line selection circuit 80 can be reduced. Thereby, power consumption can be reduced and the size of the outer frame (non-display area) of the display unit 30 can be reduced.

  In addition, this embodiment is particularly effective when, for example, the position of the partial row to be rewritten and the number of rows are determined. A unit branch power line selection circuit 801 is provided.

  Also according to this embodiment, the same effects as those of the first embodiment described above can be exhibited.

In this embodiment, one unit branch power supply line selection circuit 801 is provided for the pixel circuits P for two rows. However, the present invention is not limited to this, and the pixel circuits P for three or more rows are provided. One unit branch power supply line selection circuit 801 may be provided. Further, the plurality of rows provided with one unit branch power line selection circuit 801 do not have to be adjacent to each other.
The present embodiment can also be applied to other embodiments and modifications.

<Seventh embodiment>
FIG. 22 and FIG. 23 are pattern layout diagrams showing the main configuration of the memory-type display device according to the seventh embodiment of the present invention, respectively.

  Hereinafter, although the seventh embodiment will be described, the description will focus on the differences from the above-described embodiment, and the description of the same matters will be omitted.

In the present embodiment, the pixel circuit P1 for one pixel has the configuration shown in FIG.
In addition, the first power supply line 13 of the pixel circuit P <b> 1 is connected to the first common power supply line 130, and the second power supply line 14 is connected to the second common power supply line 140. The first common power supply line 130 is connected to the high potential side of the power supply, and the second common power supply line 140 is connected to the low high potential side of the power supply or ground. Further, the first common power supply line 130 extends in the Y direction and is disposed on the left side of the pixel circuit P1 in FIG. 22, and the second common power supply line 140 extends in the Y direction, and the pixel circuit P1. Are arranged on the right side in FIG. Further, the first branch power supply line 63 and the second branch power supply line 64 each extend in the X direction and are arranged inside the pixel circuit P1 in the Y direction.

  The electrophoretic display device 100 includes the pixel circuits P1 arranged in a matrix of m rows × n columns.

  FIG. 23 shows a pixel circuit P1 of 2 rows × 2 columns. On the left side of FIG. 23, the pixel circuit P1 having the posture shown in FIG. 22 is arranged, and on the right side of FIG. , A pixel circuit P1 having the posture shown in FIG. 22 inverted in the X direction is arranged.

  Accordingly, the second common power supply line 140 can be shared by two pixel circuits P1 adjacent in the X direction, that is, two columns of pixel circuits P1.

  Although not shown, on the right side of the right pixel circuit P1 in FIG. 23, the right side pixel circuit P1 in FIG. 23 is inverted in the X direction, that is, the pixel circuit P1 in the posture shown in FIG. Is placed.

  As a result, the first common power supply line 130 can be shared by two pixel circuits P1 adjacent in the X direction, that is, two columns of pixel circuits P1.

  As described above, according to this embodiment, the first common power supply line 130 and the second common power supply line 140 can be shared by two columns of pixel circuits P1 adjacent in the X direction. The pixel pitch in the X direction can be reduced, high definition can be achieved, and the circuit configuration can be simplified.

Also according to this embodiment, the same effects as those of the first embodiment described above can be exhibited.
Note that the present embodiment can also be applied to other embodiments and modifications.

<Eighth Embodiment>
24 and 25 are pattern layout diagrams showing the main configuration of the memory-type display apparatus according to the eighth embodiment of the present invention.

  Hereinafter, the eighth embodiment will be described. The description will focus on the differences from the above-described embodiment, and the description of the same matters will be omitted.

In the present embodiment, the pixel circuit P2 for one pixel has the configuration shown in FIG.
The first power supply line 13 of the pixel circuit P <b> 2 is connected to the first common power supply line 130, and the second power supply line 14 is connected to the second common power supply line 140. The first common power supply line 130 is connected to the high potential side of the power supply, and the second common power supply line 140 is connected to the low high potential side of the power supply or ground. Further, the first common power supply line 130 extends in the Y direction and is arranged on the left side of the pixel circuit P2 in FIG. 24, and the second common power supply line 140 extends in the Y direction, and the pixel circuit P2. 24 on the right side in FIG. Further, the first branch power supply line 63 extends in the X direction and is disposed on the upper side in FIG. 24 of the pixel circuit P2. The second branch power supply line 64 extends in the X direction and is disposed inside the pixel circuit P2 in the Y direction.

  The electrophoretic display device 100 includes the pixel circuits P2 arranged in a matrix of m rows × n columns.

  FIG. 25 shows a pixel circuit P2 of 2 rows × 2 columns. In the lower left of FIG. 25, the pixel circuit P2 having the posture shown in FIG. 24 is arranged, and in the lower right of FIG. Are arranged by inverting the pixel circuit P2 in the posture shown in FIG. 24 in the X direction. 25 is arranged by inverting the pixel circuit P2 having the posture shown in FIG. 24 in the Y direction, and the pixel circuit P2 having the posture shown in FIG. Those inverted in the direction and the Y direction are arranged.

  As a result, the second common power supply line 140 can be shared by two pixel circuits P2 adjacent in the X direction, that is, two columns of pixel circuits P2. Further, the first branch power line 63 can be shared by two pixel circuits P2 adjacent in the Y direction, that is, two rows of pixel circuits P2.

  Although not shown, on the right side of the upper right pixel circuit P2 in FIG. 25, the upper right pixel circuit P2 in FIG. 25 is inverted in the X direction, that is, the pixel circuit P2 in the posture shown in FIG. Is inverted in the Y direction. On the right side of the lower right pixel circuit P2 in FIG. 25, the lower right pixel circuit P2 in FIG. 25 is inverted in the X direction. A pixel circuit P2 having an attitude shown in FIG.

  As a result, the first common power supply line 130 can be shared by two pixel circuits P2 adjacent in the X direction, that is, two columns of pixel circuits P2.

  In the present embodiment, one first branch power supply line selection switch Trb of the unit branch power supply line selection circuit 801 is provided for two rows, and the second branch power supply line selection switch Trc is provided for one row. One is provided.

  As described above, according to the present embodiment, the first common power supply line 130 and the second common power supply line 140 can be shared by two columns of pixel circuits P2 adjacent in the X direction, and the first branch The power supply line 63 can be shared by two rows of pixel circuits P2 adjacent in the Y direction. As a result, the pixel pitch in the X direction and the pixel pitch in the Y direction can be reduced, high definition can be achieved, and the circuit configuration can be simplified.

  Also according to this embodiment, the same effects as those of the first embodiment described above can be exhibited.

One of the inversion in the Y direction of the pixel circuit P2 and the inversion in the X direction of the pixel circuit P2 may be omitted.
The present embodiment can also be applied to other embodiments and modifications.

<Ninth Embodiment>
FIG. 26 and FIG. 27 are pattern layout diagrams showing main components of the memory type display device according to the ninth embodiment of the present invention, respectively.

  The ninth embodiment will be described below, but the description will focus on the differences from the above-described embodiment, and the description of the same matters will be omitted.

In the present embodiment, the pixel circuit P3 for one pixel has the configuration shown in FIG.
In addition, the first power supply line 13 of the pixel circuit P3 is connected to the first common power supply line 130, and the second power supply line 14 is connected to the second common power supply line 140. The first common power supply line 130 is connected to the high potential side of the power supply, and the second common power supply line 140 is connected to the low high potential side of the power supply or ground. In addition, the first common power supply line 130 extends in the Y direction and is arranged on the left side of the pixel circuit P3 in FIG. 26, and the second common power supply line 140 extends in the Y direction, and the pixel circuit P3. Are arranged on the right side in FIG. Further, the first branch power supply line 63 extends in the X direction and is disposed on the upper side in FIG. 26 of the pixel circuit P3. Further, the second branch power supply line 64 extends in the X direction and is disposed below the pixel circuit P3 in FIG.

  The electrophoretic display device 100 includes the pixel circuits P3 arranged in a matrix of vertical m rows × horizontal n columns.

  27 shows a pixel circuit P3 corresponding to 2 rows × 2 columns, the pixel circuit P3 having the posture shown in FIG. 26 is arranged at the upper left in FIG. 27, and the upper right in FIG. 26 are arranged by inverting the pixel circuit P3 in the posture shown in FIG. 26 in the X direction. In the lower left of FIG. 27, a pixel circuit P3 having the posture shown in FIG. 26 inverted in the Y direction is arranged. In the lower right of FIG. 27, the pixel circuit P3 having the posture shown in FIG. Those inverted in the X and Y directions are arranged.

  Thus, the second common power supply line 140 can be shared by two pixel circuits P3 adjacent in the X direction, that is, two columns of pixel circuits P3. Further, the second branch power supply line 64 can be shared by two pixel circuits P3 adjacent in the Y direction, that is, two rows of pixel circuits P3.

  Further, although not shown, on the right side of the upper right pixel circuit P3 in FIG. 27, the upper right pixel circuit P3 in FIG. 27 is inverted in the X direction, that is, the pixel circuit P3 in the posture shown in FIG. 27 is arranged on the right side of the lower right pixel circuit P3 in FIG. 27, which is an inverted version of the lower right pixel circuit P3 in FIG. 27 in the X direction, that is, the pixel circuit P3 in the posture shown in FIG. Are inverted in the Y direction.

  Thereby, the first common power supply line 130 can be shared by two pixel circuits P3 adjacent in the X direction, that is, two columns of pixel circuits P3.

  Further, although not shown, below the lower left pixel circuit P3 in FIG. 27, the lower left pixel circuit P3 in FIG. 27 is inverted in the Y direction, that is, the pixel circuit in the posture shown in FIG. P3 is arranged, and an arrangement obtained by inverting the lower right pixel circuit P3 in FIG. 27 in the Y direction is arranged below the lower right pixel circuit P3 in FIG.

  As a result, the first branch power line 63 can be shared by two pixel circuits P3 adjacent in the Y direction, that is, the pixel circuits P3 in two rows.

  In the present embodiment, one first branch power supply line selection switch Trb and second branch power supply line selection switch Trc of the unit branch power supply line selection circuit 801 are provided for two rows.

  As described above, according to the present embodiment, the first common power supply line 130 and the second common power supply line 140 can be shared by two columns of pixel circuits P3 adjacent in the X direction, and the first branch The power supply line 63 and the second branch power supply line 64 can be shared by two rows of pixel circuits P3 adjacent in the Y direction. As a result, the pixel pitch in the X direction and the pixel pitch in the Y direction can be reduced, high definition can be achieved, and the circuit configuration can be simplified.

  Also according to this embodiment, the same effects as those of the first embodiment described above can be exhibited.

One of the inversion in the Y direction of the pixel circuit P3 and the inversion in the X direction of the pixel circuit P3 may be omitted.
The present embodiment can also be applied to other embodiments and modifications.

(Application examples)
Examples of electronic devices to which the present invention is applied will be described below. 28 and 29 show the appearance of an electronic apparatus that employs the electrophoretic display device 100 exemplified above.

  FIG. 28 is a perspective view of a portable information terminal (electronic book) 310 using the electrophoretic display device 100. As shown in FIG. 28, the information terminal 310 includes an operator 312 operated by a user and an electrophoretic display device 100 that displays an image on the display unit 314. When the operator 312 is operated, the display image on the display unit 314 is changed.

  FIG. 29 is a perspective view of an electronic paper 320 using the electrophoretic display device 100. As shown in FIG. 29, the electronic paper 320 includes an electrophoretic display device 100 formed on the surface of a flexible substrate (sheet) 322.

  The electronic device to which the present invention is applied is not limited to the above examples. For example, the electrophoretic display device (memory type display device) of the present invention is adopted in various electronic devices such as a mobile phone, a clock (watch), a portable sound reproducing device, an electronic notebook, and a touch panel mounted display device. Is possible.

  Further, the display element of the present invention is not limited to the electrophoretic element, and can be applied to an electrochromic element, a liquid crystal element, and the like. Therefore, the memory-type display device of the present invention is not limited to the electrophoretic display device, but can be applied to an electrochromic display device having a memory property or a liquid crystal display device. Examples of electronic devices include various information terminals such as an information terminal using an electrochromic display device or a liquid crystal display device, a mobile phone or a watch (watch), a portable sound reproducing device, an electronic notebook, and a touch panel mounted display device. It is possible to employ the memory type display device of the present invention in such electronic equipment.

  As mentioned above, the memory type display device and the electronic apparatus according to the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit is an arbitrary configuration having the same function. Can be substituted. Moreover, other arbitrary components may be added.

  Further, the present invention may be a combination of any two or more configurations (features) of the embodiments and the modifications.

  DESCRIPTION OF SYMBOLS 10 ... Electrophoresis panel, 13 ... 1st power supply line, 14 ... 2nd power supply line, 20 ... Control circuit, 25 ... Memory circuit, 28 ... Element substrate, 29 ... Opposite substrate, 30 ... Display part, 31 ... Adhesion Agent layer, 32, 321, 323 ... scanning line, 34, 34a, 34b ... data line, 35 ... switch circuit, 36,37 ... transfer gate, 40 ... driving unit, 42 ... scanning line driving circuit, 44 ... data line driving Circuit 44-1 Shift register 44-2 First latch circuit 44-3 Second latch circuit 50 Electrophoretic element 51 Pixel electrode 52 Common electrode 53 Microcapsule 54 Dispersion medium, 55 ... white particles, 56 ... black particles, 57 ... ion layer, 60 ... signal line, 61 ... first trunk power line, 62 ... second trunk power line, 63, 631, 632 ... first branch power line 64, 641, 642 ... 2-branch power supply line, 65 ... power supply line, 66 ... signal line, 67 ... reset signal line, 68 ... gate enable line, 80 ... branch power supply line selection circuit, 81 ... branch power supply line connection circuit, 801 ... unit branch power supply line connection Circuit, 90, 91 ... Transfer gate, 92 ... Memory circuit, 93, 94 ... Resistor, 95 ... Inverter, 96, 97 ... Transfer gate, 98 ... Gate enable circuit, 100 ... Electrophoretic display device, 130 ... First Common power line 140 ... Second common power line 310 ... Information terminal 312 ... Operator 314 ... Display unit 320 ... Electronic paper 322 ... Substrate 500 ... Electrophoretic display device 510 ... Electrophoresis panel 25p1, 25p2, 36p, 37p ... P-MOS, 25n1, 25n2, 36n, 37n ... N-MOS, C1, C2, Ca, Cb ... condensate -, GW ... scanning signal, N1 ... input terminal, N2, N3 ... output terminal, P, P1, P2, P3 ... pixel circuit, s1 to sn ... sampling signal, ST1 ... initial setting period, ST2 ... program period, ST3 ... Drive period, ST4 ... display holding period, ST2b ... second program period, ST3a ... first drive period, ST3b ... second drive period, Ts ... selection switch, Tdra, Tdrb ... drive transistor, Tra ... selection switch, Trb ... first 1-branch power supply line selection switch, Trc ... 2nd branch power supply line selection switch, Trd ... selection switch, Tre ... 1st branch power supply line connection switch, Trf ... 2nd branch power supply line connection switch, Trg, Trh, Tsa, Tsb ... Select switch, Vx ... Data signal

Claims (16)

a first control line provided for n columns (n is an integer of 2 or more);
a second control line provided for m (m is an integer of 2 or more) rows;
A display unit comprising a display element sandwiched between a pair of substrates, and a display unit composed of n × m pixels,
The display unit is connected to a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the display element, and the first control line and the second control line. A pixel switching element that switches an application state of power to the pixel electrode, and a pixel memory circuit connected to the pixel switching element,
A branch power line for supplying power to the pixel electrode for each row;
A trunk power supply line that is provided in common to the branch power supply line for each row and supplies power to the branch power supply line;
A pixel electrode switch circuit that switches a connection state between the branch power supply line and the pixel electrode according to the content stored in the pixel memory circuit;
A power line switch circuit connected between the trunk power line and the branch power line for each row, and selecting a connection state between the main power line and the branch power line for each row;
A control circuit that cuts off or connects the main power supply line and the branch power supply line for each row in response to the presence or absence of rewriting of the contents stored in the pixel memory circuit;
A scanning line driving circuit for outputting a signal to the second control line,
The scanning line driving circuit is disposed on a predetermined end side of the display unit, and the power line switch circuit is disposed on an end side different from the predetermined end portion of the display unit.
A memory-type display device. The scanning line driving circuit and the power line switching circuit are arranged along the row direction via the display unit.
The memory-type display device according to claim 1. a first control line provided for n columns (n is an integer of 2 or more);
a second control line provided for m (m is an integer of 2 or more) rows;
A display unit comprising a display element sandwiched between a pair of substrates, and a display unit composed of n × m pixels,
The display unit is connected to a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the display element, and the first control line and the second control line. A pixel switching element that switches an application state of power to the pixel electrode, and a pixel memory circuit connected to the pixel switching element,
A branch power line for supplying power to the pixel electrode for each row;
A trunk power supply line that is provided in common to the branch power supply line for each row and supplies power to the branch power supply line;
A pixel electrode switch circuit that switches a connection state between the branch power supply line and the pixel electrode according to the content stored in the pixel memory circuit;
A power line switch circuit connected between the trunk power line and the branch power line, and having a plurality of unit power line switch circuits for selecting a connection state between the trunk power line and the branch power line;
A control circuit that shuts off or connects the trunk power line and the branch power line in response to whether or not the contents stored in the pixel memory circuit are rewritten,
The unit power line switch circuits are respectively disposed on one end side and the other end side in the row direction of the display unit, and the unit power line switch circuits disposed on the one end side and the other end side are: Connected to the branch power line in the same row,
A memory-type display device. a first control line provided for n columns (n is an integer of 2 or more);
a second control line provided for m (m is an integer of 2 or more) rows;
A display unit comprising a display element sandwiched between a pair of substrates, and a display unit composed of n × m pixels,
The display unit is connected to a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the display element, and the first control line and the second control line. A pixel switching element that switches an application state of power to the pixel electrode, and a pixel memory circuit connected to the pixel switching element,
A branch power line for supplying power to the pixel electrode for each row;
A trunk power supply line that is provided in common to the branch power supply line for each row and supplies power to the branch power supply line;
A pixel electrode switch circuit that switches a connection state between the branch power supply line and the pixel electrode according to the content stored in the pixel memory circuit;
A power line switch circuit connected between the trunk power line and the branch power line, and having a plurality of unit power line switch circuits for selecting a connection state between the trunk power line and the branch power line;
A control circuit that shuts off or connects the trunk power line and the branch power line in response to whether or not the contents stored in the pixel memory circuit are rewritten,
The unit power line switch circuit is disposed on one end side and the other end side in the row direction of the display unit, and one unit power line switch circuit is provided for one branch power line.
A memory-type display device. The unit power line switch circuits are alternately arranged on one end side and the other end side in the row direction of the display unit,
The memory-type display device according to claim 1, wherein the display device is a storage-type display device. The power line switch circuit is connected between the trunk power line and the branch power line for each row, respectively, and selects a connection state between the trunk power line and the branch power line for each row, respectively.
The control circuit shuts off or connects the trunk power supply line and the branch power supply line for each row in accordance with whether or not the contents stored in the pixel memory circuit are rewritten.
The memory-type display device according to claim 1, wherein The power supply line switch circuit is connected between the trunk power supply line and the branch power supply line for each of a plurality of rows, and selects a connection state between the trunk power supply line and the branch power supply line for each of a plurality of rows, respectively.
The control circuit is configured to cut off or connect the trunk power supply line and the branch power supply line for each of a plurality of rows in accordance with whether or not the content stored in the pixel memory circuit is rewritten.
The memory-type display device according to claim 1, wherein a first control line provided for n columns (n is an integer of 2 or more);
a second control line provided for m (m is an integer of 2 or more) rows;
A display unit comprising a display element sandwiched between a pair of substrates, and a display unit composed of n × m pixels,
The display unit is connected to a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the display element, and the first control line and the second control line. A pixel switching element that switches an application state of power to the pixel electrode, and a pixel memory circuit connected to the pixel switching element,
A branch power line for supplying power to the pixel electrode for each row;
A trunk power supply line that is provided in common to the branch power supply line for each row and supplies power to the branch power supply line;
A pixel electrode switch circuit that switches a connection state between the branch power supply line and the pixel electrode according to the content stored in the pixel memory circuit;
A power line switch circuit connected between the trunk power line and the branch power line for each of a plurality of rows, and selecting a connection state between the trunk power line and the branch power line for each of a plurality of rows;
A control circuit that cuts off or connects the main power supply line and the branch power supply line for every plurality of rows in response to whether or not the contents stored in the pixel memory circuit are rewritten.
A memory-type display device. A first power line connected to a high potential power terminal of the pixel memory circuit;
A second power line connected to the low potential power terminal of the pixel memory circuit;
A first common power line to which the first power line is connected;
A second common power line to which the second power line is connected,
At least one of the first common power line and the second common power line is shared by the two pixels adjacent in the row direction.
The memory-type display device according to any one of claims 1 to 8, wherein A connection circuit for connecting the branch power supply line in a cutoff state with respect to the trunk power supply line to a power supply line connected to the common electrode;
The memory-type display device according to any one of claims 1 to 9, wherein The pixel memory circuit is a capacitor;
The memory-type display device according to claim 1, wherein the memory-type display device is a display device. The pixel memory circuit includes a latch circuit;
The memory-type display device according to claim 1, wherein the memory-type display device is a display device. The power line switch circuit includes a transfer gate,
The memory-type display device according to any one of claims 1 to 12, A power line memory circuit that is connected to the power line switch circuit and determines a drive state of the power line switch circuit; and a reset circuit that resets the contents of the power line memory circuit.
The memory-type display device according to claim 1, wherein the memory-type display device is a display device. A memory switching element for switching a connection state between the power line memory circuit and a power line selection signal line that is connected to the second control line and supplies a voltage to be written to the power line memory circuit in the reset circuit; A gate enable circuit that shuts off the pixel switching element and the second control line when the power line memory circuit and the power line selection signal line are connected to each other.
The memory type display device according to claim 1, wherein the memory type display device is a memory type display device.   An electronic apparatus comprising the memory-type display device according to claim 1.

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