JP2017005501A - Electronic circuit - Google Patents

Abstract

An electronic circuit for reducing a mounting area is provided. A transistor having a control terminal connected to an input terminal Tin, a first terminal connected to a reference potential, and a second terminal connected to an output terminal Tout, and having one end connected to the control terminal A first filter circuit 12 having a first capacitor Cg having the other end connected to a reference potential, a first resistor Rg having one end connected to the node, and a first end having a first end connected to a node N2 between the input terminal and the input terminal. And a second capacitor Cgo having the other end connected to a reference potential at the other end of the resistor. A second filter circuit 14 connected in parallel with the first filter circuit between the node and a reference potential; a second resistor Rb1 having one end connected to the node and the other end connected to a bias terminal Tvg; And a third filter circuit 16 having a third resistor Rb2 having the other end connected to the reference potential at the node. [Selection] Figure 2

Description

  The present invention relates to an electronic circuit, for example, an electronic circuit including a transistor.

  For example, in the communication field, power amplifiers and low noise amplifiers that amplify signals are used. In these amplifier circuits, a bias circuit and a matching circuit are provided at the control terminal of the transistor (for example, Patent Document 1). Thereby, the amplifier circuit amplifies a signal in a desired amplification band.

JP-A-8-162859

  The amplifier circuit suppresses signals in a band other than the amplification band. In particular, when the amplification band is a high frequency band, the amplification circuit suppresses a signal having a frequency lower than that of the high frequency band. This improves the stability of the amplifier circuit in the low frequency band. In an amplifier circuit, a bias voltage at a control terminal of a transistor may be adjusted from the outside to adjust a gain or the like. However, when adjusting the bias voltage of the control terminal from the outside and obtaining stability in the low frequency band, for example, a large capacitor is used. This increases the mounting area.

  The present electronic circuit has been made in view of the above-described problems, and aims to reduce the mounting area.

  An electronic circuit according to an embodiment of the present invention includes a transistor having a control terminal connected to an input terminal, a first terminal connected to a reference potential, and a second terminal connected to an output terminal, and one end A first filter circuit having a first capacitor with the other end connected to a reference potential at a node between the control terminal and the input terminal, a first resistor having one end connected to the node, and one end connected to the node A second capacitor having a second capacitor connected to a reference potential at the other end of the first resistor, and connected in parallel with the first filter circuit between the node and the reference potential And a third filter circuit having a second resistor having one end connected to the node and the other end connected to a bias terminal, and a third resistor having one end connected to the node and the other end connected to a reference potential. To do.

  According to this electronic circuit, the mounting area can be reduced.

FIG. 1 is a circuit diagram of an electronic circuit according to Comparative Example 1. FIG. 2 is a circuit diagram of the electronic circuit according to the first embodiment. FIG. 3 is a circuit diagram of an electronic circuit according to the second embodiment.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.
The present invention includes a transistor having a control terminal connected to an input terminal, a first terminal connected to a reference potential, and a second terminal connected to an output terminal, and one end of the control terminal and the input terminal. A first filter circuit having a first capacitor whose other end is connected to a reference potential at a node between the first resistor, a first resistor having one end connected to the node, and one end being the other end of the first resistor. A second capacitor having an end connected to a reference potential, a second filter circuit connected in parallel with the first filter circuit between the node and the reference potential, and one end connected to the node And a third filter circuit having a second resistor having an end connected to a bias terminal and a third resistor having one end connected to the node and the other end connected to a reference potential. A third filter having a second resistor and a third resistor suppresses the low frequency signal. This eliminates the need for using a large capacitor between the bias terminal and the reference potential. For this reason, the mounting area can be reduced, and the band of the signal input to the bias terminal can be widened.

  The impedance of the first filter circuit in the high frequency band is lower than the impedance of the second filter circuit and the third filter circuit in the high frequency band, and the third filter in the low frequency band whose frequency is lower than the high frequency band. The impedance of the circuit is lower than the impedance of the first filter circuit and the second filter circuit in the low frequency band, and the second filter in the intermediate frequency band having a frequency lower than the high frequency band and higher than the low frequency band. The impedance of the circuit is preferably lower than the impedances of the first filter circuit and the third filter circuit in the intermediate frequency band. Thus, the first filter circuit functions as a matching circuit that matches the impedances of the input terminal and the control terminal in the high frequency band. The second filter circuit functions as a matching circuit that removes the intermediate frequency signal input to the input terminal to the reference potential. The third filter circuit functions as a matching circuit that removes the low-frequency signal input to the input terminal to the reference potential. Therefore, the stability of the electronic circuit can be improved.

  It is preferable that a distributed constant line having one end connected to the node and the other end connected in common to one end of the first capacitor and one end of the first resistor is provided. Thereby, the impedance of the input terminal and the control terminal can be matched in the high frequency band by the first filter circuit and the distributed constant line.

  Preferably, the transistor is an FET, the first terminal is a source, the second terminal is a drain, and the control terminal is a gate. Thereby, the mounting area of the amplifier circuit having the FET can be reduced.

[Comparative Example 1]
An amplifier circuit that can adjust the gate bias voltage of the FET from the outside will be described as a first comparative example. The gain of the amplifier circuit can be controlled by adjusting the gate bias voltage. For example, in a high-frequency amplifier circuit that amplifies a signal of 20 GHz or more such as a quasi-millimeter wave band or a millimeter wave band, stability in a frequency band lower than a high frequency band that is an amplification band becomes a problem.

  FIG. 1 is a circuit diagram of an electronic circuit according to Comparative Example 1. As shown in FIG. 1, the electronic circuit 110 is an amplifier circuit having an FET 10. The source of the FET 10 is electrically connected to the ground via the distributed constant line Ls. The gate is electrically connected to the input terminal Tin. The drain is electrically connected to the output terminal Tout via the distributed constant line Ld. The distributed constant lines Ls and Ld are matching circuits for the source and drain of the FET 10, respectively.

  A node N2 between the gate of the FET 10 and the input terminal Tin is electrically connected to the ground via the distributed constant line Lg and the capacitor Cg in series. A node N3 between the distributed constant line Lg and the capacitor Cg is electrically connected to the bias terminal Tvg through resistors Rg and Ro. Capacitors Cg1, Cg2, and Cg3 are respectively connected in parallel between the node between the resistors Rg and Ro and the ground. A capacitor C1 is connected in series between the input terminal Tin and the node N2. The capacitor C1 mainly functions as a DC cut capacitor.

  The electronic circuit 110 amplifies the high frequency signal input to the input terminal Tin and outputs it from the output terminal Tout. A bias voltage Vg is applied to the bias terminal Tvg. Thereby, the gate bias voltage applied to the gate of the FET 10 can be controlled.

  The capacitor Cg passes the high frequency signal input to the input terminal Tin as indicated by the arrow 22. Thereby, the distributed constant line Lg and the capacitor Cg function as a matching circuit for the high frequency signal. Therefore, the amplifier circuit can stably perform an amplification operation in a high frequency band (for example, 50 GHz or more).

  The voltage Vg applied to the bias terminal Tvg is supplied as a gate bias voltage to the gate of the FET 10 via the resistors Ro and Rg. The capacitor Cg is open for signals having a frequency lower than the high frequency band (for example, less than 50 GHz). Therefore, capacitors Cg1 to Cg3 are provided. Cg1 to Cg3 pass a signal having a frequency lower than the high frequency band as indicated by an arrow 28. Thereby, the low frequency signal inputted from the input terminal Tin can be removed to the ground. Therefore, the amplifier circuit suppresses a frequency band lower than the high frequency band (for example, less than 50 GHz). Thereby, the amplifier circuit can operate stably in a low frequency band.

  However, in order for the capacitors Cg1 to Cg3 to function for signals from near DC (Direct Current) to, for example, 50 GHz, 10 pF, 100 pF, and 0.1 μF are used as the capacitors Cg1 to Cg3, respectively. Such a large capacitor is externally attached.

The band of the gate bias voltage is limited by the time constant between the resistor Rg and the capacitor Cg or the source gate capacitance Cgs of the FET 10. Furthermore, the band of the gate bias voltage is limited by the resistor Ro and the total capacitance C _total of the capacitors Cg1 to Cg3. For example, the effective gate bias voltage band is equal to or less than f = Vg1 / (2π · Ro · C _total ).

  Thus, in Comparative Example 1, a large capacitor is used. This increases the mounting area. The band of the gate bias voltage is limited by a large capacitor.

  FIG. 2 is a circuit diagram of the electronic circuit according to the first embodiment. As shown in FIG. 2, the electronic circuit 100 includes an FET 10 and filter circuits 12, 14 and 16. A capacitor C1 is connected in series between the input terminal Tin and the node N2. The filter circuit 12 (first filter) has a capacitor Cg (first capacitor). One end of the capacitor Cg is connected to the node N2 via the distributed constant line Lg, and the other end is connected to the ground (reference potential). The filter circuit 14 (second filter circuit) has a resistor Rg (first resistor) and a capacitor Cgo (second capacitor). One end of the resistor Rg is connected to the node N2 via the distributed constant line Lg. One end of the capacitor Cgo is connected to the other end of the resistor Rg, and the other end is connected to the ground. One end of the distributed constant line Lg is connected to the node N2, and the other end is connected to the node N3. The filter circuit 16 (third filter circuit) has resistors Rb1 (second resistor) and Rb2 (third resistor). One end of the resistor Rb1 is connected to the node N1, and the other end is connected to the bias terminal Tvg. One end of the resistor Rb2 is connected to the node N1, and the other end is connected to the ground.

  The amplification band of the electronic circuit is a high frequency band. The low frequency band is a frequency band lower than the high frequency band. The intermediate frequency band is a band that is lower in frequency than the high frequency band and higher in frequency than the low frequency band. Signals in the high frequency band, the intermediate frequency band, and the low frequency band are referred to as a high frequency signal, an intermediate frequency signal, and a low frequency signal, respectively. The high frequency band is, for example, 50 GHz or more. The intermediate frequency band is, for example, 1 GHz or more and less than 50 GHz. The low frequency band is, for example, less than 1 GHz. The high frequency band, the intermediate frequency band, and the low frequency band can be arbitrarily set in addition to the above example.

  The filter circuit 12 passes the high-frequency signal most to the ground among the signals input from the input terminal Tin as indicated by the arrow 22. The filter circuit 14 passes the intermediate frequency signal to the ground most among the signals input from the input terminal Tin as indicated by an arrow 24. The filter circuit 16 passes the low-frequency signal among the signals input from the input terminal Tin as indicated by an arrow 26 to the ground.

  First, it will be described that the filter circuit 16 functions as a bias circuit. When the voltage Vg is applied to the bias terminal Tvg, a current flows from the bias terminal Tvg to the ground as indicated by an arrow 20. A voltage divided by the resistors Rb1 and Rb2 is applied to the gate of the FET 10 as a gate bias voltage. Thereby, even when the input terminal Tin becomes unloaded, it can be suppressed that the gate bias voltage becomes high. Thus, the resistors Rb1 and Rb2 function as bleeder resistors. Although resistance Rb1 and Rb2 can be set arbitrarily, in order to make it stable at a low frequency, it is preferable that the parallel resistance of resistance R12 and Rb2 is small. For example, the resistances Rb1 and Rb2 are preferably several kΩ or less.

  Next, it will be described that the filter circuits 12, 14, and 16 function as matching circuits. In the following description, the resistance values of Rg, Rb1, and Rb2 are Rg, Rb1, and Rb2, respectively, and the capacitances of capacitors Cg and Cgo are Cg and Cgo. Let f be the frequency of the signal. At this time, the impedance Z12 of the filter circuit 12 is 1 / (2π · f · Cg). The impedance Z14 of the filter circuit 14 is Rg + 1 / (2π · f · Cgo). The impedance Z16 of the filter circuit 16 is about Rb1 or Rb2.

  The filter circuit 12 and the distributed constant line Lg match the impedance of the gate of the FET 10 viewed from the node N2 and the impedance of the input terminal Tin viewed from the node N2 in the high frequency band. Thereby, a desired amplification characteristic can be obtained in a high frequency band. The filter circuits 14 and 16 respectively pass the intermediate frequency signal and the low frequency signal among the signals input to the input terminal Tin to the ground. This suppresses the amplifier circuit from becoming unstable in bands lower than the high frequency band (intermediate frequency band and low frequency band).

  In the high frequency band, the relationship between the impedances of the filter circuits 12, 14, and 16 is set to satisfy Z16 >> Z14> Z12. As a result, the impedance Z12 is mainly visible for the high-frequency signal input from the input terminal Tin. Thereby, the input impedance to the FET 10 can be matched to the high frequency signal by the distributed constant line Zg and the capacitor Cg.

  In the low frequency band, the impedance relationship is Z12, Z14 >> Z16. Thereby, the parallel resistance of the resistors Rb1 and Rb2 is mainly seen in the low frequency signal input from the input terminal Tin. The low frequency signal input to the input terminal Tin is removed by the parallel circuit of the resistors Rb1 and Rb2. Thereby, the resistor Rb1 or Rb2 functions as a stabilization circuit for the low frequency signal.

  In the intermediate frequency band, the impedance relationship is Z16 >> Z12> Z14. Thereby, the impedance Z14 is mainly visible in the intermediate frequency signal input from the input terminal Tin. Thereby, the intermediate frequency signal input to the input terminal Tin is removed, and the amplifier circuit is stabilized. The resistance Rg is, for example, 10 to 100Ω.

  According to the first embodiment, the filter circuit 16 has a function of a control circuit that removes a low frequency signal input from the input terminal Tin and a function of a bias circuit that applies a gate bias voltage to the gate. Thereby, a mounting area can be reduced. The filter circuit 16 removes the low-frequency signal using the resistors Rb1 and Rb2. Further, a filter circuit 14 is provided to remove intermediate frequency signals that cannot be removed by the filter circuit 12. Since the filter circuit 14 does not need to remove the low-frequency signal, the capacitor Cgo can be reduced.

  In this way, a band having a frequency lower than that of the high frequency band is divided into a low frequency band and an intermediate frequency band. The low frequency signal input from the input terminal Tin is removed by the filter circuit 16 that does not use a capacitor. The intermediate frequency signal that cannot be removed by the filter circuit 16 is removed by the filter circuit 14 having the capacitor Cgo. Thereby, the large capacitors Cg1 to Cg3 as in the first comparative example are not required. Therefore, the mounting area can be suppressed. Further, the limitation of the band of the gate bias voltage caused by the large capacitors Cg1 to Cg3 can be suppressed.

  In order for the filter circuits 12, 14 and 16 to function as described above, it is preferable that the impedance between the node N1 or N2 and the ground in the filter circuits 12, 14 and 16 has the following relationship. The impedance Z12 of the filter circuit 12 in the high frequency band is lower than the impedances Z14 and Z16 of the filter circuits 14 and 16. The impedance Z16 of the filter circuit 16 in the low frequency band is lower than the impedances Z12 and Z14 of the filter circuits 12 and 14. The impedance Z14 of the filter circuit 14 in the intermediate frequency band is lower than the impedances Z12 and Z16 of the filter circuits 12 and 16.

  Furthermore, in order to make the filter circuit 12 function as a matching circuit in the high frequency band, it is preferable that a distributed constant line Lg is provided. The nodes N1 and N2 may be provided in common, or a line may be formed between the nodes N1 and N2.

  The second embodiment is a specific example of the first embodiment. FIG. 3 is a circuit diagram of an electronic circuit according to the second embodiment. As shown in FIG. 3, in the electronic circuit 102, the capacitor C1 and the distributed constant line L1 are connected in series between the input terminal Tin and the node N2. Distributed constant lines L2, L3 and a capacitor C3 are connected in series between the distributed constant line Ld and the output terminal Tout. A distributed constant line L4 and a capacitor C2 are connected in series between a node between the distributed constant lines Ld and L2 and the ground. A drain bias terminal Tvd is connected to a node between the distributed constant line L4 and the capacitor C2. A distributed constant line L5 is connected as an open stub to a node between the distributed constant lines L2 and L3.

  Capacitors C1 to C3 mainly function as DC cut capacitors. The distributed constant line L1 functions as a gate matching circuit together with the distributed constant line Lg and the capacitor Cg. The distributed constant lines L2 to L5 function as a drain matching circuit together with the distributed constant line Ld. The distributed constant line L4 also functions as a choke that blocks high-frequency signals.

Table 1 shows examples of the line length of the distributed constant line used in the second embodiment, the capacitance value of the capacitor, the resistance value of the resistor, the finger width of the transistor, and the number of fingers. The distributed constant line has a characteristic impedance of 50Ω. The FTE 10 is a HEMT (High Electron Mobility Transistor) using AlGaAs and InGaAs. The gate length of the FET 10 is 0.1 μm. Six fingers with a gate width of 50 μm are used.

  According to the second embodiment, it is possible to provide a stable amplifier circuit in which 57 GHz to 66 GHz is set as an amplification band, and the gate bias voltage can be controlled from the outside. The filter circuit 12 functions as a matching circuit for impedance matching for high frequency signals of 57 GHz or more and 66 GHz or less. The filter circuit 14 removes an intermediate frequency signal of 1 GHz or more and less than 50 GHz input to the input terminal Tin. The filter circuit 16 removes a low frequency signal of less than 1 GHz input from the input terminal Tin.

  In the first and second embodiments, the description has been given by taking the FET as the transistor, the source as the first terminal, the drain as the second terminal, and the gate as the control terminal, but the transistor is a bipolar transistor, the first terminal is the emitter, The terminal may be a collector and the control terminal may be a base.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

10 FET
12-16 Filter circuit 20-28 Arrow

Claims (4)

A transistor having a control terminal connected to the input terminal, a first terminal connected to the reference potential, and a second terminal connected to the output terminal;
A first filter circuit having a first capacitor with one end connected to a reference potential and a node between one end of the control terminal and the input terminal;
A first resistor having one end connected to the node; and a second capacitor having one end connected to the other end of the first resistor and the other end connected to a reference potential; and between the node and the reference potential A second filter circuit connected in parallel with the first filter circuit;
A third filter circuit having a second resistor having one end connected to the node and the other end connected to a bias terminal; and a third resistor having one end connected to the node and the other end connected to a reference potential;
An electronic circuit comprising: The impedance of the first filter circuit in the high frequency band is lower than the impedance of the second filter circuit and the third filter circuit in the high frequency band,
The impedance of the third filter circuit in the low frequency band whose frequency is lower than that of the high frequency band is lower than the impedance of the first filter circuit and the second filter circuit in the low frequency band,
The impedance of the second filter circuit in an intermediate frequency band having a frequency lower than that of the high frequency band and higher than that of the low frequency band is lower than impedances of the first filter circuit and the third filter circuit in the intermediate frequency band. Item 2. The electronic circuit according to Item 1.   3. The electronic circuit according to claim 1, further comprising: a distributed constant line having one end connected to the node and the other end commonly connected to one end of the first capacitor and one end of the first resistor.   4. The electronic circuit according to claim 1, wherein the transistor is an FET, the first terminal is a source, the second terminal is a drain, and the control terminal is a gate. 5.

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