JP2017005197A - Surface emitting laser, surface emitting laser array, laser processing machine, laser ignition device, display device, and method for manufacturing surface emitting laser array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a surface emitting laser capable of improving reliability thereof.SOLUTION: A surface emitting laser (light emitting section 10a) includes a mesa (mesa structure) formed by etching a laminate till at least a side face of a selectively-oxidized layer 115 is exposed, the laminate including: a substrate 101; a lower semiconductor DBR 103 laminated over the substrate 101; an active layer 105 laminated over the lower semiconductor DBR 103; and an upper semiconductor DBR 107 laminated over the active layer 105 and provided with the selectively-oxidized layer 115. The surface emitting laser further includes a p-side electrode wiring layer 110 which is laminated over at least a part of a region that excludes a central part of the top face of the mesa and which is connected to the peripheral part of the top face of the mesa, in the laminate in which the mesa is formed. The thickness D of the p-side electrode wiring layer 110 is set to be thicker than the height H of the mesa.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a surface-emitting laser, a surface-emitting laser array, a laser processing machine, a laser ignition device, a display device, and a method for manufacturing a surface-emitting laser array, and more particularly, a surface-emitting laser including a mesa structure, the surface Surface emitting laser array including a plurality of light emitting lasers, laser processing machine including the surface emitting laser array, a laser ignition device including the surface emitting laser array, a display device including the surface emitting laser array, and a surface emitting light having a mesa structure The present invention relates to a method of manufacturing a surface emitting laser array including a plurality of lasers.

  In recent years, surface emitting lasers having a mesa structure have been actively developed.

  For example, Patent Documents 1 and 2 disclose surface-emitting lasers in which electrode wiring is connected to the periphery of the upper surface of a mesa structure.

  However, the surface emitting lasers disclosed in Patent Documents 1 and 2 have room for improvement in terms of reliability.

  The present invention includes a substrate, a first reflecting mirror laminated on the substrate, an active layer laminated on the first reflecting mirror, and a second reflecting mirror laminated on the active layer. In a surface emitting laser provided with a mesa structure formed by etching a laminate including the same, at least a part of the laminate in which the mesa structure is formed, excluding a central portion of the upper surface of the mesa structure The surface light emitting device further comprising an electrode wiring layer stacked on the upper surface of the mesa structure and connected to a peripheral portion of the mesa structure, wherein the thickness of the electrode wiring layer is larger than the height of the mesa structure. It is a laser.

  According to the present invention, reliability can be improved.

It is a figure which shows roughly the structure of the light source device of 1st Embodiment of this invention. It is YZ sectional drawing of the surface emitting laser array of 1st Embodiment. It is FIG. (1) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is FIG. (2) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is FIG. (3) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is FIG. (4) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is FIG. (5) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is FIG. (6) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is FIG. (7) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is FIG. (8) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is FIG. (9) for demonstrating the manufacturing method of the surface emitting laser array of 1st Embodiment. It is YZ sectional drawing of the surface emitting laser array of 2nd Embodiment. It is the schematic of the ICP etcher of 2nd Embodiment. It is FIG. (1) for demonstrating the manufacturing method of the surface emitting laser array of 2nd Embodiment. It is FIG. (2) for demonstrating the manufacturing method of the surface emitting laser array of 2nd Embodiment. It is FIG. (3) for demonstrating the manufacturing method of the surface emitting laser array of 2nd Embodiment. It is FIG. (4) for demonstrating the manufacturing method of the surface emitting laser array of 2nd Embodiment. It is YZ sectional drawing of the surface emitting laser array of 3rd Embodiment. It is FIG. (1) for demonstrating the manufacturing method of the surface emitting laser array of 3rd Embodiment. It is FIG. (2) for demonstrating the manufacturing method of the surface emitting laser array of 3rd Embodiment. It is FIG. (3) for demonstrating the manufacturing method of the surface emitting laser array of 3rd Embodiment. It is FIG. (4) for demonstrating the manufacturing method of the surface emitting laser array of 3rd Embodiment. 6 is a YZ sectional view of a surface emitting laser array according to Modification 1. FIG. FIG. 10 is a YZ sectional view of a surface emitting laser array according to Modification 2. FIG. 25A and FIG. 25B are diagrams for explaining a schematic configuration of a laser annealing apparatus, respectively. It is a figure for demonstrating schematic structure of a laser cutting machine. It is a figure for demonstrating a laser display apparatus.

<< First Embodiment >>
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 schematically shows a light source device 100 according to the first embodiment.

  The light source device 100 is used as a light source for a laser processing machine, a display device or the like, or an excitation light source for a laser medium such as a solid laser. As an example, the light source device 100 includes a surface emitting laser array 10, a heat sink 12, a microlens array 14, a condenser lens 16, an optical fiber 18, and the like as illustrated in FIG. 1.

  In the present specification, the description will be made assuming that the oscillation direction of the surface emitting laser array 10 is the Z-axis direction, and the directions orthogonal to each other in a plane orthogonal to the Z-axis direction are the X-axis direction and the Y-axis direction. Here, the emission direction of the surface emitting laser array 10 is the + Z direction.

  As an example, as shown in FIG. 2, the surface emitting laser array 10 includes a plurality of light emitting units 10a formed in an array on a substrate 101 parallel to the XY plane, and is provided in common on the plurality of light emitting units 10a. P-side electrode wiring layer 110 and the like. Here, the plurality of light emitting units 10a are two-dimensionally arranged in parallel to the XY plane. Note that the p-side electrode wiring layer may be provided separately for each light emitting portion. In FIG. 2, only one light emitting unit 10a in the surface emitting laser array 10 is shown for convenience.

  As shown in FIG. 1, the surface emitting laser array 10 is mounted on the surface of the heat sink 12 on the + Z side via a bonding material 15 (for example, paste solder). Hereinafter, a unit including the surface emitting laser array 10, the bonding material 15, and the heat sink 12 is referred to as a light source module 60.

  Each light emitting unit 10a is, for example, a vertical cavity surface emitting laser (VCSEL) having an oscillation wavelength of 808 nm band.

  For example, the heat sink 12 is a plate-like member parallel to the XY plane. As a material for the heat sink, for example, CVD (chemical vapor deposition) diamond or ceramic with high thermal conductivity (for example, AlN on which SiC or Au thin film pattern is formed) may be used. Further, the heat sink 12 may be a member having a hollow structure and having a cooling function such as water cooling or air cooling inside. A heat spreader may be used instead of the heat sink.

  As an example, the microlens array 14 includes a plurality of microlenses 14 a that are arranged on the + Z side of the surface emitting laser array 10 and are two-dimensionally arranged parallel to the XY plane. The plurality of microlenses 14a are individually disposed on the optical paths of the plurality of laser beams from the plurality of light emitting units 10a, and make the corresponding laser beams substantially parallel lights.

  For example, the condenser lens 16 is disposed on the + Z side of the microlens array 14 so that the optical axis is substantially parallel to the Z axis, and condenses (synthesizes) a plurality of laser beams from the microlens array 14. .

  The optical fiber 18 has an incident end disposed in the vicinity of the focal position of the condenser lens 16 and guides a plurality of laser beams synthesized by the condenser lens 16. Laser light (synthetic light) guided in the optical fiber 18 is taken out at the exit end of the optical fiber 18 and used, for example, for laser processing.

  As can be seen from the above description, an optical system that guides a plurality of laser beams from the surface emitting laser array 10 includes the microlens array 14, the condenser lens 16, and the optical fiber 18.

  FIG. 2 shows a YZ sectional view of the surface emitting laser array 10.

  As an example, the surface emitting laser array 10 includes a substrate 101, an n-side electrode wiring layer 112, a buffer layer 102, a lower semiconductor DBR 103, a lower spacer layer 104, an active layer 105, an upper spacer layer 106, as shown in FIG. The upper semiconductor DBR 107, the contact layer 109, the protective layer 111, the p-side electrode wiring layer 110, and the like are included.

  As an example, the substrate 101 is an n-GaAs single crystal substrate whose surface is a mirror-polished surface.

  The n-side electrode wiring layer 112 is a gold film formed on the −Z side surface of the substrate 101. The n-side electrode wiring layer 112 may be a metal film other than a gold film or a multilayer film composed of a plurality of metal films.

  The buffer layer 102 is laminated on the + Z side surface of the substrate 101 and is a layer made of n-GaAs.

The lower semiconductor DBR 103 is stacked on the + Z side of the buffer layer 102, and includes a low refractive index layer made of n-Al _0.9 Ga _0.1 As and a high refractive index made of n-Al _0.3 Ga _0.7 As. It has 40.5 pairs of layers. Between each refractive index layer, in order to reduce an electrical resistance, a composition gradient layer having a thickness of 20 nm in which the composition is gradually changed from one composition to the other composition is provided. Each refractive index layer is set to have an optical thickness of λ / 4 (λ is an oscillation wavelength) including 1/2 of the adjacent composition gradient layer. When the optical thickness is λ / 4, the actual thickness L of the layer is L = λ / 4n (where n is the refractive index of the medium of the layer).

The lower spacer layer 104 is laminated on the + Z side of the lower semiconductor DBR 103 and is a layer made of non-doped Al _0.6 Ga _0.4 As.

The active layer 105 is laminated on the + Z side of the lower spacer layer 104 and has an active layer with a triple quantum well structure including an Al _0.12 Ga _0.88 As quantum well layer / Al _0.3 Ga _0.7 As barrier layer. It is. The active layer 105 is set to a thickness such that the wavelength λ (oscillation wavelength) of the emitted laser light is 808 nm.

The upper spacer layer 106 is laminated on the + Z side of the active layer 105 and is a layer made of non-doped Al _0.6 Ga _0.4 As.

  A portion composed of the lower spacer layer 104, the active layer 105, and the upper spacer layer 106 is also called a resonator structure, and includes a half of the adjacent composition gradient layer, and has a thickness of one wavelength (λ ) Optical thickness. The active layer 105 is provided at the center of the resonator structure at a position corresponding to the antinode in the standing wave distribution of the electric field so that a high stimulated emission probability can be obtained. Each light emitting unit 10a has one resonator structure.

The upper semiconductor DBR 107 is laminated on the + Z side of the upper spacer layer 106, and has a low refractive index layer made of p-Al _0.9 Ga _0.1 As and a high refractive index made of p-Al _0.3 Ga _0.7 As. It has 24 pairs of layers.

  Between the refractive index layers in the upper semiconductor DBR 107, a composition gradient layer is provided in which the composition is gradually changed from one composition to the other composition in order to reduce electrical resistance. Each refractive index layer is set to have an optical thickness of λ / 4 including 1/2 of the adjacent composition gradient layer.

In the upper semiconductor DBR 107, a selective oxidation layer 108 (current confinement layer) made of p-Al _0.98 Ga _0.02 As is inserted with a thickness of 30 nm at a position λ / 4 away from the resonator structure. The selective oxidation layer 108 is generated by selective oxidation (Al is oxidized) from the side of a selective oxidation layer 115 (see FIG. 4) which is one low refractive index layer of the upper semiconductor DBR 107.

  The contact layer 109 is stacked on the + Z side of the upper semiconductor DBR 107 and is a layer made of p-GaAs.

  A part of the p-side electrode wiring layer 110 insulated by a protective layer 111 made of an optically transparent dielectric layer made of p-SiN (SiN formed by plasma CVD) is in contact with the contact layer 109. Is connected. Here, gold is used as the material of the p-side electrode wiring layer 110.

  In the vicinity of the side of the mesa (mesa structure) inside the p-side electrode wiring layer 110 (region surrounded by the broken line in FIG. 2), the optically transparent material made of the same material as the protective layer 111, that is, p-SiN. A dielectric film is provided as a stress relaxation layer. Note that p-SiN has a smaller thermal expansion coefficient than gold.

  Specifically, the p-side electrode wiring layer 110 has a two-layer structure including a first wiring layer 110a and a second wiring layer 110b stacked on the first wiring layer 110a. The stress relaxation layer is disposed between the first and second wiring layers 110a and 110b.

  The p-side electrode wiring layer 110 is connected to an electrode pad disposed in a peripheral region of the region where the plurality of light emitting units 10a are disposed, and a conductive wire made of Au is connected to the electrode pad. Yes.

  Below, the manufacturing method of the light source module 60 containing the surface emitting laser array 10 is demonstrated. A plurality of surface emitting laser arrays 10 are integrally formed at the same time by a semiconductor manufacturing process, and then divided into a plurality of chip-shaped surface emitting laser arrays 10. Note that a structure in which a plurality of semiconductor layers are stacked over the substrate 101 as described above is also referred to as a “stacked body” below. The surface emitting laser array 10 is also referred to as a “chip”.

(1) The laminate is formed by crystal growth by metal organic vapor phase epitaxy (MOCVD) or molecular beam epitaxy (MBE). This crystal growth is performed in a reaction tube of a crystal growth apparatus (not shown).

Here, the MOCVD method will be described as an example. In the MOCVD method, trimethylaluminum (TMA), trimethylgallium (TMG), and trimethylindium (TMI) are used as Group III materials, and phosphine (PH ₃ ) and arsine (AsH ₃ ) are used as Group V materials. Yes. Further, carbon tetrabromide (CBr ₄ ) and dimethyl zinc (DMZn) are used as the raw material for the p-type dopant, and hydrogen selenide (H ₂ Se) is used as the raw material for the n-type dopant.

  Specifically, the buffer layer 102, the lower semiconductor DBR 103, the lower spacer layer 104, the active layer 105, the upper spacer layer 106, the upper semiconductor DBR 107 including the selective oxidation layer 115, and the contact layer 109 are formed on the substrate 101 in this order. Growing to create a laminate (see FIG. 3).

(2) A plurality of square resist patterns each having a side of 25 μm are formed in an array on the surface of the laminate by lithography. Here, the resist pattern is formed over the range corresponding to the electrode region of the p-side electrode wiring layer 110 formed in the later step.

(3) A plurality of square mesas (mesa structures) are formed in an array by the ICP dry etching method using the resist pattern as a photomask (see FIG. 4). Here, dry etching is performed until the bottom surface of the etching reaches the lower semiconductor DBR 103.

(4) The photomask is removed.

(5) By heat-treating the laminated body on which the mesa is formed in water vapor, Al (aluminum) in the selective oxidation layer 115 is selectively oxidized from the outer peripheral portion of the mesa, and the central portion of the mesa is made of Al. An unoxidized region 108b surrounded by the oxide layer 108a is formed (see FIG. 5). In this way, the selective oxide layer 108 is generated. In the selective oxidation layer 108, the driving current path of the light emitting portion is limited only to the central portion of the mesa by the oxide layer 108a (insulating layer). Therefore, the region 108b is also referred to as a current passage region (current injection region). The selective oxidation layer 108 is also called a current confinement layer. In this manner, a substantially square current passing region having a width of about 4 μm to 6 μm, for example, is formed.

(6) A resist pattern is formed by lithography so that only the region for forming the chip separation groove is exposed on the laminated body that has been subjected to the oxidation treatment, and the chip separation groove is formed using the ICP dry etching method, and then the resist is formed. Remove the pattern.

(7) The laminated body in which the mesa and the chip separation groove are formed is put in a heating chamber and held in a nitrogen atmosphere at a temperature of 380 to 400 ° C. for 3 minutes. As a result, a natural oxide film formed by oxygen or water adhering to the surface in the air or a small amount of oxygen or water in the heat treatment chamber becomes a stable passive film by heat treatment in a nitrogen atmosphere. This step (7) is not essential and may be omitted.

(8) A protective layer 111 (hereinafter also referred to as an “interlayer insulating film”) made of p-SiN is formed by vapor phase chemical deposition (CVD) (see FIG. 6).

  The thickness of the interlayer insulating film is desirably in the range of 100 nm to 400 nm. When the interlayer insulating film is thinner than 100 nm, there is a problem that the operation speed is lowered because the wiring capacity is increased. When the interlayer insulating film is thicker than 400 nm, there is a problem that a crystal defect is induced by the internal stress of the interlayer insulating film. A more desirable range of the thickness of the interlayer insulating film is 150 nm to 300 nm. Here, a p-SiN film is formed with a thickness of 200 nm by a plasma CVD method.

(9) Open the window of the p-side electrode contact on the top of the mesa. That is, a contact hole is formed in the protective layer 111 on the upper surface of the mesa (see FIG. 7). Here, after applying an etching mask with a photoresist, the upper portion of the mesa is exposed to remove the photoresist at that portion, and the protective layer 111 is wet-etched with BHF (buffered hydrofluoric acid) to form an opening (contact hole). Form. At the same time, the protective layer 111 in the scribe region on the bottom surface of the chip separation groove formed in the step (6) is also removed.

(10) The etching mask is removed.

(11) A photoresist (lift-off resist) is patterned by photolithography, and a p-side electrode material is deposited. Specifically, a square-shaped resist pattern with a side of 10 μm for forming an emission port surrounded by a p-side electrode on the top of the mesa and a resist pattern for forming a plurality of electrode pads are formed. A gold film is formed by electron beam evaporation.

(12) The first wiring layer 110a is formed by lifting off the electrode material in the region serving as the emission port (see FIG. 8), and the electrode material in the region where the plurality of electrode pads are formed is also lifted off. A pad is formed (see FIG. 8). Specifically, the photoresist is removed using an organic solvent such as NMP to leave gold in a portion where there is no photoresist, thereby forming the first wiring layer 110a and the electrode pad.

(13) A dielectric layer 120 made of p-SiN, which is a thin film having a smaller coefficient of thermal expansion than the metal (here, gold) that is the wiring material, is formed on the entire surface (see FIG. 9).

  The film thickness of the dielectric layer 120 is preferably in the range of 100 nm to 200 nm. When the dielectric layer 120 is thinner than 100 nm, the stress relaxation effect is small, and when the dielectric layer 120 is thicker than 200 nm, a part of the dielectric layer 120 remains as a stress relaxation layer only on the side of the mesa. This is because it is difficult to remove other portions of the dielectric layer 120 in the entire etch back process. That is, it is appropriate to make the thickness about the same as that of the interlayer insulating film.

  Here, a 200-nm p-SiN film was formed as the dielectric layer 120.

(14) By selectively etching the entire surface in the vertical direction by anisotropic etching (reactive ion etching) with Ar ions in 0.1 Pa high-vacuum plasma, p − as a stress relaxation layer on the side of the mesa The SiN film is left (see FIG. 10). At this time, the dielectric layer 120 at the peripheral portion in the central portion of the contact hole also remains.

  The dielectric layer 120 remaining in the contact hole is located at the periphery of the emission port and can reduce the reflectivity of the periphery, thereby suppressing high-order transverse mode oscillation without suppressing single transverse mode oscillation. can do.

(15) A photoresist (lift-off resist) is patterned by photolithography, and a p-side electrode material is deposited. Specifically, a square resist pattern having a side of 15 μm for forming an exit port surrounded by a p-side electrode is formed on the mesa, and a gold film as an electrode material is formed by electron beam evaporation.

(16) The second wiring layer 110b is formed by lifting off the electrode material on the region to be the emission port (see FIG. 11). Specifically, the photoresist is removed using an organic solvent such as NMP to leave a portion of the gold where there is no photoresist, thereby forming the second wiring layer 110b. As a result, the p-side electrode wiring layer 110 in which the second wiring layer 110b is stacked on the first wiring layer 110a is formed.

  Here, the thickness of the first wiring layer 110a is d1, the thickness of the second wiring layer 110b is d2, the thickness of the p-side electrode wiring layer 110 is D, the thickness of the protective layer 111 is e, When the height is H, d1 + d2 + e = D + e> H (P) is established (see FIG. 2). That is, the upper surface (+ Z side surface) of the p-side electrode wiring layer 110 is located farther from the substrate 101 than the upper surface of the mesa.

  In other words, the deposition amount of the p-side electrode material is set in the steps (11) and (15) so that the formula (P) is established. In addition, the ratio of the vapor deposition amount of the p-side electrode material in the steps (11) and (15) can be appropriately changed within the range in which the formula (P) is established.

  Here, since the thickness e of the protective layer 111 is sufficiently smaller than the thickness D of the p-side electrode wiring layer 110, it may be considered that d1 + d2 = D> H (Q) is substantially established. When the above equation (Q) is established, the above equation (P) is also established.

(17) After polishing the back side of the substrate 101 to a predetermined thickness (for example, about 100 μm), an n-side wiring layer 112 is formed (see FIG. 2).

(18) Ohmic conduction is established between the p-side electrode wiring layer 110 and the n-side wiring layer 112 by annealing. Thus, the mesa becomes the light emitting unit 10a.

(19) Cut by chip by scribing and braking.

  As a result, a plurality of chip-shaped surface-emitting laser arrays 10 each including a plurality of light emitting units 10a are manufactured by the steps (1) to (19).

(20) On a hot plate heated to 200 to 250 ° C., a bonding material 15 (for example, a paste) is bonded to the surface emitting laser array 10 and the heat sink 12 made of an AlN material patterned with Ni / Pt / Au having a thickness of 1 μm. Solder). The heat sink 12 is provided with a region where no Au film is formed. This prevents a short circuit between the p-side electrode wiring layer 110 and the n-side wiring layer 112.

(21) An energizing wire made of Au is connected to the electrode pad.

  The light source module 60 including the surface emitting laser array 10 is manufactured by the steps (1) to (21) (see FIG. 1).

  By the way, conventionally, in the process of forming the electrode wiring for injecting current into each light emitting portion (VCSEL) of the current confinement structure of the surface emitting laser array, the electrode wiring is arranged along the mesa shape (over the step of the mesa). Therefore, there is a possibility that disconnection or the like due to insufficient step coverage of the electrode wiring may occur, resulting in a decrease in reliability.

  Further, when VCSELs are arrayed on a large scale, for example, when 10000 or more VCSELs are integrated to output 100 W or more, it is necessary to drive with a large current exceeding 50 A. In this case, if the thickness of the electrode wiring is thin, the laser output is saturated due to heat generated by the resistance of the electrode wiring during driving, so that the lack of step coverage of the electrode wiring hinders high output of the VCSEL.

  The surface emitting laser (light emitting unit 10a) of the first embodiment described above includes a substrate 101, a lower semiconductor DBR 103 stacked on the substrate 101, an active layer 105 stacked on the lower semiconductor DBR 103, A mesa (mesa structure) formed by etching a stacked body including the upper semiconductor DBR 107 stacked on the active layer 105 and provided with the selective oxidation layer 115 until at least the side surface of the selective oxidation layer 115 is exposed. In the surface emitting laser comprising a mesa, the p-side electrode wiring layer is laminated on at least a part of the laminated body excluding the central portion of the upper surface of the mesa and connected to the peripheral portion of the upper surface of the mesa. 110, and the thickness D of the p-side electrode wiring layer 110 is set to be greater than the height H of the mesa.

In this case, sufficient step coverage can be secured in the p-side electrode wiring layer 110.
As a result, reliability can be improved.

  By the way, since a large current flows in a high-power laser, it is essential to reduce the resistance of the electrode wiring. The resistance of the wiring formed by a method that creates holes, such as vapor deposition, decreases according to the film thickness when there is no step, and when there is a mesa step, the wiring thickness is thicker than the mesa height. It was found that the effect of lowering the resistance is dramatically increased.

  Therefore, according to the surface emitting laser (light emitting unit 10a) of the first embodiment, high output can be achieved.

  Since the upper surface of the p-side electrode wiring layer 110 is located farther from the substrate 101 than the upper surface of the mesa structure, the reliability can be improved reliably.

  Further, a stress relaxation layer is provided in the vicinity of the side of the mesa inside the p-side electrode wiring layer 110.

  In this case, even when the p-side electrode wiring layer 110 generates heat, the thermal expansion of the p-side electrode wiring layer 110 is suppressed by the action of the stress relaxation layer (stress relaxation action), and the operational reliability of the laser (VCSEL) can be improved. .

  Further, the stress relaxation layer is made of a material having a smaller thermal expansion coefficient than the material of the p-side electrode wiring layer 110 (for example, gold) and absorbs the thermal expansion of the p-side electrode wiring layer 110, thereby preventing the active layer from being damaged. it can. As a result, the operational reliability of the laser can be reliably improved. The material of the stress relaxation layer is not limited to the dielectric (insulator) but may be a conductor as long as it has a smaller thermal expansion coefficient than the material of the p-side electrode wiring layer 110 (for example, gold). .

Further, a protective layer 111 (insulating layer) is disposed between the stacked body on which the mesa is formed and the p-side electrode wiring layer 110, and the stress relaxation layer is made of the same material as the protective layer 111.
In this case, the film thickness design and manufacturing process can be simplified.

  In addition, since the surface emitting laser array 10 of the first embodiment includes a plurality of surface emitting lasers as the light emitting units 10a, high reliability and high yield can be realized in units of chips.

  In the method of manufacturing the surface emitting laser array 10 according to the first embodiment, the lower semiconductor DBR 103, the active layer 105, and the upper semiconductor DBR 107 provided with the selective oxidation layer 115 are sequentially stacked on the substrate 101. Forming a mesa by etching the stacked body until at least the side surface of the selective oxidation layer 115 is exposed, and selectively oxidizing the selective oxidation layer 115 from the side surface to form the selective oxidation layer 108 ( A step of forming a current confinement layer), a step of forming a protective layer 111 having a contact hole on the upper surface of the mesa on the stacked body in which the selective oxide layer 108 is formed on the mesa, Forming a first wiring layer 110a in the periphery of the first wiring layer, forming a dielectric film (stress relaxation layer) in the vicinity of the mesa side in the first wiring layer 110a, And forming a second wiring layer 110b on the first wiring layer 110a so as to cover the dielectric film.

  In this case, the surface emitting laser array 10 that can improve the reliability can be easily manufactured by using a semiconductor manufacturing process.

  The dielectric film forming step includes a sub-step of laminating the dielectric layer 120 on the first wiring layer 110a and the center of the contact hole, and a portion of the dielectric layer 120 near the side of the mesa. And a sub-process for removing at least a part other than a certain dielectric film.

  In this case, the dielectric film (stress relaxation layer) can be easily generated using a semiconductor manufacturing process.

  Further, in the sub-step to be removed, the dielectric layer 120 in the central portion of the contact hole is not removed at the peripheral portion of the central portion, so that the higher-order lateral mode is suppressed without suppressing the oscillation in the single transverse mode. A surface-emitting laser array that can suppress the oscillation of can be manufactured.

  In the first embodiment, the SiN film is used for the stress relaxation layer. However, a dielectric film such as SiOx, SiNx (X ≠ 1), SiOxNy, TiOx, or the like may be used. However, x and y are natural numbers (for example, one-digit natural numbers).

  In the first embodiment, the stress relaxation layer is made of the same material as the interlayer insulating film, but may be a different material (for example, a dielectric or a conductor) as long as it has a stress relaxation function.

<< Second Embodiment >>
Below, 2nd Embodiment is described based on FIGS. 12-17. In the second embodiment, the configuration of the surface emitting laser array and a part of the manufacturing process are different from those in the first embodiment.

  In the surface emitting laser (light emitting unit 20a) of the second embodiment, as shown in FIG. 12, in the vicinity of the mesa side in the p-side electrode wiring layer 210 (a region surrounded by a broken line in FIG. 12) Holes having a stress relaxation function are formed. Similarly to the p-side electrode wiring layer 110, the p-side electrode wiring layer 210 has a two-layer structure of first and second wiring layers 210a and 210b.

  Next, a method for manufacturing a light source module including the surface emitting laser array 20 of the second embodiment will be described.

In the second embodiment, first, the steps (1) to (3) are performed as in the first embodiment.
At this time, the step (3), that is, the dry etching step is performed by reactive ion etching using an ICP etcher as shown in FIG. In this ICP etcher, the position of the bottom surface during the progress of etching can be grasped from the waveform of the end point monitor.

  After confirming that the bottom surface of the etching has progressed to the lower side (-Z side) than the selective oxidation layer 115, the etching is progressed in the lateral direction by changing the etching conditions to those having a chemical reaction superiority. As shown in FIG. 5, an overhang portion can be formed at the bottom of the mesa.

Table 1 below shows examples of etching conditions. Here, the etching step 1 is from the start of etching to the etching under the selective oxidation layer 115, and the etching is changed after confirming the progress of the etching under the selective oxidation layer 115 until the etching is completed. Step 2 is set.

Subsequently, the said process (4)-(8) is performed similarly to 1st Embodiment.
At this time, in the step (8), that is, the protective layer forming step, the protective layer 211 (interlayer insulating film) is formed along the overhang portion (see FIG. 15).

Subsequently, the said process (9)-(12) is performed similarly to 1st Embodiment.
At this time, in the step (12), that is, the first wiring layer forming step, the distance between the vapor deposition source and the film formation surface is set to 50 cm or more when the gold film as the p-side electrode material is subjected to electron beam vapor deposition. As a result, the gold film grows anisotropically (especially because the gold film grows from the corner), and as shown in FIG. 16, in the initial stage of film formation, the first wiring layer 210a is overshadowed. This part becomes the gap 210c.

Subsequently, the said process (15) and (16) are performed similarly to 1st Embodiment.
At this time, in the step (16), that is, the second wiring layer forming step, a gap 210d communicating with the gap 210c of the first wiring layer 210a is formed in the second wiring layer 210b (see FIG. 17).

  As a result, the p-side electrode wiring layer 210 in which the second wiring layer 210b is stacked on the first wiring layer 210a is generated. In the vicinity of the mesa side in the p-side electrode wiring layer 210, a void (space) formed by the gap 210c and the gap 210d is formed. This hole has a stress relaxation function.

  Here, the thickness of the first wiring layer 210a is d1 ′, the thickness of the second wiring layer 210b is d2 ′, the thickness of the p-side electrode wiring layer 110 is D ′, and the thickness of the protective layer 211 is e. When the height of the mesa is H ′, d1 ′ + d2 ′ + e ′ = D ′ + e ′> H ′ (R) is established (see FIG. 12). That is, the upper surface (+ Z side surface) of the p-side electrode wiring layer 210 is located farther from the substrate 101 than the upper surface of the mesa.

  In other words, the deposition amount of the electrode material on the p side is set in the steps (11) and (15) so that the formula (R) is established. Note that the ratio of the deposition amount of the p-side electrode material in the steps (11) and (15) can be changed as appropriate within the range in which the formula (R) is satisfied.

  Here, since the thickness e ′ of the protective layer 211 is sufficiently smaller than the thickness D ′ of the p-side electrode wiring layer 210, d1 ′ + d2 ′ = D ′> H ′ (S) is substantially established. You can think of it. When the above equation (S) is established, the above equation (R) is also established.

  Subsequently, the said process (17)-(21) is performed similarly to 1st Embodiment.

  As a result, the light source module including the surface emitting laser array 20 is manufactured by the steps (1) to (12) and (15) to (21).

  In the surface-emitting laser (light-emitting portion 20a) of the second embodiment described above, the stress relaxation portion is a hole formed inside the p-side electrode wiring layer 210, so that the p-side electrode wiring layer 210 is thermally expanded. Space (escape point) can be secured. As a result, the active layer 105 can be prevented from being damaged, and the operational reliability of the laser can be reliably improved.

  The mesa has an overhang portion at the bottom, and the holes are formed at locations corresponding to the overhang portion in the p-side electrode wiring layer 210.

  In this case, holes can be formed by utilizing the growth variation of the electrode material due to the mesa shape (overhang portion).

  In the method of manufacturing the surface emitting laser array 20 according to the second embodiment, the lower semiconductor DBR 103, the active layer 105, and the upper semiconductor DBR 107 provided with the selective oxidation layer 115 are sequentially stacked on the substrate 101. A first etching step for etching the stacked body until at least the side surface of the selective oxidation layer 115 is exposed, and after the side surface is exposed, the stacking is performed under an etching condition superior in chemical reaction to the first etching step. Etching a body to form a mesa structure having an overhang portion at the bottom, selectively oxidizing the selective oxidation layer 115 from the side surface to form a selective oxidation layer 108 (current confinement layer), and selection Forming a protective layer 211 (insulating film) having a contact hole on the upper surface of the mesa on the stacked body in which the oxide layer 108 is formed on the mesa; And forming a first wiring layer 210a to the peripheral portion of the upper layer 211 and the contact hole, and forming a second wiring layer 210b on the first wiring layer 210a, a.

  In this case, the surface emitting laser array 20 that can improve the reliability can be easily manufactured by using a semiconductor manufacturing process.

<< Third Embodiment >>
Below, 3rd Embodiment is described based on FIGS. 18-22. In the third embodiment, the configuration of the surface emitting laser array and a part of the manufacturing process are different from those in the first embodiment.

  In the surface emitting laser (light emitting unit 30a) of the third embodiment, as shown in FIG. 18, in the vicinity of the side of the mesa inside the p-side electrode wiring layer 310 (region surrounded by a broken line in FIG. 18) Holes (space portions) having a stress relaxation function are formed. Similarly to the p-side electrode wiring layers 110 and 210, the p-side electrode wiring layer 310 has a two-layer structure of first and second wiring layers 310a and 310b.

  Next, a method for manufacturing a light source module including the surface emitting laser array 30 according to the third embodiment will be described.

In the third embodiment, first, the steps (1) to (5) are performed as in the first embodiment.
At this time, in the step (5), that is, the selective oxidation step, after the selective oxidation layer 108 is formed, the mesa is immersed in buffered hydrofluoric acid having a concentration of 1% for 20 seconds. As a result, the oxidized portion of the low refractive index layer (Al _0.9 Ga _0.1 As layer) of the upper semiconductor DBR 107 is eluted to form a plurality of recesses on the side surface of the mesa (see FIG. 19).

Subsequently, the said process (6)-(8) is performed similarly to 1st Embodiment.
At this time, in the step (8), that is, the protective layer forming step, the protective layer 311 (interlayer insulating film) is formed along the plurality of recesses formed on the side surface of the mesa (see FIG. 20). At this time, a plurality of recesses are formed on the surface of the protective layer 311 opposite to the side surface of the mesa.

Subsequently, the said process (9)-(12) is performed similarly to 1st Embodiment.
At this time, in the step (12), that is, the first wiring layer forming step, the distance between the vapor deposition source and the film formation surface is set to 50 cm or more when the gold film as the p-side electrode material is subjected to electron beam vapor deposition. Thereby, since the gold film grows anisotropically, as shown in FIG. 21, it becomes difficult for the gold film to grow in the concave portion (shaded portion) of the protective layer 311 formed on the side surface of the mesa. As a result, a portion corresponding to the concave portion on the side surface of the mesa in the first wiring layer 310a becomes the gap 310c.

Subsequently, the said process (15) and (16) are performed similarly to 1st Embodiment.
At this time, in the step (16), that is, the second wiring layer forming step, a gap 310d communicating with the gap 310c of the first wiring layer 310a is formed in the second wiring layer 310b (see FIG. 22).

  As a result, the p-side electrode wiring layer 310 in which the second wiring layer 310b is stacked on the first wiring layer 310a is generated. In the vicinity of the mesa side in the p-side electrode wiring layer 310, a plurality of holes (space portions) formed by the gap 310c and the gap 310d are formed. This hole has a stress relaxation function.

  Here, the thickness of the first wiring layer 310a is d1 ″, the thickness of the second wiring layer 310b is d2 ″, the thickness of the p-side electrode wiring layer 110 is D ″, and the thickness of the protective layer 211 is e. “If the height of the mesa is H”, d1 ″ + d2 ″ + e ″ = D ″ + e ″> H ″ (T) is established (see FIG. 18), that is, the upper surface of the p-side electrode wiring layer 310 (see FIG. 18). (The + Z side surface) is located farther from the substrate 101 than the top surface of the mesa.

  In other words, the deposition amount of the p-side electrode material is set in the steps (11) and (15) so that the equation (T) is established. In addition, the ratio of the vapor deposition amount of the p-side electrode material in the steps (11) and (15) can be appropriately changed within the range where the above equation (T) is satisfied.

  Here, since the thickness e ″ of the protective layer 311 is sufficiently smaller than the thickness D ″ of the p-side electrode wiring layer 310, d1 ″ + d2 ″ = D ″> H ″ (U) is substantially established. You can think of it. When the above equation (U) is established, the above equation (T) is also established.

  Subsequently, the said process (17)-(21) is performed similarly to 1st Embodiment.

  As a result, the light source module including the surface emitting laser array 30 is manufactured by the steps (1) to (12) and (15) to (21).

  In the surface emitting laser (light emitting unit 30 a) of the third embodiment described above, the mesa has a recess (groove) formed on the side surface, and the hole is located at a location corresponding to the recess in the p-side electrode wiring layer 110. Formed

  In this case, holes can be formed by utilizing the variation in the growth of the electrode material due to the mesa shape (the recess on the side surface of the mesa).

  In the surface emitting laser array 30 of the third embodiment, a lower semiconductor DBR 103, an active layer 105, and an upper semiconductor DBR 107 provided with a selective oxidation layer 115 are sequentially stacked on a substrate to produce a stacked body. A step of forming a mesa by etching the stacked body until at least a side surface of the selective oxidation layer 115 is exposed; and a selective oxidation layer (current confinement layer) by selectively oxidizing the selective oxidation layer 115 from the side surface. A step of removing the oxide on the side surface of the mesa structure in which the selective oxidation layer 108 is formed, forming a recess in the side surface, and a layered structure on which the selective oxidation layer 108 is formed on the mesa. In addition, a step of forming a protective layer 311 having a contact hole on the upper surface of the mesa, a step of forming a first wiring layer 310a on the protective layer 311 and around the contact hole, And forming a second wiring layer 310b on the wiring layer 310a, a.

  In this case, the surface emitting laser array 30 that can improve the reliability can be easily manufactured by using a semiconductor manufacturing process.

  In the third embodiment, since a plurality of recesses are formed on the side surface of the mesa and the plurality of holes are formed, the thermal expansion absorbability is high and the operational reliability of the laser can be further improved.

  In each of the above embodiments, SiN is used for the interlayer insulating film. However, other dielectrics such as SiOx, SiNx (X ≠ 0), SiOxNy, TiOx may be used. However, x and y are natural numbers.

  In each of the above embodiments, the p-side electrode wiring layer has a two-layer structure including the first and second wiring layers, but is not limited thereto, and may have a single-layer structure, or three or more layers. A laminated structure may be used. In the case of a single-layer structure, it is difficult to form a stress relaxation layer (for example, a dielectric film) inside the p-side electrode wiring layer. Therefore, as in the second and third embodiments, a void is formed. Is preferably formed. Further, when the p-side electrode wiring layer has a laminated structure of two or more layers, each layer may be made of the same material or different materials. As a specific example of a different material for each layer of the p-side electrode wiring layer, for example, a multilayer film made of Cr / AuZn / Au or a multilayer film made of Ti / Pt / Au may be used.

  In each of the above embodiments, the stress relaxation portion (stress relaxation layer or hole) is formed inside the p-side electrode wiring layer, but the stress relaxation portion may not be formed.

  For example, in the light emitting portion 40a of the surface emitting laser array 40 of Modification 1 shown in FIG. 23, the p-side electrode wiring layer 410 is composed of first and second wiring layers 410a and 410b, and a stress relaxation portion is provided therein. Is not formed.

  Further, for example, in the light emitting portion 50a of the surface emitting laser array 50 of the second modification shown in FIG. 24, the p-side electrode wiring layer 510 has a single layer structure, and no stress relaxation portion is formed therein.

  In each of the above embodiments, the first and second wiring layers are formed by electron beam evaporation, but may be formed by other evaporation or sputtering. Regardless of the method used to form the first and second wiring layers, in the second and third embodiments, the shape of the pores is determined by the degree of growth of the electrode material from the corner and the surface mobility of the electrode material. Come different.

  In each of the above embodiments, an example of an AlGaAs semiconductor DBR, an AlGaInP spacer layer, and a GaInAsP active layer has been described. However, the present invention is not limited to this material system.

  In each of the above embodiments, the optical system is configured to include the condensing lens 16 and the optical fiber 18, but is not limited thereto. In short, at least one of the condensing lens 16 and the optical fiber 18 is important. It is preferable that it is comprised including. The microlens array 14 is not necessarily provided.

  In each of the above embodiments, the case where the oscillation wavelength of the light emitting unit is in the 808 nm band has been described. However, the present invention is not limited to this. By appropriately selecting the material, for example, surface emitting laser arrays having wavelength bands of 650 nm band, 780 nm band, 850 nm band, 980 nm band, 1.3 um band, and 1.5 um band can be similarly produced.

  The above is a description of an element on an n-type substrate, but it is not limited to an element on an n-type substrate, and the same can be said for an element on a p-type substrate. When a p-type substrate is used, the same effect can be obtained by replacing the conductivity type of each layer and the polarity of carriers in the above description. Further, the wavelength is not limited to the 808 nm band, but other wavelength bands using different active layer materials, such as a 650 nm band, a 780 nm band, an 850 nm band, a 980 nm band, a 1.3 μm band, and a 1.5 μm band. Also good. The substrate may be a substrate other than GaAs.

  The surface-emitting laser arrays 10, 20, 30, 40, and 50 can also be used for applications other than laser processing (for example, image formation). In that case, the oscillation wavelength may be a wavelength band such as a 650 nm band, a 780 nm band, an 850 nm band, a 980 nm band, a 1.3 μm band, or a 1.5 μm band depending on the application. In this case, a mixed crystal semiconductor material corresponding to the oscillation wavelength can be used as the semiconductor material constituting the active layer. For example, an AlGaInP mixed crystal semiconductor material can be used in the 650 nm band, an InGaAs mixed crystal semiconductor material can be used in the 980 nm band, and a GaInNAs (Sb) mixed crystal semiconductor material can be used in the 1.3 μm band and the 1.5 μm band.

<Laser annealing equipment>
As an example, FIG. 25A and FIG. 25B show a schematic configuration of a laser annealing apparatus 1500 as a laser processing machine. The laser annealing apparatus 1500 includes a light source 1010, an optical system 1020, a table apparatus 1030, a control apparatus (not shown), and the like.

  The light source 1010 includes a plurality of the surface-emitting laser arrays or the light source modules, and can emit a plurality of laser beams. The optical system 1020 guides a plurality of laser beams emitted from the light source 1010 to the surface of the object P. The table device 1030 has a table on which the object P is placed. The table can move at least along the Y-axis direction.

  For example, in the case where the object P is amorphous silicon (a-Si), when irradiated with laser light, the amorphous silicon (a-Si) is crystallized by increasing the temperature and then gradually cooling, It becomes polysilicon (p-Si).

  In this case, the laser annealing apparatus 1500 can efficiently perform the annealing process because the light source 1010 includes the surface emitting laser array or the light source module.

<Laser cutting machine>
As an example, FIG. 26 shows a schematic configuration of a laser cutting machine 2000 as a laser processing machine. The laser cutting machine 2000 includes a light source 2010, an optical system 2100, a table 2150 on which an object P is placed, a table driving device 2160, an operation panel 2180, a control device 2200, and the like.

  The light source 2010 includes the surface emitting laser array or the light source module, and emits laser light based on an instruction from the control device 2200. The optical system 2100 focuses the laser light emitted from the light source 2010 near the surface of the object P. The table driving device 2160 moves the table 2150 in the X-axis direction, the Y-axis direction, and the Z-axis direction based on instructions from the control device 2200.

  The operation panel 2180 has a plurality of keys for the operator to make various settings and a display for displaying various information. The control device 2200 controls the light source 2010 and the table driving device 2160 based on various setting information from the operation panel 2180.

  In this case, the laser cutter 2000 can efficiently perform the cutting process because the light source 2010 includes the surface-emitting laser array or the light source module.

  Note that the laser cutting machine 2000 may include a plurality of light sources 2010.

  The surface-emitting laser array or the light source module is also suitable for an apparatus that uses laser light other than a laser annealing apparatus and a laser cutting machine. For example, you may use for the light source of a display apparatus.

<Laser display device>
FIG. 27 shows a schematic configuration of a laser display device 3000 as a display device.

  The laser display apparatus 3000 modulates the light source 3001 including the surface emitting laser array or the light source module, and the laser light from the light source 3001 according to display information, and directs the modulated laser light to the screen 3010. And an optical system 3003 for output and a control device 3005 for controlling the light source 3001 and the optical system 3003.

  Since the laser display device 3000 has the surface emitting laser array or the light source module, the displayed image quality can be improved.

  Note that even a laser display device that displays an image using laser light penetrating space can improve the displayed image quality as long as the laser display device includes the light source 3001.

  The surface emitting laser array can also be used as a light source for writing in an image forming apparatus such as a laser printer or a laser copying machine.

  Further, as will be described below, a laser ignition device for an engine including the surface emitting laser array can be provided.

  The surface emitting laser array has high output, high oscillation speed, and high reliability as a microchip laser, and can be accommodated in a size incorporated in an engine of a vehicle, a ship, an aircraft, a spacecraft, or the like.

  In addition, since the surface emitting laser array can emit a plurality of laser beams, the degree of freedom of the ignition position (ignition point) is high, and it is also high in the nanosecond region of an extremely short pulse that easily ignites the mixed gas (combustion gas). It is possible to output. Also, the ignition point can be set at a free location in the combustion chamber by adjusting the condensing position of the laser beam.

  The conventional spark plug is limited to ignition from the position of the discharge electrode, but the above surface emitting laser array can ignite to the optimum spatial position. This is a great advantage because the optimal ignition position can be set in a lean combustion method for the purpose of improving fuel efficiency.

  Below, the thought process which the inventors came to invent each said embodiment and each modification is demonstrated.

  One of the steps for producing a VCSEL array is a step of forming an electrode wiring for injecting a current into the VCSEL element. Since current-confined VCSEL devices inject current from the top of the mesa shape, the upper electrode must be routed over a large mesa step, causing disconnection and poor reliability due to insufficient wiring step coverage. It was.

  In addition, when VCSEL elements are arrayed on a large scale, for example, when 10000 or more VCSEL elements are integrated to produce an output of 100 W or more, it is necessary to drive with a large current exceeding 50 A. In such a device, when the wiring thickness is thin, the output of the laser is saturated due to heat generated by the resistance of the wiring section during driving, and thus insufficient step coverage of the wiring has hindered high laser output.

As a method to eliminate this step coverage shortage,
Patent Document 1 discloses a configuration in which the entire mesa side wall is covered with p-side electrode wiring.
Patent Document 2 discloses a method of improving step coverage by a configuration in which a mesa step is flattened with polyimide.
・ Non-patent literature: <Progress in high-power high-efficiency VCSEL arrays> Proc. Of SPIE Vol.7229 722903-1 has step coverage with a structure in which a wiring thicker than a mesa step is formed by a plating method with good step coverage. Is disclosed.

  However, even when the p-side electrode wiring is formed on the entire surface of the mesa side wall as in Patent Document 1, it cannot be solved that the wiring film thickness of the step coverage portion is small. Further, since the internal stress of the electrode acts on the entire mesa, a reliability failure is likely to occur.

  In the case of the configuration of Patent Document 2, since the internal stress due to the contraction of polyimide is large, a crystal defect is induced and causes a reliability defect.

  In the case of the above-mentioned non-patent document, it is possible to achieve a high output operation because the heat generation due to the wiring resistance is suppressed by eliminating the small wiring film thickness of the step coverage part, but the periphery of the mesa side is covered with a thick wiring metal. Thus, similarly to Patent Document 1, a reliability failure is likely to occur.

  Therefore, the inventors have devised the above embodiments and modifications in order to solve the above-described problems (in particular, to suppress poor reliability).

  DESCRIPTION OF SYMBOLS 10, 20, 30, 40, 50 ... Surface emitting laser array, 10a, 20a, 30a, 40a, 50a ... Light emitting part (surface emitting laser), 101 ... Substrate, 110 ... P-side electrode wiring layer, 110a, 210a, 310a ... 1st wiring layer, 110b, 210b, 310b ... 2nd wiring layer, 1500 ... Laser annealing apparatus (laser processing machine), 2000 ... Laser cutting machine (laser processing machine), 3000 ... Laser display apparatus (display apparatus) ).

Japanese Patent No. 5087874 JP 2005-191343 A

Claims (18)

A laminate including a substrate, a first reflecting mirror laminated on the substrate, an active layer laminated on the first reflecting mirror, and a second reflecting mirror laminated on the active layer In a surface emitting laser including a mesa structure formed by etching
In the laminate in which the mesa structure is formed, an electrode wiring layer is laminated on at least a part of the mesa structure excluding a central portion on the upper surface and connected to a peripheral portion on the upper surface of the mesa structure Further comprising
The surface emitting laser according to claim 1, wherein a thickness of the electrode wiring layer is thicker than a height of the mesa structure.   2. The surface emitting laser according to claim 1, wherein the upper surface of the electrode wiring layer is located farther from the substrate than the upper surface of the mesa structure.   The surface emitting laser according to claim 1, wherein a stress relaxation portion is provided in the vicinity of the side of the mesa structure inside the electrode wiring layer.   4. The surface emitting laser according to claim 3, wherein the stress relaxation portion is made of a material having a smaller thermal expansion coefficient than the material of the electrode wiring layer. An insulating layer is disposed between the stacked body in which the mesa structure is formed and the electrode wiring layer,
5. The surface emitting laser according to claim 3, wherein the stress relaxation part is made of the same material as the insulating layer.   6. The surface emitting laser according to claim 5, wherein the material of the insulating layer is any one of SiOx, SiNx, SiOxNy, and TiOx, where x and y are natural numbers.   4. The surface emitting laser according to claim 3, wherein the stress relaxation part is a hole formed in the electrode wiring layer. The mesa structure has an overhang portion at the bottom,
The surface emitting laser according to claim 7, wherein the hole is formed at a location corresponding to the overhang portion in the electrode wiring layer. The mesa structure has a recess formed on a side surface,
The surface emitting laser according to claim 7, wherein the hole is formed at a location corresponding to the concave portion inside the electrode wiring layer.   A surface-emitting laser array comprising a plurality of surface-emitting lasers according to any one of claims 1 to 9.   A laser processing machine comprising the surface emitting laser array according to claim 10.   A laser ignition device for an engine, comprising the surface emitting laser array according to claim 10. In a display device that displays information using laser light,
A display device comprising the surface-emitting laser array according to claim 10 that emits the laser light. A step of sequentially laminating a first reflecting mirror, an active layer, and a second reflecting mirror on a substrate to produce a laminate;
Etching the laminate to form a mesa structure;
Forming a current confinement layer in the mesa structure;
Forming an insulating film having a contact hole on the upper surface of the mesa structure on the stacked body in which the current confinement layer is formed in the mesa structure;
Forming a first wiring layer on the insulating film and in the periphery of the contact hole;
Forming a dielectric film near a side of the mesa structure in the first wiring layer;
Forming a second wiring layer so as to cover the dielectric film on the first wiring layer. The step of forming the dielectric film includes a sub-step of laminating a dielectric layer on the first wiring layer and in the center of the contact hole,
The surface emitting laser array according to claim 14, further comprising: a sub-process for removing at least a part other than the dielectric film, which is a portion of the dielectric layer near the side of the mesa structure. Manufacturing method.   16. The method of manufacturing a surface emitting laser array according to claim 15, wherein, in the removing sub-step, a portion of the dielectric layer at a central portion of the contact hole is not removed at a peripheral portion of the central portion. . A step of sequentially laminating a first reflecting mirror, an active layer, and a second reflecting mirror on a substrate to produce a laminate;
Etching the laminate to form a mesa structure having an overhang portion at the bottom;
Forming a current confinement layer in the mesa structure;
Forming an insulating film having a contact hole on the upper surface of the mesa structure on the stacked body in which the current confinement layer is formed in the mesa structure;
Forming a wiring layer on the insulating film and in the peripheral portion of the contact hole. A step of sequentially laminating a first reflecting mirror, an active layer, and a second reflecting mirror on a substrate to produce a laminate;
Etching the laminate to form a mesa structure;
Forming a current confinement layer in the mesa structure;
Forming a recess on a side surface of the mesa structure;
Forming an insulating film having a contact hole on the upper surface of the mesa structure on the stacked body in which the current confinement layer is formed in the mesa structure;
Forming a wiring layer on the insulating film and in the peripheral portion of the contact hole.

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