JP2017075980A - Circuit device, electro-optical device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit device, an electro-optical device, an electronic device, and the like capable of suppressing an adverse effect of writing a data voltage on one adjacent pixel on a holding voltage of the other pixel in a dual gate structure display panel Provided.
A circuit device includes first and second pixel groups selected by first and second scanning lines, and a plurality of pixels are formed by any pixel of a first pixel group and any pixel of a second pixel group. It includes a drive unit 60 and a control unit 20 that drive a display panel in which each data line of the data lines is shared and drive the display panel based on display data. The driving unit 60 writes the second pixel data voltage to the second pixel that is a pixel of the second pixel group in the voltage writing period by scanning the second scanning line, and the first scanning period in which the first scanning line is selected. In addition, the first pixel data voltage is written to the first pixel which is a pixel of the first pixel group, and the second pixel data voltage is written to the second pixel in the second scanning period in which the second scanning line is selected. .
[Selection] Figure 1

Description

  The present invention relates to a circuit device, an electro-optical device, an electronic apparatus, and the like.

  Currently, color liquid crystal panels (display panels) are often used in electronic devices such as monitors, TVs, and notebook computers. Among them, Patent Document 1 and Patent Document 2 disclose an active matrix display device having a so-called dual gate structure display panel. The display panel having a dual gate structure is a panel having a structure in which one data line is shared by the first pixel selected by the first scanning line and the second pixel selected by the second scanning line. Such a dual-gate display panel has the advantage that the number of data lines can be halved and the apparatus can be reduced in size and cost.

  However, in a display panel having a dual gate structure, writing a data voltage to one adjacent pixel may adversely affect the holding voltage of the other pixel (for example, vertical stripes may be seen on the display screen). is there. This is because parasitic capacitance is generated between adjacent pixels, and the adjacent first and second pixels are written in a time division manner with one data line.

  On the other hand, in the prior art of Patent Document 1, the problem of the vertical stripe is solved by devising the panel structure. Specifically, the problem of vertical stripes is solved by devising the connection configuration of the first scanning line and the second scanning line to odd-numbered pixels and even-numbered pixels. Patent Document 2 discloses a display panel having a dual gate structure, which is different from Patent Document 1 in the connection configuration of the first scanning line and the second scanning line to odd and even pixels.

Japanese Patent Laid-Open No. 10-73843 Japanese Patent Laid-Open No. 10-142578

  However, in Patent Document 1 and Patent Document 2 described above, only when the disclosed dual-gate structure display panel is used, it is possible to cope with the problem of visible vertical stripes, and other dual-gate structure display panels are used. In some cases, the problem of visible vertical stripes could not be addressed.

  According to some embodiments of the present invention, in a display panel having a dual gate structure, a circuit device capable of suppressing an adverse effect of writing of a data voltage on one adjacent pixel on a holding voltage of the other pixel, An electro-optical device, an electronic device, and the like can be provided.

  According to one embodiment of the present invention, a first pixel group selected by the first scan line out of a first scan line and a second scan line provided corresponding to the display line, and the second scan line are selected. And a second pixel group, and a circuit for driving a display panel in which each data line of the plurality of data lines is shared by any pixel of the first pixel group and any pixel of the second pixel group A driving unit that drives a display panel based on display data; and a control unit that controls the driving unit, wherein the driving unit includes a voltage writing period based on scanning of the second scanning line. A second pixel data voltage is written to a second pixel that is a pixel of the second pixel group, and the pixel of the first pixel group is in the next first scanning period when the first scanning line is selected. Write the data voltage for the first pixel to the first pixel A next scanning period of the first scan period, the second scanning period in which the second scanning line is selected, related to the circuit device to write the second pixel data voltage to the second pixel.

  In one embodiment of the present invention, the second pixel data voltage is once written in the second pixel, the first pixel data voltage is written in the first pixel, and then the second pixel data voltage is again applied to the second pixel. Write. Therefore, in a display panel having a dual gate structure, it is possible to suppress an adverse effect of the writing of the data voltage to one adjacent pixel on the holding voltage of the other pixel.

  In the aspect of the invention, the length of the voltage writing period may be shorter than the length of the second scanning period.

  This also makes it possible to shorten the length of one frame, increase the number of pixels, and the like.

  In the aspect of the invention, the driving unit may make the first scanning line and the second scanning line in a non-selected state between the voltage writing period and the first scanning period.

  Accordingly, the drive unit can change the output voltage from the given voltage to the first pixel data voltage during the non-selected state.

  In the aspect of the invention, the length of the second scanning period may be shorter than the length of the first scanning period.

  This also makes it possible to shorten the length of one frame, increase the number of pixels, and the like.

  In the aspect of the invention, the driving unit may supply the second pixel data voltage to the first pixel and the second pixel in the voltage writing period when the first pixel and the second pixel have the same polarity. You may write in 2 pixels.

  Accordingly, when the polarity of the first pixel data voltage and the polarity of the second pixel data voltage in a certain frame are the same polarity, the writing time of the first pixel data voltage and the writing time of the second pixel data voltage Etc. can be shortened.

  In the aspect of the invention, the driving unit includes a driving circuit provided corresponding to the first data line and the second data line of the plurality of data lines, and the driving circuit outputs a positive voltage. A positive polarity amplifier, a negative polarity amplifier that outputs a negative voltage, and a first voltage line that outputs an output voltage from one of the positive polarity amplifier and the negative polarity amplifier to the first data line. One switch circuit and a second switch circuit that outputs an output voltage from the other amplifier different from the one to the second data line may be included.

  As a result, each drive circuit included in the data line drive unit can drive the two data lines with opposite polarities.

  Another aspect of the invention relates to an electro-optical device including the circuit device and the display panel.

  Another aspect of the invention relates to an electronic apparatus including the circuit device.

Explanatory drawing of the structural example of the circuit apparatus of this embodiment. Explanatory drawing of the display panel of the 1st dual gate structure. FIG. 10 is another explanatory diagram of a display panel having a first dual gate structure. Explanatory drawing of the display panel of the 2nd dual gate structure. Explanatory drawing of the display panel of the 3rd dual gate structure. Explanatory drawing of the process which writes a given voltage in a voltage writing period. Explanatory drawing of a process in case a given voltage is not written in a voltage writing period. FIG. 11 is another explanatory diagram of processing when a given voltage is not written during a voltage writing period. Explanatory drawing of the process which writes the given voltage for positive polarity in a voltage writing period. Explanatory drawing of the process which writes a given voltage to a 1st pixel and a 2nd pixel in a voltage writing period. Explanatory drawing of the process which writes the data voltage for 2nd pixels in a voltage writing period. Explanatory drawing of the detailed structural example of a data line drive part. FIG. 3 is an explanatory diagram of a detailed configuration example of a drive circuit. 14A and 14B are explanatory diagrams of a detailed configuration example of the positive polarity amplifier circuit. 15A and 15B are explanatory diagrams of a detailed configuration example of the negative polarity amplifier circuit. FIG. 3 is an explanatory diagram of a configuration example of an electro-optical device. Explanatory drawing of the structural example of an electronic device.

  Hereinafter, this embodiment will be described. In addition, this embodiment demonstrated below does not unduly limit the content of this invention described in the claim. In addition, all the configurations described in the present embodiment are not necessarily essential configuration requirements of the present invention.

1. Circuit Device FIG. 1 shows a configuration example of a circuit device 100 (display driver) according to this embodiment. The circuit device 100 includes an interface unit 10 (interface circuit), a control unit 20 (data processing unit, data processing circuit), a driving unit 60 (driving circuit), a first color component input terminal TRD, a second color component input terminal TGD, Including third color component input terminal TBD, clock input terminal TPCK, interface terminal TMPI, data line drive terminals TS1 to TSn (n is an integer of 2 or more), gate line drive terminals TG1 to TGm (m is an integer of 2 or more) . The drive unit 60 includes a data line drive unit 40 (data line drive circuit) and a gate line drive unit 50 (gate line drive circuit). The circuit device 100 is realized by, for example, an integrated circuit device (IC). Note that the circuit device 100 is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of these components or adding other components are possible.

  The interface unit 10 performs communication with an external processing device (display controller, such as an MPU, a CPU, or an ASIC). The communication includes, for example, transfer of display data (image data), supply of a clock signal and a synchronization signal, transfer of a command (or control signal), and the like. Further, the interface unit 10 is configured by, for example, an I / O buffer or the like.

  The control unit 20 performs display data processing, timing control, control of each part of the circuit device 100, and the like based on display data, a clock signal, a synchronization signal, a command, and the like input via the interface unit 10. In the data processing of the display data, for example, image processing such as correction processing of gradation indicated by each color component display data is performed. In the timing control, the driving timing (selection timing) of the scanning lines (gate lines) of the display panel and the driving timing of the data lines are controlled based on the synchronization signal and display data. The data processing unit 20 is configured by a logic circuit such as a gate array, for example.

  The drive unit 60 drives the display panel based on the color component display data obtained from the control unit 20 and a plurality of gradation voltages corresponding to the color component display data.

  As will be described later with reference to FIG. 13, the data line driving unit 40 of the driving unit 60 includes a gradation voltage generation circuit 42, a D / A conversion unit, and a plurality of driving circuits provided corresponding to a plurality of data line driving terminals. And including.

  The gradation voltage generation circuit 42 generates a plurality of gradation voltages and outputs them to the D / A converter. For example, each generated gradation voltage (V0 to V255) corresponds to each gradation (0 to 255) of a plurality of gradations. For example, the gradation voltage generation circuit 42 is configured with a ladder resistor or the like. The D / A converter converts the display data (input gradation) from the controller 20 into a gradation voltage (data voltage). The D / A conversion unit includes a D / A conversion circuit (a plurality of voltage selection circuits), and is configured by, for example, a switch circuit. The D / A conversion circuit selects a gradation voltage corresponding to display data (input gradation) from the plurality of gradation voltages from the gradation voltage generation circuit.

  The plurality of drive circuits output the data line drive voltages (data voltages) SV1 to SVn to the data line drive terminals TS1 to TSn based on the gradation voltage from the D / A converter, and drive the data lines of the display panel. . Each voltage of the data line drive voltages SV1 to SVn is a voltage supplied to each terminal of the data line drive terminals TS1 to TSn. As each of the data line drive voltages SV1 to SVn, any one of the gradation voltages generated by the gradation voltage generation circuit 42 is selected by the D / A converter based on the display data. Each drive circuit is provided corresponding to two (or a plurality) of data line drive terminals, and the data line drive circuit drives two data lines in a time division manner. The detailed configuration of the plurality of drive circuits of the data line drive unit 40 will be described later with reference to FIGS.

  As shown in FIG. 1, the gate line driving unit 50 of the driving unit 60 outputs the gate line driving voltages GV1 to GVm to the gate line driving terminals TG1 to TGm, and drives (selects) the scanning lines of the display panel. In a dual gate display panel, two scanning lines are selected in a time division manner in one horizontal scanning period. The gate line driving unit 50 includes, for example, a plurality of voltage output circuits (buffers, amplifiers), and one voltage output circuit is provided corresponding to each gate line driving terminal, for example.

2. Display Panel Next, a display panel used in this embodiment is shown in FIG. In the present embodiment, a description will be given taking a dual-gate display panel as an example among active matrix display panels (for example, TFT liquid crystal panels). FIG. 2 shows a configuration example of a color display panel driven by the circuit device 100 and shows a part of the pixel array. Note that the circuit device 100 of this embodiment can be applied not only to a liquid crystal panel but also to a self-luminous panel (for example, an organic EL panel).

  As shown in FIG. 2, the display panel used in the present embodiment includes a first scanning line (first gate line) G1 and a second scanning line (second gate line) G2 provided corresponding to the display line. The first pixel group (PX11, PX13, PX15, PX17) selected by the first scanning line G1 and the second pixel group (PX12, PX14, PX16, PX18) selected by the second scanning line G2. A panel in which each data line of a plurality of data lines (S1, S2, S3,...) Is shared by any pixel in the first pixel group and any pixel in the second pixel group. The same applies to pixels connected after the third scanning line G3 and the fourth scanning line G4. In other words, in a dual gate structure display panel, the data lines are shared by the pixels of the first pixel group and the pixels of the second pixel group which are adjacent to each other across a certain data line. In the pixel array, for example, a pixel in the first row and the second column is denoted by reference numeral PX12. “Row” is a line in the horizontal scanning direction, and “Column” is a line in the vertical scanning direction.

  The data line is commonly connected to two pixels in each horizontal display line. For example, in the first horizontal display line, the data line S1 is connected to the pixels PX11 and PX12, and the data line S2 is connected to the pixels PX13 and PX14. Two scanning lines are provided for each horizontal display line. One of the two scanning lines is connected to one of the two pixels connected to one data line, and two of the two pixels connected to the one data line are connected to two of the two pixels. The other of the scanning lines is connected. For example, the first horizontal display line is provided with the scanning lines G1 and G2, the scanning line G1 is connected to the pixel PX11 among the pixels PX11 and PX12 connected to the data line S1, and the scanning line G2 is connected to the pixel PX12. The

  For example, in the horizontal scanning period for driving the first horizontal display line, the circuit device 100 selects the scanning lines G1 and G2 in a time division manner during the horizontal scanning period. During the period when the scanning line G1 is selected, the gradation voltages of the pixels PX11, PX13, PX15, and PX17 are output to the data lines S1, S2, S3, and S4, and writing to the pixels PX11, PX13, PX15, and PX17 is performed. I do. During the period when the scanning line G2 is selected, the gradation voltages of the pixels PX12, PX14, PX16, and PX18 are output to the data lines S1, S2, S3, and S4, and writing to the pixels PX12, PX14, PX16, and PX18 is performed. .

  In the display panel shown in FIG. 2, in the first horizontal display line, a negative data voltage is written to the pixels of the first pixel group in the first frame, and the voltage to be written in the next second frame. And the positive data voltage is written to the pixels of the first pixel group. Also in the subsequent frames, the polarity is inverted for each frame and the voltage is written to each pixel. On the other hand, for the pixels of the second pixel group, a positive data voltage is written in the first frame, and a negative data voltage is written in the next second frame. Also in the subsequent frames, the polarity is inverted for each frame and the voltage is written to each pixel. Further, in the second and subsequent horizontal display lines, the polarity is reversed for each horizontal display line.

  However, the present embodiment is not limited to the polarity inversion pattern (voltage writing pattern) as shown in FIG. 2, and can be applied to, for example, the polarity inversion pattern as shown in FIG. The display panel shown in FIG. 3 has the same configuration as the display panel shown in FIG. 2, but the polarity inversion pattern is different from that of the display panel shown in FIG.

  Specifically, in the display panel shown in FIG. 3, the polarity is inverted every two columns. That is, in the first frame, the negative data voltage is written to PX11, PX12, PX15, PX16, PX23, PX24, PX27, PX28, PX31, PX32, PX35, PX36, and PX13, PX14, PX17, PX18. , PX21, PX22, PX25, PX26, PX33, PX34, PX37, PX38 are written with positive data voltages. For the second and subsequent frames, a data voltage in which all the polarities are inverted is written to each pixel.

  For example, when the display panel is a color display panel as shown in FIG. 2, one pixel (pixel) is constituted by three subpixels. That is, in the first horizontal display line, the subpixels PX11, PX12, and PX13 constitute one pixel, and the subpixels PX14, PX15, and PX16 constitute another one pixel. The same applies to the second and subsequent horizontal display lines. Each pixel includes RGB sub-pixels. For example, the sub-pixel PX11 is a sub-pixel provided with a first color (R) color filter, the sub-pixel PX12 is a sub-pixel provided with a second color (G) color filter, and the sub-pixel PX13. Are sub-pixels provided with a color filter of the first color (B).

  For example, in the circuit device 100, the interface unit 10 receives the RGB display data RD, GD, and BD, and the control unit 20 outputs the RGB display data RQ1, GQ1, and BQ1, and drives the gradation voltages corresponding to them. The unit 60 writes to the subpixels PX11, PX12, and PX13. In this way, RGB gradation voltages are written to each sub-pixel, and a color image is displayed on the display panel.

  The display data RD, GD, and BD are, for example, display data for R, G, and B, respectively. The first color component input terminal TRD, the second color component input terminal TGD, and the like shown in FIG. This is display data input to the interface unit 10 from the third color component input terminal TBD. For example, when the display panel is controlled with 256 gradations, each color component display data includes information indicating any gradation between 0 and 255, for example. Note that the present embodiment is not limited to 256 gradations.

  For example, when the display data RD of one pixel (or one subpixel) is 8 bits (up to 8 bits), the input terminal TRD is actually 8 terminals, and 8 bits from the 8 terminals. Display data RD is input. At this time, display data RD of a plurality of pixels is serially input in synchronization with a clock signal PCK (pixel clock) input from the clock input terminal TPCK. The same applies to the display data GD and BD.

  The display data RQ1, GQ1, and BQ1 are output data of the data processing unit 20, and are display data corresponding to the pixels of the display panel. For example, in the case of the color display panel of FIG. 2, the display data RQ1, GQ1, and BQ1 are the first color (red) subpixel PX11, the second color (green) subpixel PX12, and the third color (blue) subpixel. Corresponds to PX13. However, the display panel to which the circuit device 100 of this embodiment can be applied is not limited to a color display panel, and may be a monochrome display panel in which each of PX11 and PX12 is a pixel.

  By using such a display panel, it is possible to reduce the number of data lines of the display panel and to realize a reduction in size and cost of the device. Note that this embodiment can be applied not only to the dual-gate display panel shown in FIG. 2 but also to other dual-gate display panels. For example, the present embodiment can be applied to a display panel having a dual gate structure shown in FIGS.

  In the configuration example shown in FIG. 4, the first display lines (PX11 to PX18) have the same connection configuration as the configuration example of FIG. In the configuration example of FIG. 4, the pixels PX22, PX24, PX26, and PX28 are connected to the scanning line G3 in the second display lines (PX21 to PX28). Then, the pixels PX21, PX23, PX25, and PX27 are connected to the scanning line G4. Further, the pixel PX22 and the pixel PX21 are commonly connected to the data line S1, and the pixel PX24 and the pixel PX23 are commonly connected to the data line S2.

  Further, in the configuration example shown in FIG. 5, in the first display lines (PX11 to PX18), the pixels PX11, PX14, PX15, and PX18 are connected to the scanning line G1 and correspond to the first pixel group. Pixels PX12, PX13, PX16, and PX17 are connected to the scanning line G2 and correspond to the second pixel group. In the second display lines (PX21 to PX28), the pixels PX22, PX23, PX26, and PX27 are connected to the scanning line G3, and the pixels PX21, PX24, PX25, and PX28 are connected to the scanning line G4. Further, the pixel PX11 of the first pixel group and the pixel PX12 of the second pixel group are commonly connected to the data line S1, and the pixel PX14 of the first pixel group and the pixel PX13 of the second pixel group are commonly connected to the data line S2. . Further, the pixel PX22 and the pixel PX21 are commonly connected to the data line S1, and the pixel PX23 and the pixel PX24 are commonly connected to the data line S2. Various other modifications are possible.

  In the description above and below, the plurality of pixels selected by the scanning lines G1 provided corresponding to the first display lines (PX11 to PX18) are defined as the first pixel group, and the first display lines (PX11 to PX18). ), A plurality of pixels selected by the scanning line G2 provided corresponding to the second pixel group are described as the second pixel group, but the present embodiment is not limited to this. For example, a plurality of pixels selected by the scanning line G3 provided corresponding to the second display lines (PX21 to PX28) are set as the first pixel group, and provided corresponding to the second display lines (PX21 to PX28). A plurality of pixels selected by the scanning line G4 may be set as the second pixel group.

3. First Example Next, a first example will be described. FIG. 6 shows, for example, the time series change of the gate line driving voltage supplied to the scanning lines (G1 to G4) and the data voltage supplied to the pixels PX12, PX13, and PX14 when the display panel shown in FIG. 2 is used. The relationship of time series changes is shown. In this example, as shown in FIG. 6, the gate line driving voltage is supplied in order from the scanning line G1 to the scanning line G4. In the example of FIG. 6, the holding voltage in the initial state of the pixels PX12, PX13, and PX14 is the ground GND (indicated by a dotted line), but the present embodiment is not limited to this. The same applies to the examples of FIGS.

  As illustrated in FIG. 6, in the present embodiment, the drive unit 60 outputs the output voltage range of the drive unit 60 to the second pixels (for example, PX12 and PX14) that are pixels of the second pixel group in the voltage writing period TMP. Write a given voltage VM between a first voltage and a second voltage that defines Then, after the given voltage VM is written, the driving unit 60 applies the first pixel (for example, PX13) that is a pixel of the first pixel group in the first scanning period TM1 in which the first scanning line G1 is selected. On the other hand, the first pixel data voltage is written. Next, the driving unit 60 is the next scanning period after the first scanning period TM1, and in the second scanning period TM2 in which the second scanning line G2 is selected, the driving unit 60 performs the second scanning with respect to the second pixel (for example, PX12, PX14). Write data voltage for 2 pixels.

  Here, the comparative example of this example is demonstrated using FIG.7 and FIG.8. For example, FIG. 7 shows an example in which a data voltage is written in the voltage writing pattern shown in FIG. In the example of FIG. 7, the driving unit 60 writes the first pixel data voltage to the first pixel (for example, PX13) that is a pixel of the first pixel group in the first scanning period TM1, and the second scanning period TM2 , The second pixel data voltage is written to the second pixel (for example, PX12, PX14).

  Further, as shown in FIG. 2, in the dual gate display panel, a parasitic capacitance is generated between adjacent pixels (sub-pixels). Due to this parasitic capacitance, when the second pixel data voltage is written to the second pixel (PX12, PX14), as shown at P1 in FIG. 7, the first pixel PX13 adjacent to these second pixels The holding voltage drops by Δ1. In FIG. 7, since the second pixel (PX12, PX14) changes from positive polarity to negative polarity, the holding voltage of the first pixel PX13 decreases, but the second pixel (PX12, PX14) changes from negative polarity to positive polarity. In this case, the holding voltage of the first pixel PX13 increases. Thus, when the holding voltage of the first pixel PX13 rises or falls, the color displayed on the display screen appears to change.

  As described above, in the color display panel, three adjacent pixels (subpixels) in one display line are RGB pixels. In this case, in the pixel composed of the RGB pixels PX11, PX12, and PX13, the holding voltage of the R pixel PX11 and the B pixel PX13 in the first line drops by, for example, Δ1 in the second scanning period TM2 described above. Further, in the pixel constituted by the adjacent RGB pixels PX14, PX15, and PX16, the holding voltage of the G pixel PX15 in the first line drops by Δ1 in the second scanning period TM2 described above. That is, the color in which the voltage drops in each RGB pixel (the position of the first line) is different, and this causes the display screen to appear to have vertical stripes.

  Similarly, for example, FIG. 8 shows an example in which a voltage is written using the voltage writing pattern shown in FIG. In the case of FIG. 8, when the second pixel data voltage is written to the second pixel (PX12, PX14), as shown in P2, due to the parasitic capacitance between adjacent pixels (subpixels), The holding voltage of one pixel PX13 increases by Δ2. As a result, the display screen appears to have vertical stripes.

  On the other hand, in the present embodiment, as described above with reference to FIG. 6, the drive unit 60 writes a given voltage VM to the second pixel (PX12, PX14) in the voltage writing period TMP. Thereafter, the first pixel data voltage is written to the first pixel PX13 in the first scanning period TM1, and the second pixel data voltage is written to the second pixels (PX12, PX14) in the second scanning period TM2. .

  As a result, as shown in FIG. 6, at the start of the first scanning period TM1, the holding voltage of the second pixel (PX12, PX14) is already at VM. Therefore, it is possible to reduce the voltage fluctuation amount of the second pixels (PX12, PX14) in the second scanning period TM2. Thereby, as shown in P5, the voltage fluctuation amount of the first pixel PX13 in the second scanning period can be suppressed to Δ5 smaller than Δ1 in FIG. 7 and Δ2 in FIG. Compared to the examples of FIGS. 7 and 8, it is also possible to shorten the time for writing a desired second pixel data voltage to the second pixel (PX12, PX14) in the second scanning period TM2.

  As indicated by P3 and P4 in FIG. 6, in the first scanning period TM1, as the first pixel data voltage is supplied to the first pixel PX13, the holding voltage of the second pixel PX12 (PX14) is Δ3. May increase by (Δ4). However, even if there is such a voltage fluctuation, the holding voltage of the second pixel PX12 (PX14) is only VM + Δ3 (or VM + Δ4) at the start of the second scanning period TM2. That is, since the voltage fluctuation amount Δ3 (Δ4) of the second pixel PX12 (PX14) in the first scanning period TM1 is very small, even if there is a voltage fluctuation as shown in P3 and P4, in the second scanning period TM2. By writing the data voltage for the second pixel, the voltage fluctuation of Δ3 (Δ4) can be canceled, and the voltage fluctuation amount of the second pixel PX12 (PX14) in the second scanning period TM2 is not greatly affected. Therefore, it is possible to suppress fluctuations in the holding voltage of the first pixel PX13 in the second scanning period TM2.

  Thereby, in the display panel having a dual gate structure, it is possible to suppress an adverse effect of the writing of the data voltage to one adjacent pixel (first pixel) on the holding voltage of the other pixel (second pixel). Become. Accordingly, it is possible to suppress the occurrence of vertical stripes on the display screen. This process can be applied regardless of the type of the dual gate structure of the display panel.

  That is, in the present embodiment, in the voltage writing period TMP, the given voltage VM is written to the second pixel (PX12, PX14), so that the second pixel (PX12, PX14) is charged in advance to the given voltage VM. it can. Therefore, in the second scanning period TM2, it is only necessary to charge the differential voltage between the second pixel data voltage and the given voltage VM, so that the voltage fluctuation of the holding voltage of the second pixel (PX12, PX14) is optimally reduced. it can. Since the voltage fluctuation in the second pixel (PX12, PX14) can be reduced in this way, the writing of the data voltage to the second pixel (PX12, PX14) in the second scanning period TM2 is the holding voltage of the first pixel PX13. Can be reduced. Thereby, generation | occurrence | production of the vertical stripe etc. resulting from the parasitic capacitance between pixels etc. can be suppressed.

  In the dual-gate structure display panel, the data voltage writing period (scanning line scanning period) per pixel is shortened instead of halving the number of data lines. For this reason, writing of the data voltage may not be in time, and the pixel may not be fully charged.

  On the other hand, in this embodiment, by precharging with a given voltage VM, the time for writing the data voltage to the second pixel can be shortened, and it is possible to fully charge to a desired voltage. become.

  Further, the given voltage VM written to the second pixel in the voltage writing period TMP is a voltage between the first voltage and the second voltage that defines the output voltage range of the driving unit 60. Specifically, when the first voltage is VH, the second voltage is VL, and VH> VL, the given voltage VM is VL + 1/3 × (VH−VL) <VM <VH−1 / 3 × (VH−VL). More specifically, the output voltage range is a voltage range that defines the gradation voltage output from the data line driving unit 40, and the first voltage is, for example, the upper limit voltage of the gradation voltage output from the data line driving unit 40 The second voltage is a lower limit voltage of the gradation voltage output from the data line driving unit 40, for example. The given voltage is, for example, an intermediate voltage between the upper limit voltage and the lower limit voltage of the gradation voltage.

  Accordingly, for example, in the voltage writing period TMP, it is possible to reduce the dependence of the voltage fluctuation on the display data on the display data compared to the case where the pixel data voltage is written to the second pixel.

  A specific example is shown. For example, it is assumed that the first voltage is 0V and the second voltage is −6V. In this case, when the pixel data voltage is written to the second pixel in the voltage writing period TMP, the holding voltage of the second pixel may vary up to ± 6 V in the second scanning period TM2. On the other hand, in this example, for example, -3V, which is intermediate between the first voltage 0V and the second voltage -6V, is written as a given voltage in the voltage writing period TMP. In this case, the voltage fluctuation in the second scanning period TM2 can be suppressed to ± 3V at the maximum.

  Thus, in order to prevent vertical stripes from being generated on the display screen, it is important to reduce the voltage fluctuation in the second scanning period TM2 as much as possible. Here, for example, consider the case where the same voltage (for example, +3 V) is written in the voltage writing period regardless of the polarity of the second pixel data voltage written in the second scanning period TM2. At this time, for example, the positive output voltage range is set to 0V to + 6V, and the negative output voltage range is set to -6V to 0V. In this case, when writing the positive second pixel data voltage in the second scanning period TM2, the voltage fluctuation of the second pixel can be suppressed to ± 3 V at the maximum, but in the second scanning period TM2, the negative polarity second voltage is suppressed. When the data voltage for two pixels is written, the voltage variation of the second pixel becomes −9V at the maximum.

  Therefore, in the present embodiment, as shown in FIG. 9, the drive unit 60 writes the voltage when writing the positive second pixel data voltage to the second pixel (PX12, PX14) in the second scanning period TM2. In the period TMP, a given voltage for positive polarity between the first positive polarity voltage and the positive second voltage defining the positive output voltage range of the drive unit 60 is set to the second pixel (PX12, PX14). ) For example, when the positive first voltage is + 6V that is the upper limit voltage of the gradation voltage and the second positive voltage is 0 V that is the lower limit voltage of the gradation voltage (positive output voltage range 0V to In + 6V), + 3V, which is intermediate between the first positive polarity voltage and the second positive polarity voltage, is written in the second pixel (PX12, PX14) as a given positive polarity voltage. Therefore, for example, in this example, when the positive second pixel data voltage is written to the second pixel (PX12, PX14) in the second scanning period TM2, the voltage variation of the second pixel in the second scanning period TM2 is changed. It can be suppressed to ± 3V at maximum.

  On the other hand, as shown in FIG. 6 described above, when the driving unit 60 writes the negative second pixel data voltage to the second pixels (PX12, PX14) in the second scanning period TM2, the voltage writing period TMP is used. , A given voltage for negative polarity between the first negative polarity voltage and the second negative polarity voltage defining the negative output voltage range of the driving unit 60 is applied to the second pixel (PX12, PX14). Write. For example, when the negative polarity first voltage is 0 V that is the upper limit voltage of the gradation voltage and the negative polarity second voltage is -6 V that is the lower limit voltage of the gradation voltage (negative output voltage range− 6V to 0V), -3V between the negative first voltage and the negative second voltage is written to the second pixel (PX12, PX14) as a given negative voltage. Therefore, for example, in this example, even when a negative second pixel data voltage is written to the second pixel (PX12, PX14) in the second scanning period TM2, the voltage variation of the second pixel in the second scanning period TM2 is also performed. Can be suppressed to ± 3V at the maximum.

  As a result, voltage fluctuations in the second scanning period TM2 are caused both in the case of writing the positive second pixel data voltage in the second scanning period TM2 and in the case of writing the negative second pixel data voltage. It becomes possible to make it smaller.

  For example, when the polarity of the first pixel data voltage written in the first scanning period TM1 is opposite to the polarity of a given voltage written in the voltage writing period TMP, the output voltage is once returned to the ground voltage. Later, it is necessary to set the data voltage for the first pixel. At this time, if an unnecessary ground voltage is written to the second pixel after a given voltage is written to the second pixel, the meaning of writing the given voltage is lost. Therefore, it is preferable that an unnecessary ground voltage is not written in the second pixel. The same applies to the first pixel.

  Therefore, the driving unit 60 puts the first scanning line G1 and the second scanning line G2 into a non-selected state between the voltage writing period TMP and the first scanning period TM1. For example, as shown in FIG. 6, in the period TMOFF, the first scanning line G1 and the second scanning line G2 are brought into a non-selected state.

  Accordingly, the drive unit can change the output voltage from the given voltage to the first pixel data voltage during the non-selected state. For example, when the polarities of the first pixel and the second pixel are different, a given voltage in the voltage writing period and the first pixel data voltage in the first scanning period have opposite polarities, but the driving circuit is in the non-selected state period. Can change the polarity of the output voltage. Thereby, for example, it is possible to prevent unnecessary ground voltages from being written to the first pixel and the second pixel after a given voltage is written to the second pixel. Further, for example, after the voltage writing period, the first scanning line G1 and the second scanning line G2 are always in a non-selected state, thereby facilitating control.

  Next, a modification of the first embodiment will be described. For example, the polarity of the first pixel data voltage written to the first pixel in the first scanning period of a frame is the same as the polarity of the second pixel data voltage written to the second pixel in the second scanning period of the same frame. Can be.

  In that case, the voltage writing period TMP may be a period in which the first scanning line G1 and the second scanning line G2 are selected and voltage writing to the first pixel and the second pixel becomes possible. Then, as illustrated in FIG. 10, the driving unit 60 may write a given voltage to the first pixel and the second pixel in the voltage writing period TMP.

  Accordingly, when the polarity of the first pixel data voltage and the polarity of the second pixel data voltage in a certain frame are the same polarity, the writing time of the first pixel data voltage and the writing time of the second pixel data voltage Etc. can be shortened.

  In the display panel having the configuration shown in FIG. 2, vertical lines every two lines may be visible due to the parasitic capacitance between the pixels as described with reference to FIG. Since the configuration of the display panel is different, it is not a vertical stripe. However, the mechanism for generating the pixel value error is the same, and according to the circuit device 100 of the present embodiment, the display quality can be reduced by reducing the pixel value error when the display panel of any configuration example is driven. Can be improved.

4). Second Embodiment Next, a second embodiment will be described. In the second embodiment, as shown in FIG. 11, the driving unit 60 applies the second pixel (for example, PX12, PX14) that is a pixel of the second pixel group in the voltage writing period TMP by the scanning of the second scanning line G2. On the other hand, the second pixel data voltage is written. Then, in the next first scanning period TM1 in which the first scanning line G1 is selected, the driving unit 60 applies the first pixel data voltage to the first pixel (for example, PX13) that is a pixel of the first pixel group. Write. Next, in the second scanning period TM2 in which the driving unit 60 is the next scanning period after the first scanning period TM1 and the second scanning line G2 is selected, the second pixel data voltage PX12, PX12, PX14).

  That is, in the second embodiment, the second pixel data voltage is once written in the second pixels (PX12, PX14), the first pixel data voltage is written in the first pixel PX13, and then the second pixel is again written. The second pixel data voltage is written into (PX12, PX14). As in the first embodiment, when the first pixel data voltage is written to the first pixel PX13 as shown by P6 and P7 in FIG. 11, the second pixel (PX12, PX12, The holding voltage of PX14) varies. Specifically, in the example of FIG. 11, the holding voltage of the second pixel PX12 (PX14) is increased by Δ6 (Δ7). On the other hand, in this example, the variation (increase) in the holding voltage of the second pixel is canceled by writing the second pixel data voltage again.

  In addition, when the second pixel data voltage is written to the second pixel (PX12, PX14) in the second scanning period TM2, the second pixel data voltage is written to the second pixel (PX12, PX14) for the first time. Thus, the voltage fluctuation amount in the second pixel (PX12, PX14) can be suppressed. Therefore, it is possible to suppress fluctuations in the holding voltage of the first pixel PX13 in the second scanning period TM2. In the example of FIG. 11, the amount of change in the holding voltage of the first pixel PX13 is Δ8, but Δ8 is smaller than Δ1 in FIG. 7 and Δ2 in FIG.

  Thereby, it is possible to suppress the occurrence of vertical stripes on the display screen. This process can be applied regardless of the type of the dual gate structure of the display panel.

  In this case, in the voltage writing period TMP, it is sufficient that the holding voltage of the second pixel (PX12, PX14) can be brought close to the second pixel data voltage, and it is necessary to make it coincide with the second pixel data voltage. There is no. For example, in the voltage writing period TMP, the voltage that can be written to the second pixel (PX12, PX14) may be lower than the data voltage for the second pixel. This is because the second pixel data voltage is written again to the second pixels (PX12, PX14) in the subsequent second scanning period TM2. Therefore, the length of the voltage writing period TMP may be shorter than the length of the second scanning period TM2.

  This also makes it possible to shorten the length of one frame, increase the number of pixels, and the like.

  Further, as described above, since the second pixel data voltage is once written in the second pixel (PX12, PX14) in the voltage writing period TMP, the second pixel (PX12) is not detected for the first time in the second scanning period TM2. , PX14), writing time is shorter than when writing the second pixel data voltage. On the other hand, at the start of the first scanning period TM1, the first pixel data voltage has never been written to the first pixel PX13. Therefore, it takes longer to write the first pixel data voltage in the first scanning period TM1 than to write the second pixel data voltage in the second scanning period TM2. Therefore, the length of the second scanning period TM2 may be shorter than the length of the first scanning period TM1.

  This also makes it possible to shorten the length of one frame, increase the number of pixels, and the like.

  Similarly to the first embodiment described above, the drive unit 60 puts the first scanning line G1 and the second scanning line G2 into a non-selected state between the voltage writing period TMP and the first scanning period TM1.

  Accordingly, the drive unit can change the output voltage from the given voltage to the first pixel data voltage during the non-selected state.

  Similarly to the modification of the first embodiment described with reference to FIG. 10, when the first pixel and the second pixel have the same polarity, the driving unit 60 uses the second pixel data voltage in the voltage writing period TMP. May be written in the first pixel and the second pixel.

  Accordingly, when the polarity of the first pixel data voltage and the polarity of the second pixel data voltage in a certain frame are the same polarity, the writing time of the first pixel data voltage and the writing time of the second pixel data voltage Etc. can be shortened.

5). Detailed Configuration of Driving Unit FIG. 12 shows a detailed configuration example of the data line driving unit 40. The data line drive unit 40 includes a gradation voltage generation circuit 42 and a plurality of drive circuits DR1 to DRk (k is an integer of 2 or more). For example, the drive circuit DR1 is provided corresponding to the first data line S1 and the second data line S2 of the plurality of data lines.

  The gradation voltage generation circuit 42 has a plurality of positive polarity gradation voltages used when driving a pixel with a positive data voltage and a negative polarity voltage used when driving a pixel with a negative data voltage. Are generated and output to the plurality of drive circuits DR1 to DRk.

  Each of the drive circuits DR1 to DRk has two data lines connected to each other based on a plurality of grayscale voltages for positive polarity, a plurality of grayscale voltages for negative polarity, and display data from the control unit 20. To drive. That is, k = n / 2 drive circuits are provided for the first to nth data line drive terminals TS1 to TSn. For example, in the example of FIG. 3 described above, each drive circuit drives two data lines with opposite polarities. For example, taking the drive circuit DR1 as an example, when a positive data voltage SV1 is output to one data line S1, a negative data voltage SV2 is output to the other data line S2. When the negative data voltage SV1 is output to one data line S1, the positive data voltage SV2 is output to the other data line S2. As described above, there are two types of polarity selection methods, but which polarity each drive circuit selects is arbitrary (independent).

  The control unit 20 outputs display data corresponding to the two data lines driven by the drive circuit to each drive circuit. For example, in the display line connected to the scanning lines G1 and G2 shown in FIG. 3, the pixels PX11 to PX14 are connected to the two data lines S1 and S2. That is, for one display line, the control unit 20 outputs display data for four pixels to one drive circuit. In one display line, writing is performed in a time-sharing manner using two scanning lines G1 and G2, and therefore, during a period in which one scanning line selects a pixel, the control unit 20 transfers display data of two pixels to one driving circuit. Output.

  That is, in the example of FIG. 3, the data lines S1 and S2 are connected to the drive circuit DR1. The pixel PX11 connected to the scanning line G1 and the pixel PX12 connected to the scanning line G2 are connected to the data line S1. The pixel PX13 connected to the scanning line G1 and the pixel PX14 connected to the scanning line G2 are connected to the data line S2. In the first frame, in the first scanning period TM1 in which the scanning line G1 is selected by the gate line driving unit 50, the driving circuit DR1 of the data line driving unit 40 has a negative data voltage SV1 with respect to the data line S1. And the negative data voltage SV1 is written to the pixel PX11. On the other hand, the drive circuit DR1 outputs a positive data voltage SV2 to the data line S2, and writes the positive data voltage SV2 to the pixel PX13. Next, in the first frame, in the second scanning period TM2 in which the scanning line G2 is selected by the gate line driving unit 50, the driving circuit DR1 outputs the negative data voltage SV1 to the data line S1, and the pixel A negative data voltage SV1 is written to PX12, a positive data voltage SV2 is output to the data line S2, and a positive data voltage SV2 is written to the pixel PX14.

  In the next second frame, these polarities are reversed. That is, in the first scanning period TM1 of the second frame, the drive circuit DR1 outputs the positive data voltage SV1 to the data line S1, writes the positive data voltage SV1 to the pixel PX11, and writes it to the data line S2. On the other hand, the negative data voltage SV2 is output, and the negative data voltage SV2 is written to the pixel PX13. Further, in the second scanning period TM2 of the second frame, the drive circuit DR1 outputs the positive data voltage SV1 to the data line S1, writes the positive data voltage SV1 to the pixel PX12, and writes it to the data line S2. On the other hand, the negative data voltage SV2 is output, and the negative data voltage SV2 is written to the pixel PX14. In the subsequent frames, the drive circuit DR1 repeats the operation of the first frame and the operation of the second frame alternately.

  Next, FIG. 13 shows a detailed configuration example of the drive circuit. Although FIG. 13 illustrates the drive circuit DR1 of FIG. 12 as an example, the drive circuits DR2 to DRk can be configured similarly. The drive circuit DR1 includes a first switch circuit SWA1, a second switch circuit SWA2, a positive polarity amplifier circuit AMP that outputs a positive voltage, a negative polarity amplifier circuit AMM that outputs a negative voltage, and a positive polarity D / A conversion circuit DAP, negative polarity D / A conversion circuit DAM, third switch circuit SWB1, fourth switch circuit SWB2, and gradation voltage generation circuit 42.

  The first switch circuit SWA1 includes a switch element SPA1 that connects the output of the positive polarity amplifier circuit AMP and the data line drive terminal TS1, and a switch element SMA1 that connects the output of the negative polarity amplifier circuit AMM and the data line drive terminal TS1. ,including. The first switch circuit SWA1 outputs an output voltage from one of the positive amplifier circuit AMP and the negative amplifier circuit AMM to the first data line S1.

  The second switch circuit SWA2 includes a switch element SMA2 that connects the output of the negative polarity amplifier circuit AMM and the data line drive terminal TS2, and a switch element SPA2 that connects the output of the positive polarity amplifier circuit AMP and the data line drive terminal TS2. ,including. The second switch circuit SWA2 outputs the output voltage from the other amplifier different from the amplifier corresponding to the output voltage output from the first switch circuit SWA1 to the second data line S2.

  The third switch circuit SWB1 has a switch element SPB1 for inputting the display data HD1 for the first data line S1 to the D / A conversion circuit DAP for the positive polarity, and the display data HD2 for the second data line S2 for the positive polarity. Switch element SMB1 input to the D / A conversion circuit DAP.

  The fourth switch circuit SWB2 has a switch element SMB2 for inputting the display data HD2 for the second data line S2 to the D / A conversion circuit DAM for negative polarity and the display data HD1 for the first data line S1 for negative polarity. Switch element SPB2 input to the D / A conversion circuit DAM.

  The gradation voltage generation circuit 42 outputs a plurality of positive gradation voltage generation circuits GCP that output a plurality of positive gradation voltages VRP1 to VRP256, and a plurality of negative gradation voltages VRM1 to VRM256. And a negative polarity gradation voltage generation circuit GCM.

  Hereinafter, the operation of the drive circuit DR1 will be described. In the first state in which the data lines S1 and S2 are driven with positive polarity and negative polarity, the switch elements SPA1, SMA2, SPB1, and SMB2 are turned on. In this case, the positive polarity D / A conversion circuit DAP selects the voltage DPQ corresponding to the display data HD1 for the first data line S1 from the plurality of positive polarity gradation voltages VRP1 to VRP256. The positive amplifier circuit AMP drives the first data line S1 with the positive data voltage SV1 based on the selected voltage DPQ. On the other hand, the negative polarity D / A conversion circuit DAM selects the voltage DMQ corresponding to the display data HD2 for the second data line S2 from the plurality of negative polarity gradation voltages VRM1 to VRM256. The negative amplifier circuit AMM drives the second data line S2 with the negative data voltage SV2 based on the selected voltage DMQ.

  On the other hand, in the second state in which the data lines S1 and S2 are driven with negative polarity and positive polarity, the switch elements SMA1, SPA2, SMB1, and SPB2 are turned on. In this case, the negative polarity D / A conversion circuit DAM selects the voltage DMQ corresponding to the display data HD1 for the first data line S1 from the plurality of negative polarity gradation voltages VRM1 to VRM256. The negative amplifier circuit AMM drives the first data line S1 with the negative data voltage SV1 based on the selected voltage DMQ. On the other hand, the positive polarity D / A conversion circuit DAP selects the voltage DPQ corresponding to the display data HD2 for the second data line S2 from the plurality of positive polarity gradation voltages VRP1 to VRP256. The positive amplifier circuit AMP drives the second data line S2 with the positive data voltage SV2 based on the selected voltage APQ.

  Since one display line is written in time division by two scanning lines G1 and G2, the driving circuit DR1 writes to the pixel in either the first or second state during the period in which each scanning line selects a pixel. I do. The period in which the scanning lines G1 and G2 select the pixels and the combination of the first and second states are arbitrary (independent), and can be driven with various polarity patterns.

  As a result, each drive circuit included in the data line drive unit 40 can drive the two data lines with opposite polarities. When the drive circuits as shown in FIGS. 12 and 13 are employed, when the polarity inversion drive is realized, a pair of positive polarity amplifier circuits and negative polarity amplifier circuits are provided for two data lines. Therefore, the circuit scale can be reduced compared to the case where a pair of positive polarity amplifier circuit and negative polarity amplifier circuit is provided for one data line. However, in the present embodiment, for example, one drive circuit may be provided corresponding to one data line, and the drive circuit may include a positive polarity amplifier circuit and a negative polarity amplifier circuit.

  12 and 13, the case where each drive circuit drives two data lines with opposite polarities has been described as an example. However, the operation of the data line drive unit 40 of the present embodiment is not limited to this, for example, As in the example of FIG. 2 described above, each drive circuit may drive two data lines with the same polarity.

5.1 Configuration of Positive Amplifier Circuit and Negative Amplifier Circuit Next, a positive amplifier circuit AMP and a negative amplifier circuit included in each drive circuit of the data line driver 40 described above with reference to FIG. A configuration example of the AMM will be described. First, the positive polarity amplifier circuit AMP will be described with reference to FIG. 14, and then the negative polarity amplifier circuit AMM will be described with reference to FIG.

  As shown in FIG. 14A (or FIG. 14B), the positive amplifier circuit AMP includes an operational amplifier OPA (op-amp), a first capacitor CIA, a second capacitor CFA, and first to fifth switch elements. SA1 to SA5. The positive polarity amplifier circuit AMP is a circuit that receives an input voltage DAC, outputs an output voltage VQA, and drives a data line. The input voltage DAC is, for example, the voltage DPQ output from the positive polarity D / A conversion circuit DAP of FIG. 13, and is, for example, 0V to + 6V.

  As shown in FIG. 14A, the first capacitor CIA includes a summing node NEGA (reference node, negative node, inverting input terminal node, charge storage node) connected to the first input terminal (inverting input terminal) of the operational amplifier OPA. And the first node NA1. The second capacitor CFA is provided between the summing node NEGA and the second node NA2. Each of these capacitors CIA and CFA can be constituted by a plurality of unit capacitors, for example.

  As shown in FIG. 14A, the first switch element SA1 is provided between the input node NIA and the first node NA1 of the drive circuit (positive amplifier circuit AMP). The second switch element SA2 is provided between the first analog reference power supply VDDRMP and the first node NA1. The third switch element SA3 is provided between the second node NA2 and the output node NQA. The fourth switch element SA4 is provided between the second node NA2 and the second analog reference power supply VDDRMP. The fifth switch element SA5 is provided between the summing node NEGA and the output node NQA.

  These switch elements SA1 to SA5 can be constituted by, for example, CMOS transistors. Specifically, it can be constituted by a transfer gate composed of a P-type transistor and an N-type transistor. These transistors are turned on / off by a switch control signal from a switch control signal generation circuit (not shown). The first and second analog reference power supply VDDRMP are, for example, the high potential side power supply VDD (the first voltage VH described above, for example + 6V) and the low potential side power supply VSS (the second voltage VL described above). 0V) (for example, VDDRMP = (VDD + VSS) / 2, for example, + 3V). This VDDRMP is, for example, a given voltage VM to be written in the voltage writing period TMP in FIG. 9 described above.

  As shown in FIG. 14A, the operational amplifier OPA has a inverting input terminal (first input terminal in a broad sense) connected to a summing node NEGA, and a non-inverting input terminal (second input terminal in a broad sense). Is connected to the second analog reference power supply VDDRMP, and outputs the output voltage VQA to the output node NQA (node of the output terminal). The positive power supply of the operational amplifier is, for example, + 6V, and the negative power supply is, for example, 0V.

  As shown in FIG. 14A, in the positive polarity amplifier circuit AMP, the switch elements SA2, SA4, and SA5 are turned on in the initialization period (period in which the voltage for initialization is set in CIA and CFA).

  When the switch element SA2 is turned on in the initialization period, the other end of the capacitor CIA whose one end is electrically connected to the summing node NEGA is set to the first analog reference power supply VDDRMP. Similarly, when the switch element SA4 is turned on, the other end of the capacitor CFA whose one end is electrically connected to the summing node NEGA is set to the second analog reference power supply VDDRMP. Further, when the switch element SA5 which is a feedback switch element is turned on, the output of the operational amplifier OPA is fed back to the inverting input terminal, and the summing node NEGA is set to VDDRMP by the imaginary short function of the operational amplifier OPA.

  Thereby, in the initialization period, the output voltage VQA becomes the same voltage as the second analog reference power supply VDDRMP.

  Further, as shown in FIG. 14B, in the positive polarity amplifier circuit AMP, the switch elements SA1 and SA3 are turned on in the output period (period in which the output target is output and the drive target is driven).

  When the switch element SA1 is turned on in the output period, the other end of the capacitor CIA having one end connected to the summing node NEGA is set to the input voltage DAC. Further, when the switch element SA3 is turned on, the other end of the capacitor CFA whose one end is connected to the summing node NEGA is set to the output voltage VQA.

Thereby, in the output period, the output voltage VQA becomes a value represented by the following expression (1). In the following formula (1) and formula (2) described later, C _CIA is the capacitance of the capacitor CIA, and C _CFA is the capacitance of the capacitor CFA.

VQA = VDDRMP− (C _CIA / C _CFA ) × (DAC−VDDRMP) (1)
In the voltage writing period TMP as shown in FIG. 9 described above, the positive polarity amplifier circuit AMP is set as the initialization period, and the same voltage as the second analog reference power supply VDDRMP is output as a given voltage for positive polarity. I can do it. Further, in the second scanning period TM2 as shown in FIG. 9 described above, the output voltage VQA represented by the above equation (1) is used as the second pixel data voltage with the positive amplifier circuit AMP as the output period. Can be output.

  Next, the negative polarity amplifier circuit AMM will be described with reference to FIG. As shown in FIG. 15A (or FIG. 15B), the configuration and operation of the negative polarity amplifier circuit AMM are the same as those of the positive polarity amplifier circuit AMP. However, in the negative polarity amplifier circuit AMM, the second analog reference power supply is VDDRMN (for example, −3 V) unlike the positive polarity amplifier circuit AMP. The input voltage DAC is, for example, the voltage DMQ output from the negative polarity D / A conversion circuit DAM in FIG. 13, and is, for example, 0V to 6V. The positive power supply of the operational amplifier is 0V, for example, and the negative power supply is -6V, for example.

  Thereby, in the initialization period, the output voltage VQA becomes the same voltage as the second analog reference power supply VDDRMN, and in the output period, the output voltage VQA becomes a value represented by the following expression (2).

VQA = VDDRMN− (C _CIA / C _CFA ) × (DAC−VDDRMP) (2)
Therefore, in the voltage writing period TMP as shown in FIG. 6 described above, the negative polarity amplifier circuit AMM is set as the initialization period, and the same voltage as the second analog reference power supply VDDRMN is output as a given voltage for negative polarity. I can do it. Further, in the second scanning period TM2 as shown in FIG. 6 described above, the negative polarity amplifier circuit AMM is used as the output period, and the output voltage VQA expressed by the above equation (2) is used as the second pixel data voltage. Can be output.

  As described above, it is possible to output a given voltage in the voltage writing period and output an output voltage corresponding to the input voltage to the driving circuit in the first scanning period or the second scanning period. .

6). Electro-Optical Device FIG. 16 shows a configuration example of an electro-optical device 350 to which the circuit device 100 of this embodiment can be applied. In the following, a case where the display panel 200 is a matrix type liquid crystal display panel will be described as an example. However, the display panel 200 may be an EL (Electro-Luminescence) display panel using a self-luminous element.

  The electro-optical device 350 connects the glass substrate 210, the pixel array 220 formed on the glass substrate 210, the circuit device 100 mounted on the glass substrate 210, and the data lines of the circuit device 100 and the pixel array 220. A wiring group 230, a wiring group 240 that connects the scanning lines of the circuit device 100 and the pixel array 220, a flexible substrate 250 that is connected to the display controller 300, a wiring group 260 that connects the flexible substrate 250 and the circuit device 100, including.

  The wiring group 230, the wiring group 240, and the wiring group 260 are formed on the glass substrate 210 with a transparent electrode (ITO: Indium Tin Oxide) or the like.

  The pixel array 220 includes pixels, data lines, and scanning lines, and the glass substrate 210 and the pixel array 220 correspond to the display panel 200.

  Note that the electro-optical device may further include a substrate connected to the flexible substrate 250 and a display controller 300 mounted on the substrate.

7). Electronic Device FIG. 17 shows a configuration example of an electro-optical device 350 and an electronic device to which the circuit device 100 of this embodiment can be applied. As an electronic device of the present embodiment, for example, an in-vehicle display device (for example, a meter panel), a monitor, a display, a single plate projector, a television device, an information processing device (computer), a portable information terminal, a car navigation system, a portable type Various electronic devices equipped with a display device such as a game terminal, a DLP (Digital Light Processing) device, and a printer can be assumed.

  17 includes an electro-optical device 350, a CPU 310 (processing device in a broad sense), a display controller 300 (host controller), a storage unit 320, a user interface unit 330, and a data interface unit 340. The function of the display controller 300 may be realized by the CPU 310, and the display controller 300 may be omitted.

  The user interface unit 330 is an interface unit that accepts various operations from the user. For example, it includes a button, a mouse, a keyboard, a touch panel mounted on the display panel 200, and the like. The data interface unit 340 is an interface unit that inputs and outputs display data and control data. For example, a wired communication interface such as a USB or a wireless communication interface such as a wireless LAN. The storage unit 320 stores display data input from the data interface unit 340. Alternatively, the storage unit 320 functions as a working memory for the CPU 310 and the display controller 300. The CPU 310 performs control processing of various parts of the electronic device and various data processing. The display controller 300 performs control processing of the circuit device 100. For example, the display controller 300 converts display data transferred from the data interface unit 340 or the storage unit 320 via the CPU 310 into a format acceptable by the circuit device 100, and converts the converted display data to the circuit device 100. Output. The circuit device 100 drives the display panel 200 based on the display data transferred from the display controller 300.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. Further, the configurations and operations of the circuit device, the electro-optical device, and the electronic apparatus are not limited to those described in this embodiment, and various modifications can be made.

DESCRIPTION OF SYMBOLS 10 ... Interface part, 20 ... Control part (data processing part), 40 ... Data line drive part,
42 ... gradation voltage generation circuit, 50 ... gate line drive unit, 60 ... drive unit, 100 ... circuit device,
200 ... Display panel, 210 ... Glass substrate, 220 ... Pixel array, 230 ... Wiring group,
240 ... wiring group, 250 ... flexible substrate, 260 ... wiring group,
300 ... Display controller, 320 ... Storage unit, 330 ... User interface unit,
340: Data interface unit, 350: Electro-optical device

Claims (8)

A first pixel group selected by the first scanning line among a first scanning line and a second scanning line provided corresponding to the display line; a second pixel group selected by the second scanning line; A circuit device for driving a display panel in which each data line of a plurality of data lines is shared by any pixel of the first pixel group and any pixel of the second pixel group,
A drive unit for driving the display panel based on the display data;
A control unit for controlling the driving unit;
Including
The drive unit is
In a voltage writing period by scanning of the second scanning line, a second pixel data voltage is written to a second pixel that is a pixel of the second pixel group, and the first first after the first scanning line is selected. In the scanning period, the first pixel data voltage is written to the first pixel that is a pixel of the first pixel group, and the second scanning line is selected in the scanning period next to the first scanning period. In the second scanning period, the second pixel data voltage is written to the second pixel. In claim 1,
The length of the voltage writing period is:
A circuit device characterized by being shorter than the length of the second scanning period. In claim 1 or 2,
The drive unit is
The circuit device, wherein the first scanning line and the second scanning line are brought into a non-selected state between the voltage writing period and the first scanning period. In any one of Claims 1 thru | or 3,
The length of the second scanning period is
A circuit device characterized by being shorter than the length of the first scanning period. In any one of Claims 1 thru | or 4,
The drive unit is
When the first pixel and the second pixel have the same polarity, the second pixel data voltage is written to the first pixel and the second pixel in the voltage writing period. In any one of Claims 1 thru | or 5,
The drive unit is
A drive circuit provided corresponding to the first data line and the second data line of the plurality of data lines;
The drive circuit is
A positive polarity amplifier that outputs a positive polarity voltage;
A negative amplifier that outputs a negative voltage; and
A first switch circuit for outputting an output voltage from one of the positive polarity amplifier and the negative polarity amplifier to the first data line;
A second switch circuit for outputting an output voltage from the other amplifier different from the one to the second data line;
A circuit device comprising:   An electro-optical device comprising the circuit device according to claim 1 and the display panel.   An electronic apparatus comprising the circuit device according to claim 1.

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