JP2017055081A - Light emitting component, print head, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light emitting component that can easily achieve both suppression of oxidation of an exposed distributed Bragg reflection layer and suppression of reduction in reflectance of a distributed Bragg reflection layer compared with a case where all high aluminum composition layers forming a distributed Bragg reflection layer have the same aluminum composition ratio.SOLUTION: A light emitting chip C comprises: a substrate 80; a first multilayer film reflector 81 and a second multilayer film reflector 83 that sandwich a current constriction layer 82 and are formed of a compound semiconductor including Al; and islands (first island 301 and the like) each have a first semiconductor layer 84, second semiconductor layer 85, and third semiconductor layer 86 laminated in this order and include a light emitting element. The islands are separated into first separation parts M1 that reach the second multilayer film reflector 83 but do not reach the current constriction layer 82 and second separation parts M2 that reach the current constriction part 82; a portion of the second multilayer film reflector 83 to be exposed to the first separation part M1 is lower than a portion of the multilayer reflector not to be exposed to the first separation part M1 in terms of the aluminum composition ratio in a high aluminum composition layer.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a light emitting component, a print head, and an image forming apparatus.

  In Patent Document 1, a p-type first multilayer reflector, a current confinement layer, a p-type second multilayer reflector, an n-type gate layer, a p-type gate layer, and a cathode layer are laminated in order from the substrate side. A light emitting thyristor is described.

  In Patent Document 2, a first mesa structure having a depth not reaching the current confinement layer, a second mesa structure having a depth reaching the current confinement layer, and the first mesa structure are formed. A self-scanning type comprising: a shift unit thyristor; and a light emitting unit thyristor formed in the second mesa structure and having a current confinement structure formed by oxidizing the current confinement layer from a side surface of the second mesa structure A light emitting element array is described.

  Patent Document 3 includes a multilayer structure including a lower multilayer reflector, a lower clad layer, an active layer, an upper clad layer, and an upper multilayer reflector in order, and an oxidized constriction layer. The bottom of the mesa has a non-planar surface with exposed end faces of a plurality of layers, and the lower multilayer reflector includes a low refractive index layer having a high Al (aluminum) composition and a high refractive index having a low Al composition. The lower multilayer reflector includes at least one layer exposed in the non-planar surface among the plurality of low refractive index layers included in the lower multilayer reflector. There is described a surface emitting semiconductor laser that is an oxidation-suppressing layer containing Al having a composition ratio smaller than the Al composition ratio of a layer that is not exposed in the non-flat surface among the plurality of low refractive index layers.

Japanese Patent Laying-Open No. 2015-032812 Japanese Patent No. 5327377 JP 2009-266919 A

Incidentally, in a light-emitting component using a light-emitting element such as a light-emitting diode or a light-emitting thyristor, improvement in the amount of emitted light is required. Accordingly, a distributed Bragg reflection layer is provided in the light emitting element, and light emitted from the light emitting element in a direction different from the emission direction is reflected in the emission direction to improve light extraction efficiency. Further, a current confinement layer is provided, and the current is concentrated in the central portion of the light emitting element by the current confinement to improve the light emission efficiency. Current confinement is performed, for example, by oxidizing aluminum in the material constituting the light emitting element to narrow the current path.
In such a configuration, the current confinement layer may be oxidized while the distributed Bragg reflective layer is exposed by etching. In this case, the low refractive index layer (high aluminum composition layer) in the distributed Bragg reflective layer is also oxidized together. As a result, for example, the adhesion of the insulating layer formed on the distributed Bragg reflection layer may be weakened. On the other hand, when the aluminum composition ratio of the high aluminum composition layer in the distributed Bragg reflective layer is lowered so that the distributed Bragg reflective layer is not oxidized, the reflectivity is lowered and it is difficult to obtain a desired reflectivity.
Therefore, in the present invention, compared with the case where all the high aluminum composition layers constituting the distributed Bragg reflective layer are composed of the same aluminum composition ratio, the oxidation of the exposed distributed Bragg reflective layer and the decrease in the reflectance of the distributed Bragg reflective layer are suppressed. It aims at providing the light emitting component etc. which are compatible easily.

According to the first aspect of the present invention, there are provided a substrate, a multilayer reflector made of a compound semiconductor containing aluminum with a current confinement layer sandwiched between the substrate, and a plurality of different conductivity types on the multilayer reflector. And an island having a light emitting element. The island reaches the multilayer reflector, but does not reach the current confinement layer and the current confinement layer. The portion of the multilayer reflector that is separated by the second separator and exposed to the first separator is higher in aluminum than the portion of the multilayer reflector that is not exposed to the first separator. A light-emitting component having a low composition ratio.
According to a second aspect of the present invention, the portion of the multilayer reflector in which the aluminum composition ratio of the high aluminum composition layer is low is a portion in the thickness direction that is affected by oxidation when the current confinement layer is oxidized. The light-emitting component according to claim 1, wherein the light-emitting component is a light-emitting component.
According to a third aspect of the present invention, the portion of the multilayer reflector in which the aluminum composition ratio of the high aluminum composition layer is low is a portion farther from the substrate than the current confinement layer of the multilayer reflector. The light-emitting component according to claim 1.
The invention according to claim 4 is the light emitting component according to any one of claims 1 to 3, wherein the second separation portion is provided in contact with the light emitting element.
The invention according to claim 5 is the light emitting component according to any one of claims 1 to 4, wherein wiring is provided so as to cross the first separation portion.
According to a sixth aspect of the present invention, there is provided a substrate, a multilayer film reflecting mirror composed of a compound semiconductor containing aluminum with a current confinement layer sandwiched between the substrate, and a plurality of conductive types on the multilayer film reflecting mirror. A plurality of islands including a light emitting element, and an optical unit that forms an image of light emitted from the light emitting unit, and the plurality of islands includes: The multilayer reflection reflected by the first separation part that reaches the multilayer reflection mirror but does not reach the current confinement layer or the second separation part that reaches the current confinement layer and is exposed to the first separation part The mirror portion is a print head characterized in that the aluminum composition ratio of the high aluminum composition layer is lower than the portion of the multilayer reflector that is not exposed to the first separation portion.
According to a seventh aspect of the present invention, there is provided a multilayer film reflection comprising an image carrier, a charging means for charging the image carrier, a substrate, and a compound semiconductor containing aluminum with a current confinement layer sandwiched between the substrate and the substrate. A mirror and a plurality of islands each having a light emitting element formed by laminating a plurality of semiconductor layers having different conductivity types on the multilayer film reflecting mirror, and exposing the image carrier through optical means. An exposure unit; a developing unit that develops the electrostatic latent image formed on the image carrier exposed by the exposure unit; and a transfer unit that transfers the image developed on the image carrier to a transfer target. The plurality of islands are separated by a first separation unit that reaches the multilayer reflector but does not reach the current confinement layer, or a second separation unit that reaches the current confinement layer, and the first separation The portion of the multilayer mirror that is exposed to the Than the portion of the multilayer reflector is not exposed to parts, an image forming apparatus, wherein the aluminum composition ratio of the high aluminum composition layer is low.

According to the first aspect of the present invention, compared to the case where all the high aluminum composition layers constituting the distributed Bragg reflective layer are constructed with the same aluminum composition ratio, the oxidation suppression of the exposed distributed Bragg reflective layer and the reflection of the distributed Bragg reflective layer are performed. It is easy to achieve both reduction in rate.
According to the second aspect of the present invention, compared with the case where the aluminum composition ratio is lowered beyond the range affected by the oxidation, the decrease in the reflectance of the multilayer-film reflective mirror can be suppressed to be small.
According to the third aspect of the present invention, the current can be more concentrated on the light emitting element than when the current confinement layer is not on the substrate side.
According to the invention of claim 4, the current can be concentrated on the light emitting element as compared with the case where it is not provided in contact with the light emitting element.
According to the fifth aspect of the present invention, the formation of the wiring is facilitated as compared with the case where the wiring is provided so as to cross the second separation portion.
According to the invention of claim 6, the reliability of the print head is improved as compared with the case where all the high aluminum composition layers constituting the distributed Bragg reflection layer are constituted with the same aluminum composition ratio.
According to the seventh aspect of the present invention, the reliability of the image forming apparatus is improved as compared with the case where all the high aluminum composition layers constituting the distributed Bragg reflection layer are constructed with the same aluminum composition ratio.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which the exemplary embodiment is applied. It is sectional drawing which showed the structure of the print head. It is a top view of a light-emitting device. It is the figure which showed the structure of the light emitting chip | tip, the structure of the signal generation circuit of a light-emitting device, and the structure of wiring (line) on a circuit board. (A) shows the configuration of the light-emitting chip C, and (b) shows the configuration of the signal generation circuit of the light-emitting device and the configuration of wiring (lines) on the circuit board. It is an equivalent circuit diagram for demonstrating the circuit structure of the light emitting chip in which the self-scanning light emitting element array (SLED) in this Embodiment is mounted. It is an example of the plane layout figure and sectional drawing of the light emitting chip to which this Embodiment is applied. (A) is a plane layout view of a light-emitting chip, and (b) is a cross-sectional view taken along line VIB-VIB of (a). 6 is a timing chart for explaining operations of the light emitting device and the light emitting chip. It is a figure explaining a 1st multilayer-film reflective mirror, a current confinement layer, and a 2nd multilayer-film reflective mirror. (A) shows a 1st separation part, (b) has shown the 2nd separation part. It is a figure explaining the process to a gate extraction etching process. (A1), (b1), (c1) is sectional drawing in the PP line in Fig.6 (a). (A2), (b2), (c2) is sectional drawing in the QQ line in Fig.6 (a). It is a figure explaining the process after gate extraction etching. (A1), (b1), (c1) is sectional drawing in the PP line in Fig.6 (a). (A2), (b2), (c2) is sectional drawing in the QQ line in Fig.6 (a). It is sectional drawing which shows the modification of the light emitting chip | tip of this Embodiment.

In an image forming apparatus such as a printer, copier, or facsimile that employs an electrophotographic system, an electrostatic latent image is obtained by irradiating image information onto a charged photosensitive member by an optical recording means, and then the static image is obtained. An image is formed by adding toner to the electrostatic latent image to make it visible, and transferring and fixing it on a recording sheet. In addition to an optical scanning method in which a laser is used as the optical recording means and exposure is performed by scanning a laser beam in the main scanning direction, in recent years, a light emitting diode (LED: Light) as a light emitting element has been received in response to a request for downsizing of the apparatus. A recording apparatus using an LED print head (LPH: LED Print Head) in which a plurality of Emitting Diodes (LEDs) are arranged in the main scanning direction to form a light emitting element array is employed.
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
In the following description, element symbols are used, such as aluminum as Al.

(Image forming apparatus 1)
FIG. 1 is a diagram illustrating an example of the overall configuration of an image forming apparatus 1 to which the exemplary embodiment is applied. An image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, an image output control unit 30 that controls the image forming process unit 10, such as a personal computer (PC) 2 or an image reading device. 3 and an image processing unit 40 that performs predetermined image processing on image data received from these.

The image forming process unit 10 includes an image forming unit 11 including a plurality of engines arranged in parallel at predetermined intervals. The image forming unit 11 includes four image forming units 11Y, 11M, 11C, and 11K. The image forming units 11Y, 11M, 11C, and 11K have predetermined surfaces of the photosensitive drum 12 and the photosensitive drum 12 as an example of an image holding body that forms an electrostatic latent image and holds a toner image, respectively. An example of a charging unit 13 as an example of a charging unit that charges at a potential, a print head 14 that exposes a photosensitive drum 12 charged by the charging unit 13, and an example of a developing unit that develops an electrostatic latent image obtained by the print head 14 The developing device 15 is provided. The image forming units 11Y, 11M, 11C, and 11K respectively form yellow (Y), magenta (M), cyan (C), and black (K) toner images.
Further, the image forming process unit 10 performs multiple transfer of the toner images of each color formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto a recording sheet 25 as an example of a transfer target. In addition, the sheet conveying belt 21 that conveys the recording sheet 25, the driving roll 22 that is a roll for driving the sheet conveying belt 21, and a transfer unit that transfers the toner image on the photosensitive drum 12 to the recording sheet 25 are exemplified. A transfer roll 23 and a fixing device 24 for fixing the toner image on the recording paper 25 are provided.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 under the control of the image output control unit 30 is subjected to image processing by the image processing unit 40 and supplied to the image forming unit 11. The For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged in a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image supplied from the image processing unit 40 is supplied. Exposure is performed by the print head 14 that emits light based on the data. As a result, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12. The electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. In the image forming units 11Y, 11M, and 11C, yellow (Y), magenta (M), and cyan (C) color toner images are formed, respectively.

Each color toner image on the photosensitive drum 12 formed by each image forming unit 11 is applied to the transfer roll 23 on the recording paper 25 supplied with the movement of the paper conveying belt 21 moving in the direction of arrow B. Electrostatic transfer is sequentially performed by the transfer electric field, and a composite toner image in which toner of each color is superimposed on the recording paper 25 is formed.
Thereafter, the recording paper 25 on which the composite toner image has been electrostatically transferred is conveyed to the fixing device 24. The synthesized toner image on the recording paper 25 conveyed to the fixing device 24 is fixed on the recording paper 25 by the fixing processing by heat and pressure by the fixing device 24, and is discharged from the image forming apparatus 1.

(Print head 14)
FIG. 2 is a cross-sectional view showing the configuration of the print head 14. The print head 14 as an example of an exposure unit includes a light source unit 63 that includes a housing 61 and a plurality of light emitting elements that expose the photosensitive drum 12 (in this embodiment, a light emitting thyristor as an example of the light emitting element). A light emitting device 65 as an example of a means and a rod lens array 64 as an example of an optical means for forming an image of light emitted from the light source unit 63 on the surface of the photosensitive drum 12 are provided.
The light emitting device 65 includes a circuit board 62 on which the above-described light source unit 63, a signal generation circuit 110 (see FIG. 3 described later) for driving the light source unit 63, and the like are mounted.

  The housing 61 is made of, for example, metal, supports the circuit board 62 and the rod lens array 64, and is set so that the light emitting surface of the light emitting element of the light source unit 63 becomes the focal plane of the rod lens array 64. Further, the rod lens array 64 is arranged along the axial direction of the photosensitive drum 12 (the main scanning direction and the X direction in FIGS. 3 and 4B described later).

(Light emitting device 65)
FIG. 3 is a top view of the light emitting device 65.
In the light emitting device 65 shown as an example in FIG. 3, the light source unit 63 includes light emitting chips C <b> 1 to C <b> 40 as examples of 40 light emitting components on a circuit board 62 in a staggered manner in two rows in the X direction that is the main scanning direction. Arranged in a shape.
In the present specification, “to” indicates a plurality of constituent elements each distinguished by a number, and includes those described before and after “to” and those between them. For example, the light emitting chips C1 to C40 include the light emitting chip C1 to the light emitting chip C40 in numerical order.

The configurations of the light emitting chips C1 to C40 may be the same. Therefore, when the light emitting chips C1 to C40 are not distinguished from each other, they are referred to as light emitting chips C.
In the present embodiment, a total of 40 light emitting chips C are used, but the present invention is not limited to this.
The light emitting device 65 includes a signal generation circuit 110 that drives the light source unit 63. The signal generation circuit 110 is configured by, for example, an integrated circuit (IC). Note that the light emitting device 65 does not have to include the signal generation circuit 110. At this time, the signal generation circuit 110 is provided outside the light emitting device 65 and supplies a control signal for controlling the light emitting chips C1 to C40 through a cable or the like. Here, it is assumed that the light emitting device 65 includes the signal generation circuit 110.
Details of the arrangement of the light emitting chips C1 to C40 will be described later.

  FIG. 4 is a diagram showing the configuration of the light emitting chip C, the configuration of the signal generation circuit 110 of the light emitting device 65, and the configuration of wiring (lines) on the circuit board 62. 4A shows the configuration of the light-emitting chip C, and FIG. 4B shows the configuration of the signal generation circuit 110 of the light-emitting device 65 and the configuration of wiring (lines) on the circuit board 62. In FIG. 4B, the light emitting chips C1 to C9 among the light emitting chips C1 to C40 are shown.

First, the configuration of the light-emitting chip C shown in FIG.
The light-emitting chip C includes a plurality of light-emitting elements (in the present embodiment, light-emitting thyristors L1 to L1) arranged in a row along the long side on the side close to one side of the long side on the surface of the substrate 80 having a rectangular surface. L128) is provided. Further, the light emitting chip C has terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) which are a plurality of bonding pads for taking in various control signals and the like at both ends in the long side direction of the surface of the substrate 80. I have. These terminals are provided in order of the φI terminal and the φ1 terminal from one end of the substrate 80, and are provided in the order of the Vga terminal and the φ2 terminal from the other end of the substrate 80. The light emitting unit 102 is provided between the φ1 terminal and the φ2 terminal. Further, a back electrode 88 (see FIG. 6 described later) is provided on the back surface of the substrate 80 as a Vsub terminal.

  Note that the “column shape” is not limited to the case where a plurality of light emitting elements are arranged in a straight line as illustrated in FIG. 4A, and the light emitting elements of the plurality of light emitting elements are arranged in the column direction. It may be in a state where they are arranged with different amounts of displacement with respect to the orthogonal direction. For example, when a light emitting surface of a light emitting element (a cathode region 311 of a light emitting thyristor L in FIG. 6 described later) is a pixel, each light emitting element is shifted by several pixels or several tens of pixels in a direction orthogonal to the column direction. You may arrange with quantity. Moreover, you may arrange | position zigzag alternately between adjacent light emitting elements or for every several light emitting element.

Next, the configuration of the signal generation circuit 110 of the light emitting device 65 and the configuration of the wiring (line) on the circuit board 62 will be described with reference to FIG.
As described above, the signal generating circuit 110 and the light emitting chips C1 to C40 are mounted on the circuit board 62 of the light emitting device 65, and wirings (lines) for connecting the signal generating circuit 110 and the light emitting chips C1 to C40 are provided. ing.

First, the configuration of the signal generation circuit 110 will be described.
Image signal processed image data and various control signals are input to the signal generation circuit 110 from the image output control unit 30 and the image processing unit 40 (see FIG. 1). Based on these image data and various control signals, the signal generation circuit 110 rearranges the image data and corrects the light amount.
The signal generation circuit 110 includes a transfer signal generation unit 120 that transmits the first transfer signal φ1 and the second transfer signal φ2 to the light emitting chips C1 to C40 based on various control signals.
In addition, the signal generation circuit 110 includes a lighting signal generation unit 140 that transmits the lighting signals φI1 to φI40 to the light emitting chips C1 to C40 based on various control signals. When the lighting signals φI1 to φI40 are not distinguished from each other, they are expressed as a lighting signal φI.
Furthermore, the signal generation circuit 110 supplies a reference potential supply unit 160 that supplies a reference potential Vsub that serves as a potential reference to the light emitting chips C1 to C40, and a power supply potential that supplies a power supply potential Vga for driving the light emitting chips C1 to C40. A supply unit 170 is provided.

Next, the arrangement of the light emitting chips C1 to C40 will be described.
The odd-numbered light emitting chips C1, C3, C5,... Are arranged in a line at intervals in the long side direction of each substrate 80. The even-numbered light emitting chips C2, C4, C6,... Are similarly arranged in a row at intervals in the direction of the long side of each substrate 80. The odd numbered light emitting chips C1, C3, C5,... And the even numbered light emitting chips C2, C4, C6,... Are arranged so that the long sides on the light emitting unit 102 side provided in the light emitting chip C face each other. They are arranged in a zigzag pattern in a state rotated by 180 °. The positions of the light emitting chips C are also set so that the light emitting elements are arranged at predetermined intervals in the main scanning direction (X direction). 4B, the direction of the arrangement of the light emitting elements of the light emitting unit 102 shown in FIG. 4A (in order of numbers of the light emitting thyristors L1 to L128 in this embodiment) is indicated by arrows. Is shown.

A wiring (line) connecting the signal generation circuit 110 and the light emitting chips C1 to C40 will be described.
The circuit board 62 is provided with a power supply line 200a that is connected to a back electrode 88 (see FIG. 6 described later) that is a Vsub terminal provided on the back surface of the substrate 80 of the light emitting chip C, and supplies a reference potential Vsub. .
The circuit board 62 is provided with a power supply line 200b that is connected to a Vga terminal provided on the light emitting chip C and supplies a power supply potential Vga for driving.

  The circuit board 62 includes a first transfer signal line 201 for transmitting the first transfer signal φ1 from the transfer signal generator 120 of the signal generation circuit 110 to the φ1 terminals of the light emitting chips C1 to C40, and the light emitting chips C1 to C40. A second transfer signal line 202 for transmitting the second transfer signal φ2 to the φ2 terminal is provided. The first transfer signal φ1 and the second transfer signal φ2 are transmitted in common (in parallel) to the light emitting chips C1 to C40.

  Further, the lighting signals φI1 to φI40 are transmitted to the circuit board 62 from the lighting signal generation unit 140 of the signal generation circuit 110 to the respective φI terminals of the respective light emitting chips C1 to C40 via the current limiting resistors RI. Lighting signal lines 204-1 to 204-40 are provided.

  As described above, the reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips C1 to C40 on the circuit board 62. The first transfer signal φ1 and the second transfer signal φ2 are also transmitted in common (in parallel) to the light emitting chips C1 to C40. On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips C1 to C40, respectively.

(Light emitting chip C)
FIG. 5 is an equivalent circuit diagram for explaining a circuit configuration of the light-emitting chip C on which the self-scanning light-emitting element array (SLED) according to the present embodiment is mounted. Each element described below is arranged based on a layout (see FIG. 6 described later) on the light emitting chip C except for terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal). Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for explanation of the connection relationship with the signal generation circuit 110. . The Vsub terminal provided on the back surface of the substrate 80 is drawn out of the substrate 80.
Here, the light emitting chip C will be described taking the light emitting chip C1 as an example in relation to the signal generation circuit 110. Therefore, in FIG. 5, the light-emitting chip C is expressed as a light-emitting chip C <b> 1 (C). The configuration of the other light emitting chips C2 to C40 is the same as that of the light emitting chip C1.

The light-emitting chip C1 (C) includes a light-emitting thyristor array (the light-emitting unit 102 (see FIG. 4A)) composed of the light-emitting thyristors L1 to L128 arranged in a line on the substrate 80 as described above. Yes.
The light-emitting chip C1 (C) includes a transfer thyristor array composed of transfer thyristors T1 to T128 arranged in a row like the light-emitting thyristor array.

The light-emitting chip C1 (C) includes two pairs of transfer thyristors T1 to T128 in numerical order, and includes coupling diodes Dx1 to Dx127 between each pair.
Further, the light emitting chip C1 (C) includes power supply line resistors Rgx1 to Rgx128.

  The light emitting chip C1 (C) includes one start diode Dx0. In order to prevent an excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 to be described later is transmitted and a second transfer signal line 73 to which a second transfer signal φ2 is transmitted. Current limiting resistors R1 and R2.

The light emitting thyristors L1 to L128 in the light emitting thyristor array and the transfer thyristors T1 to T128 in the transfer thyristor array are arranged in numerical order from the left side in FIG. Further, the coupling diodes Dx1 to Dx127 and the power line resistances Rgx1 to Rgx128 are also arranged in numerical order from the left side in the drawing.
The light emitting thyristor array and the transfer thyristor array are arranged in the order of the transfer thyristor array and the light emitting thyristor array from the top in FIG.

  Here, when the light emitting thyristors L1 to L128, the transfer thyristors T1 to T128, the coupling diodes Dx1 to Dx127, and the power supply line resistors Rgx1 to Rgx128 are not distinguished from each other, the light emitting thyristor L, the transfer thyristor T, the coupling diode Dx, and the power supply line resistor Rgx. Is written.

In the present embodiment, the light emitting thyristor L in the light emitting thyristor array, the transfer thyristor T in the transfer thyristor array, and the power supply line resistance Rgx are each 128 pieces. However, the number of coupling diodes Dx is 127, which is one less than the number of transfer thyristors T.
The number of light emitting thyristors L is not limited to the above, and may be a predetermined number.
The number of transfer thyristors T may be larger than the number of light emitting thyristors L.

  The thyristor (light-emitting thyristor L, transfer thyristor T) is a semiconductor element having three terminals: a gate terminal, an anode terminal, and a cathode terminal.

Next, electrical connection of each element in the light emitting chip C1 (C) will be described.
The anode terminals of the transfer thyristor T and the light emitting thyristor L are connected to the substrate 80 of the light emitting chip C1 (C) (anode common).
These anode terminals are connected to a power supply line 200a (see FIG. 4B) via a back electrode 88 (see FIG. 6 described later) which is a Vsub terminal provided on the back surface of the substrate 80. The power supply line 200a is supplied with the reference potential Vsub from the reference potential supply unit 160.

The cathode terminals of the odd-numbered transfer thyristors T1, T3,... Are connected to the first transfer signal line 72 along the arrangement of the transfer thyristors T. The first transfer signal line 72 is connected to the φ1 terminal via the current limiting resistor R1. The first transfer signal line 201 (see FIG. 4B) is connected to the φ1 terminal, and the first transfer signal φ1 is transmitted from the transfer signal generator 120.
On the other hand, the cathode terminals of the even-numbered transfer thyristors T2, T4,... Are connected to the second transfer signal line 73 along the arrangement of the transfer thyristors T. The second transfer signal line 73 is connected to the φ2 terminal via the current limiting resistor R2. The second transfer signal line 202 (see FIG. 4B) is connected to the φ2 terminal, and the second transfer signal φ2 is transmitted from the transfer signal generator 120.

  The cathode terminals of the light emitting thyristors L <b> 1 to L <b> 128 are connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal. In the light emitting chip C1, the φI terminal is connected to the lighting signal line 204-1 via the current limiting resistor RI, and the lighting signal φI1 is transmitted from the lighting signal generator 140 (see FIG. 4B). The lighting signal φI1 supplies a current for lighting to the light emitting thyristors L1 to L128. The lighting signal lines 204-2 to 204-40 are connected to the φI terminals of the other light emitting chips C2 to C40 via current limiting resistors RI, respectively, and the lighting signals φI2 to φI40 are transmitted from the lighting signal generator 140. (See FIG. 4B).

  The gate terminals Gt1 to Gt128 of the transfer thyristors T1 to T128 are connected one-to-one to the gate terminals Gl1 to Gl128 of the light emitting thyristors L1 to L128 having the same number. Therefore, the gate terminals Gt1 to Gt128 and the gate terminals Gl1 to Gl128 have the same number and are electrically at the same potential. Therefore, for example, the gate terminal Gt1 (gate terminal Gl1) is expressed and indicates that the potentials are the same.

  Also here, when the gate terminals Gt1 to Gt128 and the gate terminals Gl1 to Gl128 are not distinguished from each other, they are expressed as the gate terminal Gt and the gate terminal Gl. It is expressed as a gate terminal Gt (gate terminal Gl) and indicates that the potential is the same.

  Coupling diodes Dx1 to Dx127 are connected between the gate terminals Gt of which two pairs of the gate terminals Gt1 to Gt128 of the transfer thyristors T1 to T128 are arranged in order of numbers. That is, the coupling diodes Dx1 to Dx127 are connected in series so as to be sandwiched between the gate terminals Gt1 to Gt128, respectively. The direction of the coupling diode Dx1 is connected in a direction in which a current flows from the gate terminal Gt1 toward the gate terminal Gt2. The same applies to the other coupling diodes Dx2 to Dx127.

  The gate terminal Gt (gate terminal Gl) of the transfer thyristor T is connected to the power supply line 71 via the power supply line resistance Rgx provided corresponding to each of the transfer thyristors T. The power supply line 71 is connected to the Vga terminal. A power supply line 200b (see FIG. 4B) is connected to the Vga terminal, and the power supply potential Vga is supplied from the power supply potential supply unit 170.

  The gate terminal Gt1 of the transfer thyristor T1 on one end side of the transfer thyristor array is connected to the cathode terminal of the start diode Dx0. On the other hand, the anode terminal of the start diode Dx 0 is connected to the second transfer signal line 73.

  In FIG. 5, a portion including the transfer thyristor T, the coupling diode Dx, the power supply line resistance Rgx, the start diode Dx0, and the current limiting resistors R1 and R2 of the light emitting chip C1 (C) is referred to as a transfer unit 101. A portion including the light emitting thyristor L corresponds to the light emitting unit 102.

FIG. 6 is an example of a plan layout view and a cross-sectional view of a light-emitting chip C to which the present embodiment is applied. 6A is a plan layout view of the light-emitting chip C, and FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG. 6A. Here, since the connection relationship between the light-emitting chip C and the signal generation circuit 110 is not shown, it is not necessary to use the light-emitting chip C1 as an example. Therefore, it is expressed as a light emitting chip C.
FIG. 6A shows a portion centering on the light emitting thyristors L1 to L4 and the transfer thyristors T1 to T4. Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for convenience of explanation. A Vsub terminal (back surface electrode 88) provided on the back surface of the substrate 80 is drawn out of the substrate 80. If the terminals are provided corresponding to FIG. 4A, the φ2 terminal, the φI terminal, and the current limiting resistor R2 are provided at the right end portion of the substrate 80. The start diode Dx0 may be provided at the right end portion of the substrate 80.

  In FIG. 6B, which is a cross-sectional view taken along the line VIB-VIB in FIG. 6A, the light emitting thyristor L1, the transfer thyristor T1, the coupling diode Dx1, and the power supply line resistance Rgx1 are shown from the bottom in the figure. In addition, in FIG. 6A and FIG. 6B, main elements and terminals are indicated by names.

First, the cross-sectional structure of the light emitting chip C will be described with reference to FIG.
The light emitting chip C includes a first multilayer reflector 81, a current confinement layer 82, a second multilayer reflector 83, an n-type first semiconductor layer 84, and a p-type second semiconductor layer on a p-type substrate 80. 85 and an n-type third semiconductor layer 86 are sequentially stacked and configured from a plurality of islands (islands) separated from each other (a first island 301, a second island 302, a third island 303, etc. described later). ing. The first multilayer reflector 81, the current confinement layer 82, and the second multilayer reflector 83 may be referred to as a multilayer reflector. The first multilayer-film reflective mirror 81, the current confinement layer 82, and the second multilayer-film reflective mirror 83 function as a p-type semiconductor layer.
The first multilayer reflector 81, the current confinement layer 82, and the second multilayer reflector 83 will be described later.

These islands are formed on a p-type substrate 80 on a first multilayer reflector 81, a current confinement layer 82, a second multilayer reflector 83, an n-type first semiconductor layer 84, and a p-type second semiconductor layer. After the 85 and n-type third semiconductor layers 86 are sequentially stacked by epitaxial growth, the layers between the islands are separated from each other by etching. Such an island is called a mesa.
Here, the etched part between the islands is referred to as a separation part. Without reaching the current confinement layer 82, the first separation part M1 removed up to a part of the second multilayer reflector 83 and beyond the current confinement layer 82 to a part of the first multilayer reflector 81 There is the second separation part M2 removed. The second separation portion M2 only needs to reach at least the current confinement layer 82. Here, it is assumed that the second separation unit M2 is configured by removing a part of the first multilayer-film reflective mirror 81.
When the first separation unit M1 and the second separation unit M2 are not distinguished from each other, they are referred to as separation units.

  The plurality of islands do not have the n-type third semiconductor layer 86 and those that partially include the n-type third semiconductor layer 86 (for example, a first island 301 described later). (For example, a third island 303 described later).

  The light emitting chip C is provided with an insulating layer 87 provided so as to cover the surface and side surfaces of these islands. These islands and wiring such as the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, and the lighting signal line 75 are formed in through holes (in FIG. 6A). It is connected via). In FIGS. 6A and 6B, the wiring is indicated by a broken line so that the lower side of the wiring can be seen. In the following description, descriptions of the insulating layer 87 and the through hole are omitted.

The current confinement layer 82 includes a current passage portion 82a through which current flows and a current blocking portion 82b that blocks current flow. The current blocking part 82b is provided so as to surround the light emitting thyristor L1 in a U shape. The other part is a current passage part 82a.
Further, a back electrode 88 serving as a Vsub terminal is provided on the back surface of the p-type substrate 80.

  Each island surrounds the side surface of the light-emitting thyristor L (the side surface indicated by arrows α, β, and γ of the light-emitting thyristor L4) from three sides in a U-shape as shown by the light-emitting thyristor L4 in FIG. In addition, the second separation unit M2 is configured, and the other parts are separated by the first separation unit M1.

Next, the planar structure of the light-emitting chip C will be described with reference to FIG. 6A with reference to FIG.
The first island 301 is provided with a light emitting thyristor L1, a transfer thyristor T1, and a coupling diode Dx1. The second island 302 is provided with a power supply line resistance Rgx1. The third island 303 is provided with a start diode Dx0. The fourth island 304 is provided with a current limiting resistor R1, and the fifth island 305 is provided with a current limiting resistor R2.
In the light emitting chip C, a plurality of islands similar to the first island 301 and the second island 302 are provided in parallel. These islands are provided with light emitting thyristors L2 to L128, transfer thyristors T2 to T128, coupling diodes Dx2 to Dx127, and power supply line resistors Rgx2 to Rgx128. 6A shows only the light emitting thyristors L2 to L4, the transfer thyristors T2 to T4, the coupling diodes Dx2 to Dx4, and the power supply line resistors Rgx2 to Rgx4.

In the light emitting thyristor L1 provided on the first island 301, the n-type first semiconductor layer 84 (n-type gate layer) and the p-type second semiconductor layer 85 (p-type gate layer) function as gates. Then, the p-type second semiconductor layer 85 (p-type gate layer) is used as a gate, and control is performed via the gate terminal Gl1. Then, light is emitted between the n-type first semiconductor layer 84 (n-type gate layer) and the p-type second semiconductor layer 85 (p-type gate layer). The p-type substrate 80, the first multilayer-film reflective mirror 81, the current confinement layer 82, and the second multilayer-film reflective mirror 83 function as an anode (anode layer). The anode (anode layer) is connected to a back electrode 88 provided on the back surface of the p-type substrate 80. The back electrode 88 is an anode terminal.
In the light emitting thyristor L1, the n-type third semiconductor layer 86 functions as a cathode (cathode layer). Note that the n-type third semiconductor layer 86 is formed in an island shape and serves as a cathode region 311. The n-type ohmic electrode 321 provided on the cathode region 311 is used as a cathode terminal.
The p-type ohmic electrode 331 provided on the p-type second semiconductor layer 85 exposed by removing the n-type third semiconductor layer 86 is defined as a gate terminal Gl1.
Light is emitted from the cathode region 311 not covered with the p-type ohmic electrode 331 through the insulating layer 87.

The transfer thyristor T1 provided on the first island 301 has the n-type first semiconductor layer 84 (n-type gate layer) and the p-type second semiconductor layer 85 (p-type gate layer) function as gates. Similarly to the light emitting thyristor L1, the p-type second semiconductor layer 85 (p-type gate layer) is used as a gate, and control is performed via the gate terminal Gt1. Similar to the light emitting thyristor L1, the p-type substrate 80, the first multilayer-film reflective mirror 81, the current confinement layer 82, and the second multilayer-film reflective mirror 83 function as an anode (anode layer). The anode (anode layer) is connected to the back electrode 88. The back electrode 88 is an anode terminal.
In the transfer thyristor T1, the n-type third semiconductor layer 86 functions as a cathode (cathode layer). Note that the n-type third semiconductor layer 86 is formed in an island shape and serves as a cathode region 312. The n-type ohmic electrode 322 provided on the cathode region 312 is used as a cathode terminal.
The p-type ohmic electrode 331 provided on the p-type second semiconductor layer 85 exposed by removing the n-type third semiconductor layer 86 is defined as a gate terminal Gt1.

Similarly, in the coupling diode Dx1 provided on the first island 301, the p-type second semiconductor layer 85 functions as an anode (anode layer). The p-type ohmic electrode 331 provided on the p-type second semiconductor layer 85 exposed by removing the n-type third semiconductor layer 86 is used as an anode terminal.
In the coupling diode Dx1, the n-type third semiconductor layer 86 functions as a cathode (cathode layer). Note that the n-type third semiconductor layer 86 is formed in an island shape and serves as a cathode region 313. The n-type ohmic electrode 323 provided on the cathode region 313 is used as a cathode terminal.

  As shown in FIG. 6B, in the light-emitting thyristor L1, the transfer thyristor T1, and the coupling diode Dx1, the first multilayer reflector 81, the current confinement layer 82, the second multilayer reflector 83, the n-type first reflector. The first semiconductor layer 84 and the p-type second semiconductor layer 85 are connected. The gate terminal Gl1 of the light emitting thyristor L1, the gate terminal Gt1 of the transfer thyristor T1, and the anode terminal of the coupling diode Dx1 are common to the p-type ohmic electrode 331. Here, the p-type ohmic electrode 331 may be referred to as the gate terminal Gt1 / Gl1.

  The power supply line resistance Rgx1 provided on the second island 302 includes the p-type ohmic electrode 332 provided on the p-type second semiconductor layer 85 exposed by removing the n-type third semiconductor layer 86 and the p-type. The p-type second semiconductor layer 85 between the ohmic electrode 333 is a resistance.

In the start diode Dx0 provided on the third island 303, the p-type second semiconductor layer 85 functions as an anode (anode layer). The p-type ohmic electrode 334 provided on the p-type second semiconductor layer 85 exposed by removing the n-type third semiconductor layer 86 is used as an anode terminal.
In the start diode Dx0, the n-type third semiconductor layer 86 functions as a cathode (cathode layer). Note that the n-type third semiconductor layer 86 is formed in an island shape and serves as a cathode region 314. The n-type ohmic electrode 324 provided on the cathode region 314 is a cathode terminal.

  The current limiting resistor R1 provided on the fourth island 304 and the current limiting resistor R2 provided on the fifth island 305 are each two p-types like the power supply line resistor Rgx1 provided on the second island 302. The p-type second semiconductor layer 85 between the ohmic electrodes (not shown) is used as a resistor.

In FIG. 6A, the connection relationship between each element will be described.
The lighting signal line 75 includes a trunk portion 75a and a plurality of branch portions 75b. The trunk portion 75a is provided so as to extend in the row direction of the light emitting thyristor row. The branch portion 75 b branches off from the trunk portion 75 a and is connected to an n-type ohmic electrode 321 that is a cathode terminal of the light emitting thyristor L 1 provided on the first island 301. The same applies to the cathode terminals of the other light-emitting thyristors L.
The lighting signal line 75 is connected to a φI terminal provided on the light emitting thyristor L1 side in the light emitting thyristor array.

The first transfer signal line 72 is connected to an n-type ohmic electrode 322 that is a cathode terminal of the transfer thyristor T1 provided on the first island 301. The first transfer signal line 72 is also connected to the cathode terminal of another odd-numbered transfer thyristor T provided on an island similar to the first island 301. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R1 provided on the fourth island 304.
On the other hand, the second transfer signal line 73 is connected to an n-type ohmic electrode (unsigned) that is a cathode terminal of an even-numbered transfer thyristor T provided on an island without a symbol. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2 provided on the fifth island 305.

  The power supply line 71 is connected to the p-type ohmic electrode 333 that is one terminal of the power supply line resistance Rgx1 provided on the second island 302. One terminal of the other power line resistor Rgx is also connected to the power line 71. The power supply line 71 is connected to the Vga terminal.

The p-type ohmic electrode 331 which is the gate terminal Gt1 / Gl1 of the light emitting thyristor L2 and the transfer thyristor T2 in the first island 301 is connected to the p-type ohmic electrode 332 which is the other terminal of the power supply line resistance Rgx1 in the second island 302. 76 is connected. The p-type ohmic electrode 331 is connected to the n-type ohmic electrode 324 that is the cathode terminal of the start diode Dx0 in the third island 303 by a connection wiring 76.
The p-type ohmic electrode 334 that is the anode terminal of the start diode Dx0 is connected to the second transfer signal line 73.

The n-type ohmic electrode 323 that is the cathode terminal of the coupling diode Dx1 provided on the first island 301 is a p-type ohmic electrode that is the gate terminal Gt2 / Gl2 of the light-emitting thyristor L2 and the transfer thyristor T2 provided adjacent to each other. Are connected by connection wiring 77.
Although not described here, the same applies to other light-emitting thyristors L, transfer thyristors T, coupling diodes Dx, and power supply line resistors Rgx.

  The power line 71, the first transfer signal line 72, the second transfer signal line 73, the lighting signal line 75, the connection lines 76 and 77, and the like do not intersect the second separation unit M2, and the first separation unit M1. It is provided to cross.

(Operation of the light emitting device 65)
Next, the operation of the light emitting device 65 will be described.
As described above, the light emitting device 65 includes the light emitting chips C1 to C40 (see FIGS. 3 and 4).
Since the light emitting chips C1 to C40 are driven in parallel, it is sufficient to describe the operation of the light emitting chip C1.

<Thyristor>
Before describing the operation of the light emitting chip C1, the basic operation of the thyristor (transfer thyristor T, light emitting thyristor L) will be described. As described above, the thyristor is a semiconductor element having three terminals: an anode terminal, a cathode terminal, and a gate terminal.
In the following, as an example, the reference potential Vsub supplied to the back electrode 88 (see FIGS. 5 and 6), which is the Vsub terminal, is set to 0 V and the Vga terminal as a high level potential (hereinafter referred to as “H”). The power supply potential Vga supplied will be described as −3.3 V as a low level potential (hereinafter referred to as “L”).
The anode terminal of the thyristor is a reference potential Vsub (“H” (0 V)) supplied to the back electrode 88.

  As shown in FIG. 6, for example, the thyristor includes a p-type semiconductor layer (first multilayer reflector 81, current confinement layer 82, second multilayer reflector 83, and p-type first layer made of GaAs, GaAlAs, AlAs, or the like). 2 semiconductor layer 85) and an n-type semiconductor layer (n-type first semiconductor layer 84 and n-type third semiconductor layer 86) are stacked on a p-type substrate 80. That is, the thyristor has a pnpn structure. Here, a forward potential (diffusion potential) Vd of a pn junction composed of a p-type semiconductor layer and an n-type semiconductor layer is described as 1.5 V as an example.

A thyristor in an off state in which no current flows between the anode terminal and the cathode terminal transitions to an on state (turn on) when a potential lower than the threshold voltage (a negative potential having a large absolute value) is applied to the cathode terminal. To do. Here, the threshold voltage of the thyristor is a value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate terminal.
The potential of the gate terminal of the thyristor in the on state is close to the potential of the anode terminal. Here, since the anode terminal is set to the reference potential Vsub (“H” (0 V)), the potential of the gate terminal is assumed to be 0 V (“H”). Further, the cathode terminal of the thyristor in the on state has a potential close to the potential obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the anode terminal. Here, since the anode terminal is set to the reference potential Vsub (“H” (0 V)), the potential of the cathode terminal of the on-state thyristor is close to −1.5 V (the absolute value is larger than 1.5 V). Negative potential). Note that the potential of the cathode terminal is set in relation to a power source that supplies current to the thyristor in the on state.

In the on-state thyristor, the cathode terminal is set to a potential (a negative potential having a small absolute value, 0 V or a positive potential) higher than the potential necessary for maintaining the on-state (the potential close to −1.5 V). Then, the state is turned off (turned off).
On the other hand, a potential lower than the potential necessary to maintain the on state (a negative potential having a large absolute value) is continuously applied to the cathode terminal of the on state thyristor, and the current that can maintain the on state (sustain current) ) Is supplied, the thyristor remains on.
The light emitting thyristor L is turned on (emits light) when turned on, and turned off (not lit) when turned off. The amount of light emitted from the light emitting thyristor L in the on state is determined by the area of the cathode region (the cathode region 311 of the light emitting thyristor L1) and the current flowing between the cathode terminal and the anode terminal.
The transfer thyristor T emits light in the same manner as the light-emitting thyristor L. However, the area of the cathode region (the cathode region 312 of the transfer thyristor T1) is reduced or light is blocked by an electrode (the n-type ohmic electrode 322 of the transfer thyristor T1). As a result, the generation of unnecessary light is suppressed.

<Timing chart>
FIG. 7 is a timing chart for explaining operations of the light emitting device 65 and the light emitting chip C.
FIG. 7 shows a timing chart of a part that controls lighting (noted as lighting control) of the five light emitting thyristors L1 to L5 of the light emitting chip C1. In FIG. 7, the light emitting thyristors L1, L2, L3, and L5 of the light emitting chip C1 are turned on, and the light emitting thyristor L4 is turned off (not lighted).

In FIG. 7, it is assumed that time elapses from time a to time k in alphabetical order. The light emitting thyristor L1 is turned on or off in the period T (1), the light emitting thyristor L2 is turned on in the period T (2), the light emitting thyristor L3 is turned on in the period T (3), and the light emitting thyristor L4 is turned on or off in the period T (4). Lighting control (lighting control) is performed. Thereafter, the light-emitting thyristor L having a number of 5 or more is similarly controlled to be turned on.
Here, the periods T (1), T (2), T (3),... Have the same length, and are referred to as the period T when they are not distinguished from each other.

  The first transfer signal φ1 transmitted to the φ1 terminal (see FIGS. 5 and 6) and the second transfer signal φ2 transmitted to the φ2 terminal (see FIGS. 5 and 6) are “H” and “L”. A signal having two potentials. The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, the period T (1) and the period T (2)).

The first transfer signal φ1 shifts from “H” to “L” at the start time b of the period T (1), and shifts from “L” to “H” at the time f. Then, at the end time i of the period T (2), the state shifts from “H” to “L”.
The second transfer signal φ2 is “H” at the start time b of the period T (1), and shifts from “H” to “L” at the time e. Then, “L” is shifted to “H” at the end time i of the period T (2).
Comparing the first transfer signal φ1 and the second transfer signal φ2, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted after the period T on the time axis. On the other hand, in the second transfer signal φ2, in the period T (1), the waveform indicated by the broken line and the waveform in the period T (2) are repeated after the period T (3). The waveform of the period T (1) of the second transfer signal φ2 is different from that after the period T (3) because the period T (1) is a period during which the light emitting device 65 starts operating.

  As will be described later, a set of transfer signals of the first transfer signal φ1 and the second transfer signal φ2 emits light having the same number as the transfer thyristor T in the ON state by propagating the ON state in the transfer thyristor T in numerical order. The thyristor L is designated as a target for lighting or non-lighting control (lighting control).

Next, the lighting signal φI1 transmitted to the φI terminal of the light emitting chip C1 will be described. Note that lighting signals φI2 to φI40 are transmitted to the other light emitting chips C2 to C40, respectively. The lighting signal φI1 is a signal having two potentials of “H” and “L”.
Here, the lighting signal φI1 will be described in the lighting control period T (1) for the light emitting thyristor L1 of the light emitting chip C1. The lighting signal φI1 is “H” at the start time b of the period T (1), and shifts from “H” to “L” at the time c. Then, “L” is shifted to “H” at time d, and “H” is maintained at time e.

The operations of the light emitting device 65 and the light emitting chip C1 will be described according to the timing chart shown in FIG. 7 with reference to FIGS. Hereinafter, the periods T (1) and T (2) in which the lighting thyristors L1 and L2 are controlled to be lighted will be described.
(1) Time a
<Light emitting device 65>
At time a, the reference potential supply unit 160 of the signal generation circuit 110 of the light emitting device 65 sets the reference potential Vsub to “H” (0 V). The power supply potential supply unit 170 sets the power supply potential Vga to “L” (−3.3 V). Then, the power supply line 200a on the circuit board 62 of the light emitting device 65 becomes “H” of the reference potential Vsub, and the Vsub terminals of the light emitting chips C1 to C40 become “H”. Similarly, the power supply line 200b becomes “L” of the power supply potential Vga, and the Vga terminals of the light emitting chips C1 to C40 become “L” (see FIG. 4). Thereby, each power supply line 71 of the light emitting chips C1 to C40 becomes “L” (see FIG. 5).

  Then, the transfer signal generator 120 of the signal generation circuit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to “H”, respectively. Then, the first transfer signal line 201 and the second transfer signal line 202 become “H” (see FIG. 4). As a result, the φ1 terminal and φ2 terminal of each of the light emitting chips C1 to C40 become “H”. The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes “H”, and the second transfer signal line 73 connected to the φ1 terminal via the current limiting resistor R2 is also set. It becomes “H” (see FIG. 5).

  Further, the lighting signal generator 140 of the signal generation circuit 110 sets the lighting signals φI1 to φI40 to “H”, respectively. Then, the lighting signal lines 204-1 to 204-40 become “H” (see FIG. 4). Thereby, each φI terminal of the light emitting chips C1 to C40 becomes “H” via the current limiting resistor RI, and the lighting signal line 75 connected to the φI terminal also becomes “H” (see FIG. 5).

  Next, the operation of the light emitting chip C1 will be described.

<Light emitting chip C1>
Since the anode terminals of the transfer thyristor T and the light emitting thyristor L are connected to the Vsub terminal, they are set to “H”.

  The cathode terminals of the odd-numbered transfer thyristors T1, T3, T5,... Are connected to the first transfer signal line 72 and set to “H”. The cathode terminals of the even-numbered transfer thyristors T2, T4, T6,... Are connected to the second transfer signal line 73 and set to “H”. Therefore, the transfer thyristor T is in the OFF state because both the anode terminal and the cathode terminal are “H”.

  The cathode terminal of the light emitting thyristor L is connected to the “H” lighting signal line 75. Therefore, the light-emitting thyristor L is also in the off state because both the anode terminal and the cathode terminal are “H”.

  As described above, the gate terminal Gt1 at one end of the transfer thyristor array in FIG. 5 is connected to the cathode terminal of the start diode Dx0. The gate terminal Gt1 is connected to the power supply line 71 of the power supply potential Vga (“L”) via the power supply line resistance Rgx1. The anode terminal of the start diode Dx0 is connected to the second transfer signal line 73, and is connected to the φ2 terminal of “H” via the current limiting resistor R2. Therefore, the start diode Dx0 is forward-biased, and the cathode terminal (gate terminal Gt1) of the start diode Dx0 has a forward potential Vd (1.5 V) of the pn junction from the potential (“H”) of the anode terminal of the start diode Dx0. The value obtained by subtracting (−1.5 V). When the gate terminal Gt1 becomes −1.5V, the coupling diode Dx1 has an anode terminal (gate terminal Gt1) of −1.5V and a cathode terminal connected to the power supply line 71 (“L” (“L”) via the power supply resistance Rgx2. -3.3V)), it is forward biased. Therefore, the potential of the gate terminal Gt2 becomes −3 V obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (−1.5 V) of the gate terminal Gt1. However, the gate terminal Gt having a number of 3 or more is not affected by the fact that the anode terminal of the start diode Dx0 is “H” (0 V), and the potential of these gate terminals Gt is the potential of the power supply line 71. It is a certain “L” (−3.3 V).

  Since the gate terminal Gt is the gate terminal Gl, the potential of the gate terminal Gl is the same as the potential of the gate terminal Gt. Accordingly, the threshold voltages of the transfer thyristor T and the light emitting thyristor L are values obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potentials of the gate terminals Gt and Gl. That is, the threshold voltage of the transfer thyristor T1 and the light-emitting thyristor L1 is −3 V, the threshold voltage of the transfer thyristor T2 and the light-emitting thyristor L2 is −4.5 V, the threshold voltage of the transfer thyristor T and the light-emitting thyristor L having a number of 3 or more. Is -4.8V.

(2) Time b
At time b shown in FIG. 7, the first transfer signal φ1 shifts from “H” (0V) to “L” (−3.3V). As a result, the light emitting device 65 starts operating.
When the first transfer signal φ1 shifts from “H” to “L”, the potential of the first transfer signal line 72 shifts from “H” to “L” via the φ1 terminal and the current limiting resistor R1. Then, the transfer thyristor T1 having a threshold voltage of −3V is turned on. However, an odd-numbered transfer thyristor T having a cathode terminal connected to the first transfer signal line 72 and having an odd number of 3 or more cannot be turned on because the threshold voltage is −4.8V. On the other hand, the even-numbered transfer thyristor T cannot be turned on because the second transfer signal φ2 is “H” (0 V) and the second transfer signal line 73 is “H”.
When the transfer thyristor T1 is turned on, the potential of the first transfer signal line 72 is obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (“H” (0 V)) of the anode terminal. 5V.

When the transfer thyristor T1 is turned on, the potential of the gate terminal Gt1 / Gl1 becomes “H” which is the potential of the anode terminal of the transfer thyristor T1. The potential of the gate terminal Gt2 (gate terminal Gl2) is −1.5V, the potential of the gate terminal Gt3 (gate terminal Gl3) is −3V, and the potential of the gate terminal Gt (gate terminal Gl) having a number of 4 or more is “L”. "become.
Thus, the threshold voltage of the light emitting thyristor L1 is −1.5V, the threshold voltage of the transfer thyristor T2, the light emitting thyristor L2 is −3V, the threshold voltage of the transfer thyristor T3 and the light emitting thyristor L3 is −4.5V, and the number is The threshold voltage of four or more transfer thyristors T and light-emitting thyristors L becomes −4.8V.
However, since the first transfer signal line 72 is at −1.5 V by the transfer thyristor T1 in the on state, the odd-numbered transfer thyristor T in the off state is not turned on. Since the second transfer signal line 73 is “H”, the even-numbered transfer thyristor T is not turned on. Since the lighting signal line 75 is “H”, none of the light emitting thyristors L is turned on.

  Immediately after time b (in this case, when the thyristor or the like is changed due to a change in the signal potential at time b and then enters a steady state), the transfer thyristor T1 is in the on state, The transfer thyristor T and the light emitting thyristor L are in the off state.

(3) Time c
At time c, the lighting signal φI1 shifts from “H” (0 V) to “L” (−3.3 V).
When the lighting signal φI1 shifts from “H” to “L”, the lighting signal line 75 shifts from “H” to “L” via the current limiting resistor RI and the φI terminal. Then, the light emitting thyristor L1 having a threshold voltage of −1.5 V is turned on and lit (emits light). As a result, the potential of the lighting signal line 75 becomes a potential close to −1.5V (a negative potential having an absolute value greater than 1.5V). Note that the threshold voltage of the light emitting thyristor L2 is −3V, but the threshold voltage is as high as −1.5V (a negative potential having a small absolute value), the light emitting thyristor L1 is turned on, and the lighting signal line 75 is turned on. Since the potential is close to −1.5 V, the light emitting thyristor L2 is not turned on.
Immediately after time c, the transfer thyristor T1 is in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

(4) Time d
At time d, the lighting signal φI1 shifts from “L” (−3.3 V) to “H” (0 V).
When the lighting signal φI1 shifts from “L” to “H”, the potential of the lighting signal line 75 shifts from “L” to “H” via the current limiting resistor RI and the φI terminal. Then, since the anode terminal and the cathode terminal both become “H”, the light emitting thyristor L1 is turned off and turned off (not lit). During the lighting period of the light emitting thyristor L1, the lighting signal φI1 from the time c when the lighting signal φI1 shifts from “H” to “L” to the time d when the lighting signal φI1 shifts from “L” to “H” is “ L ".
Immediately after time d, the transfer thyristor T1 is in the ON state.

(5) Time e
At time e, the second transfer signal φ2 shifts from “H” (0 V) to “L” (−3.3 V). Here, the period T (1) for controlling the lighting of the light emitting thyristor L1 ends, and the period T (2) for controlling the lighting of the light emitting thyristor L2 starts.
When the second transfer signal φ2 shifts from “H” to “L”, the potential of the second transfer signal line 73 shifts from “H” to “L” via the φ2 terminal. As described above, the transfer thyristor T2 is turned on because the threshold voltage is -3V. Accordingly, the potential of the gate terminal Gt2 (gate terminal Gl2) is “H” (0 V), the potential of the gate terminal Gt3 (gate terminal Gl3) is −1.5 V, and the potential of the gate terminal Gt4 (gate terminal Gl4) is −3 V. become. Then, the potential of the gate terminal Gt (gate terminal Gl) having a number of 5 or more becomes −3.3V.
Immediately after time e, the transfer thyristors T1 and T2 are in the ON state.

(6) Time f
At time f, the first transfer signal φ1 shifts from “L” (−3.3 V) to “H” (0 V).
When the first transfer signal φ1 shifts from “L” to “H”, the potential of the first transfer signal line 72 shifts from “L” to “H” via the φ1 terminal. Then, the transfer thyristor T1 in the on state is turned off when both the anode terminal and the cathode terminal are set to “H”. Then, the potential of the gate terminal Gt1 (gate terminal Gl1) changes toward the power supply potential Vga (“L” (−3.3 V)) of the power supply line 71 via the power supply line resistance Rgx1. As a result, the coupling diode Dx1 is in a state in which a potential is applied in a direction in which no current flows (reverse bias). Therefore, the influence that the gate terminal Gt2 (gate terminal Gl2) is “H” (0 V) does not reach the gate terminal Gt1 (gate terminal Gl1). That is, in the transfer thyristor T having the gate terminal Gt connected by the reverse-biased coupling diode Dx, the threshold voltage becomes −4.8V, and the first transfer signal φ1 of “L” (−3.3V) or The second transfer signal φ2 does not turn on.
Immediately after time f, the transfer thyristor T2 is in the ON state.

(7) Others When the lighting signal φI1 shifts from “H” (0V) to “L” (−3.3V) at time g, the light emitting thyristor L2 is turned on similarly to the light emitting thyristor L1 at time c. Lights up (emits light).
At time h, when the lighting signal φI1 shifts from “L” (−3.3 V) to “H” (0 V), the light emitting thyristor L2 is turned off and extinguished similarly to the light emitting thyristor L1 at the time d. .
Further, when the first transfer signal φ1 shifts from “H” (0V) to “L” (−3.3V) at time i, similarly to the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. The transfer thyristor T3 having a threshold voltage of -3V is turned on. At time i, the period T (2) for controlling the lighting of the light emitting thyristor L2 ends, and the period T (3) for controlling the lighting of the light emitting thyristor L3 starts.
Thereafter, the above description is repeated.

  When the light-emitting thyristor L is not turned on (emitted) but remains turned off (non-lighted), the lighting signal shown from the time j to the time k in the period T (4) during which the light-emitting thyristor L4 in FIG. As with φI1, the lighting signal φI may remain “H” (0 V). By doing in this way, even if the threshold voltage of the light emitting thyristor L4 is −1.5 V, the light emitting thyristor L4 remains off (not lit).

As described above, the gate terminals Gt of the transfer thyristors T are connected to each other by the coupling diode Dx. Therefore, when the potential of the gate terminal Gt changes, the potential of the gate terminal Gt connected to the gate terminal Gt whose potential has changed via the forward-biased coupling diode Dx changes. Then, the threshold voltage of the transfer thyristor T having the gate terminal whose potential has changed changes. In the transfer thyristor T, when the threshold voltage is higher than “L” (−3.3 V) (a negative value having a small absolute value), the first transfer signal φ1 or the second transfer signal φ2 is changed from “H” (0 V). Turns on at the timing of shifting to “L” (−3.3 V).
Since the threshold voltage of the light emitting thyristor L in which the gate terminal Gl is connected to the gate terminal Gt of the transfer thyristor T in the on state is −1.5 V, the lighting signal φI is changed from “H” (0 V) to “L”. ”(−3.3V), it turns on and lights up (emits light).
That is, when the transfer thyristor T is turned on, the light emitting thyristor L that is the object of lighting control is designated, and the lighting signal φI sets the light emitting thyristor L that is the object of lighting control to be lit or not lit.
As described above, the waveform of the lighting signal φI is set according to the image data, and the lighting or non-lighting of each light-emitting thyristor L is controlled.

Hereinafter, details of the first multilayer-film reflective mirror 81, the current confinement layer 82, and the second multilayer-film reflective mirror 83 will be described.
(First multilayer film reflector 81, current confinement layer 82, second multilayer film reflector 83)
FIG. 8 is a diagram for explaining the first multilayer-film reflective mirror 81, the current confinement layer 82, and the second multilayer-film reflective mirror 83. FIG. 8A shows the first separator M1, and FIG. 8B shows the second separator M2.
The first multilayer reflector 81, the current confinement layer 82, and the second multilayer reflector 83 are sequentially stacked on the p-type substrate 80. A p-type first semiconductor layer 84 is stacked on the second multilayer-film reflective mirror 83.
The first separation unit M1 shown in FIG. 8A is configured by removing a part of the second multilayer-film reflective mirror 83 without reaching the current confinement layer 82. The second separation part M2 shown in FIG. 8B is configured by removing a part of the first multilayer-film reflective mirror 81 beyond the current confinement layer 82.

The first multilayer film reflecting mirror 81 and the second multilayer film reflecting mirror 83 are dielectric mirrors in which a plurality of layers having different refractive indexes are stacked, and utilize Bragg reflection generated between the layers. That is, the first multilayer-film reflective mirror 81 and the second multilayer-film reflective mirror 83 are distributed Bragg reflectors (DBRs) in which a plurality of layers are stacked.
2 is provided between the p-type substrate 80 and the first semiconductor layer 84 (p-type gate layer) in the light-emitting thyristor L, so that the light directed toward the p-type substrate 80 is reflected. The amount of light traveling toward the rod lens array 64 is increased. That is, the light extraction efficiency from the light emitting thyristor L is improved.

  On the other hand, the current confinement layer 82 is provided with a current blocking portion 82b that blocks the flow of current on three sides around the light emitting thyristor L (side surfaces indicated by arrows α, β, and γ of the light emitting thyristor L4 in FIG. 6A). As a result, the current flowing through the light-emitting thyristor L is concentrated (constricted) in the central portion, thereby increasing the carrier density and increasing the coupling efficiency between holes and electrons, thereby improving the light-emitting efficiency.

  That is, in the light emitting chip C of the present embodiment, the current confinement layer 82 is provided to improve the light emission efficiency of the light emitting thyristor L, and the light extraction efficiency is improved by the first multilayer film reflecting mirror 81 and the second multilayer film reflecting mirror 83. Has improved. Thus, the amount of light emitted from the light emitting chip C is improved.

The layer configuration will be described with reference to FIGS.
The light emitting chip C is configured by using a III-V group compound semiconductor such as GaAs, GaAlAs, AlAs, and the like. Note that the conductivity type and concentration of the compound semiconductor are set by the added impurities.

The p-type substrate 80 is made of, for example, GaAs.
The first multilayer-film reflective mirror 81 is configured by laminating, for example, 10 pairs (pairs) of low refractive index layers 81a and high refractive index layers 81b alternately. The low refractive index layer 81a is, for example, a high Al composition layer of Al _0.9 Ga _0.1 As, and the high refractive index layer 81b is, for example, a p-type Al _0.2 Ga _0.8 As low Al composition layer. It is. The film thickness (optical path length) of the low refractive index layer 81a and the high refractive index layer 81b is set to, for example, 0.25 (1/4) λ with respect to the central wavelength λ of the reflected light. Note that the film thickness of a pair of the low refractive index layer 81a and the high refractive index layer 81b is about 120 nm.
The refractive index varies depending on the Al composition ratio, and the smaller the Al composition ratio, the smaller the refractive index. Therefore, a distributed Bragg reflector is configured by alternately laminating AlGaAs layers having different Al composition ratios.
Note that the reflectivity increases as the difference in refractive index between the stacked AlGaAs layers increases.

The second multilayer-film reflective mirror 83 is configured by alternately stacking, for example, three pairs (pairs) of low refractive index layers 83a and high refractive index layers 83b. The low refractive index layer 83a is, for example, a high Al composition layer of Al _0.8 Ga _0.2 As, and the high refractive index layer 83b is, for example, a p-type Al _0.2 Ga _0.8 As low Al composition layer. It is. The film thickness (optical path length) of the low refractive index layer 83a and the high refractive index layer 83b is set to, for example, 0.25 (1/4) λ with respect to the center wavelength λ of the reflected light. Note that the film thickness of a pair of the low refractive index layer 83a and the high refractive index layer 83b is about 120 nm.

The current confinement layer 82 is, for example, p-type AlAs. The film thickness (optical path length) of the current confinement layer 82 is set to, for example, 0.75 (3/4) λ.
As the Al composition ratio is larger (the concentration is higher), Al is more easily oxidized by a method such as steam oxidation described later. The rate of oxidation (ease of oxidation) increases more rapidly as the Al composition ratio increases.

The oxides generated by the oxidation of _Al (Al 2 _{O 3)} is less likely to conduct current. That is, the current confinement layer 82 forms a current blocking portion 82b that blocks the flow of current by an oxide (Al ₂ O ₃ ) in which Al is oxidized. The portion of the current confinement layer 82 where Al is not oxidized is a current passage portion 82a through which a current flows.

  As described above, the current confinement layer 82 forms the current blocking portion 82b by generating an oxide of Al. Therefore, the Al composition ratio is any Al of the low refractive index layer 81a (high Al composition layer) of the first multilayer film reflector 81 and the low refractive index layer 83a (high Al composition layer) of the second multilayer film reflector 83. It is set larger than the composition ratio. Therefore, a material having a high Al composition ratio such as AlAs is preferably used for the current confinement layer 82. For example, AlGaAs having an Al composition ratio of 98% or more may be used.

The Al composition ratio of the low refractive index layer 81a (high Al composition layer) of the first multilayer film reflector 81 and the low refractive index layer 83a (high Al composition layer) of the second multilayer film reflector 83 are different. That is, the Al composition ratio of the low refractive index layer 83a (high Al composition layer) in the second multilayer film reflector 83 is set smaller than that of the low refractive index layer 81a (high Al composition layer) in the first multilayer film reflector 81. Has been.
This is because the wiring (the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, the lighting signal line 75, the connection wirings 76, 77, etc.) does not cross the second separation part M2, and the first separation. This is because it is provided so as to intersect the part M1.
Hereinafter, the reason will be described.

The current blocking portion 82b of the current confinement layer 82 is formed by oxidizing Al in the composition. The current confinement layer 82 is sandwiched between the first multilayer film reflecting mirror 81 and the second multilayer film reflecting mirror 83.
The oxidation of the current confinement layer 82 is performed by exposing the side surface of the current confinement layer 82 and oxidizing from the side surface.
For this reason, as shown in FIG. 8B, a second separation portion M2 is provided that extends beyond the current confinement layer 82 and is partly removed from the first multilayer-film reflective mirror 81. Will be exposed. At this time, a surface M2S where the first multilayer-film reflective mirror 81 is exposed is formed in the second separation portion M2. The surface M2S includes the exposed side surface of the first multilayer-film reflective mirror 81. Here, the surface M2S will be described as the bottom surface of the second separation unit M2.

As described above, the current confinement layer 82 concentrates the current flowing through the light emitting thyristor L in the central portion by the current blocking portion 82b, thereby improving the light emission efficiency. Therefore, it is not necessary to provide the current blocking unit 82b in the transfer thyristor T, the coupling diode Dx, or the like. On the other hand, in the transfer thyristor T, the coupling diode Dx, and the like, if the current blocking unit 82b is provided, the on-state resistance increases and the operation is hindered.
Therefore, for the elements other than the light emitting thyristor L, as shown in FIG. 8A, the first separation in which part of the second multilayer reflector 83 is removed without reaching the current confinement layer 82. The portion M1 is provided so that the side surface of the current confinement layer 82 is not exposed.

  Note that the film thickness of a pair of the low refractive index layer 83a and the high refractive index layer 83b constituting the second multilayer-film reflective mirror 83 is about 120 nm. Then, it is difficult to make the exposed surface M1S the high refractive index layer 83b (low Al composition layer) because of the accuracy of etching for forming the first separation portion M1. That is, on the exposed surface M1S, the high refractive index layer 83b (low Al composition layer) appears or the low refractive index layer 83a (high Al composition layer) appears. Further, a part of the surface M1S becomes the low refractive index layer 83a (high Al composition layer) and the rest becomes the high refractive index layer 83b (low Al composition layer), or the reverse state occurs.

  Then, on the exposed surface M1S of the first separation portion M1, the Al component of the low refractive index layer 83a (high Al composition layer) is oxidized with the oxidation of the current confinement layer 82, and the surface becomes rough or turns black. Or Then, the adhesiveness of the insulating layer 87 (see FIG. 6B) provided thereon is lowered, and wiring (power supply line 71, first transfer signal line 72, second transfer signal line 73, lighting signal line 75). Etc.) is difficult to form. Further, the reliability of the light emitting chip C is lowered. Furthermore, the reliability of the print head 14 and the image forming apparatus 1 is also reduced.

Therefore, in the present embodiment, the Al composition ratio of the low refractive index layer 83a (high Al composition layer) of the second multilayer film reflector 83 is set to the low refractive index layer 81a (high Al composition) of the first multilayer film reflector 81. Is set lower than that of the layer), and the oxidation of the exposed surface M1S of the first separation portion M1 is suppressed. A wiring is provided so as to intersect the first separation portion M1.
As described above, the higher the Al composition ratio, the more easily the Al component is oxidized, and the oxidation rate (ease of oxidation) of the Al component greatly varies depending on the Al composition ratio.
For example, by setting the Al composition ratio of the low refractive index layer 83a (high Al composition layer) of the second multilayer-film reflective mirror 83 to, for example, the above-described value (0.8), the oxidation of the Al component is suppressed, There is no problem in forming the insulating layer 87 and the wiring.
Even if the Al component contained in the low refractive index layer 81a (high Al composition layer) of the first multilayer-film reflective mirror 81 is oxidized during the oxidation of the current confinement layer 82, the wiring is not separated from the first separation portion. Since it intersects with M1, it does not affect the formation of wiring.
Therefore, the yield and reliability of the light emitting chip C are improved, and the reliability of the print head 14 and the image forming apparatus 1 is improved.

However, when the Al composition ratio of the low refractive index layer 83a (high Al composition layer) of the second multilayer-film reflective mirror 83 is lowered, the refractive index is increased and the reflectance as a distributed Bragg reflector is lowered. For this reason, the number of pairs of the second multilayer-film reflective mirror 83 is preferably reduced. For example, if there are three pairs, a decrease in reflectance is suppressed to a small level, and the surface M1S is provided in the second multilayer-film reflective mirror 83 in the etching of the first separation portion M1.
In the light emitting thyristor L, light emission occurs at the boundary between the n-type first semiconductor layer 84 (n-type gate layer) and the p-type second semiconductor layer 85 (p-type gate layer). Therefore, it is preferable that carriers are efficiently injected into this boundary. Therefore, the closer the distance between this boundary and the current confinement layer 82 is, the better. Also from this, the smaller the film thickness (number of pairs) of the second multilayer-film reflective mirror 83 is, the better.

  On the other hand, since no wiring is provided so as to intersect the surface M2S of the second separation portion M2 shown in FIG. 8B, even if the surface M2S is rough, it is allowed. Therefore, in the first multilayer-film reflective mirror 81, the Al composition ratio of the low refractive index layer 81a (high Al composition layer) is increased so that a high reflectance can be obtained.

As shown in FIGS. 8A and 8B, the current confinement layer 82 is between the first multilayer film reflecting mirror 81 and the second multilayer film reflecting mirror 83, and has a low refractive index layer (high Al composition layer). Function as. That is, the first multilayer film reflecting mirror 81, the current confinement layer 82, and the second multilayer film reflecting mirror 83 are regarded as a multilayer film reflecting mirror as a whole.
Further, the film thickness (optical path length) of the current confinement layer 82 may be 0.25 (1/4) λ, similarly to the low refractive index layers 81a and 83a. However, if the film thickness (optical path length) of the current confinement layer 82 is thin, the progress of oxidation becomes slow and the film becomes susceptible to variations in film thickness. Therefore, the film thickness (optical path length) of the current confinement layer 82 is preferably set to an integral multiple of 0.25 (1/4) λ.

  When the film thickness (optical path length) of the current confinement layer 82 is an odd multiple of 0.25 (1/4) λ, the lower side of the current confinement layer 82 is the high refractive index layer of the first multilayer reflector 81. 81b (low Al composition layer) and the upper side may be sandwiched between high refractive index layers 83b (low Al composition layer) of the second multilayer film reflector 83. FIGS. 8A and 8B show this configuration because the thickness (optical path length) of the current confinement layer 82 is 0.75 (3/4) λ.

  On the other hand, when the film thickness (optical path length) of the current confinement layer 82 is an even multiple of 0.25 (1/4) λ, the lower side of the current confinement layer 82 is the high refractive index layer of the first multilayer reflector 81. 81b (low Al composition layer) and the upper side may be sandwiched between low refractive index layers 83a (high Al composition layer) of the second multilayer-film reflective mirror 83.

(Method for manufacturing light-emitting chip C)
A method for manufacturing the light-emitting chip C will be described.
Here, a cross-section taken along the line P-P (P-P cross-section) in FIG. 6A and a cross-section taken along the line Q-Q (Q-Q cross-section) will be described. The cross section taken along the line P-P is a cross section at the first separation portion M1, and is a cross section of the transfer thyristor T1. The cross section taken along the line QQ is a cross section at the second separation portion M2, and is a cross section of the light emitting thyristor L1.

  FIG. 9 is a diagram for explaining the steps up to the gate out etching step. 9 (a1), (b1), and (c1) are cross-sectional views taken along the line P-P in FIG. 6 (a). FIGS. 9 (a2), (b2), and (c2) are illustrated in FIG. It is sectional drawing in the QQ line. The process proceeds in the order of (an), (bn), and (cn). n is 1 or 2.

As shown in FIGS. 9A1 and 9A2, a first multilayer reflector 81, a current confinement layer 82, a second multilayer reflector 83, and an n-type first semiconductor layer are formed on a p-type substrate 80. 84, a p-type second semiconductor layer 85 and an n-type third semiconductor layer 86 are stacked.
The p-type substrate 80, the first multilayer reflector 81, the current confinement layer 82, and the second multilayer reflector 83 have already been described. The first multilayer reflector 81, the current confinement layer 82, and the second multilayer reflector 83 are p-type semiconductor layers.
The n-type first semiconductor layer 84 is, for example, n-type Al _0.3 Ga _0.7 As having a film thickness (optical path length) of 1.25 (5/4) λ. The p-type second semiconductor layer 85 is, for example, p-type Al _0.14 Ga _0.86 As having a film thickness (optical path length) of 2.25 (9/4) λ. The n-type third semiconductor layer 86 is n-type GaAs or AlGaAs.

  Next, as shown in FIGS. 9B1 and 9B2, n-type ohmic electrodes 321 and 322 made of AuGe or the like that are in ohmic contact with the n-type third semiconductor layer 86 are formed on the n-type third semiconductor layer 86. Is formed by a lift-off method or the like.

Then, as shown in FIGS. 9C1 and 9C2, a part of the n-type third semiconductor layer 86 is removed by etching to expose the p-type second semiconductor layer 85. This process is called gate out etching.
First, by photolithography, a photoresist mask pattern 91 corresponding to the cathode region 312 of the transfer thyristor T1 is formed in FIG. 9C1, and in FIG. 9C2, it corresponds to the cathode region 311 of the light emitting thyristor L1. A photoresist mask pattern 92 is formed. Then, for example, wet etching is performed with a sulfuric acid-based etching solution (by weight, sulfuric acid: hydrogen peroxide solution: water = 1: 10: 300). As a result, the cathode region 312 of the transfer thyristor T1 is formed in FIG. 9C1, and the cathode region 311 of the light emitting thyristor L1 is formed in FIG. 9C2.
Thereafter, the mask patterns 91 and 92 are removed.

  Thereafter, although not shown, a p-type ohmic electrode 331 made of AuZn or the like that is in ohmic contact with the p-type second semiconductor layer 85 is formed on the exposed p-type second semiconductor layer 85 by a lift-off method or the like. .

  FIG. 10 is a diagram for explaining a process after the gate-etching etching. 10 (a1), (b1), and (c1) are cross-sectional views taken along the line P-P in FIG. 6 (a). FIGS. 10 (a2), (b2), and (c2) are illustrated in FIG. It is sectional drawing in the QQ line. The process proceeds in the order of (an), (bn), and (cn). n is 1 or 2.

In FIGS. 10A1 and 10A2, the first separation portion M1 is formed by etching.
First, in FIG. 10A1 and FIG. 10A2, a photoresist mask pattern 93 corresponding to the planar shape of the first island 301 is formed by photolithography. As can be seen from FIG. 6A, the mask pattern 93 is formed to be connected from the light emitting thyristor L1 to the transfer thyristor T1. Although not shown, mask patterns corresponding to islands such as other second islands 302 are also formed at the same time.
Then, for example, the second multilayer-film reflective mirror 83 is exposed by wet etching using a sulfuric acid-based etching solution (sulfuric acid: hydrogen peroxide water: water = 1: 10: 300 in weight ratio). Thereby, as shown to Fig.6 (a), (b), islands, such as the 1st island 301 and the 2nd island 302, are isolate | separated.
Thereafter, the mask pattern 93 is removed.

Next, in FIG. 10 (b2), the second separation portion M2 is formed.
First, a photoresist mask pattern 94 is formed by photolithography so as to expose the three side surfaces of the light-emitting thyristor L1 (side surfaces of the arrows α, β, and γ in the light-emitting thyristor L4 in FIG. 6A). The same applies to the other light emitting thyristors L. As shown in FIG. 10B1, the transfer thyristor T1 and the like appearing in the cross-sectional view along the line P-P are covered with a mask pattern 94 so as not to be etched. As can be seen from FIG. 6A, the mask pattern 94 is formed from the light emitting thyristor L1 to the transfer thyristor T1.
Then, for example, the exposed second multilayer reflector 83 and the current confinement layer 82 are removed by wet etching using a phosphorous etching solution (phosphoric acid: hydrogen peroxide water: water = 1: 10: 60 in weight ratio). Then, the first multilayer-film reflective mirror 81 is exposed. Thereby, the side surface of the current confinement layer 82 is exposed on the three side surfaces of the light emitting thyristor L1. However, since the side surfaces of the transfer thyristor T1 and the like are covered with the mask pattern 94, the side surfaces of the current confinement layer 82 are not exposed.
Thereafter, the mask pattern 94 is removed.

  In addition, you may perform the etching which forms the 2nd isolation | separation part M2 by anisotropic dry etching which used boron chloride, for example. If the first separation part M1 or the second separation part M2 is formed by anisotropic dry etching, a current flows on the surface of the first separation part M1 or the second separation part M2 unless an appropriate surface treatment is performed. This makes it easier for the thyristor to turn on. The light emitting thyristor L may be easily turned on. However, if the transfer thyristor T is easily turned on, the transfer using the first transfer signal φ1 and the second transfer signal φ2 is not normally performed. Therefore, the etching for forming the first separation part M1 is preferably performed by wet etching.

Then, as shown in FIG. 10C2, the current confinement layer 82 exposed on the side surface of the second isolation portion M2 is oxidized from the side surface to form a current blocking portion 82b that blocks current. The portion that remains without being oxidized becomes the current passage portion 82a.
For example, due to steam oxidation at 300 to 400 ° C., oxidation proceeds from the exposed side surface of the current constriction layer 82 that is AlAs, and current blocking by Al ₂ O ₃ that is an oxide of Al is formed around the three sides of the light-emitting thyristor L. A portion 82b is formed.
Then, a back electrode 88 is formed on the back surface of the p-type substrate 80.

  Thereafter, although not shown, an insulating layer 87 is formed. Next, a through hole is formed in the insulating layer 87 with respect to the electrodes such as the n-type ohmic electrodes 321 and 322 and the p-type ohmic electrode 331 (（in FIG. 6A). Then, wirings (power supply line 71, first transfer signal line 72, second transfer signal line 73, lighting signal line 75, connection wirings 76, 77, etc.) are formed.

As described above, the current confinement layer 82 is oxidized from three sides around the light emitting thyristor L to form the current blocking portion 82b that blocks the current, and the current is concentrated in the central portion of the light emitting thyristor L. In addition to improving the light emission efficiency (constricted), the first multilayer film reflecting mirror 81 and the second multilayer film reflecting mirror 83 reflect the light toward the substrate 80, thereby improving the light extraction efficiency. As a result, the amount of light emitted from the light emitting thyristor L is increased.
Further, the Al composition ratio of the low refractive index layer 83a (high Al composition layer) in the second multilayer film reflector 83, and the Al composition ratio of the low refractive index layer 81a (high Al composition layer) in the first multilayer film reflector 81. Compared to the above, by lowering, the surface M1S of the first separation portion M1 is prevented from being roughened by oxidation and preventing the formation of the insulating layer 87 and the wiring.

(Modification)
In the present embodiment shown in FIG. 9, the second multilayer-film reflective mirror 83 is configured by alternately laminating low refractive index layers 83a and high refractive index layers 83b. The low refractive index layer 83a (high Al composition layer) is set to have a lower Al composition ratio than the low refractive index layer 81a (high Al composition layer) in the first multilayer-film reflective mirror 81.
However, as described above, the low refractive index layer 83a (high Al composition layer) of the second multilayer-film reflective mirror 83 has a rough surface formed by oxidation on the exposed surface M1S of the first separation portion M1. Should just be suppressed. That is, the Al composition ratio of the low refractive index layer 83a (high Al composition layer) in the portion of the second multilayer film reflector 83 that can be the surface M1S may be lowered compared to other portions to suppress oxidation. .

FIG. 11 is a cross-sectional view showing a modification of the light emitting chip C of the present embodiment. Here, in FIG. 11, the substrate 80, the first multilayer-film reflective mirror 81, the current confinement layer 82, the second multilayer-film reflective mirror 83, and the n-type first semiconductor layer 84 are shown.
The second multilayer-film reflective mirror 83 includes an upper part 83A and a lower part 83B. In the upper part 83A, a low refractive index layer 83a (high Al composition layer) and a high refractive index layer 83b (low Al composition layer) are repeatedly laminated. In the lower part 83B, a low refractive index layer 83c (high Al composition layer) and a high refractive index layer 83d (low Al composition layer) are repeatedly laminated.
The Al composition ratio of the low refractive index layer 83a (high Al composition layer) in the upper part 83A is set lower than the low refractive index layer 83c (high Al composition layer) in the lower part 83B. The Al composition ratio of the low refractive index layer 83c (high Al composition layer) in the lower part 83B may be the same as that of the low refractive index layer 81a (high Al composition layer) of the first multilayer-film reflective mirror 81.
The surface M1S of the first separation part M1 is formed in the upper part 83A of the second multilayer-film reflective mirror 83. Therefore, exposure of the low refractive index layer 83c (high Al composition layer) of the lower portion 83B to the surface M1S of the first separation portion M1 is suppressed.

That is, the low refractive index layer 83a (high Al composition layer) of the second multilayer-film reflective mirror 83 appearing on the surface M1S of the first separation part M1 may have an Al composition ratio that does not cause roughening due to oxidation.
In the second multilayer film reflecting mirror 83, the low refractive index layer 83a (high Al composition layer) having a low Al composition ratio in a range (thickness) affected by oxidation, that is, a range in which roughness or the like occurs (thickness). May be configured to include.

  As described above, in the light emitting chip C of the present embodiment, both the prevention of oxidation of the exposed distributed black reflective layer and the suppression of the decrease in reflectance of the distributed black reflective layer are achieved.

  In the present embodiment, the light emitting thyristor L, the transfer thyristor T, and the coupling diode Dx are formed on one island, but the island of the light emitting thyristor L and the island of the transfer thyristor T and the coupling diode Dx may be used. That is, the second separation part M2 is formed in the peripheral part of the light emitting thyristor L, and the current confinement layer 82 is oxidized from the second separation part M2 to block the current. And a wiring should just be formed so that the 1st isolation | separation part M1 may be crossed.

In the present embodiment, the thyristor (transfer thyristor T, light emitting thyristor L) has been described as an anode common in which the anode terminal is connected to the substrate 80. The thyristor (transfer thyristor T, light-emitting thyristor L) may be a cathode common whose cathode terminal is connected to the substrate 80 by changing the polarity of the circuit.
In addition, although the n-type ohmic electrode 321 is provided at the center of the cathode region 311 of the light emitting thyristor L, the n-type ohmic electrode 321 may be provided at a position shifted from the center of the cathode region 311. .
Further, the n-type ohmic electrode 321 may not be provided.

Further, in the present embodiment, the self-scanning light emitting element array (SLED) composed of the light emitting thyristor L and the transfer thyristor T has been described. However, the self scanning light emitting element array (SLED) transfers with the light emitting thyristor L. In addition to the thyristor T, a thyristor for control and / or other members such as a diode and a resistor may be included.
Further, in the present embodiment, the transfer thyristors T are connected by the coupling diode Dx, but may be a member that can transmit a change in potential such as resistance.

  In the present embodiment, the light emitting element is the light emitting thyristor L, but the light emitting element may be a light emitting diode (LED) in which a p-type semiconductor layer and an n-type semiconductor layer are stacked.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... Image forming process part, 11 ... Image forming unit, 12 ... Photosensitive drum, 14 ... Print head, 30 ... Image output control part, 40 ... Image processing part, 62 ... Circuit board, 63 ... Light source unit, 64 ... rod lens array, 65 ... light emitting device, 71 ... power supply line, 72 ... first transfer signal line, 73 ... second transfer signal line, 75 ... lighting signal line, 75a ... trunk, 75b ... branch, 81: First multilayer mirror, 82: Current constricting layer, 82a: Current passage portion, 82b: Current blocking portion, 83: Second multilayer mirror, 84: First semiconductor layer, 85: Second semiconductor layer, 86 ... Third semiconductor layer, 87 ... Insulating layer, 88 ... Back electrode, 91, 92, 93, 94 ... Mask pattern, 110 ... Signal generation circuit, 120 ... Transfer signal generation unit, 140 ... Lighting signal generation unit, 160 ... Reference potential supply unit, 170 ... power source 1, a second transfer signal, φI (φI1 to φI40), a lighting signal, C (C1 to C40), a light emitting chip, Dx, a coupling diode, L, a light emitting thyristor, M1,. First separation unit, M2 ... second separation unit, T ... transfer thyristor, Vga ... power supply potential, Vsub ... reference potential

Claims (7)

A substrate,
On the substrate, a multilayer reflector made of a compound semiconductor containing aluminum with a current confinement layer interposed therebetween,
A plurality of semiconductor layers having different conductivity types are stacked on the multilayer reflector, and includes an island including a light emitting element.
The island is separated by a first separation part that reaches the multilayer reflector but does not reach the current confinement layer and a second separation part that reaches the current confinement layer,
The portion of the multilayer reflector that is exposed to the first separation portion has a lower aluminum composition ratio of the high aluminum composition layer than the portion of the multilayer reflector that is not exposed to the first separation portion. parts.   The multilayer reflector having a low aluminum composition ratio in the high aluminum composition layer is a portion in a thickness direction that is affected by oxidation when the current confinement layer is oxidized. The light-emitting component according to 1.   The portion of the multilayer reflector having a low aluminum composition ratio of the high aluminum composition layer is a portion farther from the substrate than the current confinement layer of the multilayer reflector. Light emitting parts.   4. The light-emitting component according to claim 1, wherein the second separation portion is provided in contact with the light-emitting element.   The light-emitting component according to claim 1, wherein wiring is provided so as to intersect the first separation portion. A substrate, a multilayer reflector made of a compound semiconductor containing aluminum with a current confinement layer sandwiched between the substrate, and a plurality of semiconductor layers having different conductivity types are stacked on the multilayer reflector. A plurality of islands comprising light emitting elements, and a light emitting means comprising:
Optical means for imaging light emitted from the light emitting means,
The plurality of islands are separated by a first separation part that reaches the multilayer reflector but does not reach the current confinement layer, or a second separation part that reaches the current confinement layer,
The multilayer film reflecting mirror portion exposed to the first separation part has a lower aluminum composition ratio of the high aluminum composition layer than the multilayer film reflection mirror part not exposed to the first separation part. head. An image carrier,
Charging means for charging the image carrier;
A substrate, a multilayer reflector made of a compound semiconductor containing aluminum with a current confinement layer sandwiched between the substrate, and a plurality of semiconductor layers having different conductivity types are stacked on the multilayer reflector. A plurality of islands having light emitting elements, and exposing means for exposing the image carrier through optical means;
Developing means for developing the electrostatic latent image exposed by the exposure means and formed on the image carrier;
Transfer means for transferring the image developed on the image holding member to a transfer target,
The plurality of islands are separated by a first separation part that reaches the multilayer reflector but does not reach the current confinement layer, or a second separation part that reaches the current confinement layer,
The portion of the multilayer reflector that is exposed at the first separation portion has a lower aluminum composition ratio of the high aluminum composition layer than the portion of the multilayer reflector that is not exposed at the first separation portion. Forming equipment.

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