JP2016503964A - Indium-doped silicon wafer and solar cell using the same - Google Patents

Abstract

Solar cells made from an indium-doped single crystal silicon wafer sliced from an ingot grown by the Czochralski method are provided. Solar cells are characterized by high efficiency and small light-induced degradation.

Description

[Cross-reference of related applications]
This application includes Italian Patent Application No. TO2012A001175 filed on December 31, 2012, International Patent Application No. PCT / EP2013 / 054878 filed on March 11, 2013, and March 11, 2013. Claims priority to filed International Patent Application No. PCT / EP2013 / 054875 and US Patent Application No. 61/886060 filed June 24, 2013, the disclosures of which are hereby incorporated by reference in their entirety Is incorporated herein by reference.

  The field relates generally to the manufacture of solar cells fabricated on single crystal silicon wafers, and more specifically solar cells fabricated on indium doped single crystal silicon wafers sliced from Czochralski grown single crystal silicon ingots. Regarding cells.

  Single crystal silicon, which is the starting material in most processes for the production of semiconductor electronic components, is generally prepared by the so-called Czochralski ("Cz") method. In this method, polycrystalline silicon (“polysilicon”) is loaded into a crucible and melted, the seed crystal is brought into contact with the molten silicon, and then slowly pulled to grow a single crystal. After the formation of the neck is complete, the crystal diameter is increased, for example, by lowering the pulling rate and / or melting temperature until the desired or target diameter is reached. Thereafter, a columnar body of crystals having a substantially constant diameter is grown by controlling the pulling speed and melting temperature while compensating for the decreasing melt level. Near the end of the growth process, before the molten silicon in the crucible disappears, the end of the end cone is generally formed by gradually reducing the crystal diameter. End cones are typically formed by increasing the crystal pull rate and the heat supplied to the crucible. After the diameter is sufficiently small, the crystals are separated from the melt.

  Solar cells can be made from single crystal silicon substrates produced by the Czochralski method. Czochralski-grown single crystal silicon substrates can be grown by either standard, ie, batch Czochralski or continuous Czochralski methods. In order to achieve an acceptable resistivity for solar cell applications, the growth crystal is mainly doped with boron. In diffusion bonded screen printed solar cells, the use of boron doped silicon wafers is industry standard (or industry standard, industry standard).

  The use of boron doped silicon wafers is not without problems. For example, it is known that oxygen impurities in Czochralski-grown crystals (generally due to crucibles) may interact with boron dopants that form complexes in the material. These oxygen complexes are activated when the substrate or the finished solar cell is exposed to light, which degrades the minority carrier lifetime and hence the efficiency of the finished solar cell. This phenomenon is called light induced degradation (LID) and is the main loss mechanism for solar cells fabricated on boron doped single crystal silicon wafers.

  In order to minimize the effects of LID, manufacturers reduce the amount of boron dopant atoms in each wafer, targeting a resistivity slightly higher than the optimum resistivity. Therefore, there is a trade-off between LID and optimal base resistance. As a result, the maximum efficiency of the solar battery cell cannot be realized.

  Briefly, therefore, one embodiment includes an indium-doped single crystal silicon wafer sliced from an ingot grown by the Czochralski method, and includes absolute air mass (or absolute air mass, absolute air mass). ) Conversion efficiency of solar spectral irradiance (or solar spectral irradiance, solar spectral illumination, solar spectral irradiance) on the surface of an indium-doped single crystal silicon wafer under 1.5 is at least 17% The present invention relates to a solar battery cell.

  Another embodiment includes an indium-doped single crystal silicon wafer sliced from an ingot grown by the Czochralski method, the wafer having an average bulk resistivity of less than about 10 Ω · cm and above 45 ° C. The present invention relates to a solar cell whose relative efficiency deteriorates by about 1% or less after being exposed to light corresponding to 0.1 to 10 SUN at a low temperature for 1 to 300 hours.

  Yet another embodiment includes an indium doped single crystal silicon wafer sliced from an ingot grown by the Czochralski method, where the wafer has an average bulk resistivity of less than about 10 Ω · cm and a temperature of less than 45 ° C. The solar battery cell has a relative efficiency of about 1% or less after being exposed to sunlight for 4 hours.

Still another aspect includes a central axis, a front surface and a rear surface that are substantially perpendicular to the central axis, a central surface that is between and parallel to the front surface and the rear surface, a peripheral edge, and a peripheral edge from the central axis. A radius R extending in the direction of at least about 1 × 10 ¹⁵ atoms / cm ³ and having a relative change in radial direction of about 15% or less over an indium concentration of at least 0.75R. It relates to crystalline silicon segments.

Another embodiment has a thickness between about 100 μm and about 1000 μm and two major dimensions between about 50 mm and about 300 mm, and has an average indium concentration of at least about 1 × 10 ¹⁵ atoms / cm ^3. And a single crystal silicon wafer having an indium concentration having a variation of about 15% or less over at least 75% of the length of either of the two major dimensions.

  Still another aspect includes a step of preparing a single crystal ingot growth apparatus including a chamber having an internal pressure and a crucible disposed in the chamber, a step of preparing a silicon melt in the crucible, and a surface of the silicon melt. Introducing an inert gas having a flow and flow rate into the chamber from a gas inlet over the silicon melt, introducing a volatile dopant containing indium into the silicon melt, and having an indium dopant concentration. A method of growing a single crystal silicon ingot, comprising: growing an indium doped single crystal silicon ingot; and controlling an indium dopant concentration in the ingot by adjusting a ratio between a flow rate of an inert gas and an internal pressure of the chamber. About.

Yet another embodiment has a central axis, a peripheral edge, a radius extending from the central axis to the peripheral edge, and a mass, an average indium concentration of at least about 5 × 10 ¹⁴ atoms / cm ³ , and an axis exceeding 20 cm. Relates to a single crystal silicon ingot having a radius greater than about 75 mm, including an axial change in indium concentration of less than about 5 × 10 ¹⁴ atoms / cm ³ over length.

  Another aspect includes a step of preparing a single crystal ingot growth apparatus including a chamber having an internal pressure, a crucible disposed in the chamber, and a liquid doping apparatus, a step of preparing a silicon melt in the crucible, and a silicon melt Introducing an inert gas having a flow rate over the surface of the silicon into the chamber from a gas inlet above the silicon melt, and introducing a volatile dopant containing indium into the silicon melt as a liquid; Single crystal silicon comprising growing an indium doped single crystal silicon ingot having an indium dopant concentration and controlling the indium dopant concentration in the ingot by adjusting a ratio between a flow rate of an inert gas and an internal pressure of the chamber It relates to a method for growing an ingot.

FIG. 1 is a cross-sectional view of a crystal growth chamber. FIG. 2 is a cross-sectional view of a liquid doping system used in a crystal growth chamber. FIG. 3 is an enlarged view of a supply pipe of the doping system shown in FIG. 4 is a cross-sectional view of the doping system of FIG. 2 being lowered toward the surface of the melt. FIG. 5 is a cross-sectional view of the doping system of FIG. 2 positioned near the surface of the melt. FIG. 6 is a depiction of a single crystal silicon ingot grown by the method disclosed herein. FIG. 7 is a depiction of an embodiment of a single crystal silicon wafer. 8A, 8B and 8C are graphs showing light absorption over the entire solar spectrum of solar cells fabricated on indium doped single crystal silicon wafers and solar cells fabricated on boron doped single crystal silicon wafers. FIG. 9 is a graph showing minority carrier lifetimes both before and after light soaking in a long-life boron-doped wafer (P01GJ-A4). Minority carrier lifetime data was obtained by the method described in Example 12. FIG. 10 is a graph showing minority carrier lifetimes both before and after light soaking in a boron doped wafer with an average lifetime (P00PC-C2). Minority carrier lifetime data was obtained by the method described in Example 12. FIG. 11 is a graph showing the minority carrier lifetime before and after light soaking (210T0N). Minority carrier lifetime data was obtained by the method described in Example 12. FIG. 12 is a box plot showing the normalized solar cell efficiency and solar cell module efficiency of boron-based and indium-based solar cells and solar cell modules after light soaking outdoors. These data were obtained by the method described in Example 13. FIG. 13 is a box-and-whisker plot showing normalized open-circuit voltages of boron-based and indium-based solar cells and solar cell modules after light soaking outdoors. These data were obtained by the method described in Example 13. FIG. 14 is a box-and-whisker diagram showing normalized short-circuit currents of boron-based and indium-based solar cells and solar cell modules after light soaking outdoors. These data were obtained by the method described in Example 13. FIG. 15 is a box-and-whisker diagram showing normalized curve factors of boron-based and indium-based solar cells and solar cell modules after light soaking outdoors. These data were obtained by the method described in Example 13. FIG. 16 is a box-and-whisker diagram showing% relative LID of boron-based and indium-based solar cells after light soaking outdoors. These data were obtained by the method described in Example 13. FIG. 17 is a box-and-whisker diagram showing the loss of solar cell absolute efficiency (or absolute solar cell efficiency) of boron-based and indium-based solar cells after outdoor light soaking. . These data were obtained by the method described in Example 13.

  The indium-doped single crystal silicon segments disclosed herein, such as wafers, are sliced from ingots grown by the Czochralski method. Indium doped single crystal silicon segments are useful in the fabrication of semiconductor and solar cells. Accordingly, in some embodiments, the present disclosure further relates to solar cells fabricated on indium-doped single crystal silicon wafers sliced from ingots grown by the Czochralski method. The indium doped single crystal silicon wafers of the present disclosure are characterized by a high conversion efficiency of sunlight spectral irradiance (eg, sunlight) on their surface. The indium-doped single crystal silicon wafer of the present disclosure is characterized by, among other things, high conversion efficiency of light in the infrared region of the solar spectrum. Thus, indium doped single crystal silicon wafers of the present disclosure have a spectral irradiance of sunlight of at least 17%, at least 18%, at least 19% or even at least 20% when measured under absolute air mass 1.5. Conversion efficiency is possible. Advantageously, the light induced degradation of the indium doped single crystal silicon wafer according to the present disclosure is substantially less than the LID of conventional boron doped solar cells. In some embodiments, the relative efficiency of solar cells degrades by about 1% or less after exposure to light, eg, sunlight. It has been observed that absolute light induced degradation is substantially less than 0.5% and in some cases less than 0.1%. In that respect, the indium doped single crystal silicon wafer of the present disclosure is particularly suitable for use in the manufacture of photovoltaic cells.

In some embodiments, the present disclosure relates to an indium doped single crystal silicon wafer sliced from a Czochralski growth ingot. Conveniently, the Czochralski growth ingot may be grown by a batch Cz process or a continuous Cz process. The use of indium as a dopant in silicon ingots grown by the Czochralski method presents several challenges. Indium is a highly volatile dopant and has a very low segregation coefficient compared to other dopants. For example, the segregation coefficient of indium is about 4 × 10 ⁻⁴ compared to the segregation coefficient of boron of 0.8. As a result, the indium dopant concentration in the silicon melt can vary by orders of magnitude during a single chocolate ski batch growth process. The axial dopant concentration in the grown ingot (ie, along the length of the ingot) can also change by orders of magnitude as a result of changing the dopant concentration in the silicon melt. Such axial variations are undesirable because the resistivity of the wafer obtained from the ingot will depend on the position of the wafer within the ingot. Thus, the disclosed method allows conditions to be controlled in either a batch Cz process or a continuous Cz process, with the length of the wafer radius measured along the axial length of the single crystal silicon ingot and from the central axis to the edge. Ensure uniform indium dopant along the length.

  In some embodiments, the single crystal silicon substrate includes segments of a single crystal silicon ingot, ie, a portion sliced from the single crystal silicon ingot. In some embodiments, the single crystal silicon substrate comprises a single crystal silicon wafer. In some embodiments, the silicon wafer comprises a wafer sliced from a single crystal silicon wafer sliced from a single crystal ingot grown by the Czochralski crystal growth method described herein. Single crystal silicon ingots have a nominal diameter achievable by the Czochralski crystal growth method. In general, the nominal diameter may be at least about 150 mm, about 200 mm, or greater than about 200 mm, such as 205 mm, 250 mm, 300 mm, or even 450 mm. Indium-doped single crystal silicon wafers may be sliced from ingots having a circular shape associated with semiconductor applications, or may be sliced to have a generally square shape for the production of solar cells.

  In some embodiments, the indium doped single crystal silicon wafer is prepared for semiconductor applications. Similar to standard processes for preparing wafers for semiconductor manufacturing, including silicon slicing, lapping, etching and polishing techniques, ingot growth is described, for example, in F.C. Shimura's Semiconductor Silicon Crystal Technology (Academic Press, 1989); Grabmaier (eds.), Silicon Chemical Etching (Springer Ferrak, New York, 1982) (incorporated herein by reference).

  In some embodiments, the indium doped single crystal silicon wafer is prepared for the production of solar cells. The wafer may be sliced into a substantially square shape (see FIG. 7). Substantially square (or semi-square) cells start from a circular wafer, but the edges are cut so that many cells can be filled more efficiently into rectangular modules.

  Ingots prepared by the Czochralski method generally contain oxygen impurities, which can enter the silicon melt from the surrounding atmosphere and crucible walls. During crystal growth, the molten silicon etches or dissolves the quartz that forms the crucible, thereby producing oxygen doping. Oxygen is dispersed throughout the crystal and may collect and form precipitates or complexes. Single crystal silicon ingots and single crystal silicon wafers sliced therefrom may contain an oxygen concentration of about 30 ppma (parts per million atomic, ASTM standard F-121-83, or SEMI standard M44), and generally Less than about 20 ppma, such as between about 11 ppma and about 20 ppma.

  Ingots prepared by the Czochralski method may also contain carbon as an impurity. In some embodiments, the single crystal silicon ingot and single crystal silicon wafer sliced therefrom may include carbon at a concentration of about 2 ppma or less.

  In some embodiments, the present disclosure relates to a single crystal silicon ingot doped with indium and prepared by the Czochralski method, such as the ingot shown in FIG. In yet a further embodiment, the present disclosure relates to a method of growing such an ingot. In still further embodiments, the present disclosure relates to segments and wafers sliced from such indium-doped Czochralski growth ingots. In some embodiments, the indium-doped single crystal silicon substrate is connected to two major generally parallel surfaces (one is the front surface of the substrate and the other is the back surface of the substrate) and the front and back surfaces. A segment including a peripheral edge, a central surface between the front surface and the rear surface, and a radius R extending from the central axis to the peripheral edge, such as a wafer. In some embodiments, the single crystal silicon substrate comprises a single crystal silicon wafer having a circular shape. The diameter of the wafer is typically the diameter of a Czochralski-grown single crystal silicon ingot excluding a portion of the ingot that is ground to achieve an ingot having a uniform diameter, as is known in the art. Similar to. The ingot is typically grown to a diameter that is larger than the diameter of the wafer, and grinding is generally performed to smooth the outer peripheral edge of the ingot, and the diameter can be reduced compared to the ingot that has just been grown. The wafer diameter may be at least about 150 mm, about 200 mm, or greater than about 200 mm, such as 205 mm, 250 mm, 300 mm, or even 450 mm, and in some embodiments between about 150 mm and about 450 mm. It may be. In some embodiments, the single crystal silicon wafer has a thickness between about 100 μm and about 1000 μm, such as between about 120 μm and about 240 μm. In certain embodiments, the thickness can be about 180 μm or about 200 μm. The thickness may vary about 20 μm thinner or thicker than the thicknesses listed above.

In some embodiments, a central axis, a front surface and a rear surface that are substantially perpendicular to the central axis, a central surface between and parallel to the front surface and the rear surface, a peripheral edge, and a peripheral edge from the central axis Indium doped single crystal silicon ingot (which may have been cut to remove seeds and seeds) and indium doped single crystal silicon sliced therefrom having a radius R extending to the ends The segment (eg, wafer) includes an average indium concentration of at least about 5 × 10 ¹⁴ atoms / cm ³ (about 0.01 ppma) or at least about 1 × 10 ¹⁵ atoms / cm ³ (about 0.02 ppma). In some embodiments, the average indium concentration is between about 1 × 10 ¹⁵ atoms / cm ³ (about 0.02 ppma) and about 1 × 10 ¹⁸ atoms / cm ³ (about 20 ppma). In some embodiments, the average indium concentration is between about 1 × 10 ¹⁵ atoms / cm ³ (about 0.02 ppma) and about 1 × 10 ¹⁷ atoms / cm ³ (about 2 ppma). In some embodiments, the average indium concentration is between about 1 × 10 ¹⁵ atoms / cm ³ (about 0.02 ppma) and about 1 × 10 ¹⁶ atoms / cm ³ (about 0.2 ppma).

  The Czochralski growth method of the present disclosure allows for the preparation of ingots and segments sliced therefrom having substantial axial and radial uniformity of indium concentration. Thus, in some embodiments, the ingot or segment sliced therefrom has a radial indium concentration of about 15% or less over at least 0.75R (ie, at least 75% of the radius of the ingot or segment). Of relative change. In some embodiments, the ingot or segment sliced therefrom has a radial relative to an indium concentration of about 10% or less over at least 0.75R (ie, at least 75% of the radius of the ingot or segment). Have a change. In some embodiments, the ingot or segment sliced therefrom has a radial relative to an indium concentration of about 15% or less over at least 0.95R (ie, at least 95% of the radius of the ingot or segment). Have a change. “Radial relative change” refers to the change in indium concentration between two points located separately at a distance along the length of the radius of the single crystal silicon ingot measured from the central axis to the peripheral edge of the wafer. It is determined by measuring and dividing the change by the indium concentration measured at the point closest to the central axis of the single crystal silicon wafer. This calculated value is multiplied by 100 to be a percentage. This percentage is the “radial relative change” of the indium concentration in this disclosure.

  In the solar cell industry, single crystal silicon ingots are typically cut and have four flat edges, each edge being substantially the same length. Accordingly, the solar battery cell includes a single crystal silicon wafer having a substantially square shape. In some embodiments, the single crystal silicon wafer is substantially square and has rounded edges. See FIG. 7, which is a depiction of a single crystal silicon wafer having an industry standard square shape of solar cells. A square-shaped single crystal silicon wafer may include a rounded edge having a radius R, where R is measured from the central axis to a peripheral edge essentially equal to the diameter of the Czochralski grown single crystal silicon ingot. In some embodiments, the single crystal silicon wafer has a thickness between about 100 μm and about 1000 μm, such as between about 120 μm and about 240 μm. In certain embodiments, the thickness can be about 180 μm or about 200 μm. The thickness may vary about 20 μm thinner or thicker than the thicknesses listed above. The length of the two major dimensions of the ingot (ie, plane-to-plane) may be between about 50 mm and about 300 mm, such as between about 100 mm and about 200 mm. In some embodiments, the two major dimension plane-to-plane dimensions may each be about 125 mm (± 0.5 mm). In some embodiments, the two major dimension plane-to-plane dimensions may each be about 156 mm (± 0.5 mm). The rounded edge may have a length between about 10 mm and about 20 mm, such as about 15.4 mm ± 1.0 mm.

As described above, an indium-doped single crystal silicon ingot used for manufacturing a solar cell generally has a substantially square shape in which a wafer sliced from the ingot has curved corners as shown in FIG. To have a flat edge. Square indium doped single crystal silicon wafers of the present disclosure have an average indium of at least about 5 × 10 ¹⁴ atoms / cm ³ (about 0.01 ppma) or at least about 1 × 10 ¹⁵ atoms / cm ³ (about 0.02 ppma). Includes concentration. In some embodiments, the average indium concentration is between about 1 × 10 ¹⁵ atoms / cm ³ (about 0.02 ppma) and about 1 × 10 ¹⁸ atoms / cm ³ (about 20 ppma). In some embodiments, the average indium concentration is between about 1 × 10 ¹⁵ atoms / cm ³ (about 0.02 ppma) and about 1 × 10 ¹⁷ atoms / cm ³ (about 2 ppma). In some embodiments, the average indium concentration is between about 1 × 10 ¹⁵ atoms / cm ³ (about 0.02 ppma) and about 1 × 10 ¹⁶ atoms / cm ³ (about 0.2 ppma). A square wafer may have a change in indium concentration of about 15% or less over at least 75% of the length of either of the two major dimensions. In some embodiments, the indium concentration of the wafer has a variation of about 15% or less over at least 75% of the length of both two major dimensions. In an even further embodiment, the indium concentration has a change of about 10% or less over at least 75% of the length of both two major dimensions. In still further embodiments, the indium concentration has a change of about 15% or less over at least 95% of the length of both two major dimensions.

  Solar cells of the present disclosure including single crystal silicon wafers having the concentration of indium dopant described herein generally have an average bulk resistivity of less than about 10 Ω · cm. In some embodiments, the average bulk resistivity is less than about 5 Ω · cm, less than about 4 Ω · cm, less than about 3 Ω · cm, less than about 1 Ω · cm, or even more than about 0.5 Ω · cm. small.

  According to the process of one embodiment, the indium doped single crystal silicon ingot is grown by the Czochralski method. In some embodiments, the indium doped single crystal silicon ingot is grown by a batch Czochralski method. In some embodiments, the indium doped single crystal silicon ingot is grown by a continuous Czochralski method.

  Indium doped single crystal silicon ingots according to the present disclosure are generally grown by the Czochralski growth system and Boronkov theory. Among other applications belonging to MMC Electronic Materials, for example, International Publication No. WO1998 / 45508; International Publication No. WO1998 / 45509; International Publication No. WO1998 / 45510; and International Publication No. WO2000 / 022196. No .; In one embodiment, the Czochralski growth chamber includes a crucible, a system for supplying silicon during ingot growth, and a system for supplying indium during ingot growth. The crucible may be any known one used for silicon crystal growth and can include both solid and liquid silicon raw materials. For example, the crucible may be a quartz crucible or a graphite crucible with a quartz inner liner. The crucible may have any cross-sectional shape that depends, for example, on the geometry of the crystal growth system, but generally has a circular cross-sectional shape. The crucible suitably includes an inner growth compartment and an outer feed compartment, which compartments are in fluid communication with each other. In some embodiments, the crucible may include a wall or other separation means that divides the crucible into an inner compartment and an outer compartment. The wall may include means for supplying silicon and / or indium during the growth of the single crystal silicon ingot.

  In some embodiments, the indium doped single crystal silicon ingot may be grown by a continuous Czochralski method. Silicon sources for forming the initial melt or for replenishing the silicon melt during ingot growth include electronic grade silicon, metal grade silicon or solar grade silicon. Silicon may be added as granular polycrystalline silicon or polycrystalline chunks (or polycrystalline chunks). In order to replenish the silicon melt as the ingot is pulled up, the silicon supply system may include means for heating the added silicon so that the silicon melt is replenished with molten silicon. In some embodiments, the silicon can be provided in either a solid form or a molten form.

  The continuous Czochralski growth system of the present disclosure further includes means for supplying indium to the crucible both in the initial melt silicon and in the silicon for replenishing the silicon melt as the ingot is pulled up. Indium can be supplied separately from the silicon replenisher, or indium can be supplied in the silicon replenisher. In order to ensure that the relative concentration of indium in the melt remains relatively constant, the silicon melt level is also relatively constant when the silicon in the melt solidifies into a growing single crystal. In order to ensure that it remains, continuous Czochralski growth includes that either continuous replenishment or intermittent replenishment of the silicon melt with silicon and indium can occur.

  In some embodiments, the method of growing an indium doped single crystal silicon ingot includes batch Czochralski. The silicon raw material for forming the initial melt in the batch Czochralski method may include electronic grade silicon, metal grade silicon or solar grade silicon. The silicon source can be, for example, granular polycrystalline silicon or polycrystalline chunks.

  A suitable method for growing an indium doped single crystal silicon ingot suitable for making the indium doped wafers and solar cells described herein will be described with reference to FIGS. Other methods are contemplated within the scope of this disclosure.

  A Czochralski growth chamber suitable for growing the indium doped ingots described herein is shown schematically at 100 in FIG. The growth chamber 100 includes a crucible 102 for holding a melt 104 of semiconductor or solar grade material, such as silicon, surrounded by a susceptor 106 housed in a furnace 108. The semiconductor grade material or the solar grade material is melted by the heat supplied from the heating element 110 surrounded by the heat insulating material 112. A heat shield or heat reflector 114 may be disposed over the melt surface 116 to provide better heat distribution within the growth chamber 100.

  A pulling mechanism (or pulling mechanism) 118 is provided in the growth chamber for growing and lifting the ingot exiting the melt 104. The pulling mechanism includes a pulling cable 120, a seed holder or chuck (or seed chuck) 122 disposed at an end of the pulling cable, and a seed crystal for starting crystal growth connected to the seed holder or chuck 122. 124.

  The growth chamber 100 may also include one or more gas inlets 126 for introducing an inert gas into the growth chamber. The gas inlet 126 may be located anywhere along the growth chamber 100. The gas inlet 126 in FIG. 1 is located above the melt surface 116. The gas introduced through the gas inlet flows through the surface of the silicon melt and the surface of the growing ingot, thereby preventing the impurity particles from reaching the interface where the single crystal is growing. Suitable inert gases include argon, helium, nitrogen, neon, mixtures thereof and any other suitable inert gas. The inert gas flow over the surface of the silicon melt tends to increase the evaporation of species from the silicon melt, particularly volatile dopants such as indium. This effect is amplified when the inert gas flows through a narrow passage above the silicon melt, such as a passage made by a heat shield or heat reflector 114. Accordingly, the gas inlet 126 may be attached to one or more flow controllers 128 (described in more detail below) for controlling the flow rate of the incoming inert gas.

  The growth chamber may also include one or more exhausts 130 for removing fluids such as chemical species evaporated from the inert gas and melt and impurity particles from the growth chamber. The exhaust 130 may be attached to one or more pressure regulators 132 (described in more detail below) for regulating the chamber pressure inside the growth chamber 100. The exhaust may be attached to a pump 134 (described in more detail below) that may be operated independently or in conjunction with a pressure regulator 132 that regulates the chamber pressure inside the growth chamber 100.

  In a batch or continuous Czochralski process, the indium dopant may be introduced in a solid or liquid state. Advantageously, the indium dopant may be introduced in a liquid state using a liquid doping system, such as the liquid doping system 200 shown in FIG. 2, and evaporation of the indium dopant during the doping and / or growth process. Reduce the amount and provide a more predictable indium dopant concentration in the resulting indium doped silicon ingot.

  The liquid doping system 200 shown in FIG. 2 may be placed in a growth chamber, such as the growth chamber 100, as shown in FIG. 1, and during the doping process described herein, the liquid doping system 200 is shown. May be suspended by a cable or wire 202 from a dummy seed 204 attached to a lifting mechanism such as the lifting mechanism 118 shown in FIG. The dummy seed 204 may be sized and shaped to be received or coupled within the seed holder or chuck 122 of the pulling mechanism 118 used to grow the single crystal ingot. In the embodiment shown in FIG. 2, the cable or wire 202 is made from molybdenum or tungsten, although other materials may be used for the cable or wire 202. The dummy seed 204 may be made of stainless steel or any other material suitable to support the weight of the liquid doping system. If the shape and size of the dummy seed 204 is the same as or similar to the shape and size of the seed crystal 124 used in the pulling mechanism 118 for growing a single crystal ingot, the liquid doping system 200 is shown in FIG. It can be attached to a growth chamber, such as the growth chamber 100 shown, with little modification.

  The liquid doping system 200 includes a dopant storage device 206 for holding the dopant 208 and an elongated supply tube 300 extending from the first or top opening 210 of the dopant storage device 206. The liquid doping system 200 may be made of any material suitable for high temperature applications (eg, refractory ceramic, molybdenum, tungsten and graphite). Quartz is suitable to minimize the risk of impurities from the liquid doping system 200. In the embodiment shown in FIG. 2, the liquid doping system 200 has a single structure (or unitary structure, unitary structure). In other embodiments, the liquid doping system 200 may be assembled from separate parts. The dopant storage device 206 includes a quartz sidewall 212 defining a generally cylindrical body 214 and a tapered end (or tapered end) defining a first opening 210 having a cross-sectional area smaller than the cross-sectional area of the body 214. taped end) 216. The tapered end 216 has a conical shape to guide the dopant to the lowest point of the dopant storage device 206. In the embodiment shown in FIG. 2, the side wall 212 of the tapered end 216 is linearly tapered, but the side wall 212 defining the tapered end 216 has a tapered end 216 having a saddle shape. It may be curved inward to have. The end of the body 214 distal from the tapered end 216 includes one or more holes 218 spaced equidistantly around the periphery of the body 214 to allow liquid during the doping process described herein. To position the doping system 200, a cable or wire 202 is inserted through the hole to secure the liquid doping system 200 to the lifting mechanism 118. The embodiment shown in FIG. 2 has four holes 218, but other embodiments may have a different number of holes.

  Referring to FIG. 3, the supply pipe 300 includes a side wall 302 extending L from the upper opening 210, a first or upper end 304 positioned near the upper opening 210, and an upper end. Including a second or lower end 306 distal from the portion 304 and having a second or lower opening 308 formed therein. An inclined tip 310 is disposed at the lower end 306 of the supply pipe 300. The beveled tip 310 provides a better visual indicator of contact between the lower end 306 of the supply tube and the melt surface 116 compared to the tip without the bevel. The angled tip 310 therefore helps an operator (not shown) to minimize contact between the melt 104 and the liquid doping system 200.

  As described in more detail below, during the doping process, the doping system is lowered toward the melt surface 116 until the inclined tip 310 contacts the melt surface 116. Accordingly, the dopant storage device 206 is positioned on the melt surface 116 at a distance approximately equal to the length L of the supply tube 300. The length L of the supply tube 300 is such that during the doping operation, the height H is such that the dopant reservoir is above the melt surface 116 and the temperature in the dopant reservoir is just above the melting temperature of the dopant 208. (Shown in FIG. 5) is selected, thereby minimizing dopant evaporation.

  The supply pipe 300 has an inner diameter d defined by the inner side wall 312 of the supply pipe 300, and the inner diameter d is a volume surrounded by the supply pipe 300 when the liquid dopant passes through the supply pipe 300. The size is substantially occupied by the liquid dopant. As a result, the free surface of the liquid dopant is minimized, thereby reducing the evaporation of the liquid dopant. The inner diameter d of the supply tube 300 is also sized so that capillarity does not impede the passage of the liquid dopant through the supply tube 300. Since the capillary force acting on the liquid dopant is inversely proportional to the temperature of the liquid dopant, the inner diameter d of the supply pipe 300 may be narrowed inward toward the lower end 306 of the supply pipe 300.

  The supply pipe 300 also has an outer diameter D based on the thickness of the side wall 302 of the supply pipe and the size of the inner diameter d. In the embodiment shown in FIG. 2, the outer diameter D of the supply pipe 300 is the same as the outer diameter of the tapered end 216 in the upper opening 210.

  The inner sidewall 312 of the supply tube 300 extends inward near the opening 210 and forms a first restriction 314 configured to restrict movement of the solid dopant 208 through the supply tube 300. Alternatively, the first restriction 314 may be formed from the inner sidewall 316 of the tapered end 216, or the first restriction 314 may extend to the supply tube 300 and the tapered end 216. The first restriction 314 has a diameter that prevents the solid dopant from moving through the supply tube 300. In the embodiment shown in FIGS. 2 and 3, the first restriction has an inner diameter of 1 mm.

  The second restriction 318 of this embodiment is formed near the lower end 306 of the supply tube 300 to prevent the flow of liquid dopant through the supply tube 300 and reduce the velocity. By reducing the velocity of the liquid dopant, the impact of the liquid dopant on the surface 116 of the melt is reduced, thereby reducing the splashing or splashing of the melt 104. Further, obstructing the flow of the liquid dopant at the lower end 306 of the supply tube 300 further heats the liquid dopant before it is introduced into the melt 104. Accordingly, the liquid dopant is heated to a temperature close to that of the melt 104 before being introduced into the melt 104. This reduces the thermal shock between the dopant 208 and the melt 104. In addition, increasing the temperature of the liquid dopant reduces the speed of the liquid dopant, thereby further reducing splashing or splashing of the melt 104 as the liquid dopant is introduced.

  The second restriction 318 also reduces the cross-sectional area of the liquid dopant flow present in the supply tube 300 and reduces the resulting free surface area of the liquid dopant at the melt surface 116. By reducing the free surface area of the liquid dopant at the melt surface 116, the second restriction 318 further reduces the evaporation of the liquid dopant.

  In the embodiment shown in FIG. 3, the second restriction 318 is the first in that the inner sidewall 312 of the supply tube 300 narrows inward near the lower opening 308 that forms the second restriction 318. This has a configuration similar to the restriction 314. The second restriction 318 extends downward toward the end of the supply pipe 300 and defines an opening 308 at the bottom of the supply pipe 300. The diameter of the second restriction 318 is smaller than the inner diameter d of the supply tube 300 and is sufficient to allow the liquid dopant to overcome the capillary force acting on the liquid dopant from the inner side wall 312 of the supply tube 300. Big. In the embodiment shown in FIG. 3, the diameter of the second restriction is 2 mm.

  With reference to FIGS. 2, 4 and 5, a method of using a liquid doping system 200 for introducing a liquid dopant into a melt of semiconductor grade material or solar grade material will be described. As shown in FIG. 2, a predetermined amount of dopant particles 208 is introduced into the dopant storage device 206 to position the liquid doping system 200 away from the surface 116 of the melt. The tapered end 216 causes the dopant particles 208 to flow toward the lowest position of the dopant storage device 206. The first restriction 314 prevents the solid dopant particles 208 from passing through the supply tube 300.

  As shown in FIGS. 4 and 5, in order to introduce the dopant 208 into the melt 104, the liquid doping system 200 is lowered to near the melt surface 116 via a pulling mechanism 118. The liquid doping system 200 is lowered until the inclined tip 310 of the supply tube 300 contacts the melt surface 116. By providing a better visual indicator of contact between the melt surface 116 and the supply tube 300, the slanted tip 310 of the supply tube 300 is positioned near the melt surface 116 in the liquid doping system 200. Makes it easy to position. Accordingly, the liquid doping system 200 is positioned near the surface 116 of the melt and is in contact with the melt 104 (thermal shock and deformation, solidification of the molten material around the supply tube, and silicon monoxide vaporized from the melt 104. The deposition on the inner surface of the feed tube is configured to minimize (which can cause gradual degradation of the doping system).

により見積もることができ、式中、Ｔ_ｍはドーパントの融解温度であり、Ｔ_ｓはドーピングプロセスの開始時における固体ドーパント粒子２０８の温度（通常は室温）であり、ｃ_ｄは固体ドーパント粒子２０８の比熱容量であり、ｍ_ｄは固体ドーパント粒子２０８の全質量であり、ｃ_ｄｄは液体ドーピングシステム２００の比熱容量であり、ｍ_ｄｄは液体ドーピングシステム２００の質量であり、ｄＥ／ｄｔは、融液１０４および成長チャンバ１００の他の構成部品から固体ドーパント粒子２０８および液体ドーピングシステム２００へのエネルギー移動の速度である。液体ドーピングシステム２００を移動時間内に融液の表面１１６近傍に位置付けることは、液体ドーピングシステム２００を融液の表面１１６から離して位置付けつつ、液体ドーパントが放出されることを防ぎ、それにより融液の表面１１６での液体ドーパントの激しい衝撃を防ぐ。供給管３００の傾斜した先端部３１０は、融液の表面１１６と供給管３００との間の接触のより良好な目で見える表示を提供するため、液体ドーピングシステム２００を位置付けるのに必要な時間を減らす。従って、傾斜した先端部３１０は、作業者（示されない）が液体ドーピングシステム２００を移動時間内に位置付けるのに役立つ。 As the liquid doping system 200 is lowered toward the melt surface 116, the temperature inside the dopant reservoir 206 begins to rise. In order to reduce the likelihood that the dopant 208 prior to positioning the liquid doping system 200 near the melt surface 116 will melt, the travel time may be determined within the time to position the liquid doping system 200. The travel time may be based on the time required to melt the solid dopant particles 208, the time required to raise the temperature of the solid dopant particles 208 to the melting point, or

Can be estimated by, where, T _m is the melting temperature of the dopant, T _s is the temperature of the solid dopant particles 208 at the beginning of the doping process (usually room temperature), c _d is the solid dopant particles 208 the specific heat capacity, _{m d} is the total mass of the solid dopant particles _{208, c dd} is the specific heat capacity of a liquid doping system _{200, m dd} is the mass of a liquid doping system 200, dE / dt is melt The rate of energy transfer from the 104 and other components of the growth chamber 100 to the solid dopant particles 208 and the liquid doping system 200. Positioning the liquid doping system 200 in the vicinity of the melt surface 116 within the transit time prevents the liquid dopant from being released while positioning the liquid doping system 200 away from the melt surface 116, and thereby the melt. To prevent violent impact of the liquid dopant on the surface 116 of the substrate. The inclined tip 310 of the supply tube 300 provides the time required to position the liquid doping system 200 to provide a better visual indication of contact between the melt surface 116 and the supply tube 300. cut back. Thus, the inclined tip 310 helps an operator (not shown) to position the liquid doping system 200 within the travel time.

  After positioning the liquid doping system 200 near the melt surface 116, the temperature inside the dopant storage device 206 increases toward the melting temperature of the dopant particles 208. As the solid dopant particles 208 liquefy, the resulting liquid dopant 220 flows through the first restriction 314 and the supply tube 300. The size of the diameter d of the supply tube 300 limits the resulting free surface of the liquid dopant 220 as the liquid dopant 220 flows through the supply tube 300, thereby minimizing the evaporation of the liquid dopant 220. .

  The liquid dopant 220 flowing through the supply tube 300 passes through the lower opening 308 and exits the supply tube 300 and enters the melt 104 before a second restriction at the lower end 306 of the supply tube 300. Blocked by 318. The second throttle 318 impedes and reduces the velocity of the liquid dopant 220 through the supply pipe 300, thereby impacting the liquid dopant 220 at the melt surface 116 and the melt 104. Reduce any splashing or splashing. Further, hindering the flow of liquid dopant at the lower end 306 of the supply tube 300 further heats the liquid dopant 220 before entering the melt 104. As a result, the temperature of the liquid dopant 220 can be heated to a temperature close to that of the melt 104 before entering the melt, thereby reducing the thermal shock between the liquid dopant 220 and the melt 104. In addition, increasing the temperature of the liquid dopant 220 decreases the viscosity of the liquid dopant, thereby further reducing splashing or splashing of the melt 104 when the liquid dopant 220 is introduced into the melt 104.

0048
The second restriction 318 also reduces the cross-sectional area of the liquid dopant flow present in the supply tube 300 and reduces the resulting free surface area of the liquid dopant 220 at the melt surface 116. By reducing the free surface area of the liquid dopant 220 at the melt surface 116, the second restriction 318 reduces evaporation of the liquid dopant 220.

  Once the dopant particles 208 have liquefied and / or a predetermined time has elapsed, the liquid doping system 200 is raised by the pulling mechanism 118 and removed from the furnace 108. Thereafter, the doping process may be repeated, or the liquid doping system 200 may be stored for later use.

  If the dopant 208 has a relatively low melting point (eg, below 1400 ° C., or even below 800 ° C.), the above doping method can be performed in a relatively short time. As a result, the temperature of the body 214 of the dopant storage device 206 is sufficiently low so that the liquid doping system 200 can be removed from the furnace 108 immediately after the doping process and without the need for a cooling step. In addition, the dummy seed 204 can be immediately removed from the chuck 122 and replaced with a seed crystal such as the seed crystal 124 shown in FIG. 1 used to grow a single crystal ingot.

  For example, introducing liquid indium using a liquid doping system, such as the liquid doping system described herein, reduces evaporation of indium during the doping and / or growth process and results in an indium doped silicon ingot. Provides a more predictable indium dopant concentration in it.

  Referring to FIG. 1, during the growth process, an inert gas is added to the silicon melt 104 to remove evaporated species generated by the impurities or melt and reduce the risk of inclusion of impurities in the growth ingot. May be introduced into the growth chamber from one or more gas inlets 126 disposed above. The inert gas flows through the melt surface 116 and the surface of the growing ingot 136, thereby preventing impurity particles from reaching the interface 138 on which the single crystal is growing. Suitable inert gases include argon, helium, nitrogen, neon, mixtures thereof and any other suitable inert gas.

  As mentioned above, indium has a relatively high segregation coefficient and high evaporation rate compared to boron. The flow of inert gas on the surface of the silicon melt tends to increase the evaporation rate of indium in the silicon melt and may result in unpredictable dopant concentrations in the grown ingot. Therefore, the concentration of indium dopant in the grown ingot can be controlled by adjusting the flow rate of the inert gas in relation to other parameters in the growth chamber. In particular, the concentration of indium dopant in the grown ingot is a relationship between the flow rate of the inert gas and the inner chamber pressure and the effective evaporation rate of indium in the silicon melt (or effective evaporation rate). Can be controlled by adjusting the ratio between the flow rate of the inert gas and the inner chamber pressure.

のように表すことができる。式中、ｇ^＊はシリコン融液中のインジウムの有効蒸発速度であり、ｆは流入する不活性ガスの流量であり、ｐはチャンバの内圧であり、ＡおよびＢはそれぞれ成長チャンバの構成に依存する係数である。従って、ＡおよびＢが既知である場合、不活性ガスの流量とチャンバの内圧との比率は、シリコン融液中のインジウムの望ましい有効蒸発速度を得るように調整することができる。本明細書で用いられる場合、「流入する不活性ガスの流量」とは、本明細書に記載の１つ以上のガス入口を通過して成長チャンバに入る不活性ガスの全流量を意味し、体積流量、質量流量または流量測定の任意の他の適当な手段として測定される。 Specifically, the relationship between the effective evaporation rate of indium in the silicon melt, the flow rate of inert gas, and the inner chamber pressure is:

It can be expressed as Where g ^* is the effective evaporation rate of indium in the silicon melt, f is the flow rate of the inert gas flowing in, p is the internal pressure of the chamber, and A and B depend on the growth chamber configuration, respectively. It is a coefficient to do. Thus, if A and B are known, the ratio of the inert gas flow rate to the chamber internal pressure can be adjusted to obtain the desired effective evaporation rate of indium in the silicon melt. As used herein, “inflowing inert gas flow rate” means the total flow rate of inert gas that passes through one or more gas inlets described herein and enters the growth chamber; It is measured as volume flow, mass flow or any other suitable means of flow measurement.

により、成長プロセスの間の経過時間と関連付けられ得る。式中、Ｃ_ｌは成長プロセスの間の与えられた時間におけるシリコンインゴット中のインジウムドーパント濃度であり、Ｃ_ｌ,０はシリコン融液中の初期のインジウムドーパント濃度であり、ｇ^＊はインジウムドーパントの有効蒸発速度であり、Ｈは融液の自由表面（すなわち、インゴットの断面の表面積より小さいシリコン融液の表面積）に対する融液の体積の比率である。シリコン融液中のインジウムの有効蒸発速度は、成長させたインゴット中の望ましいドーパント濃度プロファイルに基づいて選択されてもよい。例えば、固液界面における成長するインゴット中のドーパント濃度は、

を用いて近似計算することができる。式中、Ｃ_ｓは固液界面における凝固したインゴット中のインジウムドーパント濃度であり、ｋはシリコン中のインジウムの偏析係数（約４×１０^−４）である。シリコン融液中のインジウムの有効蒸発速度は、成長させたインゴット中の望ましい抵抗率プロファイルに基づいて選択されてもよい。例えば、インジウムドープシリコンの抵抗率は、ＤＩＮ５０４４４、ＳＥＭＩ ＭＦ７２３−０３０７に記載のアービンカーブのような業界基準を用いて、シリコン中のインジウムドーパント濃度と関連付けることができる。望ましい抵抗率プロファイルのために、対応するインジウムドーパント濃度プロファイルが決定されてよく、シリコン融液中の対応するインジウムドーパント濃度が決定さてよく、またシリコン融液中のインジウムの有効蒸発速度がそれに応じて選択されてよい。シリコン中のインジウムドーパント濃度を決定するためのアービンカーブの使用に加えて、またはその代替手段として、１つ以上の較正インゴット（または、較正用インゴット、キャリブレーションインゴット、ｃａｌｉｂｒａｔｉｏｎ ｉｎｇｏｔ）を作製して、インジウムドープシリコンの抵抗率とインジウムドープシリコンのインジウムドーパント濃度との間の経験的関係を決定するのに利用してよい。そのような実施形態において、インジウムドーパント濃度は、例えば、二次イオン質量分析法（ＳＩＭＳ）または低温フーリエ変換赤外分光法（ＬＴ−ＦＴＩＲ）を用いて、抵抗率とは独立に測定されてよい。そのような測定技術は、シリコン中の比較的高いイオン化エネルギー（約１６０ＭｅＶ）を有するインジウムの結果として、インジウムドープシリコン中のインジウムドーパント濃度についてより正確な値を提供し得る。独立に測定されたインジウムドーパント濃度は、上述のように、シリコン融液中のインジウムの有効蒸発速度を選択するために、測定された抵抗率の値と組み合わせて用いられてよい。 The effective evaporation rate of indium in the silicon melt can be selected based on the desired indium dopant concentration in the silicon melt at a given time t during the ingot growth process. The indium dopant concentration in the silicon melt is

Can be associated with the elapsed time during the growth process. _Where C _l is the indium dopant concentration in the silicon ingot at a given time during the growth process, C _{l, 0} is the initial indium dopant concentration in the silicon melt, and g ^* is the indium dopant concentration. Effective evaporation rate, H is the ratio of the volume of the melt to the free surface of the melt (ie, the surface area of the silicon melt that is smaller than the surface area of the ingot cross section). The effective evaporation rate of indium in the silicon melt may be selected based on the desired dopant concentration profile in the grown ingot. For example, the dopant concentration in the growing ingot at the solid-liquid interface is

Approximate calculation can be performed using Where C _s is the concentration of indium dopant in the solidified ingot at the solid-liquid interface, and k is the segregation coefficient of indium in silicon (about 4 × 10 ⁻⁴ ). The effective evaporation rate of indium in the silicon melt may be selected based on the desired resistivity profile in the grown ingot. For example, the resistivity of indium-doped silicon can be related to the concentration of indium dopant in silicon using industry standards such as the Irvine curve described in DIN 50444, SEMI MF723-0307. For a desired resistivity profile, a corresponding indium dopant concentration profile may be determined, a corresponding indium dopant concentration in the silicon melt may be determined, and an effective evaporation rate of indium in the silicon melt may be determined accordingly. May be selected. In addition to, or as an alternative to the use of an Irvine curve to determine the concentration of indium dopant in silicon, one or more calibration ingots (or calibration ingots, calibration ingots, calibration inots) are created, It may be used to determine an empirical relationship between the resistivity of indium doped silicon and the indium dopant concentration of indium doped silicon. In such embodiments, the indium dopant concentration may be measured independent of resistivity using, for example, secondary ion mass spectrometry (SIMS) or low temperature Fourier transform infrared spectroscopy (LT-FTIR). . Such a measurement technique can provide a more accurate value for the indium dopant concentration in indium-doped silicon as a result of indium having a relatively high ionization energy (about 160 MeV) in silicon. The independently measured indium dopant concentration may be used in combination with the measured resistivity value, as described above, to select the effective evaporation rate of indium in the silicon melt.

のように表される。式中、ｋはシリコン中のインジウムの偏析係数（約４×１０^−４）であり、Ｈは融液の自由表面に対する融液の体積の比率であり、ｖは結晶引き上げ装置の平均の引き上げ速度であり、δはシリコンの液体対固体の密度比である。シリコン中のインジウムの有効偏析係数ｋ_ｅは、成長させたインジウムドープシリコンインゴットから切り出された断片から得られた測定から、

を用いて計算されてよい。式中、Ｃ_ａは測定されるインゴット断片の種結晶端部におけるドーパント濃度であり（すなわち、インゴットの種結晶端部に最も近いインゴット断片の端部）、Ｃ_ｚは測定されるインゴット断片の末端部におけるドーパント濃度であり（すなわち、インゴットの末端部に最も近いインゴット断片の端部）、ｍ_ａはインゴット断片の種結晶端部におけるシリコンインゴットの凝固率（ｓｏｌｉｄｉｆｉｅｄ ｆｒａｃｔｉｏｎ）であり、ｍ_ｚはインゴット断片の末端部におけるシリコンインゴットの凝固率である。式５を参照して用いられる場合、インゴットの縦軸に垂直なシリコンインゴットの所定の断面において、用語「凝固率」とは、インゴットの種結晶端部と参照する（または、基準、ｒｅｆｅｒｅｎｃｅ）断面との間のインゴットの質量を、インゴットを成長させるのに用いられる初期の装填量の全質量で割ったものを意味する。 The coefficients A and B in Equation 2 may be determined empirically based on measurements obtained from the grown indium doped silicon ingot. For example, coefficients A and B may be determined by using the relationship between the effective segregation coefficient k _e indium effective evaporation rate and silicon indium,

It is expressed as Where k is the segregation coefficient of indium in silicon (about 4 × 10 ⁻⁴ ), H is the ratio of the volume of the melt to the free surface of the melt, and v is the average pulling speed of the crystal pulling apparatus. Δ is the density ratio of silicon liquid to solid. Effective segregation coefficient k _e indium in silicon, the measurement obtained from the cut from indium-doped silicon ingot grown fragments,

May be used to calculate. Where C _a is the dopant concentration at the seed end of the ingot fragment being measured (ie, the end of the ingot fragment closest to the seed end of the ingot) and C _z is the end of the ingot fragment being measured. a dopant concentration in the section (i.e., the end closest ingot fragments to the end of the ingot), _{m a} is the solidification rate of the silicon ingot at the seed crystal end of the ingot fragments (solidified fraction), _{m z} ingot It is the solidification rate of the silicon ingot at the end of the fragment. When used with reference to Equation 5, in a given cross section of a silicon ingot perpendicular to the longitudinal axis of the ingot, the term “solidification rate” refers to the seed end of the ingot (or reference) cross section. Divided by the total mass of the initial charge used to grow the ingot.

  Thus, using the relationship between the inert gas flow rate and the inner chamber pressure described herein, the evaporation rate of the indium dopant adjusts the ratio of the inert gas flow rate to the inner chamber pressure. Can be controlled. Consequently, the indium dopant concentration in the grown indium doped silicon ingot can also be controlled by adjusting the ratio of the inert gas flow rate to the inner chamber pressure. In certain embodiments, the flow rate of the inert gas and the inner chamber pressure is such that the ratio of the inert gas flow rate to the inner chamber pressure is about 0.05 normal liters / (min · mbar) to about 1.40 normal. Liter / (min · mbar), between about 0.10 normal liter / (min · mbar) and about 1.00 normal liter / (min · mbar), or about 0.10 normal liter / (min May be adjusted to be between mbar) and about 0.80 normal liters / (min · mbar). In still further embodiments, the flow rate of the inert gas is between about 20 normal liters / min and about 200 normal liters / min, between about 30 normal liters / min and about 140 normal liters / min, or about 30 It may vary between normal liters / min and about 80 normal liters / min. In still further embodiments, the internal pressure of the growth chamber may vary between about 20 mbar and about 400 mbar, between about 30 mbar and about 200 mbar, or between about 30 mbar and about 100 mbar. As used herein, the term “normal liters” refers to 1 liter of reference gas (referenced) at 273.15 K and 101.325 kPa.

  The ratio of inert gas to inner chamber pressure may be adjusted before, during, or both before and during the growth process to obtain the desired indium dopant concentration in the grown ingot. The flow rate of the inert gas and / or the inner chamber pressure may be adjusted once more during the growth process or continuously during the growth process. The inert gas flow rate and / or inner chamber pressure may be adjusted based on real-time measurements of the Czochralski growth process or at one or more predetermined times following the start of the growth process. The predetermined time during which the flow rate of the inert gas or the inner chamber pressure is adjusted is the elapsed time after the start of the growth process, that the ingot has reached the desired length, that the pulling speed has reached the desired pulling speed, Alternatively, it may be based on the amount of silicon melt consumed by the growth process.

  The flow rate of the inert gas flowing through the gas inlet 126 is adjusted using one or more flow controllers 128 attached to the gas inlet 126. The flow regulator 128 is suitable for regulating the flow of inert gas through the gas inlet 9 and into the growth chamber, such as a mass flow regulator, volumetric flow regulator, throttle valve or butterfly valve. It can be any device. The flow controller 128 may be automated or may be manually controlled. The automatic flow controller may be controlled by one or more programmable devices 140 that can adjust the flow rate of the inert gas based on user-defined conditions (eg, after a predetermined period of time). The flow controller shown in FIG. 1 is an automated mass flow controller controlled by a programmable device 140 that can adjust the flow of inert gas based on user-defined conditions.

  The internal pressure of the growth chamber 100 may be controlled using one or more pressure regulators 132 in fluid communication with the growth chamber exhaust 130. The pressure regulator 132 may be any type of device suitable for regulating the pressure in the growth chamber 100 and includes an electronic pressure controller, a throttle valve, a butterfly valve, and a ball valve. The pressure regulator 132 may be automated or controlled manually. The automatic pressure regulator may be controlled by one or more programmable devices 140 that can regulate the internal pressure within the growth chamber 100 based on user-defined conditions (eg, after a predetermined period of time). The programmable device 140 used to control the pressure regulator 132 may be separate or the same as the programmable device 140 used to control the flow controller 128. The pressure regulator shown in FIG. 1 is automated and controlled by a programmable device 140 that can regulate the internal pressure of the growth chamber based on user-defined conditions.

  A pump 134 in fluid communication with the exhaust 130 of the growth chamber 100 removes inert gases, impurities, and species evaporated from the silicon melt (eg, species related to SiO and dopants) out of the growth chamber. May be used to drain. The pump 134 may be operated independently or in conjunction with the pressure regulator 132 that regulates or regulates the chamber pressure inside the growth chamber 100. The pump 134 may be controlled by a programmable device 140 that can adjust the pump settings based on user-defined conditions (eg, after a predetermined period of time). Programmable device 140 may be the same as or different from the programmable device used to control flow controller 128 and / or pressure regulator 132.

  Adjusting the ratio of the inert gas flow rate to the inner chamber pressure ensures that the relative concentration of indium in the melt remains relatively constant as the indium doped silicon ingot grows. In addition, it ensures that the dopant concentration in the indium doped silicon ingot is relatively uniform.

The advantages of the disclosed process include an indium dopant concentration axis in a direction parallel to the central axis 602 of the ingot, in addition to a small radial change along the radius 604 measured from the central axis toward the peripheral edge 606. 7 is a commercial sized single crystal silicon ingot preparation such as the ingot 600 shown in FIG. 6 with a small change in direction. In some embodiments, the axial change in indium concentration may be less than about 5 × 10 ¹⁴ atoms / cm ³ over a single crystal silicon ingot axial length greater than 20 cm and greater than 20 cm. Over the axial length of the ingot may be less than about 1 × 10 ¹⁴ atoms / cm ³ , and over the axial length of the single crystal silicon ingot over 20 cm, it may be less than about 5 × 10 ¹³ atoms / cm ³ , Alternatively, it may be smaller at about 4 × 10 ¹³ atoms / cm ³ over the axial length of the single crystal silicon ingot greater than 20 cm. In some embodiments, the axial change in indium concentration may be less than about 1 × 10 ¹⁵ atoms / cm ³ over a single crystal silicon ingot axial length greater than 40 cm and greater than 40 cm single crystal silicon. It may be less than about 5 × 10 ¹⁴ atoms / cm ³ over the axial length of the ingot, or even less than about 2 × 10 ¹⁴ atoms / cm ³ over the axial length of the single crystal silicon ingot over 40 cm. It's okay. In some embodiments, the relative axial change in indium concentration may be less than about 20% over a single crystal silicon ingot axial length greater than 20 cm, and to a single crystal silicon ingot axial length greater than 20 cm. May be less than about 10%, over an axial length of a single crystal silicon ingot greater than 20 cm, may be less than about 5%, or even over an axial length of a single crystal silicon ingot greater than 20 cm. It may be smaller than 2%. In some embodiments, the axial relative change in indium concentration may be less than about 33% over a single crystal silicon ingot axial length greater than 40 cm, and to a single crystal silicon ingot axial length greater than 40 cm. May be less than about 25%, over a single crystal silicon ingot axial length greater than 40 cm, may be less than about 15%, or even over a single crystal silicon ingot axial length greater than 40 cm. It may be smaller than 10%. In some embodiments, the mass of the indium doped silicon ingot 600 may be at least about 30 kg, at least about 40 kg, at least about 50 kg, at least about 60 kg, at least about 70 kg, or at least about 80 kg. In still further embodiments, the mass of the indium doped silicon ingot 600 may exceed 175 kg, such as at least about 180 kg, at least 200 kg, or even at least 220 kg. “Relative change in the axial direction” is the measurement of the indium concentration between two points located at a certain distance along the axial length of the single crystal silicon ingot, and the change is most reflected in the seed cone of the single crystal silicon ingot. Determined by dividing by the concentration of indium measured at a close point. This calculated value is multiplied by 100 to be a percentage. This percentage is the “relative change in the axial direction” of the indium concentration in this disclosure. The process of the present disclosure results in a single crystal silicon ingot having a small axial relative change in indium concentration over a substantial length of the silicon ingot. Thus, it can be sliced into a population of indium-doped single silicon wafers having properties of substantially uniform resistivity, conversion efficiency and resistance to light-induced degradation.

  The single crystal silicon ingot may be processed into a single crystal silicon wafer or a population of single crystal silicon wafers suitable for solar cell applications. In that case, the ingot is subjected to a substantially uniform indium concentration and in accordance with industry standards including cutting, grinding, edge chamfering, cropping and wire saw cutting to obtain a flat edge, as described herein. It may be processed into a population of single crystal silicon wafers having resistivity characteristics. The cutting operation generally follows the guidelines provided by the manufacturer of the cutting tool. Single crystal silicon ingots are cut into a population of indium doped single crystal silicon wafers having industry standard shapes and sizes that meet the geometrical requirements of end use in solar cells. The indium-doped single crystal silicon wafer processed and sliced according to industry standards is then further processed into solar cells again according to industry standards.

  In the process of manufacturing solar cells from an indium doped single crystal silicon wafer, the surface of the wafer may be textured to minimize reflections. Any “roughening” of the surface reduces reflection by increasing the chance that reflected light bounces off the surface rather than going out into the ambient air. The single crystal substrate can be textured by etching along the plane of the crystal plane. If the surface is properly aligned with the internal atoms, the silicon crystal structure results in a surface composed of a pyramid structure. Another type of surface texturing used is known as “inverted pyramid” texturing. By using this texturing scheme, the pyramid structure is etched down into the silicon surface, rather than being etched up from the surface. The textured wafer is then processed according to industry standards, including emitters by industry standard processes such as phosphorus diffusion or implants, followed by edge isolation. In some embodiments, an antireflective coating may be applied. The antireflective coating in solar cells is similar to the antireflective coating used in other optical instruments such as camera lenses. They consist of a thin layer of dielectric material having a thickness such that the interference effect in the coating causes a reflected wave from the top surface of the antireflective coating that is out of phase with the reflected wave from the semiconductor surface. These reflected waves with different phases interfere with each other so as to cancel each other, resulting in a net zero reflected energy. A commonly used coating is silicon nitride. Alternatively, a double layer anti-reflective coating such as zinc sulfide / magnesium fluoride may be applied. Patterned metal screens (eg, silver, aluminum) are applied to the front and back surfaces of the wafer by screen printing, followed by baking of the wafer to obtain solar cells useful for example in an array grid.

The solar cell of the present disclosure is characterized by high conversion efficiency of sunlight spectral irradiance. The conversion efficiency of the spectral irradiance of sunlight may be measured according to industry standards. For example, conversion efficiency may be measured according to the criteria described in ASTM G173-03 entitled Terrestrial Reference Spectra for American Society for Testing and Materials (ASTM) photovoltaic characterization. The spectrum of ASTM G173 represents the spectral irradiance of sunlight on the ground on a surface in a predetermined direction under the setting of predetermined atmospheric conditions. The distribution of power as a function of wavelength (bandwidth W / (m ² · nm)) is a spectral selectivity with respect to performance measured under various natural light sources and artificial light sources of light with various spectral distributions. Provides a single common standard for evaluating PV materials. The selected conditions are considered to be a reasonable average for 48 states in the United States (US) over the course of a year. The selected tilt angle is approximately the average latitude for the contiguous United States. The light receiving surface is defined by the standard as an inclined surface that is inclined by 37 ° C. toward the equator and faces the sun. (That is, the plane normal points to the sun with an elevation angle of 41.81 ° above the horizon). The prescribed atmospheric conditions are:
a) Temperature, pressure, aerosol density (country aerosol amount (or load amount, lodi)
ng)), air density, 1 having the density of molecular species described in 33 layers
976 US standard atmosphere b) Absolute air mass 1.5 (solar zenith angle 48.19 °)
c) Angstrom turbidity coefficient at 500 nm (based on e) 0.084 ^C
d) Total air column water vapor equivalent to 1.42 cm e) Total air column ozone equivalent to 0.34 cm f) ASTER spectral reflection database of the Jet Propulsion Laboratory (http: // s
pelib. jpl. nasa. gov. ) Ground surface spectrum of lightweight soil recorded in albedo (reflectance)
It is.

のように定義される。 The efficiency of a solar cell is the ratio of the electrical output of the solar cell to the incident energy in the form of sunlight. The ground solar cell is measured at 25 ° C. under AM1.5 conditions. The energy conversion efficiency (η) of a solar cell is the percentage of solar energy that the cell is exposed to and converted to electrical energy. Solar cell efficiency is determined as the fraction of incident power converted to electricity:

Is defined as follows.

_Where P _max is the maximum output, V _oc is the open circuit voltage; I _sc is the short circuit current; FF is the fill factor; and η is the efficiency.

  Solar cell efficiency is customarily expressed as a percentage. In some embodiments of the present disclosure, the solar cells are at least 17%, at least 18%, at least 19%, at least 19.5%, at least 20%, at least 20. 5%, at least 21%, at least 22%, at least 24%, at least 26%, at least 28%, at least 30% characterized by the conversion efficiency of solar spectral irradiance at the surface of indium doped single crystal silicon wafers Indium doped single crystal silicon wafers are included.

Due to the absorption capacity of the indium-doped single crystal silicon wafer and the up-conversion of light in the infrared region of the solar spectrum, high efficiency of solar spectral irradiance is achieved at least in part. In particular, the indium doped single crystal silicon wafer of the present disclosure absorbs more light in the infrared region of the solar spectrum than a boron doped single crystal silicon wafer having a substantially similar or equal resistivity. In some embodiments, indium doped single crystal silicon wafers of the present disclosure have more light in the wavelength range between 830 nm and 1400 nm than boron doped single crystal silicon wafers having substantially similar or equal resistivity. Absorbs. FIG. 8A is a graph showing better light absorption across the solar spectrum of solar cells made from indium doped single crystal silicon wafers compared to solar cells made from boron doped single crystal silicon wafers. 8B and 8C. Although the resistivity (about 2.4 Ω · cm) of the boron-doped wafer is lower than the resistivity (about 3.5 Ω · cm) of the indium-doped wafer, the absorption of solar cells made from the indium-doped wafer is made from the boron-doped wafer. Was greater than the solar cell absorption. Based on calculations from the PC1D model (a freely available solar cell modeling program; available from the University of New South Wales), the difference in J _sc cannot be accounted for in resistivity. In other words, the resistivity of the wafer in each solar cell cannot explain the increase in absorption of the indium doped wafer. It is believed that the higher absorption of the lower energy IR light is due to the higher band gap position of the indium dopant atoms compared to the boron dopant atoms.

  In addition to high efficiency and enhanced upconversion of light across the solar spectrum, the indium doped single crystal silicon wafers of the present disclosure are characterized by small light-induced degradation in both relative and absolute basis. In this regard, the relative efficiency of solar cells including an indium doped single crystal silicon wafer degrades by about 2% or less after exposure to light corresponding to 0.1-10 SUN at temperatures below 45 ° C. for 1-300 hours. In some embodiments, after exposure to light corresponding to 0.1-10 SUN at temperatures below 45 ° C. for 1-300 hours, the relative efficiency of the solar cells degrades by about 1% or less. In some embodiments, after exposure to light corresponding to 0.1-10 SUN at temperatures below 45 ° C. for 1-300 hours, the relative efficiency of the solar cells degrades by about 0.5% or less. In some embodiments, after exposure to light corresponding to 0.1-10 SUN at temperatures below 45 ° C. for 1-300 hours, the relative efficiency of the solar cells degrades by about 0.3% or less. In some embodiments, after 24 hours exposure to light corresponding to 0.7 SUN at a temperature below 45 ° C., the relative efficiency of the solar cells is about 2% or less, or about 1% or less, or about 0.00. 5% or less, or about 0.3% or less. As expressed herein, the relative efficiency refers to exposing the indium-doped single crystal silicon wafer to illumination, for example 24 hours exposure to light equivalent to 0.7 SUN at a temperature below 45 ° C. Determined by measuring the decrease in efficiency compared to. The difference in efficiency (the efficiency of the wafer in the initial state after subtracting the efficiency of the wafer after illumination) is divided by the efficiency of the wafer in the initial state. The calculated value may be multiplied by 100 to derive the percentages expressed herein.

  Indium doped single crystal silicon wafers are further characterized by low absolute light-induced degradation of efficiency. Absolute light induced degradation is determined by subtracting the degraded wafer efficiency (expressed as a percentage) from the initial wafer efficiency (also expressed as a percentage). In some embodiments, the absolute efficiency of a solar cell comprising an indium-doped single crystal silicon wafer after exposure to light corresponding to 0.1-10 SUN at a temperature below 45 ° C. for 1-300 hours is About 0.5% or less, about 0.2% or less, about 0.1% or less, or about 0.06% or less. In some embodiments, after 24 hours exposure to light equivalent to 0.7 SUN at temperatures below 45 ° C., the absolute efficiency of solar cells comprising indium doped single crystal silicon wafers is about 0.5% or less, Deterioration is about 0.2% or less, about 0.1% or less, or about 0.06% or less. In some embodiments, the absolute efficiency of a solar cell comprising an indium doped single crystal silicon wafer after exposure to sunlight at a temperature below 45 ° C. for 4 hours is about 1.0% or less, about 0.5% Hereinafter, the deterioration is about 0.2% or less, about 0.1% or less, or about 0.06% or less.

  Having described the disclosure in detail, it will be apparent that modifications and variations are possible without departing from the scope of the invention as defined in the appended claims.

The following examples are non-limiting.

Example 1 Indium-doped single crystal silicon ingot grown by batch Czochralski method
An indium-doped single crystal silicon ingot was grown by a conventional batch Czochralski method. The ingot was grown to a diameter greater than 200 mm and then ground to a uniform diameter of 200 mm by industry standard methods.

  The ingot was sliced into wafers having a thickness between about 180 μm and about 200 μm with a wire saw, and the wafers were selected from various lengths from the seed cone for analysis. Wafers were tested for changes in resistivity at the wafer center and 6 mm from the wafer edge, indium concentration at the wafer center, oxygen concentration at the wafer center, carbon concentration at the wafer center, and radial resistivity. The indium concentration was determined using the Irvine curve described in DIN 50444, SEMI MF723-0707. These data are given in Table 1 below.

[Example 2] Indium-doped single crystal silicon ingot grown by batch Czochralski method
An indium-doped single crystal silicon ingot was grown by the batch Czochralski method. During the growth process, the ratio of the inert gas flow rate to the inner chamber pressure was adjusted by the method described herein to control the concentration of indium dopant in the growth ingot. The ingot was grown to a diameter greater than 200 mm and then ground to a uniform diameter of 200 mm by industry standard methods.

  The ingot was sliced into wafers having a thickness between about 180 μm and about 200 μm with a wire saw, and the wafers were selected from various lengths from the seed cone for analysis. The wafers were tested for changes in resistivity at 6 mm from the wafer center and wafer edge, indium concentration at the wafer center, oxygen concentration at the wafer center, carbon concentration at the wafer center, and radial resistivity. The indium concentration was determined using the Irvine curve described in DIN 50444, SEMI MF723-0707. These data are given in Table 2 below.

Example 3 Indium-doped single crystal silicon ingot grown by batch Czochralski method
An indium-doped single crystal silicon ingot was grown by the batch Czochralski method. During the growth process, the ratio of the inert gas flow rate to the inner chamber pressure was adjusted by the method described herein to control the concentration of indium dopant in the growth ingot. The ingot was grown to a diameter greater than 200 mm and then ground to a uniform diameter of 200 mm by industry standard methods.

  The ingot was sliced into wafers having a thickness between about 180 μm and about 200 μm with a wire saw, and the wafers were selected from various lengths from the seed cone for analysis. Wafers were tested for changes in resistivity at the wafer center and 6 mm from the wafer edge, indium concentration at the wafer center, oxygen concentration at the wafer center, carbon concentration at the wafer center, and radial resistivity. The indium concentration was determined using the Irvine curve described in DIN 50444, SEMI MF723-0707. These data are given in Table 3 below.

[Example 4] Indium-doped single crystal silicon ingot grown by batch Czochralski method
An indium-doped single crystal silicon ingot was grown by the batch Czochralski method. During the growth process, the ratio of the inert gas flow rate to the inner chamber pressure was adjusted by the method described herein to control the concentration of indium dopant in the growth ingot. The ingot was grown to a diameter greater than 200 mm and then ground to a uniform diameter of 200 mm by industry standard methods.

  The ingot was sliced into wafers having a thickness between about 180 μm and about 200 μm with a wire saw, and the wafers were selected from various lengths from the seed cone for analysis. Wafers were tested for changes in resistivity at the wafer center and 6 mm from the wafer edge, indium concentration at the wafer center, oxygen concentration at the wafer center, carbon concentration at the wafer center, and radial resistivity. The indium concentration was determined using the Irvine curve described in DIN 50444, SEMI MF723-0707. These data are given in Table 4 below.

  For comparison, the indium dopant concentration of each wafer was measured using SIMS and LT-FTIR independently of the resistivity. These data are given in Table 5 below.

[Example 5] Wafer obtained from indium-doped single crystal silicon ingot grown by batch Czochralski method
200 wafers were selected from the ingots grown by the method described in Example 3. The wafer had a plane-to-plane length with major dimensions of 156 mm ± 0.5 mm. The diagonal dimension of the wafer was 200 mm ± 0.5 mm. The length of the corner was 15.4 mm ± 1 mm. The thickness of the wafer was 200 μm ± 20 μm or 180 μm ± 20 μm.

The resistivity of 200 wafers was in the range of 3.03 Ω · cm to 3.5 Ω · cm. The oxygen concentration of the wafer was in the range of 14.9 PPMA to 15.4 PPMA. The lifetime of the wafer was in the range of 325 μs to 651 μs (measured at crystal level (or crystal field level, crystal level, crystal level) at an implantation level of 5 × 10 ¹⁴ / cm ³ ; Sinton BCT 400) .

Example 6 Initial State Test of Indium-Doped Single Crystal Silicon Wafer Implanted with 90Ω / sq Emitter
A solar battery cell was produced from the indium-doped wafer prepared by the method described in Example 5. The wafer was selected to have a resistivity of 3.5 Ω · cm and implanted with a 90 Ω / sq emitter.

  Solar cells were measured to determine their initial characteristics. The results are shown in Table 6 below.

This example table and the following example provide several performance characteristics for comparing solar cells. V _oc indicates the open circuit voltage, that is, the maximum voltage obtained from the solar battery cell. FF indicates a _fill factor which is a maximum output obtained from the solar battery cell, and is defined as a ratio of the maximum output from the solar battery cell to the product of V _OC and I _SC (short circuit current). Efficiency is defined as the ratio of output energy from solar cells to input energy from the sun. The N factor represents the ideal factor of the diode and can be in the range of 1-2. Values closer to 1 indicate ideal behavior. R _S represents a series resistance. R _SH indicates a shunt resistance.

Test the initial state of Example 7 POCL ₃ -HNS 65Ω / indium-doped single crystal silicon wafer which has been diffused by sq]
A solar battery cell was produced from the indium-doped wafer prepared by the method described in Example 5. The wafer was selected to have a resistivity of 3.5 Ω · cm and diffused with a POCL ₃ -HNS 65 emitter.

  Solar cells were measured to determine their initial characteristics. The results are shown in Table 7 below.

[Comparative Example 1 Boron-doped single crystal silicon ingot grown by continuous Czochralski method]
200 wafers were selected from boron-doped ingots grown by the continuous Czochralski method. The wafer had a plane-to-plane length with major dimensions of 156 mm ± 0.5 mm. The diagonal dimension of the wafer was 200 mm ± 0.5 mm. The length of the corner was 15.4 mm ± 1 mm. The thickness of the wafer was 200 μm ± 20 μm or 180 μm ± 20 μm.

The resistivity of the 200 boron doped wafers was between about 2.4 Ω · cm and about 2.73 Ω · cm. The oxygen concentration of the wafer was about 14.6 PPMA. The lifetime of the wafer was about 320 μs (measured at crystal levels at an implantation level of 5 × 10 ¹⁴ / cm ³ ; Sinton BCT400).

[Comparative Example 2 Test of Initial State of Boron-Doped Single Crystal Silicon Wafer Implanted with 90Ω / sq Emitter]
Solar cells were prepared from the boron-doped wafer prepared by the method described in Comparative Example 1. The wafer was selected to have a resistivity of 2.4 Ω · cm and implanted with a 90 Ω / sq emitter.

  Solar cells were measured to determine their initial characteristics. The results are shown in Table 8 below.

[Comparative Example 3 Test of Initial State of Boron-Doped Single Crystal Silicon Wafer Diffused with POCL ₃ -HNS 65Ω / sq]
A solar battery cell was produced from the indium-doped wafer prepared by the method described in Comparative Example 1. The wafer was selected to have a resistivity of 2.4 Ω · cm and implanted with a POCL ₃ -HNS 65 emitter.

  Solar cells were measured to determine their initial characteristics. The results are shown in Table 9 below.

[Example 8 Photoinduced degradation test of solar cell made from indium-doped single crystal silicon wafer and solar cell made from boron-doped single crystal silicon wafer]
In order to test the light-induced degradation of solar cells of various performance characteristics, solar cells made from the indium doped single crystal silicon wafer of Example 6 and solar cells made from the boron doped single crystal silicon wafer of Comparative Example 2 The cell was exposed to a spectral irradiance of sunlight corresponding to 0.7 SUN at a temperature below 45 ° C. for 24 hours. The initial solar cell performance characteristics and the solar cell performance characteristics after 24 hours of irradiation are shown in Table 10 below.

  Photoinduced degradation was evaluated for solar cells made from indium-doped single crystal silicon wafers and solar cells made from boron-doped single crystal silicon wafers (selected so that the oxygen and dopant concentrations closely matched). It was. Solar cells made from indium-doped wafers showed significantly less light-induced degradation after illumination compared to solar cells made from boron-doped wafers. More specifically, the efficiency of solar cells made from indium doped wafers remains above 19% after illumination, and about 3% relative degradation (about 0.6% for boron doped cells). Compared to absolute degradation, the relative degradation for the indium doped cell was only about 0.4% (0.08% absolute degradation). From these results, solar cells made from indium-doped cells showed significantly less photoinduced degradation than solar cells made from boron-doped cells.

Example 9 Testing of the initial state of an indium-doped single crystal silicon wafer implanted with an emitter of 90 to 110 Ω / sq
Solar cells were prepared from indium-doped wafers. The wafer was selected to have a resistivity of 3.4 Ω · cm and implanted with an emitter of 90-110 Ω / sq.

  Solar cells were measured to determine their initial characteristics. The results are shown in Table 11 below.

Example 10 Initial state test of an indium-doped single crystal silicon wafer implanted with an emitter of 90 to 110 Ω / sq
Solar cells were prepared from indium-doped wafers. The wafer was selected to have a resistivity of 3.1 Ω · cm and implanted with an emitter of 90-110 Ω / sq.

  Solar cells were measured to determine their initial characteristics. The results are shown in Table 12 below.

[Comparative Example 4 Initial State Test of Boron-Doped Single Crystal Silicon Wafer Implanted with 90-110 Ω / sq Emitter]
Solar cells were prepared from boron-doped wafers. The wafer was selected to have a resistivity of 2.6 Ω · cm and implanted with an emitter of 90-110 Ω / sq.

  Solar cells were measured to determine their initial characteristics. The results are shown in Table 13 below.

[Comparative Example 5 Initial State Test of Boron-Doped Single Crystal Silicon Wafer Implanted with 90-110Ω / sq Emitter]
Solar cells were prepared from boron-doped wafers. The wafer was selected to have a resistivity of 2.5 Ω · cm and implanted with an emitter of 90-110 Ω / sq.

  Solar cells were measured to determine their initial characteristics. The results are shown in Table 14 below.

[Example 11 Photoinduced degradation test of solar cell made from indium-doped single crystal silicon wafer and solar cell made from boron-doped single crystal silicon wafer]
In order to test the light-induced degradation of solar cells with various performance characteristics, the solar cells made from the indium doped single crystal silicon wafers of Example 9 and Example 10 and the boron doped single cells of Comparative Example 4 and Comparative Example 5 were used. Solar cells made from crystalline silicon wafers were exposed to spectral irradiance of sunlight corresponding to 0.7 SUN at a temperature lower than 45 ° C. for 24 hours. The average performance characteristics of the initial solar cells and the average performance characteristics of the solar cells after 24 hours of irradiation are shown in Table 15 below.

  Photoinduced degradation was evaluated for solar cells made from indium-doped single crystal silicon wafers and solar cells made from boron-doped single crystal silicon wafers (selected so that the oxygen and dopant concentrations closely matched). It was. Solar cells made from indium-doped wafers showed significantly less light-induced degradation after illumination compared to solar cells made from boron-doped wafers. More specifically, the efficiency of solar cells made from indium doped wafers remains 19% after illumination, compared to about 0.5% absolute degradation for boron doped cells, or 19 % Remained very close. From these results, solar cells made from indium-doped cells showed significantly less photoinduced degradation than solar cells made from boron-doped cells.

Example 12 Influence of Photo-Induced Degradation on Minority Carrier Life of Solar Cell Made from Indium-Doped Single Crystal Silicon Wafer and Solar Cell Made from Boron-Doped Single Crystal Silicon Wafer
Three groups of wafers were selected from three different crystals. Each group of wafers is from the same segment. There are four wafers in each group. The first group of wafers was sliced from long-lived boron-doped continuous Cz segments. A second group of wafers were sliced from boron-doped continuous Cz segments with an average lifetime. A third group of wafers was sliced from indium doped Cz crystals.

  All wafers were simultaneously etched and cleaned in the same container. Initial removal of damage was seen and 16 microns were removed from each wafer by a texture etching process. The wafer was cleaned after texture etching and passivated with an iodine-ethanol solution immediately after the final hydrogen fluoride (HF) acid cleaning step. Lifetime measurements were performed on iodine-ethanol passivation wafers before and after the wafers were light soaked for 6 days outdoors. A Sinton WTC-120 wafer tool was used in Transient mode to perform injection level life time measurement. After light soaking outdoors, etching and cleaning were performed in the same manner as before the lifetime measurement. The only difference was that about 12 microns of material was removed from each wafer after light soaking.

The crystal segment lifetime and resistivity for all three groups are shown in Table 16. Using a Sinton Instruments BCT-400, the lifetime at MCD = 5 × 10 ¹⁴ cm ⁻³ was measured. For all four P01GJ-A4 (high life, boron doped) wafers, the implantation level life before and after light soaking for 6 days outdoors is shown in FIG. For all four P00PC-C2 wafers (average lifetime, boron doped), the implant level lifetime before and after light soaking for 6 days outdoors is shown in FIG. For all four 210T0N wafers (indium doped), the implantation level lifetimes before and after light soaking for 6 days outdoors are shown in FIG.

A comparison of minority carrier lifetimes measured at 1 × 10 ¹⁵ cm ⁻³ implantation levels (MCD) for all 12 wafers is shown in Table 17.

  The minority carrier lifetime of indium-doped Cz wafers does not degrade after 6 days exposure to sunlight, while the minority carrier lifetime of boron-doped CCz wafers degrades. For boron doped silicon wafers and indium doped silicon wafers, the LID test, a minority carrier lifetime measurable performance parameter, is a solar cell for solar cells fabricated on indium doped Cz silicon wafers and boron doped CCz silicon wafers. Corresponds to efficiency data. In particular, the efficiency of solar cells fabricated on indium-doped Cz wafers does not degrade after exposure to light, while solar cells fabricated on boron-doped CCz exhibit light-induced degradation.

The efficiency of silicon solar cells is related to the minority carrier lifetime of the silicon wafer. The following equation relates to an ideal semiconductor diode with no charge recombination in the space charge region. A more general equation can be made, but the overall relationship can be revealed using an ideal diode model. Solar cell efficiency is given by Equation 9.

In Formula 9, V _oc is the open circuit voltage of the solar cell, I _sc is the short circuit current, FF is the fill factor of the diode, P _in is the power density of the incident illumination on the solar cell. P _in is a 1kW / ^{m 2} for the solar spectrum of AM1.5.

V _oc has a strong correlation with the minority carrier diffusion length of the base silicon. The open circuit voltage function for an ideal diode is given in Equation 10.

In Equation 10, k is the Boltzmann constant, T is the temperature, q is the electron elementary charge (fundamental charge), _{I L} is the current caused by the illumination, _{I 0} is the solar cell with an assumption of pn junction The saturation current of the cell. The open circuit voltage is related to the minority carrier diffusion length via the solar cell saturation current given in Equation 11.

In Equation 11, A is the area of the solar cell, D _e and D _h are the diffusion coefficients of electrons and holes, respectively, N _A is the number of acceptor dopants (or dopant acceptors), N _D Is the number of donor dopants (or dopant donors), L _e and Lh are the diffusion lengths of electrons and holes, respectively. In standard industrial solar cells, p-type silicon wafers are used to form junctions with heavily doped n-type emitters. Because of this electronic structure, the second term in Equation 11 is significantly smaller than the first term and can be ignored. All variables in the first term are fixed by the process or are physical constants except for the electron diffusion length. Since this is a p-type material, _Le is the minority carrier diffusion length. This parameter is used as a measure of crystal integrity. It represents the average distance that minority carriers will travel through the crystal before they recombine with the majority carriers. Its value is affected by many crystal properties such as metal impurities, crystal defects (dislocations, vacancies, etc.), intentional impurities (dopants) and other defects. The minority carrier diffusion length is related to the minority carrier lifetime through the minority carrier diffusion coefficient. This relationship for electrons that are minority carriers in p-type silicon is shown in Equation 12.

τ _e is the minority carrier lifetime of the electrons.

  As a result, a material with a higher minority carrier lifetime will have a lower saturation current, leading to higher open current and solar cell efficiency.

Another important mechanism to longer minority carrier diffusion length improves solar cell efficiency can be seen in the section I _L in Formula 10. Photocurrent (illuminated current) _{I L} of the solar cell is given by Equation 13.

G is the generation rate of electron-hole pairs for silicon. It is based on how crystalline silicon absorbs light and depends on the spectrum. W is the width of the depletion region of the solar cell junction. Other variables have already been explained. Equation 13 shows that on either side of the depletion region, the current due to illumination occurs mainly within one diffusion length. In a standard industrial solar cell, the depletion width is small and can be considered less than 0.5 microns, the thickness of the n-type diffused emitter region is smaller than the depletion width, and the active region for current generation due to illumination Will be one diffusion length into the p-type silicon wafer. The recombination rate of electron-hole pairs will be determined by minority carriers, which are electrons in p-type silicon. This has two implications for solar cell efficiency. First, as shown in Equation 10, by increasing the I _L, is that it will V _oc increases. Second, increasing the minority carrier diffusion length will increase the portion of the silicon wafer that will actively generate electron-hole pairs and increase the short-circuit current _Isc. .

Therefore, minority carrier diffusion length is also one of the most important material properties of silicon wafers used as the base of solar cells, also by extending the minority carrier lifetime. What has a significant effect on the open circuit voltage V _OC of the solar cell is a measurement of crystal integrity. It also increases the electrically active volume of the base silicon wafer and contributes to the open circuit voltage V _OC and short circuit current I _SC of the solar cells. Ultimately, silicon wafers with longer minority carrier lifetimes have better solar cell efficiency when the silicon wafer is the same electronic structure, such as industry standard diffusion bonded screen printed solar cells. Therefore, by replacing boron with indium to maintain the minority carrier lifetime of the wafer, solar cell efficiency will not degrade due to illumination, and for solar cells fabricated on indium doped wafers, light The efficiency of solar cells after exposure will be higher.

[Example 13: Effects of light-induced degradation on the minority carrier lifetime of solar cells and solar modules and solar cells and solar modules made from indium-doped single crystal silicon wafers Comparative test]
A population of solar cells was made (by a manufacturer of large industrial solar cells) using production line equipment. Solar cells were fabricated on both a boron doped single crystal silicon wafer and an indium doped single crystal silicon wafer. Solar cells were first measured with a photocurrent versus voltage measuring device from Sinton Instruments FCT-400. A total of 93 solar cells were measured, including 27 solar cells made on a boron-doped silicon wafer and 66 solar cells made on an indium-doped silicon wafer. The initial solar cell efficiency was between 19.1% and 19.2% for both boron-based and indium-based solar cells. After the initial measurement, all 93 solar cells were simultaneously light soaked outdoors. In St. Peters, Missouri, light soaking was conducted by placing solar cells outdoors from 12:00 PM to 10:00 AM four days later.

In addition, a solar cell module was fabricated from solar cells fabricated on an indium doped single crystal silicon wafer and a boron doped single crystal silicon wafer. Six modules were made from an indium-doped single crystal silicon wafer. One reference module was made from a boron doped single crystal silicon wafer. Modules were made using standard module materials (MEMC Singapore Inc.). Each module was manufactured from 72 solar cells. These modules were light soaked by placing the modules outdoors in Singapore until the modules were exposed to a total solar irradiance of about 150 kWhr / m ² . In order to compare the performance of the solar cells, the performance data of the solar cell module after exposure to a total solar irradiance of about 20 kWhr / m ² was used.

  After light soaking, a total of 93 solar cells were measured using a photocurrent versus voltage measuring device of Sinton Instruments FCT-400. Measurement of the most relevant performance parameters: solar cell efficiency, open circuit voltage, short circuit current and fill factor are normalized to the initial value of each solar cell. The initial value of each solar cell is 1. Measurements after light soaking indicate normalized degradation. The normalized solar cell efficiency, open circuit voltage, short circuit current and fill factor before and after light soaking are shown in FIGS. 12, 13, 14 and 15, respectively. For comparison, the same performance parameters for solar cells are also included.

The average normalized performance parameters after light soaking for solar cells made from boron doped silicon wafers and indium doped silicon wafers are shown in Table 18 below. The normalized solar cell efficiency shown in FIG. 12 is degraded by less than 1% for solar cells fabricated on indium-doped silicon wafers, while solar cells fabricated on boron-doped silicon wafers are It shows that it deteriorates more than 2%. Degradation of solar cells fabricated on boron-doped silicon wafers is significantly greater than solar cells fabricated on indium-doped silicon wafers, which occurs with all performance parameters; V _OC , I _SC and FF. The greatest difference between solar cells made on indium doped silicon wafers compared to solar cells made on boron doped silicon wafers is seen in the fill factor. This is mainly a result of the implantation level lifetime behavior of boron-doped silicon after light soaking and shows a dramatic decrease in lifetime at all implantation levels.

In addition, the LID performance of the solar cell module shows almost the same behavior as the data of the solar cell. The only difference can be seen in the open circuit voltage. However, after longer exposure time to sunlight (150 kWhr / m ² ), the open-circuit voltage data for solar cells and modules approach.

  Solar cells made on boron and indium doped silicon wafers made in mass production equipment can also be shown in terms of percent relative LID and absolute efficiency loss. Both are commonly used in the solar cell industry to report losses due to light-induced degradation. The percent relative LID and absolute efficiency loss of solar cells fabricated on boron-doped and indium-doped silicon wafers are shown in FIGS. 16 and 17, respectively.

  An outdoor light soaking test for industry standard diffusion bonded screen printed silicon solar cells manufactured on a solar cell mass production line shows that light-induced degradation for indium doped silicon wafers is significantly higher than for boron doped silicon wafers. Indicates small. Furthermore, the magnitude of degradation of solar cells fabricated on boron-doped silicon wafers is significant, while the degree of degradation is almost negligible in solar cells fabricated on indium-doped silicon wafers. Solar cell modules made from the same group of solar cells (made from boron-doped silicon wafers and indium-doped silicon wafers) functioned similarly to single solar cells. Solar cell modules that include solar cells fabricated on indium doped silicon wafers exhibit less than 1% efficiency degradation, while solar cell modules that include solar cells fabricated on boron doped silicon wafers It showed an efficiency degradation greater than 2%.

  Since various changes can be made in the above-described process without departing from the scope of the present disclosure, all matters contained therein are intended to be interpreted as illustrative and not in a limiting sense. Further, when introducing elements of the present disclosure or embodiments thereof, the articles “a”, “an”, “the” and “said” may include one or more Is intended to mean that there is an element. The terms “comprising”, “including” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. The

  This description includes examples disclosing the invention, including the best mode, and allows any person skilled in the art to practice the invention (make and use any device or system, or any incorporation). Use of an embodiment that also allows for the implementation of the described method). The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Where such other embodiments include elements that do not differ from the literal language of the claims, or where such other embodiments are not substantially different from the literal language of the claims Such alternative embodiments are intended to be within the scope of the following claims, including equivalent components that have:

Claims (56)

  Conversion of spectral irradiance of sunlight on the surface of indium doped single crystal silicon wafer under absolute air mass 1.5, including indium doped single crystal silicon wafer sliced from ingot grown by Czochralski method A solar cell having an efficiency of at least 17%.   The solar cell according to claim 1, wherein the conversion efficiency of the spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under an absolute air mass of 1.5 is at least 18%.   The solar cell according to claim 1, wherein the conversion efficiency of the spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under the absolute air mass 1.5 is at least 19%.   The solar cell according to claim 1, wherein the conversion efficiency of spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under an absolute air mass of 1.5 is at least 19.5%.   The solar cell according to claim 1, wherein the conversion efficiency of the spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under an absolute air mass of 1.5 is at least 20%.   The solar cell according to claim 1, wherein the conversion efficiency of the spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under the absolute air mass 1.5 is at least 20.5%.   The solar cell according to claim 1, wherein the conversion efficiency of the spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under an absolute air mass of 1.5 is at least 21%.   The solar cell according to claim 1, wherein the conversion efficiency of spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under an absolute air mass of 1.5 is at least 22%.   The solar cell according to claim 1, wherein the conversion efficiency of the spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under the absolute air mass 1.5 is at least 24%.   The solar cell according to claim 1, wherein the conversion efficiency of spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under an absolute air mass of 1.5 is at least 26%.   The solar cell according to claim 1, wherein the conversion efficiency of the spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under the absolute air mass 1.5 is at least 28%.   The solar cell according to claim 1, wherein the conversion efficiency of the spectral irradiance of sunlight on the surface of the indium-doped single crystal silicon wafer under the absolute air mass 1.5 is at least 30%.   The solar cell of claim 1, wherein the indium-doped single crystal silicon wafer has an average bulk resistivity less than about 10 Ω · cm.   The solar cell of claim 1, wherein the indium-doped single crystal silicon wafer has an average bulk resistivity less than about 5 Ω · cm.   The solar cell of claim 1, wherein the indium-doped single crystal silicon wafer has an average bulk resistivity less than about 4 Ω · cm.   The solar cell of claim 1, wherein the indium-doped single crystal silicon wafer has an average bulk resistivity less than about 3 Ω · cm.   The solar cell of claim 1, wherein the indium-doped single crystal silicon wafer has an average bulk resistivity less than about 1 Ω · cm.   The solar cell of claim 1, wherein the indium-doped single crystal silicon wafer has an average bulk resistivity less than about 0.5 Ω · cm.   The solar cell according to claim 1, wherein the relative efficiency of the solar cell deteriorates by about 2% or less after being exposed to light corresponding to 0.1 to 10 SUN at a temperature lower than 45 ° C for 1 to 300 hours.   The solar cell according to claim 1, wherein the relative efficiency of the solar cell is deteriorated by about 1% or less after being exposed to light corresponding to 0.1 to 10 SUN at a temperature lower than 45 ° C for 1 to 300 hours.   The solar cell according to claim 1, wherein the relative efficiency of the solar cell deteriorates by about 2% or less after being exposed to light corresponding to 0.7 SUN at a temperature lower than 45 ° C for 24 hours.   The solar cell according to claim 1, wherein the relative efficiency of the solar cell deteriorates by about 1% or less after being exposed to light corresponding to 0.7 SUN at a temperature lower than 45 ° C for 24 hours.   The solar cell according to claim 1, wherein the absolute efficiency of the solar cell deteriorates by about 0.5% or less after exposure to light corresponding to 0.1 to 10 SUN at a temperature lower than 45 ° C for 1 to 300 hours.   The solar cell according to claim 1, wherein the absolute efficiency of the solar cell deteriorates by about 0.2% or less after being exposed to light corresponding to 0.1 to 10 SUN at a temperature lower than 45 ° C for 1 to 300 hours.   The solar cell according to claim 1, wherein the absolute efficiency of the solar cell deteriorates by about 0.1% or less after being exposed to light corresponding to 0.1 to 10 SUN at a temperature lower than 45 ° C for 1 to 300 hours.   The solar cell according to claim 1, wherein the absolute efficiency of the solar cell deteriorates by about 0.5% or less after being exposed to light corresponding to 0.7 SUN at a temperature lower than 45 ° C for 24 hours.   The solar cell according to claim 1, wherein the absolute efficiency of the solar cell deteriorates by about 0.2% or less after being exposed to light corresponding to 0.7 SUN at a temperature lower than 45 ° C for 24 hours.   The solar cell according to claim 1, wherein the absolute efficiency of the solar cell deteriorates by about 0.1% or less after being exposed to light corresponding to 0.7 SUN at a temperature lower than 45 ° C for 24 hours.   The solar cell of claim 1, wherein the indium-doped wafer absorbs more light having a wavelength between 830 nm and 1400 nm than a boron-doped wafer having the same resistivity.   Indium doped single crystal silicon wafer sliced from an ingot grown by the Czochralski method, said wafer having an average bulk resistivity of less than about 10 Ω · cm and at a temperature below 45 ° C. A solar cell whose relative efficiency deteriorates by about 1% or less after being exposed to light corresponding to 10 SUN for 1 to 300 hours.   The solar cell of claim 30, wherein the indium-doped single crystal silicon wafer has an average bulk resistivity of less than about 5 Ω · cm.   31. The solar cell of claim 30, wherein the indium doped single crystal silicon wafer has an average bulk resistivity less than about 4 Ω · cm.   32. The solar cell of claim 30, wherein the indium doped single crystal silicon wafer has an average bulk resistivity less than about 3 Ω · cm.   The solar cell of claim 30, wherein the indium-doped single crystal silicon wafer has an average bulk resistivity less than about 1 Ω · cm.   31. The solar cell of claim 30, wherein the indium doped single crystal silicon wafer has an average bulk resistivity less than about 0.5 Ω · cm.   The solar cell according to claim 30, wherein the absolute efficiency of the solar cell deteriorates by about 0.5% or less after exposure to light corresponding to 0.1 to 10 SUN at a temperature lower than 45 ° C for 1 to 300 hours.   The solar cell according to claim 30, wherein the absolute efficiency of the solar cell deteriorates by about 0.2% or less after being exposed to light corresponding to 0.1 to 10 SUN at a temperature lower than 45 ° C for 1 to 300 hours.   The solar cell according to claim 30, wherein the absolute efficiency of the solar cell deteriorates by about 0.1% or less after exposure to light corresponding to 0.1 to 10 SUN at a temperature lower than 45 ° C for 1 to 300 hours.   The solar cell according to claim 30, wherein the absolute efficiency of the solar cell deteriorates by about 0.5% or less after being exposed to light corresponding to 0.7 SUN at a temperature lower than 45 ° C for 24 hours.   The solar cell of claim 30, wherein the absolute efficiency of the solar cell deteriorates by about 0.2% or less after being exposed to light corresponding to 0.7 SUN at a temperature lower than 45 ° C for 24 hours.   The solar cell according to claim 30, wherein the absolute efficiency of the solar cell deteriorates by about 0.1% or less after being exposed to light corresponding to 0.7 SUN at a temperature lower than 45 ° C for 24 hours.   31. The solar cell of claim 30, wherein the indium doped wafer absorbs more light having a wavelength between 830 nm and 1400 nm than a boron doped wafer with the same resistivity.   Indium doped single crystal silicon wafer sliced from an ingot grown by the Czochralski method, said wafer having an average bulk resistivity of less than about 10 Ω · cm, and less than 45 ° C. to sunlight A solar cell whose relative efficiency deteriorates by about 1% or less after time exposure. A central axis, a front surface and a rear surface that are substantially perpendicular to the central axis, a central surface between and parallel to the front surface and the rear surface, a peripheral edge, and from the central axis to the peripheral edge With an extending radius R:
An average indium concentration of at least about 1 × 10 ¹⁵ atoms / cm ³ ;
The indium concentration has a relative radial change of about 15% or less over at least 0.75R;
Single crystal silicon segment.   45. The single crystal silicon segment of claim 44, wherein the indium concentration has a relative radial change of about 15% or less over at least 0.95R.   45. The single crystal silicon segment of claim 44, wherein the indium concentration has a relative radial change of about 10% or less over at least 0.75R. 45. The single crystal silicon segment of claim 44, wherein the average indium concentration is between about 1 × 10 ¹⁵ atoms / cm ³ and about 1 × 10 ¹⁷ atoms / cm ³ .   45. The single crystal silicon segment of claim 44, having an oxygen concentration between about 11 ppma and about 20 ppma.   45. The single crystal silicon segment of claim 44, having a carbon concentration of about 2 ppma or less. Having a thickness between about 100 μm and about 1000 μm and two main dimensions between about 50 mm and about 300 mm:
An average indium concentration of at least about 1 × 10 ¹⁵ atoms / cm ³ ;
The indium concentration has a change of about 15% or less over at least 75% of the length of either of the two major dimensions;
Single crystal silicon wafer.   Having a thickness between about 120 μm and about 240 μm and two major dimensions between about 100 mm and about 200 mm, wherein the indium concentration is at least 75% of the length of both of the two major dimensions. 51. The single crystal silicon wafer of claim 50 having a radial relative change of about 15% or less.   51. The single crystal silicon wafer of claim 50, wherein the indium concentration has a relative radial change of about 15% or less over at least 95% of the length of both of the two major dimensions.   51. The single crystal silicon wafer of claim 50, wherein the indium concentration has a relative radial change of about 10% or less over at least 75% of the length of both of the two major dimensions. 51. The single crystal silicon wafer of claim 50, wherein the average indium concentration is between about 1 * 10 < ¹⁵ > atoms / cm < ³ > and about 1 * 10 < ¹⁷ > atoms / cm < ³ >.   51. The single crystal silicon wafer of claim 50, having an oxygen concentration between about 11 ppma and about 20 ppma.   The single crystal silicon wafer of claim 50 having a carbon concentration of about 2 ppma or less.

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