JP2016224341A - Drive circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit capable of improving the display quality by using a leader line with uniform resistance, which is connected to the drive circuit.SOLUTION: The drive circuit includes: plural output circuits which output signal to leader lines, which are electrically connected to signal lines disposed on a display panel; and plural resistors which are electrically connected to output terminals of at least one of plural output circuits. The resistance value of the resistors is preset depending on the resistance value of the leader lines which are electrically connected to the resistors.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a driving circuit and a display device including the driving circuit.

  In the display area of the display device, for example, gate lines extend in the row direction (horizontal direction) and are arranged at a predetermined pitch in the column direction (vertical direction), and data lines extend in the column direction. They are arranged in the row direction at a predetermined pitch. A data signal is supplied from the source driver IC to the data line, and a gate signal is supplied from the gate driver IC to the gate line. Since the pitch of the terminal of the driver IC is smaller than the pitch of the signal line (data line, gate line), the length of the lead line that relays between the terminal of the driver IC and the signal line differs depending on the location.

  If the lengths of the lead lines differ, the electrical resistance from the terminal of the driver IC to the signal line varies depending on the location. As a result, a luminance difference occurs in the display area, and the display quality is degraded. Patent Document 1 discloses a technique for making the resistance of a lead line uniform by adjusting the width (line width) of the lead line.

JP-A-8-76136

  However, in recent display devices, the spacing between adjacent lead lines is narrowing as the definition and size are reduced. In particular, the extending direction of the lead lines is an oblique direction with respect to the extending direction of the signal lines, and the interval is narrower. For this reason, in the conventional technique, for example, there is a problem that adjacent wirings come into contact with each other by increasing the width of the leader line, or disconnection occurs by reducing the width of the leader line.

  The present invention has been made in view of the above problems, and an object of the present invention is to improve display quality in a display device by making the resistance of a lead line connected to a drive circuit uniform.

  In order to solve the above-described problem, a driving device according to the present invention includes an output circuit that outputs a signal to a lead line electrically connected to a signal line provided in a display panel, and at least one of the plurality of output circuits. A resistor electrically connected to an output terminal of one of the output circuits, and a resistance value of the resistor is set according to a resistance value of the lead wire electrically connected to the resistor It is characterized by being.

  In the driving device according to the present invention, the resistance value of the resistor is such that the longer the length of the lead wire electrically connected to the resistor, the smaller the value, and the shorter the length of the lead wire, the larger the resistance value. It may be set.

  In the drive device according to the present invention, a plurality of the resistors are arranged in a first direction in which the plurality of signal lines electrically connected to the drive circuit are arranged, and each of the resistance values of the plurality of resistors is arranged. May be set so as to decrease from the center of the driving circuit toward both ends in the first direction.

  In the drive device according to the present invention, each resistance value of the plurality of resistors may be set so as to decrease from the center of the drive circuit toward both ends in the first direction.

  In the driving apparatus according to the present invention, a plurality of the resistors are provided for each of the plurality of output circuits, and each resistance value of the plurality of resistors connected to each of the output circuits is , Different values may be set.

  In the drive device according to the present invention, a first resistor and a second resistor set to a resistance value smaller than that of the first resistor are connected in parallel to the output terminal of each output circuit. Also good.

  A display device according to the present invention includes a display panel provided with a plurality of signal lines and a plurality of lead lines electrically connected to the plurality of signal lines, and a plurality of signals that output signals to the plurality of lead lines. And a drive circuit including a resistor electrically connected to an output terminal of at least one of the plurality of output circuits, and the resistance value of the resistor is It is set according to the resistance value of the lead wire electrically connected to the resistor.

  In the display device according to the present invention, a first resistor and a second resistor set to a resistance value smaller than that of the first resistor are connected in parallel to the output terminals of the output circuits. The plurality of lead lines may be patterned so as to be electrically connected to the plurality of first resistors or the plurality of second resistors.

  In the display device according to the present invention, a first resistor and a second resistor set to a resistance value smaller than that of the first resistor are connected in parallel to the output terminals of the output circuits. The plurality of lead wires are electrically connected to the plurality of first resistors, the plurality of second resistors, or both of the plurality of first resistors and the plurality of second resistors. The pattern may be formed as described above.

  In the display device according to the present invention, some of the plurality of lead lines extend in an oblique direction with respect to a direction in which the plurality of signal lines electrically connected to the drive circuit extend. Also good.

  In the display device according to the present invention, the width of the lead line may be thicker as the length of the lead line is shorter, and may be thinner as the length of the lead line is longer.

  In the display device according to the present invention, the width of the lead line connected to the center side of the drive circuit may be larger than the width of the lead line connected to both ends of the drive circuit.

  According to the configuration of the driving device according to the present invention, the resistance of the lead line connected to the driving circuit can be made uniform, so that the display quality in the display device can be improved.

It is a top view which shows schematic structure of the liquid crystal display device which concerns on this embodiment. It is a top view which shows schematic structure of a display panel. It is a top view which shows the structural example of a leader line. It is a graph which shows the result of having simulated the distribution of resistance of the leader line shown to Fig.3 (a). It is a figure which shows the circuit structure of a gate driver IC. It is a graph which shows distribution of the resistance value set to a resistor corresponding to the resistance distribution in the leader line of FIG. It is a graph which shows distribution of the resistance of a leader line. It is a figure which shows the other circuit structure of gate driver IC. It is a graph which shows distribution of the resistance value set to a 1st resistor and a 2nd resistor. It is a graph which shows distribution of the resistance of a leader line. It is a graph which shows distribution of the resistance of a leader line. It is a graph which shows distribution of the resistance of a leader line. It is a top view which shows the connection structure of the 1st pattern of a gate driver IC and a leader line. It is a top view which shows the connection structure of the 2nd pattern of a gate driver IC and a leader line. It is a top view which shows the connection structure of the 3rd pattern of a gate driver IC and a leader line. It is a figure which shows the other circuit structure of gate driver IC. It is a top view which shows the other structural example of a leader line. It is a graph which shows the result of having simulated the resistance distribution of the leader line shown to Fig.17 (a). It is a graph which shows distribution of the resistance value set to a resistor corresponding to resistance distribution in the leader line of FIG.

  An embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, a liquid crystal display device is taken as an example of the display device, but the present invention is not limited to this, and may be, for example, an organic EL display device. In this embodiment, a COG (Chip On Glass) display device is taken as an example, but the present invention is not limited to this, and for example, a COF (Chip On Film) display device or a TCP (Tape Carrier Package) method is used. The display device or the like may be used.

  FIG. 1 is a plan view showing a schematic configuration of the liquid crystal display device according to the present embodiment. The liquid crystal display device 100 includes a display panel 10, a plurality of source driver ICs 20 (driving circuits), a plurality of gate driver ICs 30 (driving circuits), a control circuit (not shown), and a backlight device (not shown). It consists of The number of source driver ICs 20 and gate driver ICs 30 is not limited. In FIG. 1, the source driver IC 20 and the gate driver IC 30 are individually arranged in a line along two different sides (the left side and the upper side in the drawing) of the display panel 10. They may be arranged in a line. The display panel 10 includes a display area 10a and a frame area around the display area 10a (outside the display area). In the frame region, a lead line 11a electrically connected to the output terminal of the source driver IC 20 and a lead line 12a electrically connected to the output terminal of the gate driver IC 30 are provided. A plurality of lead lines 11 a are electrically connected to each source driver IC 20, and a plurality of lead lines 12 a are electrically connected to each gate driver IC 30. The source driver IC 20 outputs a data signal (data voltage) to the lead line 11a, and the gate driver IC 30 outputs a gate signal (gate voltage) to the lead line 12a.

  FIG. 2 is a plan view showing a schematic configuration of the display panel 10. The display area 10a of the display panel 10 includes a plurality of data lines 11 extending in the column direction and arranged at a predetermined pitch in the row direction, and a plurality of data lines 11 extending in the row direction and arranged at a predetermined pitch in the column direction. Gate line 12 is provided. In the frame region, each data line 11 is electrically connected to each lead line 11a, and each gate line 12 is electrically connected to each lead line 12a. That is, each data line 11 is electrically connected to a corresponding source driver IC 20 via each lead line 11a, and each gate line 12 is electrically connected to a corresponding gate driver IC 30 via each lead line 12a. Has been.

  The arrangement pitch of the output terminals of the source driver IC 20 is smaller than the arrangement pitch of the data lines 11, and the arrangement pitch of the output terminals of the gate driver IC 30 is smaller than the arrangement pitch of the gate lines 12. A part of the plurality of lead lines 11a extends obliquely with respect to the column direction, and a part of the plurality of lead lines 12a extends obliquely with respect to the row direction. For this reason, the length of each lead-out line 11a, 12a changes with places.

  At each intersection of each data line 11 and each gate line 12, a thin film transistor 13 (TFT) is provided. In the display panel 10, a plurality of pixels 14 are arranged in a matrix (row direction and column direction) corresponding to each intersection of each data line 11 and each gate line 12. Although not shown, the display panel 10 includes a thin film transistor substrate (TFT substrate), a color filter substrate (CF substrate), and a liquid crystal layer sandwiched between the substrates. The TFT substrate is provided with a plurality of pixel electrodes 15 corresponding to each pixel 14 and a common electrode 16 common to each pixel 14. The common electrode 16 may be provided on the CF substrate.

  Each data line 11 is supplied with a data signal (data voltage) from the corresponding source driver IC 20 via each lead line 11a. Each gate line 12 is supplied with a gate signal (gate voltage) from the corresponding gate driver IC 30 via the lead line 12a. A common voltage Vcom is supplied to the common electrode 16 from a common driver (not shown) via a common wiring. When an on voltage (gate on voltage) of the gate signal is supplied to the gate line 12, the thin film transistor 13 connected to the gate line 12 is turned on, and the data voltage is supplied to the pixel electrode via the data line 11 connected to the thin film transistor 13. 15 is supplied. An electric field is generated by the difference between the data voltage supplied to the pixel electrode 15 and the common voltage Vcom supplied to the common electrode 16. The liquid crystal is driven by this electric field, and the image display is performed by controlling the light transmittance of the backlight. In the case of performing color display, a desired data voltage is applied to each data line 11 connected to the pixel electrode 15 of each pixel 14 corresponding to red, green, blue, etc. formed by a striped color filter. This is realized by supplying

  Here, the resistance of the lead line (wiring resistance) will be considered. Here, the lead line 12a connected to the gate driver IC 30 is taken as an example. As described above, since the arrangement pitch of the output terminals of the gate driver IC 30 is smaller than the arrangement pitch of the gate lines 12, the lead line 12a depends on the location of the output terminal of the gate driver IC 30 to which the lead line 12a is connected. The length is different. For example, as shown in FIG. 3A, the lead wire 12a connected to the output terminal arranged on the center side of the gate driver IC 30 has a short length, and the lead wire connected to the output terminals arranged on both end sides. The line 12a becomes longer. FIG. 3A shows a configuration in which the length of the lead line 12a is vertically symmetrical. However, as shown in FIG. 3B, the length of the lead line 12a is vertically asymmetric. An arranged configuration may be used. In FIG. 3B, the lead wire 12a connected to the output terminal disposed on one end side (the upper end side in the drawing) of the gate driver IC 30 has a short length and is connected to the other end side (the lower end side in the drawing). The length of the lead wire 12a connected to the arranged output terminal is increased. Thus, the resistance of the lead line 12a varies depending on the location where the lead line 12a is disposed.

  FIG. 4 is a graph showing the result of simulating the resistance distribution of the lead line 12a shown in FIG. The horizontal axis of the graph in FIG. 4 indicates the number (ch) of the output terminal of the gate driver IC 30, and the vertical axis indicates the resistance value (Ω) of the lead line 12a. Note that the resistance values shown in FIG. 4 are specific resistance values according to the characteristics (length, width, etc.) of the lead wire 12a. 0ch on the horizontal axis represents an output terminal at one end of the gate driver IC 30 (the upper end of FIG. 3A), 350ch represents an output terminal at the center of the gate driver IC 30, and 700ch represents the other end of the gate driver IC 30 (FIG. 3 ( The output terminal of the lower end of a) is shown. As shown in FIG. 4, the lead line 12a connected to the center output terminal of the gate driver IC 30 has the smallest resistance, and the resistance of the lead line 12a increases linearly from the center to the end output terminal. I understand that. This resistance difference appears as a luminance difference of the display panel, resulting in a decrease in display quality.

  The liquid crystal display device 100 according to the present embodiment, particularly a driver IC (source driver IC, gate driver IC), has a configuration for reducing the resistance difference (making the resistance value uniform). Details of this configuration will be described below. Hereinafter, the gate driver IC 30 will be described as an example, but the same applies to the source driver IC 20.

  FIG. 5 is a diagram illustrating a circuit configuration of the gate driver IC 30. The gate driver IC 30 includes a plurality of shift register circuits SR1 to SRn. The gate driver IC 30 corresponding to the graph shown in FIG. 4 includes 700 shift register circuits SR1 to SR700 (n = 700). The clock CK1 and the start pulse SP are input to the first-stage shift register circuit SR1. The output signal of the shift register circuit SR1 is input to the first-stage resistor R1 and the second-stage shift register circuit SR2. The clock CK2 and the output signal of the shift register circuit SR1 are input to the second-stage shift register circuit SR2. The output signal of the second-stage shift register circuit SR2 is input to the second-stage resistor R2, the third-stage shift register circuit SR3, and the first-stage shift register circuit SR1 as a reset signal. The clock CK1 and the output signal of the shift register circuit SR2 are input to the third-stage shift register circuit SR3. The output signal of the third-stage shift register circuit SR3 is input to the third-stage resistor R3, the fourth-stage shift register circuit SR4, and the second-stage shift register circuit SR2 as a reset signal. In this way, the shift operation of the shift register circuits SR1 to SR700 is performed. Note that the structure of the shift register circuit SR is not limited to the above structure, and a known structure can be applied. One end (input terminal) of the resistor R is connected to the output terminal of each shift register circuit SR. The other end (output terminal) of the resistor R is connected to the output terminal OUT of the gate driver IC 30.

  The resistance value of each resistor R is set to a different value depending on where the resistor R is disposed in the gate driver IC 30. For example, the resistance value of the resistor R is the largest for the resistor R connected to the center output terminal OUT of the gate driver IC 30 and the smallest for the resistor R connected to the output terminal OUT at the end of the gate driver IC 30. It is set to be. FIG. 6 is a graph showing a distribution of resistance values set in the resistor R, corresponding to the resistance distribution in the lead line 12a of FIG. As shown in FIG. 6, the resistance value of the resistor R connected to the center output terminal OUT (350ch) of the gate driver IC 30 is the largest, and the distance from the center to the end output terminal OUT (0ch, 700ch) increases. The resistance value of the resistor R is set to be small. In FIG. 6, the resistance value changes linearly, but the present invention is not limited to this.

  According to the above configuration, the inherent resistance value of the lead line (see FIG. 4) and the set resistance value of the resistor R (see FIG. 6) are combined, and as shown in FIG. Is made uniform. Thereby, since the luminance difference is reduced, it is possible to prevent the display quality from being deteriorated due to the wiring resistance. Further, since there is no need to adjust the width of the lead lines, contact or disconnection between the lead lines can be prevented, and the area of the frame region can be reduced.

  The configuration of the gate driver IC 30 is not limited to the configuration of FIG. FIG. 8 is a diagram showing another circuit configuration of the gate driver IC 30. Hereinafter, description of the same configuration as that of FIG. 5 is omitted.

  The gate driver IC 30 includes a plurality of shift register circuits SR1 to SRn. One end (input terminal) of each of the first resistor Ra and the second resistor Rb connected in parallel to each other is connected to the output terminal of each shift register circuit SR. The other end (output terminal) of the first resistor Ra is connected to the first output terminal OUT1 of the gate driver IC30, and the other end (output terminal) of the second resistor Rb is the second output terminal OUT2 of the gate driver IC30. It is connected to the. The output signal of the shift register circuit SR at each stage is input to the first resistor Ra and the second resistor Rb at each stage.

  The resistance value of each first resistor Ra is set to a different value depending on the location where the first resistor Ra is arranged in the gate driver IC 30, and the resistance value of each second resistor Rb is set in the gate driver IC 30. Are set to different values depending on where the second resistor Rb is disposed. For example, the resistance value of the plurality of first resistors Ra is the largest at the first resistor Ra connected to the center output terminal OUT of the gate driver IC 30 and is connected to the output terminal OUT at the end of the gate driver IC 30. The first resistor Ra is set to be the smallest. Similarly, the resistance value of the plurality of second resistors Rb is the largest at the second resistor Rb connected to the center output terminal OUT of the gate driver IC 30 and is connected to the output terminal OUT at the end of the gate driver IC 30. The set second resistor Rb is set to be the smallest.

  Further, the resistance value of the first resistor Ra and the resistance value of the second resistor Rb are set to different values. FIG. 9 is a graph showing a distribution of resistance values set in the first resistor Ra and the second resistor Rb. As shown in FIG. 9, the resistance value set in the first resistor Ra and the second resistor Rb is the highest in the resistance value of the resistor R connected to the output terminal OUT in the center of the gate driver IC 30. The resistance value of the resistor R is set so as to decrease from the output terminal OUT to the end. The resistance value of the second resistor Rb is set to be smaller than the resistance value of the first resistor Ra. FIG. 9 shows a resistance value (combined resistance value) obtained by combining the resistance values of the first resistor Ra and the second resistor Rb connected in parallel. Each resistance distribution shown in FIG. 9 has different functional characteristics (here, linearity).

  According to the above configuration, three patterns of resistance distribution can be set by one gate driver IC 30. Therefore, for example, in the case of the display panel 10 in which the lead line 12a has the resistance distribution shown in FIG. 10, the lead line 12a is connected to the first resistor Ra (first pattern), whereby the resistance of each lead line 12a. The value can be made uniform. Further, for example, in the case of the display panel 10 in which the lead line 12a has the resistance distribution shown in FIG. 11, the resistance value of each lead line 12a is obtained by connecting the lead line 12a to the second resistor Rb (second pattern). Can be made uniform. Further, for example, in the case of the display panel 10 in which the lead line 12a has the resistance distribution shown in FIG. 12, by connecting the lead line 12a to the first resistor Ra and the second resistor Rb in parallel (third pattern), The resistance value of each lead line 12a can be made uniform.

  Thus, by changing the connection destination (output terminal of the gate driver IC 30) of the lead line 12a according to the type (size, resolution, etc.) of the display panel 10 without changing the design of the gate driver IC 30, The resistance value of the lead line 12a can be made uniform. FIG. 13 shows the connection configuration of the first pattern, FIG. 14 shows the connection configuration of the second pattern, and FIG. 15 shows the connection configuration of the third pattern. The connection method of the first to third patterns can be realized by forming corresponding wiring patterns in the manufacturing process of the TFT substrate.

  Further, the connection of the first to third patterns may be switched by a switching circuit. FIG. 16 is a diagram illustrating another circuit configuration of the gate driver IC 30. As shown in FIG. 16, the gate driver IC 30 includes a switching circuit SW between the output terminals of the first resistor Ra and the second resistor Rb connected in parallel and the output terminal OUT of the gate driver IC 30. Yes. In the above configuration, the first to third patterns are switched by the switching circuit SW according to the type of the display panel 10. Thereby, according to the kind of display panel 10, the resistance value of each leader line 12a can be equalize | homogenized.

  The present invention is not limited to the above embodiment. For example, the resistor R may not be provided in the region where the resistance value of the lead wire 12a is high (both ends in FIG. 4). The number of resistors R connected to one shift register circuit SR is not limited. For example, three resistors R are connected to the shift register circuit SR on the center side, and the number of resistors R connected to one shift register circuit SR decreases as it goes to both ends. The shift register circuit SR may not be connected to the resistor R.

  Further, the widths of the lead lines 12a may be equal to each other or different from each other. For example, you may form so that the width | variety of the leader line 12a may become thick, so that the length of the leader line 12a becomes short. For example, as shown in FIG. 17A, the lead line 12a connected to the output terminal disposed on the center side of the gate driver IC 30 has a large width and is connected to the output terminal disposed on both ends. The line 12a may be narrowed. As shown in FIG. 17B, the lead wire 12a connected to the output terminal disposed on one end side (the upper end side in the drawing) of the gate driver IC 30 has a larger width and the other end side (in the drawing). The width of the lead wire 12a connected to the output terminal arranged on the lower end side may be reduced.

  Comparing the configuration of FIG. 17A and the configuration of FIG. 3A, the width of the lead line 12a shown in FIG. 17A is equal to the width of the lead line shown in FIG. It is equal to the width of 12a and is thicker than the width of the lead line 12a shown in FIG. FIG. 18 is a graph showing a result of simulating the resistance distribution of the lead line 12a shown in FIG. In FIG. 18, the resistance distribution (see FIG. 4) of the lead line 12a corresponding to the configuration of FIG. As shown in FIG. 18, it can be seen that the resistance value of the lead-out line 12 a decreases from the output terminal at the end toward the center output terminal as compared with the configuration of FIG.

  In the case of the configuration shown in FIG. 17A, the resistance value of the resistor R is set higher than the resistance value of the resistor R corresponding to the configuration of FIG. 3A (see FIG. 6). FIG. 19 is a graph showing a distribution of resistance values set in the resistor R, corresponding to the resistance distribution in the lead line 12a of FIG. In FIG. 19, the distribution of resistance values set in the resistor R (see FIG. 6) corresponding to the resistance distribution in the lead line 12a of FIG. In this way, the resistance value of the resistor R may be set in consideration of both the length and width of the leader line.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to said each embodiment, The form suitably changed by those skilled in the art from said each embodiment within the range which does not deviate from the meaning of this invention. Needless to say, it is included in the technical scope of the present invention.

  DESCRIPTION OF SYMBOLS 100 Liquid crystal display device, 10 Display panel, 10a Display area, 11 Data line, 12 Gate line, 11a, 12a Lead line, 13 Thin-film transistor, 14 pixel, 15 Pixel electrode, 16 Common electrode, 20 Source driver IC, 30 Gate driver IC , OUT output terminal, OUT1 first output terminal, OUT2 second output terminal, R resistor, Ra first resistor, Rb second resistor, SR shift register circuit, CK1, CK2 clock, SP start pulse.

Claims (12)

An output circuit for outputting a signal to a lead line electrically connected to a signal line provided on the display panel;
A resistor electrically connected to an output terminal of at least one of the plurality of output circuits;
Including
The resistance value of the resistor is set according to the resistance value of the lead wire electrically connected to the resistor,
A drive circuit characterized by that. The resistance value of the resistor is set to be smaller as the length of the lead wire electrically connected to the resistor is longer, and larger as the length of the lead wire is shorter.
The drive circuit according to claim 1. A plurality of the resistors are arranged in a first direction in which a plurality of the signal lines electrically connected to the drive circuit are arranged,
Each resistance value of the plurality of resistors is set to be smaller as it goes from the center of the driving circuit to both ends in the first direction.
The drive circuit according to claim 1. Each resistance value of the plurality of resistors is set to decrease from the center of the drive circuit toward both ends in the first direction.
The drive circuit according to claim 3. A plurality of resistors are provided for each of the plurality of output circuits,
The resistance values of the plurality of resistors connected to the output circuits are set to different values from each other.
The drive circuit according to claim 1. A first resistor and a second resistor set to a resistance value smaller than that of the first resistor are connected in parallel to the output terminals of the output circuits.
The drive circuit according to claim 5. A display panel provided with a plurality of signal lines and a plurality of lead lines electrically connected to the plurality of signal lines;
A drive circuit comprising: a plurality of output circuits for outputting signals to the plurality of lead lines; and a resistor electrically connected to an output terminal of at least one of the plurality of output circuits.
Including
The resistance value of the resistor is set according to the resistance value of the lead wire electrically connected to the resistor,
A display device characterized by that. A first resistor and a second resistor set to a resistance value smaller than that of the first resistor are connected in parallel to the output terminals of the output circuits.
The plurality of lead lines are patterned to be electrically connected to the plurality of first resistors or the plurality of second resistors,
The display device according to claim 7. A first resistor and a second resistor set to a resistance value smaller than that of the first resistor are connected in parallel to the output terminals of the output circuits.
The plurality of lead wires are electrically connected to the plurality of first resistors, the plurality of second resistors, or both of the plurality of first resistors and the plurality of second resistors. As patterned,
The display device according to claim 7. Some of the plurality of lead lines extend in an oblique direction with respect to a direction in which the plurality of signal lines electrically connected to the drive circuit extend.
The display device according to claim 7. The width of the lead line is thicker as the length of the lead line is shorter, and the width of the lead line is thinner as the length of the lead line is longer.
The display device according to claim 7. The width of the lead line connected to the center side of the drive circuit is thicker than the width of the lead line connected to both ends of the drive circuit,
The display device according to claim 7.

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