JP2016219589A - Solid-state imaging device - Google Patents

Abstract

A solid-state imaging device capable of improving sensitivity while suppressing color mixing is provided. A red pixel R1 is arranged so as to overlap in a depth direction over one pixel of a green pixel G, and a blue pixel B1 is overlapped in a depth direction over one pixel of a green pixel G. The reset component SigGt of the green pixel G is stored in the frame memory 41, and the subtractor 43 subtracts the reset component SigGt from the signal component SigGs of the green pixel G, thereby causing CDS of the green pixel G to be performed. [Selection] Figure 11

Description

  Embodiments described herein relate generally to a solid-state imaging device.

  In recent years, a camera module mounted on a mobile phone or the like is required to be thin and have high resolution. In response to the reduction in the thickness and the resolution of the camera module, the image sensor has been miniaturized. In the image sensor, as the pixel area becomes smaller, the amount of light incident on the pixel decreases, so that the signal amount decreases and the signal-to-noise ratio (SNR) deteriorates. For this reason, the image sensor is desired to achieve high sensitivity by improving light utilization efficiency.

JP-T-2002-513145 JP 2006-120773 A JP 2006-278446 A JP 2012-238648 A

  An object of one embodiment of the present invention is to provide a solid-state imaging device capable of improving sensitivity while suppressing color mixing.

  According to one embodiment of the present invention, it comprises pixels partitioned along a grid set at 45 ° with respect to the column direction. The pixel includes a green pixel, a red pixel arranged to overlap the green pixel in the depth direction, and a blue pixel arranged to overlap the green pixel in the depth direction.

FIG. 1A is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment, and FIG. 1B illustrates an example of the layout of the photoelectric conversion layer of the solid-state imaging device in FIG. A perspective view and FIG.1 (c) are perspective views which show the other example of the layout of the photoelectric converting layer of the solid-state imaging device of Fig.1 (a). FIG. 2A is a plan view illustrating a layout example of green pixels of the solid-state imaging device according to the first embodiment, and FIG. 2B is a plan view of red pixels and blue pixels of the solid-state imaging device according to the first embodiment. FIG. 2C is a plan view showing a layout example of the microlenses of the solid-state imaging device according to the first embodiment. FIG. 3 is a circuit diagram showing a two-pixel one-cell configuration in the red pixel and the blue pixel in FIG. FIG. 4 is a circuit diagram showing a 2-pixel 1-cell configuration in the green pixel of FIG. FIG. 5 is a plan view illustrating a layout example for four pixels of the solid-state imaging device according to the first embodiment. FIG. 6 is a cross-sectional view illustrating an example of a schematic configuration of the solid-state imaging device cut along AA ′ in FIG. 5. FIG. 7 is a cross-sectional view illustrating another example of the schematic configuration of the solid-state imaging device cut along the line AA ′ in FIG. 5. FIG. 8A is a plan view illustrating a layout example of green pixels of the solid-state imaging device according to the second embodiment, and FIG. 8B is a diagram illustrating red pixels and blue pixels of the solid-state imaging device according to the second embodiment. FIG. 8C is a plan view showing a layout example of microlenses of the solid-state imaging device according to the second embodiment. FIG. 9 is a plan view illustrating a layout example for six pixels of the solid-state imaging device according to the second embodiment. FIG. 10 is a cross-sectional view illustrating an example of a schematic configuration of the solid-state imaging device cut along AA ′ in FIG. 9. FIG. 11A is a block diagram showing a schematic configuration of the solid-state imaging device according to the third embodiment, and FIG. 11B shows an example of the layout of the photoelectric conversion layer of the solid-state imaging device of FIG. A perspective view and FIG.11 (c) are perspective views which show the other example of the layout of the photoelectric converting layer of the solid-state imaging device of Fig.11 (a). FIG. 12A is a timing chart showing the read operation of the red and blue pixels of the solid-state imaging device according to the third embodiment, and FIG. 12B is the green pixel of the solid-state imaging device according to the third embodiment. It is a timing chart which shows read-out operation. FIG. 13A is a block diagram showing a schematic configuration of the solid-state imaging device according to the fourth embodiment, and FIG. 13B shows an example of the layout of the photoelectric conversion layer of the solid-state imaging device of FIG. A perspective view and FIG.13 (c) are perspective views which show the other example of the layout of the photoelectric converting layer of the solid-state imaging device of Fig.13 (a). FIG. 14A is a timing chart showing the read operation of the red and blue pixels of the solid-state imaging device according to the fourth embodiment, and FIG. 14B is the green pixel of the solid-state imaging device according to the fourth embodiment. It is a timing chart which shows read-out operation. FIG. 15 is a timing chart showing a green pixel readout operation of the solid-state imaging device according to the fifth embodiment. FIG. 16 is a circuit diagram showing a one-cell one-cell configuration in red and blue pixels according to the sixth embodiment. FIG. 17A is a block diagram showing a schematic configuration of the solid-state imaging device according to the seventh embodiment, and FIG. 17B shows an example of the layout of the photoelectric conversion layer of the solid-state imaging device of FIG. A perspective view and FIG.17 (c) are perspective views which show the other example of the layout of the photoelectric converting layer of the solid-state imaging device of Fig.17 (a). FIG. 18 is a block diagram illustrating a schematic configuration of a digital camera to which the solid-state imaging device according to the eighth embodiment is applied. FIG. 19 is a cross-sectional view illustrating a schematic configuration of a camera module to which the solid-state imaging device according to the ninth embodiment is applied.

  Hereinafter, a solid-state imaging device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1A is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment, and FIG. 1B illustrates an example of the layout of the photoelectric conversion layer of the solid-state imaging device in FIG. A perspective view and FIG.1 (c) are perspective views which show the other example of the layout of the photoelectric converting layer of the solid-state imaging device of Fig.1 (a).
1A, in the solid-state imaging device, a pixel array 1 in which pixels PC for storing photoelectrically converted charges are arranged in a matrix in a row direction RD and a column direction CD, and a pixel PC to be read out are vertically arranged. Vertical scanning circuit 2 that scans in the direction, column ADC circuit 3 that detects and converts the signal component of each pixel PC by CDS, horizontal scanning circuit 4 that scans pixel PC to be read in the horizontal direction, and each pixel PC Are provided with a timing control circuit 5 for controlling the timing of reading and storage of data and a reference voltage generating circuit 6 for outputting a reference voltage VREF to the column ADC circuit 3. Note that a master clock MCK is input to the timing control circuit 5.

Here, the pixel PC is partitioned along a grid GU set obliquely with respect to the column direction CD. The inclination of the grid GU with respect to the column direction CD can be set to 45 degrees. At this time, the pixels PC can be two-dimensionally arranged with a shift of ½ pixel for each line. When the pixel PC is colored, as shown in FIG. 1B, a green pixel G, a red pixel R1, and a blue pixel B1 can be provided as the pixel PC. The red pixel R1 can be disposed so as to overlap in the depth direction over one pixel of the green pixel G. The blue pixel B1 can be arranged so as to overlap in the depth direction over one pixel of the green pixel G. The red pixels R1 and the blue pixels B1 can be alternately arranged in a checkered pattern in the same plane. In addition, as a material of the green pixel G, an inorganic material or an organic material mainly sensitive to green can be used. As an organic photoelectric material that absorbs green light and is transparent to red light and blue light, a perylene compound, a quinacridone compound, rhodamine 6G, or the like can be used. In order to collect charges photoelectrically converted by the green pixel G, transparent electrodes can be provided above and below the green pixel G. The organic photoelectric film can be formed by vacuum deposition, and the transparent electrode can be formed by sputtering. As a material of the red pixel R1 and the blue pixel B1, a semiconductor such as Si can be used.
When the pixel PC is colorized, a green pixel G, a red pixel R2, and a blue pixel B2 may be provided as the pixel PC in addition to the configuration of FIG. 1B, as shown in FIG. The red pixel R2 can be arranged so as to overlap in the depth direction over the two pixels of the green pixel G. The blue pixel B2 can be arranged so as to overlap in the depth direction over the two pixels of the green pixel G. The blue pixel B1 can be arranged on the red pixel R1 so as to overlap in the depth direction. The longitudinal direction of the red pixel R2 and the blue pixel B2 can coincide with the direction of the grid GU.

  In the pixel array unit 1, a horizontal control line Hlin for performing readout control of the pixel PC is provided in the row direction RD. In the column direction CD, a vertical signal line VlinG for transmitting a signal read from the green pixel G is provided, and a signal read from the red pixel R1 and the blue pixel B1 or the red pixel R2 and the blue pixel B2 is provided. Is provided with a vertical signal line VlinBR. At this time, the column ADC circuit 3 includes an AD converter ADCg that AD converts a signal transmitted via the vertical signal line VlinG and an AD converter ADCbr that AD converts a signal transmitted via the vertical signal line VlinBR. It can be provided for each column.

The pixel PC is scanned in the vertical direction by the vertical scanning circuit 2 so that the pixel PC in the row direction RD is selected, and the signal read from the pixel PC is columned via the vertical signal lines VlinG and VlinBR. It is sent to the ADC circuit 3. Then, by taking a difference between the signal level of the pixel signal read from the pixel PC and the reset level, the signal component of each pixel PC is detected for each column by CDS (Correlated Double Sampling), and is output as the output signal Vout1. Is output.
Here, by interpolating the signal between the pixels PC based on the pixel signal obtained from the green pixel G by two-dimensionally arranging the pixels PC with a shift of 1/2 pixel for each line, the horizontal and vertical directions are 0. Pixel signals can be generated at a pitch of 5 pixels, and the resolution can be improved.
Further, as shown in FIG. 1B, by arranging the green pixel G so as to overlap the red pixel R1 and the blue pixel B1 in the depth direction, it is possible to reduce color mixing and The green pixel size can be doubled with respect to the Bayer array structure. As a result, the sensitivity can be improved by a factor of two by obtaining twice the amount of incident light.
Further, as shown in FIG. 1C, the red pixel R2 and the blue pixel B2 are arranged so as to overlap each other over two pixels, so that the red and blue sensitivities can be obtained with respect to the single-layer Bayer arrangement structure. Can be improved four times.
In this configuration, the green pixels G are arranged for each column, and the red pixels R1 and the blue pixels B1 are alternately arranged for each column. At this time, when the pixel signal is read, the vertical signal line VlinG is assigned to the green pixel G for each column, and the vertical signal line VlinBR is alternately assigned to the red pixel R1 and the blue pixel B1 for each column. Can do. For this reason, pixel signals can be simultaneously read from the green pixel G, red pixel R1, and blue pixel B1 for each line, and pixel signals are read from the green pixel G, red pixel R1, and blue pixel B1 in time series for each line. The operation speed can be improved compared to the case. The same applies to the combination of the green pixel G, red pixel R2, and blue pixel B2.

FIG. 2A is a plan view illustrating a layout example of green pixels of the solid-state imaging device according to the first embodiment, and FIG. 2B is a plan view of red pixels and blue pixels of the solid-state imaging device according to the first embodiment. FIG. 2C is a plan view showing a layout example of the microlenses of the solid-state imaging device according to the first embodiment.
In FIG. 2A, green pixels Gr and Gb are provided as green pixels G. At this time, the green pixel G can cover the entire pixel array unit 1. The green pixels Gr and Gb can be alternately arranged in a checkered pattern in the same plane.
In FIG. 2B, the blue pixel B1 and the red pixel R1 are arranged so as to overlap the green pixel G in the depth direction. The red pixels R1 and the blue pixels B1 can be alternately arranged in a checkered pattern in the same plane.
In FIG. 2C, each pixel PC can be provided with a microlens Z1. The micro lens Z1 can be disposed on the green pixel G. In order to increase the light collection efficiency, it is preferable that the center of each microlens Z1 coincides with the center of each pixel PC. Note that the microlens Z1 may not be provided.

FIG. 3 is a circuit diagram showing a two-pixel one-cell configuration (shared output circuit) in the red and blue pixels of FIG.
In FIG. 3, this cell is provided with photodiodes PD-B and PD-R, a row selection transistor TRadrBR, an amplification transistor TRampBR, a reset transistor TRrstBR, and read transistors TGb and TGr. The photodiode PD-B can be provided in the blue pixel B1. The photodiode PD-R can be provided in the red pixel R1. In addition, a floating diffusion FD is formed as a detection node at a connection point between the amplification transistor TRampBR, the reset transistor TRrstBR, and the read transistors TGb and TGr. Here, the floating diffusion FD, the row selection transistor TRadBR, the amplification transistor TRampBR, and the reset transistor TRrstBR are shared as output circuits of the photodiodes PD-B and PD-R.

  The source of the read transistor TGr is connected to the photodiode PD-R, and the source of the read transistor TGb is connected to the photodiode PD-B. The source of the reset transistor TRrstBR is connected to the drains of the read transistors TGb and TGr, and the drains of the reset transistor TRrstBR and the row selection transistor TRadrBR are connected to the power supply potential VDD. The source of the amplification transistor TRampBR is connected to the vertical signal line VlinBR, the gate of the amplification transistor TRampBR is connected to the drains of the read transistors TGb and TGr, and the drain of the amplification transistor TRampBR is connected to the source of the row selection transistor TRadBRBR. Has been. The vertical signal line VlinBR is grounded via the bias transistor VBi ′ and is connected to the column ADC circuit 3.

FIG. 4 is a circuit diagram showing a one-pixel one-cell configuration (the output circuit is independent) in the green pixel of FIG.
In FIG. 4, this cell is provided with photoelectric conversion elements OPD-Gr, OPD-Gb, storage diodes SD-Gr, SD-Gb, row selection transistors TRadrGr, TRadrGb, amplification transistors TRampGr, TRampGb, and reset transistors TRrstGr, TRrstGb. It has been. Note that the photoelectric conversion element OPD-Gr can be provided in the green pixel Gr. The photoelectric conversion element OPD-Gb can be provided in the green pixel Gb.

The source of the reset transistor TRrstGr is connected to the gate of the amplification transistor TRampGr and the cathode of the storage diode SD-Gr, and the drain of the reset transistor TRrstGr is connected to the power supply potential Vsd. The drain of the amplification transistor TRampGr is connected to the power supply potential VDD, and the source of the amplification transistor TRampGr is connected to the vertical signal line VlinG via the row selection transistor TRadrGr. The source of the reset transistor TRrstGb is connected to the gate of the amplification transistor TRampGb and the cathode of the storage diode SD-Gb, and the drain of the reset transistor TRrstGb is connected to the power supply potential Vsd. The drain of the amplification transistor TRampGb is connected to the power supply potential VDD, and the source of the amplification transistor TRampGb is connected to the vertical signal line VlinG via the row selection transistor TRadrGb. A bias voltage VB is applied to the photoelectric conversion elements OPD-Gr and OPD-Gb. The vertical signal line VlinG is grounded via the bias transistor VBi and is connected to the column ADC circuit 3.
Here, by directly connecting the photoelectric conversion elements OPD-Gr and OPD-Gb to the gates of the amplification transistors TRampGr, kTC noise is reduced when signals are read from the photoelectric conversion elements OPD-Gr and OPD-Gb. be able to.

FIG. 5 is a plan view illustrating a layout example for four pixels of the solid-state imaging device according to the first embodiment. This layout can be used for the green pixel G, red pixel R1, and blue pixel B1 in FIG.
In FIG. 5, the blue pixel B1 is provided with a photodiode PD-B1, and the red pixel R1 is provided with a photodiode PD-R1. The side of the photodiode PD-B1 is disposed adjacent to the side of the photodiode PD-R1. A floating diffusion FD is disposed between the apexes of the four photodiodes PD-B1 and PD-R1 adjacent to each other. The floating diffusion FD is shared by the photodiodes PD-B1 and PD-R1. At this time, the floating diffusion FD can be arranged every other column. That is, the vertex of the photodiode PD-B1 can be arranged at a position adjacent to the column direction CD, and the vertex of the photodiode PD-R1 can be prevented from being arranged at a position adjacent to the column direction CD. A read transistor TGb is disposed between the photodiode PD-B1 and the floating diffusion FD, and a read transistor TGr is disposed between the photodiode PD-R1 and the floating diffusion FD.
Further, between the sides of the photodiodes PD-B1 and PD-R1, the reset transistor TRrstBR, the amplification transistor TRampBR, and the row selection transistor TRadBRBR are sequentially arranged along a direction inclined by 45 degrees with respect to the column direction CD. .
Further, between the sides of the photodiodes PD-B1 and PD-R1, the storage diode SD-Gr, the reset transistor TRrstGr, the amplification transistor TRampGr, and the row selection transistor TradrGr are inclined by −45 degrees with respect to the column direction CD. Are arranged sequentially. A contact CT-Gr that connects the photoelectric conversion element OPD-Gr to the storage diode SD-Gr is disposed adjacent to the storage diode SD-Gr.
Further, between the sides of the photodiodes PD-B1 and PD-R1, the storage diode SD-Gb, the reset transistor TRrstGb, the amplification transistor TRampGb, and the row selection transistor TradrGb are inclined by −45 degrees with respect to the column direction CD. Are arranged sequentially. A contact CT-Gb connecting the photoelectric conversion element OPD-Gb to the storage diode SD-Gb is disposed adjacent to the storage diode SD-Gb.

  Vertical signal lines VlinBR and VlinG are provided as the vertical signal lines Vlin. The vertical signal line VlinBR is connected to the source of the amplification transistor TRampBR. The vertical signal line VlinG is connected to the sources of the row selection transistors TRadrGr and TRadrGb. Horizontal control lines SGr, SGb, SrstBR, SadrBR, SrstGr, SadrGr, SrstGb, and SadrGb are provided as the horizontal control lines Hlin. The horizontal control line SGr is connected to the gate of the amplification transistor TRampGr. The horizontal control line SGb is connected to the gate of the amplification transistor TRampGb. The horizontal control line SrstBR is connected to the gate of the reset transistor TRrstBR. The horizontal control line SadrBR is connected to the gate of the row selection transistor TRadrBR. The horizontal control line SrstGr is connected to the gate of the reset transistor TRrstGr. The horizontal control line SadrGr is connected to the gate of the row selection transistor TRadrGr. The horizontal control line SrstGb is connected to the gate of the reset transistor TRrstGb. The horizontal control line SadrGb is connected to the gate of the row selection transistor TRadrGb.

  Here, the reset transistor TRrstBR, the amplification transistor TRampBR, and the row selection transistor TRadBRBR are sequentially arranged along a direction inclined by 45 degrees with respect to the column direction CD, and the storage diodes SD-Gb, SD-Gr, the reset transistor TRrstGb, By sequentially arranging TRrstGr, amplification transistors TRampGb, TRampGr, and row selection transistors TRradGb, TRadrGr along the direction inclined by −45 degrees with respect to the column direction CD, the photoelectric conversion elements OPD-Gr, OPD-Gb, and photo The layout area of the output circuit of the diodes PD-B1 and PD-R1 can be reduced.

FIG. 6 is a cross-sectional view illustrating an example of a schematic configuration of the solid-state imaging device cut along AA ′ in FIG. 5. In the example of FIG. 6, a back-illuminated CMOS sensor is shown.
In FIG. 6, an impurity diffusion layer H2 is formed in the semiconductor layer SB1, and a gate insulating film H0 is formed on the surface side of the impurity diffusion layer H2. An impurity diffusion layer H1 is formed on the back side of the impurity diffusion layer H2. The semiconductor layer SB1 may be a semiconductor substrate. In the photodiode PD-B1, the impurity diffusion layer H3 is formed over one pixel in the semiconductor layer SB1, and the impurity diffusion layer H5 is formed on the surface side of the impurity diffusion layer H3. In the photodiode PD-R1, the impurity diffusion layer H4 is formed over one pixel in the semiconductor layer SB1, and the impurity diffusion layer H6 is formed on the surface side of the impurity diffusion layer H4.
In the storage diode SD-Gb, an impurity diffusion layer H8 is formed in the semiconductor layer SB1. In the storage diode SD-Gr, an impurity diffusion layer H9 is formed in the semiconductor layer SB1. In the floating diffusion FD, an impurity diffusion layer H7 is formed in the semiconductor layer SB1. The impurity diffusion layers H1, H5, and H6 can be set to p ⁺ type. The impurity diffusion layer H2 can be set to p-type. The impurity diffusion layers H3 and H4 can be set to n-type. The impurity diffusion layers H7 to H9 can be set to n ⁺ type.

  Further, on the surface side of the semiconductor layer SB1, a gate electrode G1 is disposed on the impurity diffusion layer H2 between the impurity diffusion layers H5 and H7, and on the impurity diffusion layer H2 between the impurity diffusion layers H6 and H7. Is arranged. The gate electrodes G1 and G2 can be used for the read transistors TGb and TGr. Further, wirings P1 and P2 connected to the impurity diffusion layers H8 and H9, respectively, are arranged on the surface side of the semiconductor layer SB1. An interlayer insulating film E1 is formed on the back side of the semiconductor layer SB1, and a blue filter Fb and a red filter Fr are embedded in the interlayer insulating film E1. The blue filter Fb is disposed on the photodiode PD-B1, and the red filter Fr is disposed on the photodiode PD-R1. A green photoelectric conversion film G is provided on the interlayer insulating film E1 so as to cover the entire back surface of the semiconductor layer SB1. Transparent electrodes D1 and D2 are provided on the lower surface of the green photoelectric conversion film G for each of the green pixels Gb and Gr, and a transparent electrode D3 is provided on the lower surface of the green photoelectric conversion film G. An interlayer insulating film E2 is formed on the transparent electrode D3, and a micro lens Z1 is disposed for each pixel PC on the interlayer insulating film E2. Contact electrodes CT-Gb and CT-Gr are embedded in the interlayer insulating film E1. The contact electrode CT-Gb connects the impurity diffusion layer H8 and the transparent electrode D1. The contact electrode CT-Gr connects the impurity diffusion layer H9 and the transparent electrode D2.

FIG. 7 is a cross-sectional view illustrating another example of the schematic configuration of the solid-state imaging device cut along the line AA ′ in FIG. 5. In the example of FIG. 7, a back-illuminated CMOS sensor is shown.
In the configuration of FIG. 6, the case where the microlens Z1 is on the green photoelectric conversion film G is shown, but in the configuration of FIG. 7, the microlens Z1 is disposed below the green photoelectric conversion film G. That is, the microlens Z1 is disposed on the blue filter Fb and the red filter Fr, and the interlayer insulating film E3 is formed on the microlens Z1. The interlayer insulating film E3 can planarize the surface on the microlens Z1. A green photoelectric conversion film G is provided on the interlayer insulating film E3 so as to cover the entire back surface of the semiconductor layer SB1. Transparent electrodes D1 and D2 are provided on the lower surface of the green photoelectric conversion film G for each of the green pixels Gb and Gr, and a transparent electrode D3 is provided on the lower surface of the green photoelectric conversion film G.

(Second Embodiment)
FIG. 8A is a plan view illustrating a layout example of green pixels of the solid-state imaging device according to the second embodiment, and FIG. 8B is a diagram illustrating red pixels and blue pixels of the solid-state imaging device according to the second embodiment. FIG. 8C is a plan view showing a layout example of microlenses of the solid-state imaging device according to the second embodiment.
In FIG. 8A, green pixels Gr and Gb are provided as green pixels G. At this time, the green pixel G can cover the entire pixel array unit 1. The green pixels Gr and Gb can be alternately arranged in a checkered pattern in the same plane.
In FIG. 8B, the blue pixel B2 and the red pixel R2 are arranged so as to overlap the green pixel G in the depth direction over two pixels. The blue pixel B2 is disposed on the red pixel R2 so as to overlap in the depth direction.
In FIG. 8C, each pixel PC can be provided with a microlens Z2. The micro lens Z2 can be disposed on the green pixel G. In order to increase the light collection efficiency, it is preferable that the center of each microlens Z2 coincides with the center of each pixel PC. Note that the microlens Z2 may not be provided.

FIG. 9 is a plan view illustrating a layout example for six pixels of the solid-state imaging device according to the second embodiment. This layout can be used for the green pixel G, the red pixel R2, and the blue pixel B2 in FIG.
In FIG. 9, the blue pixel B2 is provided with a photodiode PD-B2, and the red pixel R2 is provided with a photodiode PD-R2. Each photodiode PD-B2 and PD-R2 is continuously arranged over two pixels. The photodiode PD-B2 is disposed so as to overlap the photodiode PD-R2 in the depth direction. At this time, the longitudinal direction of the photodiodes PD-B2 and PD-R2 can coincide with the direction of the grid GU.

The reset transistors TRrstBR, TRrstGb, TRrstGr, the amplification transistors TRampBR, TRampGb, TRampGr, the row selection transistors TRradBR, TRadrGb, TRradGr, and the storage diodes SD-Gb, SD-Gr can be arranged in the same manner as in FIG. The vertical signal lines VlinBR and VlinG and the horizontal control lines SGr, SGb, SrstBR, SadrBR, SrstGr, SadrGr, SrstGb, and SadrGb can also be arranged similarly to the configuration of FIG.
Here, by making the longitudinal direction of the photodiodes PD-B2 and PD-R2 coincide with the direction of the grid GU, the photodiode PD- is also formed in the empty region between the sides of the photodiodes PD-B1 and PD-R1 in FIG. B2 and PD-R2 can be arranged, and the output circuits of the photoelectric conversion elements OPD-Gr and OPD-Gb and the photodiodes PD-B2 and PD-R2 are arranged around the photodiodes PD-B2 and PD-R2. Can be arranged without any gaps, and the layout area can be reduced.

FIG. 10 is a cross-sectional view illustrating an example of a schematic configuration of the solid-state imaging device cut along AA ′ in FIG. 9. In the example of FIG. 10, a back-illuminated CMOS sensor is shown.
In FIG. 10, an impurity diffusion layer H12 is formed in the semiconductor layer SB2, and a gate insulating film H10 is formed on the surface side of the impurity diffusion layer H12. An impurity diffusion layer H11 is formed on the back side of the impurity diffusion layer H12. The semiconductor layer SB2 may be a semiconductor substrate. Further, in the photodiode PD-B2, an impurity diffusion layer H13 is formed over two pixels on the back surface side of the semiconductor layer SB2, and a part of the impurity diffusion layer H13 is drawn to the surface side of the semiconductor layer SB2. . In the photodiode PD-R2, the impurity diffusion layer H14 is formed on the surface side of the semiconductor layer SB2 so as to overlap the impurity diffusion layer H13 in the depth direction, and the impurity diffusion layer H15 is formed on the surface side of the impurity diffusion layer H14. Is formed.
In the storage diode SD-Gb, an impurity diffusion layer H18 is formed in the semiconductor layer SB2. In the storage diode SD-Gr, an impurity diffusion layer H19 is formed in the semiconductor layer SB2. In the floating diffusion FD, an impurity diffusion layer H17 is formed in the semiconductor layer SB2. The impurity diffusion layers H11 and H15 can be set to p ⁺ type. The impurity diffusion layer H12 can be set to p-type. The impurity diffusion layers H13 and H14 can be set to n-type. The impurity diffusion layers H17 to H19 can be set to n ⁺ type.

  Further, on the surface side of the semiconductor layer SB2, a gate electrode G11 is disposed on the impurity diffusion layer H12 between the impurity diffusion layers H15 and H17, and on the impurity diffusion layer H12 between the impurity diffusion layers H13 and H17. Is arranged. The gate electrodes G11 and G12 can be used for the read transistors TGb and TGr. Further, wirings P11 and P12 connected to the impurity diffusion layers H18 and H19, respectively, are arranged on the surface side of the semiconductor layer SB2. An interlayer insulating film E4 is formed on the back side of the semiconductor layer SB2. On the interlayer insulating film E4, a green photoelectric conversion film G is provided so as to cover the entire back surface of the semiconductor layer SB2. Transparent electrodes D1 and D2 are provided on the lower surface of the green photoelectric conversion film G for each of the green pixels Gb and Gr, and a transparent electrode D3 is provided on the lower surface of the green photoelectric conversion film G. An interlayer insulating film E5 is formed on the transparent electrode D3, and a micro lens Z2 is disposed for each pixel PC on the interlayer insulating film E5. Contact electrodes CT-Gb and CT-Gr are embedded in the interlayer insulating film E4. The contact electrode CT-Gb connects the impurity diffusion layer H18 and the transparent electrode D1. The contact electrode CT-Gr connects the impurity diffusion layer H19 and the transparent electrode D2.

(Third embodiment)
FIG. 11A is a block diagram showing a schematic configuration of the solid-state imaging device according to the third embodiment, and FIG. 11B shows an example of the layout of the photoelectric conversion layer of the solid-state imaging device of FIG. A perspective view and FIG.11 (c) are perspective views which show the other example of the layout of the photoelectric converting layer of the solid-state imaging device of Fig.11 (a).
In the solid-state imaging device of FIG. 11A, a frame memory 41, a demultiplexer 42, a subtractor 43, and a multiplexer 44 are added to the configuration of FIG.
Each pixel PC in the pixel array unit 1 is sequentially driven line by line by a horizontal control line Hlin arranged in the vertical direction by a vertical scanning circuit 2 that operates in synchronization with a horizontal synchronization signal HD generated by the timing control circuit 5.
The green pixel G first resets an extra pixel signal accumulated in the green pixel G. Then, after the reset component SigGt of the storage diode SD-Gr or SD-Gb of the reset green pixel G is read, the reset component SigGt is stored in the frame memory 41. Then, the accumulation operation for the green pixel G is started. When the column ADC circuit 3 reads out the pixel signal after the accumulation operation from the green pixel G, the signal component SigGs of the green pixel G is generated.
The blue pixel B1 or the blue pixel B2 first resets the pixel B1 or B2. Then, the accumulation operation for the blue pixel B1 or the blue pixel B2 is started. When the pixel signal accumulated from the blue pixel B1 or the blue pixel B2 is read out at the end of the accumulation operation, the column ADC circuit 3 detects the reset level of the floating diffusion FD unit that is the detection node of the pixel unit PC and the floating diffusion FD unit. The blue signal SigB is generated by taking the difference from the pixel signal level.
Similarly, when a pixel signal is read from the red pixel R1 or the red pixel R2, in the column ADC circuit 3, the pixel signal level detected by the floating diffusion FD portion of the pixel portion PC and the reset level of the floating diffusion FD portion that is a detection node are detected. As a result, the red signal SigR is generated. The signal component SigGs, the blue signal SigB, and the red signal SigR of the green pixel G are output from the column ADC circuit 3 to the demultiplexer 42. In the demultiplexer 42, the signal component SigGs of the green pixel G is separated from the blue signal SigB and the red signal SigR and output to the subtractor 43. At this time, the reset component SigGt of the green pixel G is read from the frame memory 41 and output to the subtractor 43. Then, the subtracter 43 subtracts the reset component SigGt from the signal component SigGs of the green pixel G to generate a green signal SigG and outputs it to the multiplexer 44. Then, in the multiplexer 44, the green signal SigG, the blue signal SigB, and the red signal SigR are integrated to generate the output signal Vout2.

  Here, the reset component SigGt of the green pixel G is stored in the frame memory 41, and the reset component SigGt is subtracted from the signal component SigGs of the green pixel G by the subtractor 43, whereby CDS of the green pixel G can be performed. . Therefore, as shown in FIG. 4, even when there is no readout transistor for the green pixel G, it is possible to reduce the threshold variation for each column of the amplification transistors TRampGr and TRampGb, and the reset transistors TRrstGr and TGrstGb. KTC noise generated by the reset operation can be reduced.

FIG. 12A is a timing chart showing the read operation of the red and blue pixels of the solid-state imaging device according to the third embodiment, and FIG. 12B is the green pixel of the solid-state imaging device according to the third embodiment. It is a timing chart which shows read-out operation. Note that in FIG. 12A and FIG. 12B, a reset line where charge accumulation is started and a read line where reading is performed are shown separately. As for the reset signal for the CDS operation, in the red pixel and the blue pixel, the reset signal and the readout line of the accumulated pixel signal are the same line. In the green pixel, the reset signal and the accumulated pixel signal readout line are not the same line. Further, FIG. 12B shows the green pixel Gr, but the same applies to the green pixel Gb. HD is a horizontal synchronization signal.
In the reset line of FIG. 12A, when the row selection transistor TRadrBR is off, the amplification transistor TRampBR does not operate as a source follower, so that no signal is output to the vertical signal line VlinBR. At this time, when the reset transistor TRrstBR is off, the read transistors TGb and TGr are turned on, so that the charges accumulated in the photodiodes PD-B and PD-R are discharged to the floating diffusion FD. When the reset transistor TRrstBR is turned on, the charge of the floating diffusion FD is discharged to the power supply potential VDD.

  After the charges accumulated in the photodiodes PD-B and PD-R are discharged to the floating diffusion FD, when the read transistors TGb and TGr are turned off, the photodiodes PD-B and PD-R have effective signal charges. Accumulation starts.

  Next, in the readout line of FIG. 12A, excess charge generated due to leakage current or the like in the floating diffusion FD is reset when the reset transistor TRrstBR is on.

  When the row selection transistor TRadrBR is turned on, the power supply potential VDD is applied to the drain of the amplification transistor TRampBR, so that the amplification transistor TRampBR and the constant current source constitute a source follower. At this time, the bias transistor VBi ′ can operate as a constant current source. A voltage corresponding to the reset components SigBr and SigRr of the floating diffusion FD is applied to the gate of the amplification transistor TRampBR. Here, since the source follower is configured by the amplification transistor TRampBR and the constant current source, the voltage of the vertical signal line VlinBR follows the voltage applied to the gate of the amplification transistor TRampBR, and the pixels of the reset components SigBr and SigRr. The signal is output to the column ADC circuit 3 through the vertical signal line VlinBR.

  At this time, a ramp wave is given as the reference voltage VREF, and the pixel signals of the reset components SigBr and SigRr are compared with the reference voltage VREF. The pixel signals of the reset components SigBr and SigRr are down-counted until they match the level of the reference voltage VREF, whereby the pixel signals of the reset components SigBr and SigRr are converted into digital values and held in the column ADC circuit 3. The

Next, when the reset transistor TRrstBR is off, the read transistors TGb and TGr are turned on, so that the charges accumulated in the photodiodes PD-B and PD-R are transferred to the floating diffusion FD, and the signal of the floating diffusion FD A voltage corresponding to the components SigBs and SigRs is applied to the gate of the amplification transistor TRampBR. Here, since the amplification transistor TRampBR and the constant current source constitute a source follower, the voltage of the vertical signal line VlinBR follows the voltage applied to the gate of the amplification transistor TRampBR, and the pixels of the signal components SigBs and SigRs. The signal is output to the column ADC circuit 3 through the vertical signal line VlinBR.
At this time, a ramp wave is given as the reference voltage VREF, and the pixel signals of the signal components SigBs and SigRs are compared with the reference voltage VREF. Then, the pixel signals of the signal components SigBs and SigRs are up-counted until the pixel signals of the signal components SigBs and SigRs coincide with the level of the reference voltage VREF, thereby converting the pixel signals of the signal components SigBs and SigRs into digital values. The difference between the pixel signals of the reset components SigBr and SigRr and the pixel signals of the signal components SigBs and SigRs is held and output as a blue signal SigB and a red signal SigR.

On the other hand, in the reset line of FIG. 12B, the charge photoelectrically converted by the photoelectric conversion element OPD-Gr is stored in the storage diode SD-Gr. At this time, excess charge generated due to a leakage current or the like in the storage diode SD-Gr is reset when the reset transistor TRrstGr is on.
When the row selection transistor TRadrGr is turned on, the power supply potential VDD is applied to the drain of the amplification transistor TRampGr, so that the amplification transistor TRampGr and the constant current source constitute a source follower. At this time, the bias transistor VBi can operate as a constant current source. A voltage corresponding to the reset component SigGt of the storage diode SD-Gr is applied to the gate of the amplification transistor TRampGr. Here, since the source follower is configured by the amplification transistor TRampGr and the constant current source, the voltage of the vertical signal line VlinG follows the voltage applied to the gate of the amplification transistor TRampGr, and the pixel signal of the reset component SigGt is vertical. The signal is output to the column ADC circuit 3 through the signal line VlinG.

  At this time, a ramp wave is applied as the reference voltage VREF, and the pixel signal of the reset component SigGt is compared with the reference voltage VREF. The pixel signal of the reset component SigGt is up-counted until it matches the level of the reference voltage VREF, whereby the pixel signal of the reset component SigGt is converted into a digital value and held in the frame memory 41.

  When the reset transistor TRrstGr is turned off after the charge of the storage diode SD-Gr is reset, the storage diode SD-Gr starts to accumulate effective signal charge.

  Next, in the readout line of FIG. 12B, when the row selection transistor TRadrGr is turned on, the power supply potential VDD is applied to the drain of the amplification transistor TRampGr, thereby forming a source follower with the amplification transistor TRampGr and the constant current source. Is done. At this time, the bias transistor VBi can operate as a constant current source. A voltage corresponding to the signal component SigGs of the storage diode SD-Gr is applied to the gate of the amplification transistor TRampGr. Here, since the amplification transistor TRampGr and the constant current source constitute a source follower, the voltage of the vertical signal line VlinG follows the voltage applied to the gate of the amplification transistor TRampGr, and the pixel signal of the signal component SigGs is vertical. The signal is output to the column ADC circuit 3 through the signal line VlinG.

At this time, a ramp wave is applied as the reference voltage VREF, and the pixel signal of the signal component SigGs is compared with the reference voltage VREF. The pixel signal of the signal component SigGs is up-counted until it matches the level of the reference voltage VREF, whereby the pixel signal of the signal component SigGs is converted into a digital value and input to the subtractor 43. At this time, the digital value of the reset component SigGt is read from the frame memory 41 and input to the subtractor 43. Then, the subtractor 43 subtracts the digital value of the reset component SigGt from the digital value of the signal component SigGs to generate a green signal SigG.
Here, the reset line of the storage diode SD portion of the green pixel and the readout line for reading out the stored pixel signal are changed to the same line by switching within the horizontal synchronization signal HD period, and the horizontal synchronization signal between the green pixel, the red pixel and the blue pixel. By matching the timing of the CDS process within the HD period, the CDS process can be speeded up.

(Fourth embodiment)
FIG. 13A is a block diagram showing a schematic configuration of the solid-state imaging device according to the fourth embodiment, and FIG. 13B shows an example of the layout of the photoelectric conversion layer of the solid-state imaging device of FIG. A perspective view and FIG.13 (c) are perspective views which show the other example of the layout of the photoelectric converting layer of the solid-state imaging device of Fig.13 (a).
In the solid-state imaging device of FIG. 13A, column ADC circuits 3A, 3B, horizontal scanning circuits 4A, 4B, and reference instead of the column ADC circuit 3, horizontal scanning circuit 4, and reference voltage generating circuit 6 of FIG. Voltage generation circuits 6A and 6B are provided. The column ADC circuit 3, the horizontal scanning circuit 4, and the reference voltage generation circuit 6 are shared by the green pixel, the red pixel, and the blue pixel. On the other hand, the column ADC circuit 3A, the horizontal scanning circuit 4A, and the reference voltage generating circuit 6A are assigned to the red pixel and the blue pixel, and the column ADC circuit 3B, the horizontal scanning circuit 4B, and the reference voltage generating circuit 6B are assigned to the green pixel. It is done. The column ADC circuit 3A is provided with an AD converter ADCbr for AD converting a signal transmitted via the vertical signal line VlinBR for each column. The column ADC circuit 3B is transmitted via the vertical signal line VlinG. An AD converter ADCg for AD converting the signal is provided for each column. The reference voltage generation circuit 6A generates the reference voltage VREFbr exclusively for the red pixel and the blue pixel. The reference voltage generation circuit 6B generates the reference voltage VREFg exclusively for the green pixel.

Then, after the reset component SigGt of the green pixel G is read from the column ADC circuit 3B, an accumulation operation for the green pixel G is started. The reset component SigGt is stored in the frame memory 41. When the pixel signal after the accumulation operation is read from the green pixel G in the column ADC circuit 3B, the signal component SigGs of the green pixel G is generated. When the pixel signal is read from the blue pixel B1 or the blue pixel B2, the column ADC circuit 3A generates a blue signal SigB by taking a difference between the signal level of the pixel signal and the reset level. When the pixel signal is read from the red pixel R1 or the red pixel R2, the column ADC circuit 3A generates a red signal SigR by taking a difference between the signal level of the pixel signal and the reset level. When the signal component SigGs of the green pixel G is output to the subtractor 43, the reset component SigGt of the green pixel G is read from the frame memory 41 and output to the subtractor 43. Then, the subtracter 43 subtracts the reset component SigGt from the signal component SigGs of the green pixel G to generate a green signal SigG and outputs it to the multiplexer 44. In the multiplexer 44, the green signal SigG, the blue signal SigB, and the red signal SigR are integrated to generate the output signal Vout3.
Here, the reset component SigGt of the green pixel G is stored in the frame memory 41, and the reset component SigGt is subtracted from the signal component SigGs of the green pixel G by the subtractor 43, whereby CDS of the green pixel G can be performed. . Therefore, as shown in FIG. 4, even when there is no readout transistor for the green pixel G, it is possible to reduce the threshold variation for each column of the amplification transistors TRampGr and TRampGb, and to reduce kTC noise. Can do.
Here, by generating the reference voltage VREFbr exclusively for the red pixel and the blue pixel and generating the reference voltage VREFg exclusively for the green pixel, the polarity and signal level of the red pixel and the blue pixel differ from the green pixel. Even in such a case, the CDS process can be performed properly. If the signal of the green pixel is an electron, the polarity is the same as that of the red pixel and the blue pixel. When the signal of the green pixel is a hole, the polarity is opposite to that of the red pixel and the blue pixel.

FIG. 14A is a timing chart showing the read operation of the red and blue pixels of the solid-state imaging device according to the fourth embodiment, and FIG. 14B is the green pixel of the solid-state imaging device according to the fourth embodiment. It is a timing chart which shows read-out operation.
14 (a) and 14 (b) are the same as FIGS. 12 (a) and 12 (b) except that the reference voltage VREF is separated into reference voltages VREFbr and VREFg. Here, in the blue pixel and the red pixel, the CDS processing is performed by subtracting the reset components SigBr and SigRr from the pixel signal components SigBs and SigRs in the column ADC circuit 3A after charge accumulation. On the other hand, in the green pixel, the reset component SigGt is output from the column ADC circuit 3B at the start of charge accumulation and stored in the frame memory 41. At the end of charge accumulation, the signal component SigGs is output from the column ADC circuit 3B. Then, the CDS process is performed by subtracting the reset component SigGt from the pixel signal component SigGs by the subtractor 43. At this time, the timing of the CDS processing of the blue pixel and the red pixel in the column ADC circuit 3A can be matched with the timing of the CDS processing of the green pixel in the subtractor 43.

(Fifth embodiment)
FIG. 15 is a timing chart showing a green pixel readout operation of the solid-state imaging device according to the fifth embodiment.
In the method of FIG. 12B, the reset line for reading the reset signal of the storage diode SD portion of the green pixel and the read line for reading the accumulated pixel signal are not the same line. For this reason, the 1 / f noise when the amplification transistor TRampGr performs the source follower operation is the frequency of the difference (frame time) between the reset time and the read time, and the 1 / f noise when the amplification transistor TRampBR performs the source follower operation. Compared to larger.
In order to reduce the 1 / f noise, in the method of FIG. 15, the voltage applied to the gate of the bias transistor VBi is temporarily increased before reading out the reset component SigGt and before reading out the pixel signal component SigGs, and the amplification transistor The current Iup flowing through the TRampGr source follower circuit is temporarily increased. This makes it possible to temporarily increase the current flowing through the amplification transistor TRampGr before reading out the reset component SigGt and before reading out the signal component SigGs, and increase the number of electrons trapped at the gate interface of the amplification transistor TRampGr. it can. As a result, fluctuations in the number of electrons trapped at the gate interface of the amplification transistor TRampGr can be reduced, and signal fluctuation due to 1 / f noise can be reduced.

(Sixth embodiment)
FIG. 16 is a circuit diagram showing a one-cell one-cell configuration in red and blue pixels according to the sixth embodiment.
In FIG. 16, this cell is provided with photodiodes PD-B, PD-R, row selection transistors TRadB, TRadrR, amplification transistors TRampB, TRampR, and reset transistors TRrstB, TRrstR. Here, the row selection transistor TRadrB, the amplification transistor TRampB, and the reset transistor TRrstB are used as an output circuit of the photodiode PD-B. The row selection transistor TRadRR, the amplification transistor TRampR, and the reset transistor TRrstR are used as an output circuit of the photodiode PD-R.

The source of the reset transistor TRrstR is connected to the gate of the amplification transistor TRampR and the cathode of the photodiode PD-R, and the drain of the reset transistor TRrstR is connected to the power supply potential Vsd. The drain of the amplification transistor TRampR is connected to the power supply potential VDD, and the source of the amplification transistor TRampR is connected to the vertical signal line VlinBR via the row selection transistor TRadrR. The source of the reset transistor TRrstB is connected to the gate of the amplification transistor TRampB and the cathode of the photodiode PD-B, and the drain of the reset transistor TRrstB is connected to the power supply potential Vsd. The drain of the amplification transistor TRampB is connected to the power supply potential VDD, and the source of the amplification transistor TRampB is connected to the vertical signal line VlinBR via the row selection transistor TRadB.
Here, by directly connecting the photodiodes PD-B and PD-R to the gates of the amplification transistors TRampB and TRampR, the layout and driving method of the red and blue pixels are made equal to the layout and driving method of the green pixel. In addition, the pixel layout and the driving circuit can be simplified.

(Seventh embodiment)
FIG. 17A is a block diagram showing a schematic configuration of the solid-state imaging device according to the seventh embodiment, and FIG. 17B shows an example of the layout of the photoelectric conversion layer of the solid-state imaging device of FIG. A perspective view and FIG.17 (c) are perspective views which show the other example of the layout of the photoelectric converting layer of the solid-state imaging device of Fig.17 (a).
In the solid-state imaging device of FIG. 17A, a frame memory 45 and a subtracter 46 are added to the configuration of FIG.
Then, after the reset component SigGt of the green pixel G is read, an accumulation operation for the green pixel G is started. Further, after the reset component SigBt of the blue pixel B1 or the blue pixel B2 is read, the accumulation operation for the blue pixel B1 or the blue pixel B2 is started. Further, after the reset component SigRt of the red pixel R1 or the red pixel R2 is read, the accumulation operation for the red pixel R1 or the red pixel R2 is started. These reset components SigGt, SigBt, and SigRt are stored in the frame memory 45. Then, when the pixel signal after the accumulation operation is read from the green pixel G in the column ADC circuit 3, the signal component SigGs of the green pixel G is generated. When the pixel signal after the accumulation operation is read from the blue pixel B1 or the blue pixel B2, the signal component SigBs of the blue pixel B1 or the blue pixel B2 is generated. When the pixel signal after the accumulation operation is read from the red pixel R1 or the red pixel R2, the signal component SigRs of the red pixel R1 or the red pixel R2 is generated. These signal components SigGs, SigBs, and SigRs are output to the subtractor 46. At this time, the reset components SigGt, SigBt, and SigRt are read from the frame memory 45 and output to the subtractor 46. The subtractor 46 subtracts the reset components SigGt, SigBt, and SigRt from the signal components SigGs, SigBs, and SigRs, respectively, thereby generating a green signal SigG, a blue signal SigB, and a red signal SigR.

  Here, the reset components SigGt, SigBt, and SigRt of the green pixel, red pixel, and blue pixel are stored in the frame memory 45, and the reset components SigGt, By subtracting SigBt and SigRt by the subtractor 46, CDS of the green pixel, red pixel and blue pixel can be performed. Therefore, as shown in FIG. 4 and FIG. 16, even when there are no green pixel, red pixel, and blue pixel readout transistors, the threshold variation for each column of each amplification transistor TRampGr, TRampGb, TRampR, TRampB is reduced. KTC noise can be reduced.

(Eighth embodiment)
FIG. 18 is a block diagram illustrating a schematic configuration of a digital camera to which the solid-state imaging device according to the eighth embodiment is applied.
In FIG. 18, the digital camera 11 includes a camera module 12 and a post-processing unit 13. The camera module 12 includes an imaging optical system 14 and a solid-state imaging device 15. The post-processing unit 13 includes an image signal processor (ISP) 16, a storage unit 17, and a display unit 18. The solid-state imaging device 15 can use the configuration shown in FIG. 1, FIG. 11, FIG. 13, or FIG. Further, at least a part of the configuration of the ISP 16 may be integrated with the solid-state imaging device 15 into one chip.

  The imaging optical system 14 takes in light from a subject and forms a subject image. The solid-state imaging device 15 captures a subject image. The ISP 16 processes an image signal obtained by imaging with the solid-state imaging device 15. The storage unit 17 stores an image that has undergone signal processing in the ISP 16. The storage unit 17 outputs an image signal to the display unit 18 in accordance with a user operation or the like. The display unit 18 displays an image according to the image signal input from the ISP 16 or the storage unit 17. The display unit 18 is, for example, a liquid crystal display. In addition to the digital camera 11, the camera module 12 may be applied to an electronic device such as a mobile terminal with a camera.

(Ninth embodiment)
FIG. 19 is a cross-sectional view illustrating a schematic configuration of a camera module to which the solid-state imaging device according to the ninth embodiment is applied.
In FIG. 19, light incident on the lens 22 of the camera module 21 from the subject enters the solid-state imaging device 29 through the main mirror 23, the sub mirror 24, and the mechanical shutter 28. Note that the solid-state imaging device 29 can use the configuration of FIG. 1, FIG. 11, FIG. 13, or FIG.
The light reflected by the sub mirror 24 enters an auto focus (AF) sensor 25. In the camera module 21, focus adjustment is performed based on the detection result of the AF sensor 25. The light reflected by the main mirror 23 enters the finder 30 through the lens 26 and the prism 27.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 pixel array unit, 2 vertical scanning circuit, 3 column ADC circuit, 4 horizontal scanning circuit, 5 timing control circuit, 6 reference voltage generating circuit, Vlin vertical signal line, Hlin horizontal control line, PC pixel, GU grid, G green pixel , R1, R2 Red pixel, B1, B2 Blue pixel

Claims (7)

Comprising pixels partitioned along a grid set at 45 ° to the column direction;
The pixel is
Green pixels,
A red pixel disposed to overlap the green pixel in the depth direction;
A solid-state imaging device comprising: the green pixel and a blue pixel arranged to overlap in the depth direction. A first output circuit for the red pixel and the blue pixel is arranged along the grid between the red pixel and the blue pixel;
2. The solid-state imaging device according to claim 1, wherein the second output circuit for the green pixel is arranged between the red pixel and the blue pixel in a direction orthogonal to the arrangement direction of the first output circuit. Green pixels,
A red pixel disposed to overlap the green pixel in the depth direction;
A blue pixel disposed to overlap the green pixel in the depth direction;
A memory for storing a reset level of a pixel signal read from the green pixel;
A solid-state imaging device comprising: a difference calculation unit that calculates a difference between a signal level of a pixel signal read from the green pixel and the reset level. The red pixel is arranged so as to overlap over one pixel of the green pixel,
The blue pixel is arranged so as to overlap over one pixel of the green pixel,
The solid-state imaging device according to claim 1, wherein the red pixel and the blue pixel are arranged on the same plane. The red pixel is arranged so as to overlap over two pixels of the green pixel,
The blue pixel is arranged so as to overlap over two pixels of the green pixel,
4. The solid-state imaging device according to claim 1, wherein the red pixel and the blue pixel are disposed so as to overlap in a depth direction. 5. A reference voltage generating circuit for outputting a reference voltage;
An ADC circuit for AD converting the pixel signal for each column based on a comparison result between the reference voltage and the pixel signal;
The timing control circuit which performs AD conversion of the pixel signal read from the green pixel at the same timing as AD conversion of the pixel signal read from the red pixel or the blue pixel. The solid-state imaging device according to item.   The timing control circuit reads out from a first line which is a readout line of a reset level of a pixel signal read from the red pixel or the blue pixel and a signal level of the pixel signal, and outputs a pixel signal read from the green pixel. The solid-state imaging device according to claim 6, wherein a signal level is also read from the first line, and a reset level of a pixel signal read from the green pixel is read from a second line that is a reset line of a storage diode.

Images